JP5436327B2 - Electronic circuit and wiring system - Google Patents

Description

  The present invention relates to an electronic circuit and a wiring system.

  An electronic circuit that mimics the structure and function of the brain is called a neural network or neurocomputer, and many artificial neurons (hereinafter referred to as neurons unless otherwise confused) operate in parallel. It is a computer to do. Hereinafter, an electronic circuit or software simulator that mimics the structure and function of the brain is referred to as a neural network.

  The Neumann computer is suitable for sequential processing using a fixed algorithm. On the other hand, since neural networks can mimic the features of the brain, they can be used for applications where it is difficult to accurately describe their control algorithms, such as welding control of metals and operation control of large-scale plants. Yes. It is also considered that it can be used for parallel processing (for example, image recognition, voice recognition, etc.) of a large amount of data that is ambiguous and has a large amount of loss or fluctuation. If a neural network with the same scale and function as a human brain can be realized, not only robots and cars can be greatly enhanced, but also an interface function with high compatibility with humans can be added to all machines, and past data can be used. It is expected to be able to predict the future.

  There are mainly two ways to implement a neural network. One is a method of building a simulator by software on a normal Neumann computer. In this method, a precise model that makes use of knowledge obtained from brain research can be created, and the neural network can be operated while observing or controlling the internal states of the neurons and the neural network. However, since it is a simulation method using a normal computer, it is difficult to move a large-scale (10,000 neurons or more) neural network in real time (all neurons calculate in about 4 ms). It is. In addition, the advantage of small size / low power consumption, which is a feature of the neural network, cannot be enjoyed. Therefore, this method is suitable when a small-scale neural network is mainly used for research purposes.

  The other realization method is a method in which a neuron is modeled by an electronic circuit and is implemented as hardware in which a large number of the neurons are mounted. In this method, there is a possibility that a large number (about 10,000) neurons can be operated in parallel in real time.

As an example of a conventional neural network, a part of the neural network will be described with reference to FIG. FIG. 21 is a schematic diagram showing a part of a neural network. The L1 layer is a data input layer. For example, a neuron 210 _i (i is an integer from 1 to 1,000) that converts 4-bit wide input data into a pulse train having a period of 4 [ms] is 1 There are 1,000. The L2 layer is a data processing layer, and there are, for example, 900 neurons 212 _j (j is an integer from 1 to 900) for processing data.

Each neuron 210 _i has one output signal line 211 _i . Since the number of neurons 212 _j is 900, the output signal line 211 _i branches to a maximum of 900 and is connected to the neuron 212 _j via the synapse connection 213 _{i, j} . Accordingly, there are a maximum of 1,000 synapse connections 213 _{i, j} per neuron 212 _j . Data a _i (output of the i-th neuron 210 _{i in} the L1 layer) transmitted through each signal line 211 _i is a 1-bit signal.

Each synapse connection 213 _{i, j} holds, for example, 8-bit width weight data w _{i, j} (the weight of the synapse connection of the _jth neuron 212 _{j in} the L2 layer that receives a signal from the neuron 210 _{i in the} L1 layer). and which calculates the product _{a i} × _{w i, j} and _{a i.} Each neuron 212 _j calculates the total sum of i of up to 1,000 products a _i × w _{i, j} calculated by the synaptic connections attached to each neuron 212 _j .

When the total value exceeds a predetermined threshold value θ, the output signal line 214 _{j is set} to 1, and when the total value does not exceed the threshold value θ, the output signal line 214 _{j is set} to 0. Ideally, a series of these operations is completed within 4 [ms]. Since the neural network has a small number of neurons of 1,900, whether the neural network is simulated by software or the neural network is implemented by an electronic circuit, each of the neurons 212 _j in the L2 layer in 4 [ms]. However, the series of operations can be performed once.

As is clear from the above description, the 1,000 neurons 210 _i in the L1 layer are connected to the 900 neurons 212 _{j in} the L2 layer in a round-robin manner, so that the synapse connection 213 _{i, j} used for the connection The number reaches a maximum of 900,000, and the total number of branches of the wiring 211 _i also reaches a maximum of 900,000.

Here, since an unnecessary synapse connection is removed depending on a use used in an actual neural network and a learning result, it is various which neuron 212 _j and synapse connection 213 _{i, j} an output of each neuron 210 _i forms. is there. That is, a mechanism is required that allows the neuron 210 _i to selectively create the synapse connection 213 _{i, j} with the neuron 212 _j , which makes the wiring problem more difficult.

  In the human brain, it is said that one neuron has 1,000 to 10,000 synaptic connections. Therefore, when the number of artificial neurons increases, the number of wirings required is 1, If it is less than 000, it is almost proportional to the square, and if it is 10,000 or more, it is considered to be almost proportional to the first power. Therefore, it can be estimated that about 100 billion to 1 trillion wirings are required to realize a neural network having a brain level of 100 million neurons. It is necessary to appropriately carry out such an enormous amount of wiring under appropriate rules or environments.

  In order to realize a large-scale neural network, several methods for reducing wiring between neurons have already been devised because wiring between neurons becomes a problem. For example, there is Patent Document 1. In this technique, the output data of all neurons in the L1 layer are time-division multiplexed and sent to one common signal line, which is received by all neurons in the L2 layer and used for computation. When this method is used, there is a remarkable effect that only one signal line connecting the two layers is required.

  On the other hand, a medium-scale (about 10,000 neurons) neural network is often made of a digital circuit from the viewpoint of circuit stability and calculation accuracy. In a neural network of this scale, AER (Address Event Representation) devised by a group of Professor Mead of California Institute of Technology is often used for data transfer between neurons (for example, Non-Patent Document 1).

  The format of AER will be described with reference to FIG. FIG. 22 shows a data format used for data transfer between neurons in the AER. In the AER, a number (Local address) is assigned to a neuron, and a number (Node address) is assigned to an LSI (Large Scale Integration), a PCB (Printed-Circuit Board), or a device in which the neuron is mounted.

  For example, assuming a PCB on which four LSIs incorporating 256 neurons are mounted as the L1 layer, 1,024 neurons can be identified by the following method. It combines 10 bits to 1,024 neurons by combining 2 bits Node address to distinguish 4 LSIs and 8 bits Local address to distinguish 256 neurons in each LSI. It is to do.

Similarly for the L2 layer, assuming a PCB on which four LSIs incorporating 256 neurons are mounted, the neurons in the L2 layer can be identified by 10-bit address information.
Consider a case in which data is sent from a certain neuron 210 _{i in} the L1 layer to a certain neuron 212 _j in the L2 layer. Neurons 212 _j addressing to be 10 bits required. Payload can be used in two ways.

The first method is a method in which the identification number ID _i (10 [bit]) of the neuron 210 _i is Payload. The neuron 212 _j uses the received identification number ID _i as index information to access a memory that stores synapse connection weights _, thereby determining the synapse connection weights u _{i, j} . In this method, two pieces of address information are sent for one data transmission, so one data amount is 20 [bit] (= 10 [bit] +10 [bit]).

  On average, if data is sent from the L1 layer to half of the neurons in the L2 layer, the total is 20 [bit] × (1,024 ÷ 2) × 1,024 = 10,485,760 [bit] = 1.3 [MB] data transmission is required. In order to execute this in 4 [ms], a data transfer rate of 1.3 [MB] ÷ 4 [ms] = 328 [MBps] is required.

  Further, in the L1 layer, it is necessary to store which neuron in the L2 layer to transfer data, so 10 [bit] × (1,024 ÷ 2) × 1,024 = 5,242,880 [bit] = A memory of 655 [KB] is required.

The second method is a method of calculating and sending a _i × u _{i, j} as Payload. When a _i is 1 bit and u _{i, j} is 8 bits, since a _i × u _{i, j} is 8 bits, one data amount is 18 [bit] (= 10 [bit] +8 [bit]). .
Therefore, the total data transfer amount is 18 [bit] × (1,024 ÷ 2) × 1,024 = 9,437, 184 [bit] = 1.2 [MB]. The total data transfer amount is slightly smaller than the transfer amount of the first method. However, the need for 655 [KB] memory in the L1 layer remains the same.

Japanese Patent Publication No. 5-47870

Serrano-Gotarredona R, Oster M, Lichtsteiner P, Linares-Barranco A, Paz-Vicente R, Gomez-Rodriguez F, Camunas-Mesa L, Berner R, Rivas-Perez M, Delbruck T, Liu SC, Douglas R, Hafliger P , Jimenez-Moreno G, Civit Ballcels A, Serrano-Gotarredona T, Acosta-Jimenez AJ, Linares-Barranco B, "CAVIAR: a 45k neuron, 5M synapse, 12G connects / s AER hardware sensory-processing- learning-actuating system for high-speed visual object recognition and tracking. ", IEEE Transactions on Neural Networks, Vol. 20, No.9, September, pp.1417-38, 2009.

  The neural network has the basic problem that the wiring between neurons becomes enormous when the number of neurons increases, so the conventional technology has a limit of realizing about tens of thousands of neurons, and the scale of a human brain There is no prospect of realizing (10 billion to 100 billion neurons).

  There are 10 to 100 billion neurons in the human brain, but it is said that only a few percent are actually used, so if there are more than 100 million artificial neurons, at least brain function It seems that it can imitate a part of (such as figure recognition and language recognition) fairly accurately.

However, due to the problems described below, it is difficult to construct a 100 million neuron-scale neural network that mimics the brain using the technique of Patent Document 1.
The first problem is that the connection form of the L1 layer and the L2 layer is fixed to all neurons versus all neurons. Where it is not desired to create synaptic connections, it is said that the synaptic connection weight can be substantially eliminated by setting the synaptic connection weight to 0, but this is very wasteful.

  For example, if a neural network of 100 million neurons is realized by a six-layer structure used as a model of the cerebral cortex and the same number of neurons is allocated to each layer, the number of neurons is approximately 17 million neurons. For one neuron in the L2 layer that receives this data, only less than 10,000 of the approximately 17 million data are meaningful, and the remaining approximately 16,699,000 data must be ignored. Don't be. Since the data that should be ignored differs for each neuron of the L2 layer, a huge circuit and a memory of 8 [bit] × 16.99 million × 17 million = 289 [TB] are required only for the L2 layer. Become.

  The second problem is that the fan-in (number of inputs) and fan-out (number of outputs) of the common signal line become enormous. As in the first problem, if a neural network of 100 million neurons is realized with a six-layer structure, there are about 17 million neurons per layer. That is, the fan-in of the common bus is about 17 million and the fan-out is about 17 million. It is very difficult to realize this with an electronic circuit.

  In addition, since the circuit unit that generates about 17 million pieces of data is physically quite large, if it is forced to combine it into one, it must be divided into several stages and the circuit is enormous. become. Although it is conceivable to use several common signal lines instead of one, it becomes a problem which neuron belongs to each common line. In addition, how to communicate over different common lines becomes a big problem, and it is difficult to solve it.

  Because of these problems, the technique of Patent Document 1 is suitable for a small-scale neural network having several tens to several hundreds of neurons, but is difficult to apply to a neural network having several thousand neurons or more.

  On the other hand, the AER method requires a large amount of data transmission for connection between neurons, and further requires a memory for storing a destination address in the transmission source. In a medium-scale neural network, the amount of data to be transmitted is proportional to the square of the number of neurons, and the number of bits of the address increases.

For example, if the L1 layer and the L2 layer each have 10,000 neurons, an address of 14 bits or more is required, so the communication speed is (14 [bit] +8 [bit]) × 5,000 × 10,000 ÷ 4 [ms. ] = 34.4 [GB / s] is required. Further, the memory of (14 [bit] +8 [bit]) × 5,000 × 10,000 = 138 [MB] is required for the L1 layer.
For this reason, the AER method can be applied only to a neural network having about several tens of thousands of neurons and each neuron having several hundred synaptic connections.

  Therefore, the present invention has been made in view of the above problems, and an object thereof is to provide an electronic circuit and a wiring system that reduce the number of wirings between neurons.

In order to solve the above problem, the invention described in claim 1 is a synapse that connects a plurality of layers, a plurality of artificial neurons existing in the layers, and the artificial neurons and artificial neurons existing in other layers. A product of the output data of the artificial neuron of the first layer of the plurality of layers and the weight information of the synaptic connection, and outputs an output corresponding to a result of accumulating the product to the second An electronic circuit that realizes a neural network that outputs an artificial neuron of a layer, and divides the virtual space by an arbitrary number of arbitrary polytopes (for example, regular hexagonal cells CN in the embodiment) in a virtual space of two or more dimensions And a circuit unit (for example, the circuit unit 10 in the embodiment) arranged for each polytope and the circuit unit arranged in an adjacent polytope. In, and a wiring for transmitting the output data of the artificial neurons of the first layer,
The circuit unit implements a plurality of artificial neurons belonging to the first layer and a plurality of artificial neurons belonging to the second layer, and the first layer artificial neurons time-division multiplex their output data, The time division multiplexed data is output to the second layer artificial neuron in the same circuit unit and the second layer artificial neuron of the circuit unit arranged in the polytope adjacent to its own polytope. The artificial neurons of the second layer in the circuit unit include the output data output from the artificial neurons of the first layer in the same circuit unit and the first layer of the circuit unit arranged in the polytope adjacent to its own polytope. In this electronic circuit, the output data output from the artificial neuron is processed as input data.
As a result, a signal line necessary for wiring between the neurons can be one output signal line to a polytope adjacent to its own polytope per one polytope.

In the invention described in claim 2, in the invention described in claim 1, in the synapse connection in which the circuit unit does not need to input the output data of the artificial neuron of the first layer, the weight information is set to 0. It is characterized by doing.
Thereby, the output data from the first artificial neuron can be given in common to the second layer artificial neuron regardless of the necessity of receiving the output data of the first layer artificial neuron, The input from the first layer artificial neuron to the second layer artificial neuron is blocked without losing the wiring to the second layer artificial neuron that does not require information from the first layer artificial neuron. can do.

The invention described in claim 3 is the invention according to claim 1 or 2, wherein the virtual space is configured by a virtual two-dimensional plane, the polytope is configured by a regular hexagon, and the virtual two-dimensional plane is arbitrarily set. It divides | segments by the said regular hexagon of the number.
As a result, the virtual two-dimensional plane can be filled with regular hexagons without gaps. In addition, each artificial neuron in the virtual two-dimensional plane can form a synaptic connection with an artificial neuron within approximately the same distance.

According to a fourth aspect of the present invention, in the invention according to any one of the first to third aspects, the circuit unit outputs the output data of the artificial neuron of the second layer to the second layer or the first layer. It is characterized by being input data to the artificial neuron.
Thereby, the output data of a neuron in a certain layer can be fed back to the neuron in the same layer or a layer before the layer.

According to a fifth aspect of the present invention, in the invention according to any one of the first to fourth aspects, the circuit unit includes a first storage unit that holds input data of the first layer of artificial neurons (for example, The memory 21) in the embodiment, the second storage unit (for example, the memory 25 in the embodiment) that holds the weight information of the synapse connection, and the artificial neuron in the first layer time-division multiplex the input data. Output data to the second layer artificial neuron in the same circuit unit and output the output data to the second layer artificial neuron in the circuit unit arranged in the adjacent polytope (for example, The pulse train modulation circuit 22) in the embodiment and a multiplication circuit that calculates the product of the output data and the weight information (for example, the multiplier 50 in the embodiment) Based on the comparison result between the adder (for example, the adder 27 in the embodiment) that uses the product as one input signal and calculates the sum, and the sum and the predetermined threshold, And a magnitude comparator for determining output data (for example, the magnitude comparator 29 in the embodiment).
Thereby, the data processing based on the information input to the first layer can be executed at high speed.

According to a sixth aspect of the present invention, in the invention according to any one of the first to fifth aspects, the circuit unit includes a first storage unit that holds input data of the first layer of artificial neurons (for example, , Memory 21) in the embodiment, a second storage unit (for example, memory 25 in the embodiment) that holds the weight information of the synapse connection, output data of the artificial neuron in the first layer, and the weight information A multiplication circuit (for example, the AND gate 26 in the embodiment) that calculates the product of the above and an operation that calculates a value obtained by multiplying the product corresponding to the predetermined first layer artificial neuron by a constant among the products calculated by the multiplication circuit A circuit (for example, the 1-bit left shifter 36 in the embodiment) and an adder (for example, the adder 2 in the embodiment) that calculates a sum of the values multiplied by the constant as one input signal ) And a size comparator (for example, the size comparator 29 in the embodiment) that determines output data of the artificial neuron group of the second layer based on a comparison result between the sum and a predetermined threshold value. It is characterized by.
As a result, when realizing a neural network in which a normal neuron and a power neuron having an influence that is a power of two times that of a normal neuron are mixed, a synaptic connection weight storage memory is obtained without reducing the resolution of the synaptic connection weight. The required capacity can be greatly reduced.

According to a seventh aspect of the present invention, in the invention according to the fifth or sixth aspect, the circuit unit is a multiplier that multiplies the sum by a predetermined attenuation amount (for example, the multiplier in the embodiment). and 52), a third storage unit for holding the multiplied multiplication result (e.g., memory 53) and further comprising a in the embodiment, the adder, the multiplication result held in the third storage unit The other input signal is used.
As a result, it is possible to obtain initial input data when the adder performs the summation calculation while attenuating the sum total output by the adder by a predetermined time constant.

According to an eighth aspect of the present invention, in the invention according to any one of the first to seventh aspects, the circuit unit includes a first storage unit that holds input data of the first layer of artificial neurons (for example, , The memory 21) in the embodiment, the second storage unit (for example, the memory 25 in the embodiment) that holds the absolute value of the weight of the synapse connection, the output data of the artificial neuron in the first layer, and the weight Code information for outputting the sign information of the weight of the synapse connection indicating whether the multiplication circuit (for example, the AND gate 26 in the embodiment) for calculating the product of the absolute value and the first layer neuron is excitatory or inhibitory. Based on the output information (for example, the sign storage 33, the magnitude comparator 34 or the AND gate 34B in the embodiment) and the sign information, the product value or the negative value of the product is Based on the result of comparison between the adder (for example, the adder / subtractor 32 in the embodiment) that calculates the sum as an input signal and the calculated sum and a predetermined threshold, the output data of the artificial neuron in the second layer is determined. And a large / small comparator (for example, the large / small comparator 29 in the embodiment).
As a result, when realizing a neural network in which excitatory and inhibitory neurons are mixed, the capacity required for a memory for storing synaptic connection code information can be greatly reduced.

The invention according to claim 9 is the invention according to any one of claims 1 to 8, wherein a predetermined value predetermined for each artificial neuron of the second layer is maintained, and further, for each artificial neuron. A threshold value calculation circuit that calculates the pseudo random number and adds the predetermined value and the pseudo random number to a predetermined threshold value commonly set for the second layer artificial neurons (for example, the threshold value calculation circuit 38 in the embodiment) Is further provided.
As a result, since a predetermined value predetermined for each artificial neuron can be added to the threshold value of the artificial neuron, the threshold value can be changed for each artificial neuron. Moreover, since the pseudo random number calculated for each artificial neuron can be added to the threshold value of the artificial neuron, the threshold value can be changed pseudo-randomly for each artificial neuron.

In order to solve the above problem, the invention described in claim 10 is a synapse that connects a plurality of layers, a plurality of artificial neurons existing in the layers, and the artificial neurons and artificial neurons existing in other layers. A product of the output data of the artificial neurons of the first layer of the plurality of layers and the weight information of the synapse connection, and an output corresponding to a result of accumulating the products is output to the second layer A wiring system that realizes a neural network that outputs an artificial neuron in a virtual space of two or more dimensions, dividing the virtual space by an arbitrary number of arbitrary polytopes, arranging circuit units for each of the polytopes, and adjacent to each other A first wiring arranged to transmit a signal including the output data of the first layer between the circuit units arranged in the polytope, and a complex belonging to the first layer. And a plurality of artificial neurons belonging to the second layer, the first layer artificial neurons time-division multiplex their own output data, and the time-division multiplexed data is converted into the same circuit unit. To the second layer artificial neuron and the second layer artificial neuron of the circuit unit arranged in the polytope adjacent to its own polytope, and the second layer artificial neuron of the same circuit unit And a second wiring wired to input the output data output from the first layer artificial neuron of the circuit unit arranged in the polytope adjacent to the own polytope. .
As a result, the wiring between the artificial neurons constituting the neural network can be connected to the adjacent polytope using one data output line for each polytope, so that the communication between existing polytopes is not affected even if a polytope is added. I do not receive it. Therefore, any number of artificial neurons can be wired while keeping the data communication speed between the artificial neurons constant.

  According to the first aspect of the present invention, it is possible to realize an electronic circuit in which wiring between neurons is performed at a low speed with a small number of wirings.

  According to the second aspect of the present invention, the synapse connection can be substantially invalidated, so that it is not necessary to physically eliminate the wiring in the portion where the synapse connection is lost later. In addition, a synapse connection can be newly generated at a location where the weight of the synapse connection is 0 as necessary.

  According to the invention described in claim 3, since the virtual two-dimensional plane is divided into regular hexagons, each neuron included in each circuit unit can form a synaptic connection with a neuron within a substantially equal distance in the virtual plane. it can.

  According to the invention described in claim 4, since the output data of the artificial neuron in the second layer can be fed back to the second layer or the first layer, a neural network having a signal feedback circuit is implemented by an electronic circuit. it can.

  According to the invention described in claim 5, a large-scale neural network in which the first layer is an excitatory neuron can be implemented by an electronic circuit.

  According to the invention described in claim 6, a neural network in which a normal neuron that gives a normal influence to a neuron in the next layer and a power neuron that gives a larger influence to a neuron in the next layer is mixed with an electronic circuit. As a result, it is possible to greatly reduce the capacity required for the synaptic connection weight storage memory.

  According to the seventh aspect of the present invention, the sum total calculation of the data received from the synapse connection is performed. As a result, when the neuron does not fire, the sum total calculation result is attenuated by a predetermined time constant, and the next sum total is calculated. Since it is the initial value of the calculation, a neural network that can handle the time history can be implemented with an electronic circuit.

  According to the eighth aspect of the invention, by using the memory means for storing the code information, the electronic circuit that implements the neural network can simulate the excitatory artificial neuron and the inhibitory artificial neuron. Further, the memory capacity can be reduced by storing the code information in the memory for each neuron instead of for each synapse connection.

  According to the invention described in claim 9, since the threshold value can be changed for each artificial neuron in the second layer, a neural network having a different threshold for each artificial neuron in the second layer can be used as an electronic circuit. Can be implemented. In addition, since the threshold value can be changed pseudo-randomly for each artificial neuron in the second layer, it is possible to prevent the local network from falling into a local minimum state when the neural network learns.

  According to the invention described in claim 10, it is possible to wire between an arbitrary number of neurons while keeping the data transfer rate between neurons constant.

It is the figure for demonstrating the schematic diagram of the neural network in Example 1 of this invention, and the signal which time-division multiplexed the output of the L1 layer. It is a figure for demonstrating the wiring between the circuit units by one Embodiment of this invention. It is a figure for dividing a virtual plane by one embodiment of the present invention, and explaining wiring between circuit units. It is a figure for divide | segmenting the virtual space by one Embodiment of this invention by a cube, and demonstrating the wiring between circuit units. It is a circuit diagram which simulated the neuron group which uses the circuit unit by one Embodiment of this invention with a pulse neural network. It is a figure for demonstrating the data conversion table hold | maintained at the memory for pulse train modulation. 6 is a timing chart for explaining the operation of the circuit shown in FIG. 5. It is a circuit diagram which simulated the neuron group which uses the circuit unit by one Embodiment of this invention in the neural network in which information is represented by multiple bits. FIG. 6 is a circuit diagram for realizing a neuron in which information received by a synaptic connection is attenuated with a predetermined time constant. It is another circuit diagram which simulated the neuron group which uses the circuit unit by one Embodiment of this invention with a pulse neural network. It is a circuit diagram of a circuit unit in which an excitatory neuron group and an inhibitory neuron group are mixed according to a second embodiment of the present invention. It is a circuit diagram of the circuit unit which is a modification of the 2nd example of the present invention. FIG. 6 is a circuit diagram of a circuit unit that simulates a neural network in which an excitatory neuron group and an inhibitory neuron group are mixed, other than a pulse neural network. It is a circuit diagram of a circuit unit in which a normal neuron group and a power neuron group are mixed according to a third embodiment of the present invention. It is a circuit diagram of the circuit unit which is a modification of the 3rd example of the present invention. FIG. 10 is a circuit diagram of a circuit unit simulating a neuron group having offsets and fluctuations in threshold values according to a fourth embodiment of the present invention. It is a circuit diagram of an 8-bit pseudo random number generator (Galois LFSR). It is the figure for demonstrating the schematic diagram of the neural network in Example 5 of this invention, and the format of the signal which flows between layers. FIG. 10 is a circuit diagram of a circuit unit of a neural network that feeds back an output of an L2 layer neuron group to an L2 layer neuron group according to a fifth embodiment of the present invention. FIG. 10 is a circuit diagram of a circuit unit of a neural network that feeds back an output of an L3 layer neuron group to an L2 layer neuron group, which is a modification of the fifth embodiment of the present invention. It is a schematic diagram showing a part of the neural network. This is a data format used for data transfer between neurons in AER. It is a schematic diagram showing a neural network having a three-layer structure having a feedback loop.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, the configuration of the neural network of the present invention will be described. FIG. 1A is a diagram showing the configuration of a neural network. The neural network is composed of two layers, an L1 layer and an L2 layer.

The neural network includes a first layer (L1 layer) neuron 20 _i (i is an integer from 0 to 4,863) and a second layer (L2 layer) neuron 22 _j (j is 0 to 4,863). an integer), the wiring 21 _i to neuron 22 _j of the L2 layer from the neuron 20 _i of the L1 layer, the synaptic connections _{23 i} of neuron 22 _j of L2 layer corresponding to the wiring 21 _i, and _j, the L2 layer of neurons 22 _j output terminals _24j .

The synaptic connection includes a weight w _{i, j} of the synaptic connection that determines how much the output of the neurons in the L1 layer is transmitted to the neurons in the L2 layer. For unnecessary connections, the synaptic connection weight w _{i, j} can be set to 0 to substantially invalidate the synaptic connection.

The same number of neurons 20 _{i in the} L1 layer are divided into 19 groups (hereinafter referred to as cells). Then, the neuron 20 _i of the L1 layer present on per single cell is 256. Similarly, the neuron 22 _{j in the} L2 layer is divided into 19 cells. Then, there are 256 neurons in the L2 layer 22 _j that exist per cell. Accordingly, the neural network of FIG. 1A is divided by 19 cells CN (N is an integer from 0 to 18).

FIG. 1B is a diagram for explaining a signal obtained by time-division multiplexing the output of the L1 layer. The output data of 256 neurons in the L1 layer of the cell CN is time-division multiplexed as shown in FIG. 1B, and is output from the P0 terminal as signals x _{i, t} .

x _{i, t} is the output of the t-th (t is an integer greater than or equal to 0) round of the i-th (i is an integer from 0 to 255) neuron in the L1 layer. That is, x _{0, t} is the output of the neuron 20 ₀ , x _{1, t} is the output of the neuron 20 ₁ ,..., X _{255, t} is the output of the neuron 20 ₂₅₅ . Here, a round is a processing unit for processing data of 256 neurons once.

  FIG. 2 is a diagram for explaining wiring between circuit units according to an embodiment of the present invention. Neurons in the brain basically make synaptic connections with physically close neurons. The wiring problem between neurons is solved by referring to this feature.

FIG. 2A is a diagram in which the virtual plane is divided into a plurality of cells. In FIG. 2A, each cell has a regular hexagonal shape. FIG. 2B is a diagram showing wiring between cells. There is one circuit unit in each cell.

Since there are 19 cells in FIG. 1, there are 256 × 19 = 4,864 neurons 20 _i and 22 _{j in} the L1 layer and the L2 layer, respectively. Each cell has one output terminal P0 and six input terminals P1 to P6 (FIG. 2B). There are certain rules regarding the arrangement of cells and the wiring to the input terminals.

  As shown in FIG. 2B, an output terminal P0 of a certain cell is connected only to an adjacent cell. Further, there is a certain rule in the arrangement of each input terminal and a cell that outputs a signal connected to the input terminal. Here, the cell C0 will be described as an example. As shown in FIG. 2B, the input terminal P1 of the cell C0 is connected to the output terminal P0 of the cell C1 adjacent immediately above the cell C0.

  Similarly, the input terminal P2 of the cell C0 is connected to the output terminal P0 of the cell C2 adjacent to the upper right of the cell C0. The input terminal P3 of the cell C0 is connected to the output terminal P0 of the cell C3 adjacent to the lower right of the cell C0. The input terminal P4 of the cell C0 is connected to the output terminal P0 of the cell C4 adjacent immediately below the cell C0. The input terminal P5 of the cell C0 is connected to the output terminal P0 of the cell C5 adjacent to the lower left of the cell C0. The input terminal P6 of the cell C0 is connected to the output terminal P0 of the cell C6 adjacent to the upper left of the cell C0.

  That is, the input data received by the input terminal P1 of a certain circuit unit is the data output from the output terminal P0 of the circuit unit adjacent immediately above. Similarly, the input data received by the input terminal P2 of a certain circuit unit is data output from the output terminal P0 of the circuit unit adjacent to the upper right. The input data received by the input terminal P3 of a certain circuit unit is data output from the output terminal P0 of the circuit unit adjacent to the lower right. The input data received by the input terminal P4 of a certain circuit unit is the data output from the output terminal P0 of the circuit unit adjacent immediately below. The input data received by the input terminal P5 of a certain circuit unit is data output from the output terminal P0 of the circuit unit adjacent to the lower left. The input data received by the input terminal P6 of a certain circuit unit is data output from the output terminal P0 of the circuit unit adjacent to the upper left.

  In the L2 layer of a certain cell, the signal input from the L1 layer of the cell and the six signals input to the input terminals P1 to P6 from the adjacent cell are used to transmit the L1 layer in the cell and the adjacent cell. Create synaptic connections with all neurons. That is, each neuron in the L2 layer of the cell C0 in FIG. 2A forms a synaptic connection with the cell C0 and 256 × 7 = 1,792 neurons in the L1 layer in the six adjacent cells C1 to C6. .

  Similarly, for example, each neuron of the L2 layer in the cell C1 forms a synaptic connection with all the neurons of the L1 layer in the cell C1 and six adjacent cells C8, C9, C2, C0, C6, and C7. Each neuron in the L2 layer can make a synaptic connection with 1,792 neurons in the L1 layer, and some of them are unnecessary.

  In general, since each neuron in the L1 layer is connected only to its own cell and the neuron in the L2 layer in the adjacent cell in the virtual plane, there are few places where the synapse connection is unnecessary, and the weight W of the synapse connection is 0. It is thought that there are few places to make.

  In the embodiment of FIG. 1, the number of neurons included in the L1 layer and the L2 layer is 256. However, the present invention is not limited to this, and any number of 2 or more is generally applicable. Further, the number of neurons in the L1 layer and the L2 layer need not be the same. In the present embodiment, as shown in FIG. In addition, this invention is not restrict | limited to this, It is also possible to extend to three or more layers.

  In this embodiment, the virtual plane on which neurons are arranged is divided into regular hexagons, but the present invention is not limited to this. FIG. 3 is a diagram for explaining wiring between circuit units by dividing a virtual plane according to an embodiment of the present invention. For example, as shown in FIG. 3A, it can be divided into squares, or can be divided into equilateral triangles.

  Further, instead of arranging the same polygons, it is also possible to divide into a plurality of types (three types) of polygons as shown in FIG. Further, since the virtual plane is virtual, there is no particular problem even if overlap occurs between polygons or a gap occurs between polygons. The input terminal to which no signal is input is connected to the ground potential.

  The shape of the polygon is related to the maximum number of synaptic connections that one neuron can form. For example, in the case of a regular hexagon, since there are six adjacent cells, assuming that 256 neurons are included in the L1 layer of one cell, a maximum of 256 × 7 = 1,792 synaptic connections are formed in the neurons of the L2 layer. .

  On the other hand, in the case of FIG. 3A, since there are eight adjacent cells, a maximum of 256 × 9 = 2,304 synapse connections are formed. In the case of FIG. 3B, it can be interpreted that three types of circuit units having different maximum synapse coupling numbers are mixed, and a gap other than a regular pentagon can be ignored. Furthermore, the present invention can be similarly applied even if the virtual plane is divided by a figure of an arbitrary shape instead of a regular polygon.

  In the description of the present embodiment, the virtual two-dimensional plane is considered and the neurons are distributed and arranged there. However, the present invention is not limited to this. When imitating the human brain, a two-dimensional plane is sufficient, but the present invention can be similarly applied to a three-dimensional space as a structure exceeding this.

  FIG. 4 is a diagram for explaining wiring between circuit units by dividing a virtual space according to an embodiment of the present invention into cubes. For example, as shown in FIG. 4, a virtual three-dimensional space is divided into cubes, and neurons in the L1 layer of an arbitrary cube make synaptic connections with neurons in the L2 layer in the cube adjacent to the cube.

  As shown in FIG. 4, there is one output terminal at the top and one input terminal on each surface for each cell. A cell adjacent to a certain cell is a total of six cells adjacent in a front-back, up-down, left-right direction. One input terminal on each of the front, back, top, bottom, left and right surfaces of a cell is connected to the output terminal of an adjacent cell.

  As another example, one output terminal per cell, one input terminal on each side (6 in total), 1 on each side (12 in total), 1 on each corner (8 in total), that is, 26 in total. A cell adjacent to a cell is a total of 26 cells adjacent to each other by a face, a side, and a corner. The 26 input terminals existing in a certain cell are connected to the output terminals of 26 adjacent cells, respectively.

  Further, the three-dimensional space can be divided not by a cube but generally by an arbitrary polyhedron. As described above, the present invention is generally applicable to a case where an arbitrary degree space of two or more dimensions is divided by an arbitrary polytope. The polytope represents a polygon in the case of two dimensions, a polyhedron in the case of three dimensions, and a polytope in the case of four dimensions or more. In general, a polytope is a figure obtained by generalizing a two-dimensional polygon or a three-dimensional polyhedron into a general dimension. However, in the case of a four-dimensional or larger space, the illustration is omitted because it cannot be illustrated.

<Description of Example 1 of Circuit Unit>
Next, a first embodiment of the circuit unit of the present invention will be described. FIG. 5 is a circuit diagram simulating a neuron group using a circuit unit according to an embodiment of the present invention in a pulse neural network. The entire circuit unit 10 in FIG. 5 corresponds to the circuit unit existing in one cell shown in FIG. In this embodiment, each neuron is not a separate electronic circuit, but 256 neurons are collectively mounted for each layer as virtual excitatory neurons.

  A method for implementing 256 neurons in each layer is as follows. Input data (4 [bit] data) of 256 neurons in the L1 layer is stored in the memory 21. The synaptic connection weight (8 [bit] data) of the neurons in the L2 layer is stored in the memory 25. On the other hand, the output data of 256 neurons in the L2 layer is represented by a 1 [bit] signal of 0 or 1.

  The circuit unit 10 includes an 8-bit counter 20 belonging to the L1 layer, a memory 21, a pulse train modulation circuit 22, an 8-bit counter 23A belonging to the L2 layer, an 8-bit counter 23B, a memory 24A, a memory 24B, and a memory. 25, an AND gate 26, an adder 27, an AND gate 28, a magnitude comparator 29, a latch 30, and a counter 31.

  Each time the count-up signal is input to the input terminal 41, the 8-bit counter 20 increases the count value by 1 and outputs the count value to the memory 21. The 8-bit counter 20 is set to 0 in advance by a reset signal (not shown), and when it counts up to 255, it returns to 0 at the next count-up timing.

The memory 21 stores input data of the neurons 20 _{i in} the L1 layer. Since data is sent from the L1 layer to the L2 layer as a 1-bit signal, 4-bit data is converted into a 15-bit bit string and transferred over 15 rounds. Here, a value of 1 corresponds to the firing of a neuron. Since the number of neurons 20 _{i in} the L1 layer included in one circuit unit is 256, the memory 21 has a capacity of 4 [bits] × 256 = 1,024 [bits]. The input data of the i-th neuron in the L1 layer is stored at address i of the memory 21.

  The memory 21 reads 4-bit data from the address indicated by the count value of the 8-bit counter 20 and sends the data to the pulse train modulation circuit 22.

  The pulse train modulation circuit 22 converts the 4-bit data read by the memory 21 into a 15-bit pulse train. The pulse train modulation circuit 22 includes a data conversion memory that stores a data conversion table. FIG. 6 is a diagram for explaining the data conversion table. In FIG. 6, 4-bit data on the left is data received by the pulse train modulation circuit 22 and serves as an address signal to the data conversion memory. The upper 15-bit data is data stored in the data conversion memory.

  The pulse train modulation circuit 22 outputs the LSB (Least Significant bit) from the 15-bit data train to the memories 24A and 24B of its own cell for each round to be described later. Further, the pulse train modulation circuit 22 outputs the data to the input terminals P1 to P6 of the adjacent cells via the P0 terminal. Thereafter, in the own cell and adjacent cells, the memories 24A and 24B are switched for each round to be described later to store the data.

Each time the number of rounds increases, the pulse train modulation circuit 22 increases the bit position to be transmitted by 1 and outputs data at the bit position.
In round 14, when the most significant bit data of the 15-bit data is transferred to the memory 24A of the cell adjacent to the self-cell memory 24A, the data stored in the memory 21 is converted into a pulse train and transferred. Processing ends.

  In this embodiment, data is output in order from the least significant bit, but it may start from an arbitrary bit position. Further, the order of the output bit positions may be determined appropriately. This is because the output information of the L1 layer neuron is represented by the frequency with which 1 appears in the pulse train, so the order in which the data is output is not relevant.

  When data is written to the memory 24A or the memory 24B, the count-up signal input to the terminal 41 of the 8-bit counter 20 and the terminal 42A of the 8-bit counter 23A belonging to the L2 layer and the terminal 42B of the 8-bit counter 23B A count-up signal having the same frequency is input. Each time the count-up signal is input, the 8-bit counter 23A and the 8-bit counter 23B increment the count value by 1, and output the count value to the memory 24A or the memory 24B. The 8-bit counter 23A and the 8-bit counter 23B are set to 0 in advance by the same reset signal as the reset signal of the 8-bit counter 20 (not shown). When counting up to 255, the counter returns to 0 at the next count-up timing.

  The memory 24A and the memory 24B (each 7 [bit] × 256 [capacity] capacity) alternately store the data transmitted through the seven signal lines for each round. Here, the data input to the terminal P0 is data output from the pulse train modulation circuit 22 of the own cell. The data input from terminals P1 to P6 is data output from the pulse train modulation circuit 22 of the adjacent cell.

When reading data from the memory 24A or the memory 24B, the 8-bit counter 23A and the 8-bit counter 23B count up at a frequency of 64 [kHz] × 256 = 16.384 [MHz]. The memory 24A and the memory 24B read the stored 7-bit width data at 16.384 [MHz], and further parallel-converts the data to 7 times the 14.7-bit 1-bit signal a ′. _{i, p, q} . Here, i is an integer from 0 to 255, p is an integer from 0 to 14 representing the bit position, and q is an integer from 0 to 6 representing the input (out) force terminal number. However, i and q change during one round, but p is constant. p changes every time the round changes (in this embodiment, it starts from 0 and increases by 1). The 1-bit signals a ′ _{i, p, q} are sent to the AND gate 26 through one signal line.

The counter 31 counts each time a count-up signal of 7 × 256 = 1,792 times (114.7 [MHz]) the count-up signal input to the terminal 41 of the 8-bit counter 20 is input to the terminal 47. Is increased by 1. The count value of the counter 31 enters the address input A of the memory 25. The memory 25 reads the synaptic connection weights w ′ _{i, q, j} from the address corresponding to the count value. j is an integer from 0 to 255 and represents the L2 layer neuron number. The subscripts i and q change first, and j increases by 1 each time 1,792 w ′ _{i, q, j} are read out.
The counter 31 is set to 0 in advance by the same reset signal as that of an 8-bit counter 20 (not shown).

The storage capacity of the memory 25 is 8 [bits] × 256 × 7 × 256 = 459 [KB]. The weights w ′ _{i, q, j} of the synapse connection from the i-th neuron in the L1 layer to the j-th neuron in the L2 layer are stored in advance through the terminal I of the memory 25 by a circuit not shown.

The memory 25 reads the weight w ′ _{i, q, j} of the synapse connection at 114.7 [MHz] which is the frequency of CLK1 described later, and sends it to the AND gate 26.

The AND gate 26 multiplies the 1-bit signal a ′ _{i, p, q} read by the memory 24A or the memory 24B and the 8-bit signal w ′ _{i, q, j} read by the memory 25. The AND gate 26 sends the multiplication result y _{i, p, q, j} = a ′ _{i, p, q} × w ′ _{i, q, j} to the adder 27.

The adder 27 receives the output data y _{i, p, q, j} of the AND gate 26 and calculates the sum of i and q for each jth neuron in the L2 layer. When performing the sum calculation, the adder 27 sequentially adds y _{i, p, q, j} to the partial sum calculated up to the previous CLK 1 at 114.7 [MHz] which is the frequency of CLK 1 described later. To do. The partial sum is supplied by the AND gate 28.
The adder 27, the j-th neuron of the L2 _{layer, y i, p, q,} summation relating _j i and q _{Y p,} when finishes calculating the _j, the sum _{Y p,} the magnitude comparator 29 _j send.

  When the control signal 0 is input to the terminal 44 at the beginning of the summation calculation of the jth neuron in the L2 layer, the AND gate 28 outputs 0 to the one-side input of the adder 27, and the summation starts from the state where the partial sum is 0. Control the calculation to start.

The magnitude comparator 29 receives the sum Yp _{, j} calculated by the adder 27, and when the sum Yp _{, j} is larger than a threshold value θ supplied from a terminal (not shown) or externally from the terminal 43, 1 is output. The size comparator 29 outputs 0 in other cases.

  The latch 30 receives the signal output from the magnitude comparator 29, and stores the output signal when the timing signal input from the terminal 45 changes from 0 to 1. The latch 30 outputs the stored signal from the terminal 46, and the output signal becomes an output signal of the L2 layer neuron.

  Although the weight of the synapse connection is positive or negative, it does not affect the effect of the present invention. Therefore, in this embodiment, only the positive data will be described.

  Subsequently, the operation of the present embodiment will be described. Before the processing in the neural network of FIG. 5 starts, the input data of the neurons of the L1 layer is stored in the memory 21 in advance by an arbitrary method (not shown), and the weight data of the synapse connection is also stored in the memory 25. . The counter 20, the counter 23A, the counter 23B, and the counter 31 are set to 0 beforehand by a reset signal (not shown).

  First, since the count value of the counter 20 is 0, the address input of the memory 21 becomes 0. Since the address input of the memory 21 is 0, the 4-bit data (of the 0th neuron in the L1 layer) is read from address 0 and sent to the pulse train modulation circuit 22.

  The pulse train modulation circuit 22 converts the 4-bit data received from the memory 21 into 15-bit data. The pulse train modulation circuit 22 selects data at an appropriate bit position of the 15-bit data and outputs it to the memory 24A or 24B of its own cell. At the same time, the selected data is output to the memory 24A or 24B of the adjacent cell via the P0 terminal.

Next, a data processing method will be described. When the sum of a ′ _{i, p, q} × w ′ _{i, q, j} is calculated by the adder 27, the bit position p of data and j which is the number of the L2 layer neuron are fixed, and the number of the L1 layer is fixed. Calculate the sum of i and input terminal number q. For this purpose, data input from the terminals P0 to P6 in the L2 layer is temporarily stored in the memory 24A or the memory 24B and used for processing in the L2 layer from the time when the first round (round 0) is completed.
Here, the round is a unit of a series of processing for storing each piece of data (1 [bit] data) of neurons 0 to 255 of the L1 layer in the memory 24A or 24B.

  Next, the data flow will be described. FIG. 7 is a timing chart for explaining the operation of the circuit shown in FIG. In FIG. 7A, the uppermost stage is a clock CLK0 operating at 64 [kHz], which is turned on and off 256 times within a round of 4 [ms].

The second stage is a signal x _{i, k} (i is an integer from 0 to 255 and represents the number of a neuron in the L1 layer _{. K} is an integer and represents a round number) output to the output terminal P0. Yes, it represents the output signal of the i-th neuron in round k. For example, in the clock number 2 of round 0, the signal output from the terminal P0 is x _2,0 .

  The third row represents data stored in the memory 24A. “Valid” indicates that 1,792 valid values are arranged in the memory 24A. That is, the data is input from the input / output force terminals P0 to P6 and written in the memory 24A from the even-numbered first CLK0 to the first CLK0 in the next round being turned on. .

  The fourth row represents data stored in the memory 24B. “Valid” indicates that 1,792 valid values are arranged in the memory 24B. That is, the data is input from the input / output force terminals P0 to P6 and written in the memory 24B from the odd first CLK0 in the round until the first CLK0 in the next round is turned on. .

  In the timing chart of FIG. 7A, in round 0, the pulse train modulation circuit 22 controls to output LSB of 15-bit data shown in FIG. 6, that is, bit 0. The pulse train modulation circuit 22 outputs the LSB from the output terminal P0 to an adjacent cell and also outputs it to the memory 24A of the cell to which the pulse train modulation circuit 22 belongs.

  In this embodiment, in round 0, the pulse train modulation circuit 22 outputs LSB of 15-bit data obtained by converting the data of each neuron in the L1 layer at the rising edge of every CLK0.

  The adjacent cell memory 24A receives the data output from the terminal P0. In the memory 24A of the own cell, since the cell arrangement is symmetrical, the data output from the pulse train modulation circuit 22 of the adjacent cell is received from the input terminals P1 to P6. Here, the output data of the pulse train modulation circuit 22 of the own cell and the data input from the terminals P1 to P6 are combined into 7-bit data, and the memory 24A stores the 7-bit data at address 0.

  In the timing chart of FIG. 7B, the time width of the first clock of CLK0 in round 1 is expanded. In FIG. 7B, the top row is the clock CLK1 operating at 114.7 [MHz], and is turned on 1,792 times during 15.6 [μs] (= 4 [ms] ÷ 256). Turn off.

The second stage is a count-up signal input to the terminal 42A. Turns on and off 256 times during 15.6 [μs].
The third level is data Q-23A output from the counter 23A. Each time the count signal input to the terminal 42A rises, it increases by one.

The fourth level is signals a ′ _{i, p, q} output from the memory 24A or the memory 24B.

The fifth row shows synaptic connection weights w ′ _{i, q, j} output from the memory 25.

The sixth stage is the output of the adder 27. Σy _{i, q} is the sum of y _{i, q} with respect to i and q. Here, y _{i, q} is the product of a ′ _{i, p, q} and w ′ _{i, q, j} output at the clock immediately before a certain CLK1. Since p and j are constant during the total calculation for the neuron 22 _{j in} any L2 layer, the subscript p and the subscript j are not shown in order to make the timing chart easier to see.

The adder 27 receives the _{y i, q} of the AND gate 26 is outputted, _y was calculated immediately before the clock _i, the partial sum of _q, and adds the _{y i, q.} Accordingly, when CLK1 is turned on 1,792 times, the adder 27 calculates a sum Y _j of y _{i, q} that is input to the j-th neuron of the L2 layer with respect to i and q. Here, the display of the subscript p is omitted.
The seventh row represents the signal of the terminal 46 output from the latch 30. “Valid” represents a valid value. The signal at terminal 46 represents the output of the jth neuron in the L2 layer. The latch 30 outputs the output of the j-th neuron in the L2 layer to the terminal 46 for 15.6 [μs].

When the signal input to the terminal 41 and the signal input to the terminal 42A rise and the count values of the 8-bit counter 20 and the 8-bit counter 23A become u (u is an integer), the memory 21 reads the data at address u. However, it is output to the pulse train modulation circuit 22.
The pulse train modulation circuit 22 receives the data output from the memory 21 and converts it into 15-bit data.

Then, the pulse train modulation circuit 22 outputs only the LSB of the 15-bit data to the memory 24A and also outputs it to the memory 24A of the adjacent cell via the terminal P0. Then, the memory 24A stores 7-bit data in which the data output from the terminal P0 and the data input from the terminals P1 to P6 are combined at the u address.
In this way, the round 0 ends when the data transfer is performed until the counter 20 and the counter 23A exceed 255 and return to 0.

  Since 256 (256 bits) data is transferred from the L1 layer to the L2 layer in 4 [ms], a series of processing speeds is 64 [kHz]. In the next round 1, the pulse train modulation circuit 22 outputs 15 bits of data one bit higher than the least significant bit to the memory 24B.

The memory 24B receives the data output from the pulse train modulation circuit 22 of its own cell and the data output from the pulse train modulation circuit 22 of the adjacent cell, and stores the data.
In this way, the memories 24A and 24B are used alternately each time the round is switched.

  When the pulse train modulation circuit 22 finishes transferring the most significant bit data of the 15-bit data to the memory 24A of the cell adjacent to the self-cell memory 24A in round 14, the processing of the data stored in the memory 21 is performed. End. Further, when the processing in the neural network is continued, new data is written into the memory 21 by an external circuit (not shown), or the memory 21 is made to have a double buffer structure in parallel with the processing in the neural network. Then, the next data is written by an external circuit. This is the end of the description of the operation of the L1 layer neuron.

Next, the operation of the L2 layer neuron will be described. In FIG. 7A, when round 0 is completed and 1,792 (= 256 [neuron] × 7 [cell]) a _i are arranged in the memory 24A, L2 from the rising edge of the first CLK0 in round 1 Processing in the neurons of the layer begins.

  On the L2 layer side, 1,792 product-sum operations must be performed for each neuron, so as shown in FIG. 7B, the speed is 1,792 times that of the L1 layer side, that is, 114.7 [ [MHz].

The memory 24A reads 7-bit data at 16.384 [MHz], which is 256 times 64 [kHz], and converts the 7-bit data into a parallel signal, thereby converting the 7-bit data by 114.7 [Mbps] into a 1-bit signal a. ' _{I, p, q} (4th stage in FIG. 7B). Along with this operation, the memory 25 reads the corresponding 8-bit synapse connection weight data w ′ _{i, q, j} at 114.7 [MHz] and outputs it to the AND gate 26 (FIG. 7B, the fifth stage). ).

When the input a ′ _{i, p, q} and w ′ _{i, q, j} are aligned, the AND gate 26 multiplies the inputs to obtain 8-bit y _{i, q} (= a ′ _{i, p, q} × w ′ _{i, q, j} ) is calculated. Here, since p and j are constant during the summation calculation for one neuron in the L2 layer, these notations are omitted. The AND gate 26 outputs the calculated y _{i, q} to the adder 27.

The adder 27 sequentially adds y _{i, q} to the partial sum calculated up to the previous CLK1, and calculates the next partial sum of y _{i, q} with respect to _{i and q at} the next rising edge of CLK1 ( FIG. 7B (6th stage). At the beginning of the summation calculation, 0 is input to the terminal 44 and the data input to one side of the adder 27 becomes 0, whereby the partial sum is initialized.

When the summation calculation is completed, the magnitude comparator 29 compares the summation _Yj with the threshold value θ, and sets the output to 1 if the summation _Yj is larger than the threshold value θ, and sets the output to 0 if it is smaller. This output is in the form of a pulse of 114.7 [MHz]. However, the output as it is is difficult to handle in subsequent processing.

Therefore, the latch 30 holds the data output from the magnitude comparator 29 according to the timing signal input from the terminal 45, and outputs it as a signal of 64 [Kbps].
For example, when the contents of the memory 25 are changed according to the Hebb's learning rule, the latch 30 is replaced with the memory, and the output data of the L2 layer is recorded in the memory.

Note that the memory 25 for storing the synaptic connection weights w _{i, j} stores a mixture of weight information for the neurons in the L1 layer of the own cell and weight information for the neurons of the adjacent cells. If this is inconvenient, the memory 25 can be divided into seven for each of the terminals P0 to P6. If seven AND gates 26, adders 27, and AND gates 28 are prepared for each of the seven circuits, not only the contents of the memory 25 are easy to handle, but also the calculation speed of the adder 27 is 16.4 of 1/7. [MHz] can be set.

  In this embodiment, a so-called pulse neural network in which information is transmitted from the L1 layer to the L2 layer by a pulse train has been described. However, the present invention is not limited to this, and a neural network that transmits information by a plurality of bits is similarly used. Applicable. An example of the application is shown in FIG.

FIG. 8 is a circuit diagram simulating a neuron group that uses a circuit unit according to an embodiment of the present invention in a neural network in which a signal is represented by a plurality of bits. The circuit of FIG. 8 is a circuit in which the signals a ′ _{i, q} transmitted from the L1 layer to the L2 layer are changed from 1 bit to 4 bits. Along with _this, in the circuit of Figure 8, by replacing the multiplier 50 and the AND gate 26 of FIG. 5, it is increased from the terminal P0~P6 the wiring to the memory 24A or the memory 24B to 28 present the seven, memory 24A or the memory The number of wires from 24B to the multiplier 50 is increased from one to four.

Only the differences of the circuit of FIG. 8 from the circuit of FIG. 5 will be described below.
In this embodiment, since the pulse train modulation circuit is unnecessary, the data read from the memory 21 is output as it is to the memory 24A, the memory 24B, and the output terminal P0.

The memory 24A and the memory 24B combine the data input from the 4-bit width terminal P0 and the input terminals P1 to P6 through 28 signal lines into 28-bit width data, and sequentially store them. Accordingly, the storage capacities of the memory 24A and the memory 24B are each required to be four times (28 [bit] × 256).
The multiplier 50 multiplies the a ′ _{i, q} read by the memory 24 A or the memory 24 B and the weight w ′ _{i, q, j} of the synapse connection read by the memory 25, and outputs the result to the adder 27. Thus, the present invention can be applied to other than the pulse neural network.

  In the case of the above example, the information output from the terminal P0 is sent through four low-speed signal lines of 64 [kbps], and the input terminals of P1 to P6 that receive it have a 4-bit width. In general, adding an LSI terminal or a wiring on a PCB increases costs, and this is useless.

  Therefore, if a parallel-to-parallel converter is inserted in the output section of the memory 21 to form a single signal line with a data transmission rate of 4 times, adjacent cells can be connected by a single signal line. On the side of receiving the parallel-converted signal, it can be directly written into the memory 24A or the memory 24B as a 7-bit signal at a speed four times, or it can be converted again and again as 28-bit width data. You can also write.

In the embodiments of the present invention shown in FIGS. 5 and 8, the virtual neuron in the L2 layer has been described as ignoring the processing result in the previous round, but processing may be performed in consideration of the time history.
FIG. 9 is a circuit diagram for realizing a neuron that considers the time history of the summation calculation result. For example, the sum calculated by the adder 27 is appropriately attenuated by a circuit obtained by replacing the circuit from the multiplier 50 to the magnitude comparator 29 in the circuit of FIG. 8 with the circuit of FIG. It becomes the initial value of.

  The circuit considering the time history of the sum calculation result shown in FIG. 9 includes a multiplier 50, an adder 27, a magnitude comparator 29, a multiplier 52, a memory 53, and data in the memory 53 at the beginning of cumulative addition. It is comprised using the selector 51 for adding. The multiplier 50 and the magnitude comparator 29 are the same as those in FIG.

In the memory 53, 0 is initially stored in all addresses by a circuit (not shown). At the beginning of the summation calculation of the j-th neuron in the L2 layer, the memory 53 reads the data stored after the summation calculation result stored in the j-th address is attenuated, and the selector 51 Send to A input.
At the beginning of the sum calculation of the j-th neuron in the L2 layer, the selector 51 outputs a signal received from the terminal 48 as 0 and the data received from the memory 53 to the terminal Y. Thereafter, the signal input from the terminal 48 becomes 1, and the partial sum output from the adder 27 is output to the terminal Y.
The adder 27 receives, via the selector 51, the attenuated sum calculation result in the previous round stored in the memory 53 via the selector 51 at the beginning of the sum calculation of the Lth layer jth neuron, and receives another input. To calculate the partial sum of a ′ _0,0 × w ′ _{0,0, j} . Thereafter, the selector 51 outputs the partial sum calculated by the adder 27, so that a ′ _{i, q} × w ′ _{i, q, j} are sequentially accumulated and added. The multiplier 52 adds the terminal sum to the sum calculated by the adder 27. Multiply by a register (not shown) input from 49 or a signal giving an attenuation factor after a certain time supplied from the outside, and the multiplication result is output to the memory 53. However, when the output of the magnitude comparator 29 becomes 1, that is, since the neuron has fired, in order to start the next summation calculation from 0, the multiplier 52 sets its output to 0 by a circuit (not shown). Is sent to the memory 53.

  The memory 53 receives the attenuated sum calculation result output from the multiplier 52 and writes the data at address j.

  The selector 51 switches between the signal A input from the memory 53 and the signal input from the adder 27 according to the signal S input to the terminal 48, and outputs the switched signal from the terminal Y to the adder 27.

  If the circuit considering the time history of the output shown in FIG. 9 is used, data obtained by multiplying the sum calculated in the previous round by the attenuation factor can be input to one input terminal of the adder 27. Thereby, it is possible to perform processing in consideration of the time history.

In the embodiment of FIG. 5, in the L2 layer, the data input from the terminals P0 to P6 is temporarily stored in the memory 24A or the memory 24B and used for processing in the L2 layer from the time when the first round is completed. It was. This is because when calculating Σ (a ′ _{i, p, q} × w ′ _{i, q, j} ) for the j-th neuron in the L2 layer, the number j of the L2 layer is fixed and j in the L1 layer is fixed. This is because the sum for the number i and the terminal number q is calculated at once. _{Incidentally, a'i, p, q} are seven _{(a'i, p, 0 ~a'} i, p, 6) a' every arriving _{i, p, q × w'i} , q, all _j J is added to the partial sum for each neuron of the L2 layer, which is calculated up to the time when the previous a ′ _{i−1, p, q} arrives, and a new partial sum is obtained. It is also possible to calculate the total sum by a procedure in which it is once stored in the memory, and when the next a ′ _{i + 1, p, q} arrives, the partial sum is read from the memory and used for calculating a new partial sum. .

  An example of the circuit is shown in FIG. FIG. 10 is another circuit diagram simulating a neuron group using a circuit unit according to an embodiment of the present invention in a pulse neural network. Compared with the circuit of FIG. 5, instead of the memory 24 </ b> A and the memory 24 </ b> B, a parallel-to-parallel conversion circuit 54 is inserted between the terminals P <b> 0 to P <b> 6 and the AND gate 26. A memory 55 is inserted. Only differences from the circuit of FIG. 5 will be described below.

The parallel-to-serial conversion circuit 54 performs parallel-to-serial conversion on the 7-bit data input from the terminals P0 to P6 and outputs the data to the AND gate 26 as 1-bit signals a ′ _{i, p, and q} .
The adder 27 receives the data output from the AND gate 26 and the data output from the selector 51, adds the two data, and outputs the added data to the selector 51, the memory 55, and the magnitude comparator 29.

The memory 55 receives the partial sum during the sum calculation of the j-th neuron output from the adder 27 and temporarily stores it in the j-th address. Further, the memory 55 reads out data according to a signal input to the terminal A from a circuit (not shown) and outputs the data to the selector 51.
When the input terminal 48 is 0, the selector 51 sends 0 to the adder 27. When the input terminal 48 is 1, the selector 51 sends the data output from the memory 55 to the adder 27. The data output from the adder 27 is sent to the adder 27.

Next, the process flow of the circuit of FIG. 10 will be described. First, when seven pieces of data a ′ _{0,0, q} (q is an integer of 0 to 6) of the zeroth neuron arrive from the L1 layer, the memory 25 receives the signal from the terminal P0 of the neuron number 0 of the L2 layer. The corresponding synapse connection weight data w ′ _0,0,0 is sequentially read out from the synapse connection weight data w ′ _0,6,0 corresponding to the signal from the terminal P6.

Next, the AND gate 26 multiplies the a ′ _{0,0, q} output from the parallel-to-serial converter 54 by the weight data w ′ _{0, q, 0} output from the memory 25 and outputs the result to the adder 27. Is repeated from q to 0-6.
The input terminal 48 of the selector 51 becomes 0 when q is 0, that is, when a ′ _0,0,0 × w ′ _0,0,0 enters the adder 27, and sets the initial value of the sum calculation to 0. . Thereafter, q becomes 2 at the timing of 1 to 6, and the output a ′ _{0,0, q} × w ′ _{0, q, 0} of the adder 27 is accumulated.
When the adder 27 performs accumulation up to a ′ _0,0,6 × w ′ _0,6,0 , the memory 55 stores the calculation result (partial sum) at address 0.
Similarly, the same calculation is performed up to the neuron number 255 of the L2 layer, and the process is repeated until the memory 55 stores the partial sum at address 255.

Next, when seven pieces of data a ′ _{1, 0, q} of the first neuron arrive from the L1 layer, the same calculation is performed, but at the timing when the terminal 48 of the selector 51 becomes 0 in the previous processing, the terminal 48 The signal going into is 1. At the same time, the memory 55 reads the stored partial sum and sends it to the selector 51. Then, the data (a ′ _{1, 0, q} × w ′) newly calculated according to the output from the first neuron of the L1 layer is added to the partial sum calculated according to the output from the 0th neuron of the L1 layer. _{1, q, j} ) is added, and the result is stored at address j of the memory 55.
Thereafter, the same operation is repeated up to the 255th neuron in the L1 layer.

  By processing in this way, when the 255th data arrives from the L1 layer, all the processing in the L2 layer is completed. Note that the parallel-to-serial conversion circuit 54 can be omitted if seven circuits such as the AND gate 26 and the adder 27 in the subsequent stage are prepared. The memory 55 can be shared with the memory 53 in the embodiment of FIG. The partial sum up to the 255th data in the L1 layer is the sum. When the sum is calculated, the comparator 29 compares the sum with the threshold value θ and outputs the comparison result to the latch 30. The latch 30 latches the comparison result with a timing signal supplied from a circuit (not shown) to the terminal 45, and outputs the latched signal from the terminal 46. Therefore, the output signal of the terminal 46, which is the output of the L2 layer, comes out in a burst manner at a speed 256 times that of the output signal of the L1 layer. The latch 30 is replaced with a 1 [bit] × 256 memory, the data of the large / small comparator 29 is temporarily stored in the memory, the data is read from the memory at the same speed as the output data of the L1 layer, and is output. Output data can also be output from the L2 layer at the same speed as the layer.

  As described above, in another embodiment of the present invention, the memories 24A and 24B for temporarily storing data from the L1 layer can be omitted, but the memory 55 for storing data being calculated is required. Since the adder 27 does not overflow, 16 bits or more are necessary, so the capacity of the memory 55 is 16 [bit] × 256.

  On the other hand, the capacities of the memories 24A and 24B are 7 [bit] × 256, respectively. The number of words in the memories 24A and 24B is proportional to the number of neurons in the L1 layer, and the number of words in the memory 55 is proportional to the number of neurons in the L2 layer. Depending on the number of neurons in the L1 layer and the L2 layer, it is possible to select either the embodiment of FIG. 5 or the embodiment of FIG.

<Effect of Example 1>
According to the method of the first embodiment, the output data output by the L1 layer neuron of a certain cell is shared by all the neurons of the L2 layer to which the output signal is supplied. There is no need to identify. Therefore, it is not necessary to send the destination address information required by the AER method together with the output data. In addition, data is transferred synchronously between the L1 layer and the L2 layer, and the L2 layer identifies the number of the neuron in the L1 layer from the time when the data is received, so the source address information sent as Payload by the AER method is also unnecessary become. If 256 [bit] data is sent from the L1 layer to the L2 layer at 4 [ms], the data transfer rate is very low at 256 [bit] ÷ 4 [ms] = 64 [Kbps]. Easy.

  Further, a memory for storing destination address information necessary for the L1 layer is also unnecessary. As is clear from FIG. 2 (b), the wiring between cells is a local wiring between adjacent cells. Even if a new cell is added to the outer periphery where no cell is arranged, the existing wiring No effect at all. That is, cells can be added as necessary, and wiring is performed only between adjacent cells. Therefore, even if the number of cells is increased, wiring does not increase between existing cells. Therefore, the communication speed between cells and the operation speed of each neuron in the cell are kept constant.

  As described above, when the technology of this embodiment is used, a maximum of 1 per neuron in the L2 layer can be obtained by connecting the L1 layer and the L2 layer per cell with one low-speed local signal line. , 792 neural networks having synaptic connections can be easily constructed. In order to increase or decrease the maximum number of synaptic connections per neuron, the number of neurons existing in each layer of the cell may be increased or decreased.

  For example, if 1,024 neurons are included in each of the L1 layer and the L2 layer of one cell, a maximum of 7,168 (= 1, 024 × 7) synaptic connections can be made per neuron in the L2 layer. However, since the data transfer rate required for the signal connecting the L1 layer and the L2 layer is proportional to the number of neurons included in the L1 layer, the data transfer rate is 256 [Kbps], which is four times the memory 25 for storing the weight of the synapse connection. Is proportional to both the number of neurons included in the L1 layer and the number of neurons included in the L2 layer, so 16 times 7 [MB] (= 8 [bit] × 1,024 × 7 × 1,024) become.

  In addition, the memory 25, the adder 27, etc. must be operated at 16 times. However, as described above, by dividing the memory and preparing a plurality of adders 27, etc., the operation speed of the circuit can be lowered. Can do.

  In this embodiment, one data transfer time (or calculation time) is 4 [ms], but the present invention is not limited to this, and an arbitrary time can be set. Since the data transfer speed on the signal line connecting the cells is low, the entire system can be further increased by increasing the speed.

  The neurons are arranged in a virtual plane, the plane is divided into regular hexagons (cells), and the number of neurons entering each cell is, for example, 256 (input layer L1) +256 (intermediate layer L2). The output of the L1 layer of a cell makes a synaptic connection only with the L2 layer neuron of that cell and the six cells adjacent to that cell, and with all the neurons of the L2 layer.

  By determining in this way, 1-bit data may be transferred to the L2 layer from one neuron in the L1 layer. In the L2 layer, two 7 [bit] × 256 memories are prepared and stored in this memory in synchronization with the data output from the neurons in the L1 layer. With this architecture, it is not necessary to send address information required in the conventional AER technology, and only 256-bit data needs to be transmitted from 256 neurons in the L1 layer.

  To construct a neural network with 100 million neurons, for example, prepare a four-layer neural network of L1 layer (512), L2 layer (512), L3 layer (512), and L4 (64). If the L1 layer is not counted in the number of neurons, there are 1,088 neurons per cell, so it is sufficient to connect approximately 90,000 cells. In this case, the signal lines connecting the cells time-division-multiplex the output data from the L1, L2, and L3 layers, and transfer 1,536 (= 512 [bit] × 3) bit data.

  As is clear from the embodiment of FIG. 5, the output signal of the L2 layer is the same data rate as the output signal of the L1 layer, so that time division multiplexing is easy. When this is performed at 4 [ms], the data transfer rate is set to 384 [Kbps]. That is, in this case as well, cells can be connected with only one low-speed signal line, and the virtual neuron circuit itself can be realized with a small number of adders and memories, so that a large-scale neural network that operates in parallel in real time can be realized. Can do.

  In the technology of the present invention, 0 is stored in several percent to several tens of percent of memory for storing synaptic connection weight data, and the memory is used extensively. The part can be slowed down. Up to now, with the progress of semiconductor process technology, if the width of a transistor is constant, the current drive capability has increased in inverse proportion to the reduction in gate length. Then, the switching speed of the transistor increased substantially in proportion to the increase of the current driving capability of the transistor, and as a result, the operation speed of the circuit also improved.

  However, recently, the wiring capacity is relatively larger than the current driving capability of the transistor, and it is difficult to improve the operation speed of the circuit even if the process technology advances. On the other hand, since the transistor size is almost inversely proportional to the square of the gate length, an increase in the amount of memory that can be used in the future can be expected. Thus, we believe that the architecture of the present invention can benefit from future semiconductor advances.

  Patent No. 3586464 describes a method of concentrically connecting a certain cell to a neighboring cell. Since the cell in this patent corresponds to one neuron, It is completely different from the cell described. In this patent, since neurons are directly connected, it is difficult to construct a large-scale neural network.

<Problem of Embodiment 2 of Circuit Unit>
Next, a circuit unit (cell) that realizes a mixture of excitatory and inhibitory neuron groups will be described for a second embodiment of the circuit unit of the present invention. In the circuit of the first embodiment shown in FIG. 5, the synaptic connection weight values w ′ _{i, q, j} stored in the memory 25 are converted into signals a ′ _{i, p, q} from the L1 layer by the AND gate 26. The result of multiplication is a ′ _{i, p, q} × w ′ _{i, q, j} , which is input to the adder 27. In order to realize an inhibitory neuron with this conventional technique, a method of giving code information to the values w ′ _{i, q, j} stored in the weight data memory 25 is general.

  However, this method has the disadvantage that the storage capacity required for the memory 25 increases and the manufacturing cost increases. For example, if the memory 25 has a bit width of 8 and is limited to a positive or zero number representing the weight of the synaptic connection with the excitatory neuron, the 8-bit data can be interpreted as 0 to 255, so the data resolution is 1/255. become.

  On the other hand, if the weight information has a positive / negative value and the negative number is represented by 2's complement, the 8-bit data is interpreted as -128 to 127. Therefore, the value of positive or 0 indicating the weight of synaptic connection with the excitatory neurons is 0 to 127, and the resolution is halved. If the bit width of the memory 25 is kept at 8, the manufacturing cost does not increase, but the resolution of the synaptic connection weight is halved, and the calculation accuracy and storage accuracy as a neural network are lowered.

  Therefore, in order to maintain the resolution of the synaptic connection weight data at 1/255, the bit width of the memory 25 must be set to 9, and 9 [bit] × 256 × 7 × 256 is required. Large storage capacity is increased by 458,752 bits (12.5%).

  The circuit of the second embodiment provides a method for realizing an inhibitory neuron and a power neuron while suppressing a decrease in calculation accuracy and storage accuracy of a neural network and suppressing an increase in manufacturing cost as much as possible. Here, the power neuron is a neuron that has a large influence on the next-stage neuron, which is twice or four times as large as that of a normal neuron.

  Whether a certain neuron is excitable or inhibitory is determined when the structure of the neural network is determined. Whether a certain neuron is a power neuron or a normal neuron is determined when the structure of the neural network is determined. These do not change with neural network learning or self-organization. By utilizing this fact, an increase in the number of transistors required to realize an inhibitory neuron or a power neuron is suppressed.

<Description of Example 2 of Circuit Unit>
FIG. 11 is a circuit diagram of a circuit unit in which an excitatory neuron group and an inhibitory neuron group are mixed according to the second embodiment of the present invention. The same number is assigned to the same part as the circuit simulating only the excitatory neuron of FIG. Compared with the circuit of FIG. 5, the circuit of FIG. 11 has an 8-bit counter 23 </ b> C and a sign storage 33 added to the circuit of FIG. 5, and the adder 27 of FIG.

The code storage 33 stores code information (1 [bit] × 256 data) corresponding to each neuron of the L1 layer. All synaptic connections made by certain inhibitory neurons in the L1 layer on neurons in the L2 layer become inhibitory synaptic connections. If one inhibitory neuron in the L1 layer forms an inhibitory synaptic connection with 1,792 neurons in the L2 layer, and if each weight data has a sign bit, 1,792 bits of data are required. Become. On the other hand, if information indicating that the neuron in the L1 layer is inhibitory is stored, one bit may be stored per neuron. Based on the data output from the counter 23C, the code storage 33 outputs to the adder / subtractor 32 the code information of the neuron at the address corresponding to the data.
The adder / subtractor 32 receives the neuron code information output from the code storage 33. When the sign information is 0, the L1 layer neuron is regarded as an excitatory neuron and operates as an adder, adds the data received from the AND gate 26 and the data received from the AND gate 28, and adds the data after the addition. The data is output to the AND gate 28 and the magnitude comparator 29.

  When the sign information is 1, it is regarded as an inhibitory neuron, processed as a subtractor, subtracts the data received from the AND gate 26 from the data received from the AND gate 28, and sets the value after subtraction as the AND gate 28. Output to the large / small comparator 29.

Subsequently, the operation of the circuit of FIG. 11 will be described. The neurons in the L1 layer are virtually realized by combining 256 neurons, and excitability or inhibition is determined for each neuron number. Therefore, before the processing in the neural network starts, s _{i is set} to 0 in the case of excitability according to the neuron number i, s _{i is set} to 1 in the case of inhibition, and the code storage unit is previously stored by an arbitrary method (not shown). Write to 33. Since the neurons of all cells have the same structure, it is not necessary to separately have information on the L1 layer of adjacent cells.

The input data of the L1 layer neurons is stored in the memory 21 and the synaptic connection weight data is stored in advance in the memory 25 by any method not shown. The counter 20, the counter 23A, the counter 23B, and the counter 23C are set to 0 in advance by a reset signal (not shown). Note that the absolute value | w ′ _{i, q, j} | of the weight data is stored in the memory 25.

  When the calculation starts, the counter 20 first outputs a count value 0 to the memory 21. Next, when receiving 0 data from the counter 20, the memory 21 reads 4-bit data from address 0 and outputs it to the pulse train modulation circuit 22.

  The pulse train modulation circuit 22 receives 4-bit data from the memory 21, converts the 4-bit data into 15-bit data, and sequentially converts the 15-bit data from the LSB in each round via the output terminal P0 to the memory 24A or the memory 24B. Output to.

  In the first round 0, only the LSB of the data shown in FIG. 6 is transferred. This data is output to the outside from the output terminal P0 and simultaneously sent to the memory 24A. Data output from terminal P0 is received by the adjacent cell. Since the circuit is symmetrical, its own cell receives data output by the adjacent cells at the input terminals P1 to P6.

  Therefore, the output data of the pulse train modulation circuit 22 and the data from the terminals P1 to P6 are bundled into 7-bit data, and the data is stored in the address 0 of the memory 24A. Thereafter, when the signal input to the terminal 41 and the signal input to the terminal 42A become active and the counter 20 and the counter 23A become 1, the memory 21 reads the data at the first address and outputs it to the pulse train modulation circuit 22.

  The pulse train modulation circuit 22 receives data at address 1 from the memory 21 and converts the data into 15-bit data. Then, the pulse train modulation circuit 22 outputs LSB out of the 15-bit data to the memory 24A. Along with this operation, the LSB is output to the memory 24A of the adjacent cell via the output terminal P0.

  Then, the memory 24A bundles the data from the pulse train modulation circuit 22 and the data from the terminals P1 to P6 and stores them as 7-bit data in the first address of the memory 24A. In this way, when data transfer is performed until the count values of the counter 20 and the counter 23A exceed 255 and return to 0, round 0 ends.

  Since 256 (256 [bit]) data is transferred from the L1 layer to the L2 layer in 4 [ms], a series of processing speeds is 64 [kHz]. In the next round 1, the pulse train modulation circuit 22 transmits bit 1 data, and the transferred data is written in the memory 24B. In this way, processing is performed using the memory 24A and the memory 24B alternately. When the transfer of bit 14 ends in round 14, the processing of the data stored in memory 21 ends.

  Further, when the processing in the neural network is continued, new data is written into the memory 21 by an external circuit (not shown), or the memory 21 is made to have a double buffer structure in parallel with the processing in the neural network. The external circuit writes the next data. This is the end of the description of the operation of the L1 layer neuron.

Next, the operation of the L2 layer neuron will be described. When round 0 ends and 1,792 a'i _{, p, q} are prepared in the memory 24A, the calculation starts in the L2 layer. On the L2 layer side, 1,792 product-sum operations must be performed for each neuron, so processing is performed at a speed 1,792 times that of the L1 layer side, that is, 114.7 [MHz]. It is assumed that Σ (a ′ _{i, p, q} × w ′ _{i, q, j} ) is calculated in the j-th virtual neuron in the L2 layer. Here, Σ represents the sum of i and q.

The memory 24A reads out 7-bit data at 16.384 [MHz], which is 256 times 64 [kHz], and converts it into a parallel signal, thereby converting the 7-bit 114.7 [Mbps] 1-bit signal a ′ _{i, The} signals a ′ _{i, p, q} are output to the AND gate 26. At the same timing, the memory 25 reads the 8-bit weight data | w ′ _{i, q, j} | of the synapse connection at 114.7 [MHz] and outputs it to the AND gate 26.

The AND gate 26 receives the signals a ′ _{i, p, q} output from the memory 24A and the weight data | w ′ _{i, q, j} | output from the memory 25, and multiplies them to obtain 8-bit 0 or | w ′ _{i, q, j} | and outputs to the adder / subtractor 32.
Further, the code storage 33 reads a 1-bit code data code s _i at 16.384 [MHz] and outputs it to the adder / subtractor 32. s _i is commonly used for seven pieces of data | w ′ _{i, q, j} | whose i is the same and q is 0 to 6.

When the sign s _i is 0, the adder / subtractor 32 adds the a ′ _{i, p, q} × | w ′ _{i, q, j} | to the partial sum calculated so far (output of the AND gate 28). . On the other hand, when the code s _i is 1, the a ′ _{i, p, q} × | w ′ _{i, q, j} | is subtracted from the partial sum calculated so far. In this way, the sum of a ′ _{i, p, q} × w ′ _{i, q, j} for _{i and q} is calculated with _j fixed.

  At the beginning of the summation calculation, the signal input to the terminal 44 of the AND gate 28 becomes 0, and the data input to one side input terminal of the adder / subtractor 32 becomes 0. When 1,792 times of sum calculation for i and q are completed, the adder / subtractor 32 outputs the sum to the magnitude comparator 29.

  The magnitude comparator 29 receives the sum output from the adder / subtractor 32, compares the sum with the threshold θ, and sets the output to 1 if the sum is greater than the threshold θ, and sets the output to 0 if the sum is smaller. This output has a frequency of 114.7 [MHz] and is output in the form of a pulse having a width of 1 clock every 256 clocks. Therefore, a 64 [kHz] rising pulse is applied to the terminal 45 of the latch 30, the comparison result output from the magnitude comparator 29 is held in the latch 30, and is output to the terminal 46 as a 64 [Kbps] signal.

  As described above, when the second embodiment of the present invention is used, a neural network in which excitatory neurons and inhibitory neurons are mixed can be realized without increasing the capacity of the memory 25 for storing synaptic connection weight data. . However, a new memory 33 for storing code information of the neurons in the L1 layer is required.

  Since the memory 33 is 256 (= 1 [bit] × 256) bits, the capacity of the memory to be increased is 1/1 and 792, compared to the case where the synapse connection weight including the code information is stored in the memory 25. Further, the adder 27 needs to be an adder / subtractor 32, but what is required here is an 8-bit exclusive OR circuit, and the number of transistors to be increased is very small compared to the number of transistors required for the entire neural network. It is.

    FIG. 12A shows a circuit diagram of a circuit unit which is a modification 1 of the second embodiment of the present invention. The same elements as those in the second embodiment shown in the circuit of FIG. Compared with the circuit of FIG. 11, the circuit of FIG. 12 is obtained by inserting a magnitude comparator 34 instead of the code storage 33.

  The magnitude comparator 34 receives the neuron number i (8 bits) of the L1 layer output from the counter 23C, and receives a value α (8 bits) supplied from a register (not shown) or from the outside at a terminal 47b. The magnitude comparator 34 compares i with α, and when i is smaller than α, the output s is set to 1 and output to the adder / subtractor 32. When i is greater than or equal to α, the output s is set to 0. To the adder / subtractor 32. As a result, when the neuron number i is smaller than α, the neuron assigned with the neuron number becomes an inhibitory neuron.

  In the second embodiment of the present invention, any number of neurons in the L1 layer can be set as inhibitory neurons. However, since the neuron number is virtual, it has no meaning in itself. Therefore, even if all the neurons in the L1 layer whose number is smaller than α are inhibitory neurons, there is no inconvenience as the operation of the neural network. The output signal s of the magnitude comparator 34 becomes 1 when the value of the counter 23C, that is, the neuron number of the L1 layer is smaller than α, and the adder / subtractor 32 performs subtraction. A detailed description of the operation of the circuit is omitted.

  FIG. 12B shows a part of a circuit of a circuit unit that is a second modification of the second embodiment of the present invention. In the circuit of FIG. 12B, an AND gate 34B is inserted instead of the magnitude comparator 34 of FIG. In this example, the AND gate 34B receives the least significant bit (0th bit) of the 8-bit data output from the counter 23C and the bit (first bit) left one from the least significant bit, and takes the AND. The result is output to the adder / subtractor 32 as a code s. Therefore, the neurons with the numbers 3, 7, 11, and so on become inhibitory.

The AND gate 34B can have 3 inputs or 4 inputs as required, and can change the bit position of AND. Alternatively, when making half of the L1 layer suppressive, the AND gate 34B can be omitted, and any one bit of the output of the counter 23 can be set as the code s.
The unused bits of the counter 23C need not be implemented. Specifically, in the example shown in FIG. 12B, since bits 2 to 7 of the 8-bit counter 23C are not used, it is not necessary to mount them, and it is sufficient to mount them as a 2-bit counter.

  In the second embodiment of the present invention, the first modification of the second embodiment, and the second modification of the second embodiment, a so-called pulse neural network in which information is transmitted from the L1 layer to the L2 layer by a pulse train has been described. The present invention is not limited to this, and the present invention can be similarly applied to a neural network that transmits information by a plurality of bits.

  FIG. 13 shows an example of a circuit that realizes an inhibitory neuron group other than the pulse neural network. The 4-bit data of each neuron in the L1 layer is stored in the 4 [bit] × 256 memory 21, and is sequentially read from the memory 21 and output from the output terminal P0 having a 4-bit width. Along with this operation, the data input from the input terminals P1 to P6 having a 4-bit width is combined with the 28-bit width data and stored in the memory 24A or the memory 24B of 28 [bits] × 256.

The a ′ _{i, q} read from the memory 24A or the memory 24B and | w ′ _{i, q, j} | read from the synaptic connection weight memory 25 are multiplied by the multiplier 50, and the multiplication result is added to the adder / subtractor 32. To accumulate. Thus, the present invention can be applied to other than the pulse neural network.

<Effect of Embodiment 2 of Circuit Unit>
In the prior art, regardless of excitability or inhibition, all the synaptic connection weight information for receiving signals from neurons is stored in a memory for storing synaptic connection weight data. Since the output of one neuron creates 1,000 to 10,000 synapse connections, and the weights of these synapse connections are basically different, a memory for storing 1,000 to 10,000 weight information is provided. is necessary.

  However, since all axons coming out of excitatory neurons make excitatory synaptic connections, and all axons coming out of inhibitory neurons make inhibitory synaptic connections, the sign of 1,000 to 10,000 weight information Are all the same. Therefore, by dividing the synapse connection weight information into “code” and “absolute value”, the capacity of the memory for storing the code information can be greatly reduced. In the second embodiment of the present invention, the capacity of the memory for storing the code information is reduced to 1/1, 792 based on this idea.

  In the present invention, neurons are implemented as virtual neurons. Therefore, the number of individual neurons has no physical meaning. Therefore, it is possible to determine the code information of synaptic connections using only information indicating what percentage of the entire neural network is inhibitory neurons. In the first modification of the second embodiment of the present invention and the second modification of the second embodiment, the memory itself for storing the code information can be omitted based on this idea. As a result, the circuit area can be reduced.

<Problems Specific to Circuit Unit Example 3>
Next, consider a case where a specific neuron (referred to as a power neuron) in the L1 layer gives, for example, twice as much influence to a neuron in the L2 layer as compared to a normal neuron. In other words, the weight of the synaptic connection that the normal neurons in the L1 layer make with the neurons in the L2 layer is 0 to 255, but the synaptic connection that the power neurons in the L1 layer make with the neurons in the L2 layer The weight can be from 0 to 511. A method of simply realizing this is to set the bit width of the synaptic connection weight data memory 25 to 9 and limit the maximum value of the weight to 255 in the synaptic connection created by a normal neuron.

  However, as in the case of the inhibitory neuron, the necessary memory capacity increases and the manufacturing cost of the neural network increases. Since about 10% of the number of power neurons is sufficient, it is inconvenient for the entire weight memory for synaptic connections to enlarge. On the contrary, the bit width of the memory 25 can be kept at 8 bits and the weight of the synapse connection for the power neuron can be set to 0 to 255. However, the normal neuron weight data becomes 0 to 127, and as a neural network, Calculation accuracy and storage accuracy will be reduced.

<Description of Embodiment 3 of Circuit Unit>
FIG. 14 is a circuit diagram of a circuit unit simulating a power neuron group according to the third embodiment of the present invention. The same elements as those in FIG. 5 are given the same numbers. Compared to the circuit simulating only the normal neuron group in FIG. 5, an 8-bit counter 23C, a memory 35, and a 1-bit left shifter 36 are added in the circuit in FIG. In the third embodiment, a 1-bit left shifter 36 is used as an arithmetic circuit for calculating a value obtained by multiplying an input signal by a constant. The arithmetic circuit is not limited to the 1-bit left shifter 36, but may be any circuit that multiplies the input signal by a constant and outputs it.

The counter 23C generates a neuron number i (8-bit data) of the L1 layer and outputs it to the memory 35.
The memory 35 stores shift information (1 [bit] × 256) for each neuron in the L1 layer. The memory 35 receives the neuron number i of the L1 layer output from the counter 23C, reads the shift data sft _i (1-bit data) from the address i, and outputs it to the 1-bit left shifter 36.

The 1-bit left shifter 36 receives the data output from the AND gate 26 and the shift data sft _i output from the memory 35. If the shift data is 0, the 1-bit left shifter 36 outputs the data output from the AND gate 26 to the adder 27 as it is. The 1-bit left shifter 36 shifts the data output from the AND gate 26 1 bit to the left if the shift data is present, and outputs the shifted data to the adder 27.

When the calculation in the L2 layer starts, the memory 24A reads out 7-bit data at 16.384 [MHz], and converts it into a parallel signal, which is 7 times the 11-bit 1-bit signal a ′ _{i, p and q} are output to the AND gate 26. At the same time, the synaptic connection weight memory 25 reads the corresponding 8-bit weight data w ′ _{i, q, j} at 114.7 [MHz] and outputs it to the AND gate 26. The AND gate 26 multiplies the 1-bit signal a ′ _{i, p, q} by the 8-bit weight data w ′ _{i, q, j} to obtain 8-bit 0 or w ′ _{i, q, j} , Bit data is output to the left shifter 36.

Further, 1-bit shift data sft _i is read out from the memory 35 at 16.384 [MHz] and output to the left shifter 36. When the shift data sft _i is 1, the output data of the AND gate 26 that has entered the left shifter 36 is shifted left by one bit, that is, doubled. If the shift data sft _i is 0, the output data is left as it is. Is output. In this way, a neuron having twice the influence of a normal neuron can be realized. Since the circuit of each cell is the same, the shift data sft _i is common to a ′ _{i, p, 0 to} a ′ _{i, p, 6} .

  As described above, by using the third embodiment of the present invention, it is possible to produce a neural network in which power neurons and normal neurons are mixed without increasing the capacity of the memory 25 for storing synaptic connection weight data. The memory 35 for storing the shift information is newly required. Since this is 256 (= 1 [bit] × 256) bits, the memory size required is smaller than when the weight data memory 25 is 9 bits wide. Is 1 / 1,792. Further, the 8-bit counter 23C and the left shifter 36 are required, but the number of transistors increased by these is extremely small compared to the number of transistors necessary for the entire neural network.

  Here, since the power neuron has an influence twice as large as that of a normal neuron, the shift information is 1 bit, and the shifter is a 1-bit left shifter. However, for example, if the shift information is 2 bits and the shifter is a 2 bit left barrel shifter, it is possible to mix neurons having influences that are 1 ×, 2 ×, 4 ×, and 8 × the normal.

  FIG. 15 is a circuit diagram of a circuit unit which is a modification of the third embodiment of the present invention. FIG. 15A shows a circuit diagram of a circuit unit which is a first modification of the third embodiment of the present invention. The same elements as those in the circuit of the third embodiment shown in FIG. Compared with the circuit of FIG. 14, in the circuit of FIG. 15A, a size comparator 37 is inserted instead of the memory 35.

  The magnitude comparator 37 receives data i indicating the neuron number of the L1 layer output from the counter 23C and a value α supplied from a register (not shown) or from the outside. Further, the magnitude comparator 37 compares the data i with the α, and when i is smaller than α, sets the output sft to 1 and outputs the sft to the 1-bit left shifter 36.

  In the first modification of the third embodiment of the present invention, any number of neurons in the L1 layer can be set as the power neuron. However, since the neuron number is virtual, it has no meaning in itself. That is, even if all of the neurons in the L1 layer whose number is smaller than α are power neurons, there is no inconvenience as the operation of the neural network. The output sft of the magnitude comparator 37 becomes 1 when the value of the counter 23C, that is, the neuron number i is smaller than α. When 1 is input to the sft input, the left shifter 36 doubles the value of the data output by the AND gate 26 and outputs the doubled data to the adder 27. A detailed description of the operation of the circuit is omitted.

  FIG. 15B shows a part of a circuit of a circuit unit that is a second modification of the third embodiment of the present invention. In the circuit of FIG. 15B, an AND gate 37B is inserted instead of the size comparator 37 of FIG. In this example, the AND gate 37B takes AND of the 0th bit and the 1st bit of the output of the counter 23C, and outputs the value obtained by taking the AND to the 1-bit left shifter 36 as the shift data sft.

Therefore, the neurons with the numbers 3, 7, 11, and so on become the power neurons. The AND gate 37B can have 3 inputs or 4 inputs as required. Alternatively, when half of the L1 layer is suppressed, the AND gate may be omitted and any one bit of the output of the counter 23C may be set to the code sft.
The unused bits of the counter 23C need not be implemented. Specifically, in the example shown in FIG. 12B, since bits 2 to 7 of the 8-bit counter 23C are not used, it is not necessary to mount them, and it is sufficient to mount them as a 2-bit counter.

<Effect of Embodiment 3 of Circuit Unit>
By storing information on whether or not it is a power neuron in a memory that stores weight data of synapse connections, it is possible to suppress an increase in the required memory amount. In the first modification of the third embodiment of the present invention, the capacity of the memory storing the power neuron information is reduced to 1/1, 792 in the case of storing in the synaptic connection weight memory based on this idea.

  Further, in the third embodiment, whether or not each neuron is a power neuron is set. However, if there is no problem even if only setting a ratio, the first modification of the third embodiment of the present invention, the implementation As shown in Modification 2 of Example 3, the memory itself for storing power neuron information can be omitted, and a large / small comparator or an AND gate can be substituted.

  In the second and third embodiments of the present invention, the inhibitory neuron and the power neuron are separately mounted. However, they can be realized by mixing them. In addition, an inhibitory and neuron called a power neuron can be easily realized.

    The embodiment of the present invention has been described based on a feedforward type neural network that creates a connection only with neighboring cells based on the first embodiment. However, the neural network having a feedback loop shown in the fifth embodiment, which will be described later, may also be used. Applicable.

<Problems Specific to Embodiment 4 of Circuit Unit>
Neurons in the brain convert the information received at the synaptic connection into potential changes in the plasma membrane near the synapse, and add local potential changes due to numerous synaptic connections across the cell membrane, resulting in the membrane near the axon hill. Fires when the potential exceeds the threshold. This process is governed by the ion channel protein and ion pump protein embedded in the cell membrane, the amount of ions passing therethrough, and the ion concentration difference inside and outside the cell membrane.

  Therefore, this process is inherently fluctuating, and even if exactly the same information is received through synaptic connections, the membrane potential changes near the synapse and the membrane potential near the axon hill, which is a combination of many membrane potential changes. Because the firing threshold is fluctuating, whether or not to ignite is not constant. Even in neurons of the same function that exist in a very narrow region of the brain, the axon hill shape, the number and distribution of ion channel proteins, etc. present in the axon mound are different, so the thresholds are also diverse.

  However, conventional neural network hardware cannot imitate these states, and the threshold value is the same fixed value for all neurons. Therefore, if the scale of the neural network (the number of neurons and the number of synapse connections) is increased, there is a problem that it becomes easy to fall into a local minimum during the learning process, and learning becomes difficult to proceed.

  In the fourth embodiment of the present invention, an appropriate offset value is given to each threshold value for each neuron, and the threshold value fluctuates for each neuron. An object is to realize a large-scale neural network of a neuron level.

  When the circuit unit shown in FIG. 5 of the first embodiment is used, the wiring problem between neurons can be solved and a large-scale neural network can be constructed. However, the threshold θ is constant and all the neurons in the L2 layer are used. There is a problem that the threshold value θ becomes the same.

Therefore, in the fourth embodiment of the present invention, a hardware technique is provided in which the threshold θ _j of the j-th neuron in the L2 layer can be expressed as θ _j = θ ₀ + δ _j + r _{j, v} . Here, θ ₀ is a threshold base value, δ _j is an offset amount for each j-th neuron, r _{j, v} are fluctuations for each j-th neuron, and an appropriate period V (v = [0: V− 1]) is a pseudo-random amount.

<Description of Embodiment 4 of Circuit Unit>
FIG. 16 is a circuit diagram of a circuit unit simulating a neuron group having a threshold value having an offset and fluctuation, according to a fourth embodiment of the present invention. The same elements as in FIG. 5 are given the same numbers as in FIG.

  A circuit unit that simulates a group of neurons having fluctuations in threshold values includes an 8-bit counter 20, a memory 21, a pulse train modulation circuit 22, an 8-bit counter 23A, an 8-bit counter 23B, a memory 24A, and a memory 24B. A memory 25, an AND gate 26, a 19-bit adder 27, an AND gate 28, a magnitude comparator 29, a latch 30 for holding the result of the magnitude comparator 29, a 19-bit counter 31, and a threshold calculation. The circuit 38 is used.

Therefore, the circuit unit simulating the neuron group in which the threshold value has the offset and fluctuation is obtained by adding the threshold value calculation circuit 38 to the circuit of FIG.
The threshold calculation circuit 38 includes an 8-bit counter 56, an 8 [bit] × 256 memory 57 for storing a threshold offset amount, a 12-bit adder 58, a 13-bit adder 59, and an 8-bit pseudorandom number generator. 60.

Each time the 8-bit counter 56 receives the count-up signal at the terminal 48 b, the 8-bit counter 56 increments the count value j by 1 and outputs the count value j to the memory 57.
The memory 57 holds a threshold offset amount for each L2 layer neuron. The memory 57 receives the count value j output from the counter 56, reads the threshold value offset amount δ _j of the L2 layer neuron from the address corresponding to the count value j, and adds the offset amount δ _j to the 12-bit adder 58. Output to.

The 12-bit adder 58 receives the offset amount δ _j of the j-th neuron output from the memory 57, adds the offset amount δ _j and the threshold base value θ _b input to one side, Data (12-bit data) is output to the 13-bit adder 59.
The 13-bit adder 59 receives the data output from the 12-bit adder 58 and the pseudo-random numbers r _{j, v} output from the 8-bit pseudo-random number generator _, and adds the data and the pseudo-random numbers r _{j, v.} , The data after the addition is output to the magnitude comparator 29 as the threshold θ _j .

The 8-bit pseudo random number generator 60 receives the count signal at the terminal 48b and uses it as the signal ck. The 8-bit pseudo random number generator 60 receives the fixed signal at the terminal 49b and uses it as the signal fix. The 8-bit pseudo random number generator 60 generates the pseudo random numbers r _{j, v} using the ck and the fix and outputs the pseudo random numbers r _{j, v} to the 13-bit adder 59.

    As an example of the internal circuit of the 8-bit pseudorandom number generator 60, FIG. 17 shows a Galois type LFSR (Linear Feedback Shift Register). When this circuit starts from an initial value other than 0, at the rise of 255 ck inputs, the value of 1 to 255 is generated pseudo-randomly once and returns to the initial value.

In the circuit example of FIG. 17, when the signal fix becomes 1, the most significant bit is reset and the other bits are set, so that they are initialized to x′7F ′. The signal fix becomes 1 for two purposes. One is to set an initial value other than zero. The other is to fix r _{j, v} to x′7F ′, which is an approximately intermediate value of the fluctuation range _, when it is not desired to change the threshold value. The latter will be described later. It is also important that this pseudo random number generator makes a round in 255 times, which will be described later. Since this circuit itself has been conventionally used for generating pseudo-random numbers, a detailed description thereof is omitted here.

  The operation of the present invention will be described with reference to examples. Before the calculation starts, the counter 20, counter 23A, counter 23B, counter 31, and counter 56 are set to 0 by a reset signal (not shown), the signal fix is also set to 1, and the output value of the pseudo random number generator 60 is x. Initialized to '7F'. In addition, the L1 layer input data is stored in the memory 21, the synaptic connection weight data is stored in the memory 25, and the threshold value offset amount of the L2 layer neuron is stored in the memory 57 by any means (not shown). To do.

  Since the counter 20 is 0 when the calculation is started, 4-bit data is read from address 0 of the memory 21 (0th neuron of the L1 layer), sent to the pulse train modulation circuit 22, and converted to 15-bit data. This conversion is performed, for example, by reading 15-bit data from the memory in which the data shown in FIG. 6 is written using the data sent from the memory 21 as an address.

  In the first round 0, bit 0 in the 15-bit data is transferred. When this data is output from the output terminal P0 to the outside, it is sent to the memory 24A together with the operation.

  Although the data output from the terminal P0 is received by the adjacent cell, the circuit is symmetrical, so that the data of the adjacent cell can be received from the input terminals P1 to P6 together with the operation. Therefore, the data from the pulse train modulation circuit 22 and the data from the terminals P1 to P6 are bundled into 7-bit data and stored in the address 0 of the memory 24A.

  Thereafter, when the signal input to the terminal 41 becomes active, the counter 20 outputs 1 to the memory 21. The memory 21 reads the data at address 1 and outputs the data to the pulse train modulation circuit 22. The pulse train modulation circuit 22 converts the data output from the memory 21 into 15-bit data, and sends bit 0 of the 15-bit data to the terminal P0.

  When the signal input to the terminal 41 becomes active and the signal input to the terminal 42A becomes active, the counter 23A outputs 1 to the memory 24A. The memory 24A bundles the data output from the pulse train modulation circuit 22 and the data input from the terminals P1 to P6 into 7-bit data, and stores the 7-bit data in the first address.

In this way, when data transfer is performed until the counters 20 and 23A exceed 255 and return to 0, round 0 ends. Since 256 data is transferred from the L1 layer to the L2 layer at 4 [ms], the series of processing speed is 64 [kHz], and the data rate of the signal (1 bit) output from the P0 terminal is 64 [Kbps]. is there.
In the next round 1, the pulse train modulation circuit 22 transmits bit 1 in the 15-bit data, and the transferred data is written in the memory 24B.

  Data transfer is continued by alternately using the memories 24A and 24B for each round. When the transfer of bit 14 is completed in round 14, the transfer of data stored in the memory 21 is completed. When it is desired to continue the processing in the neural network, new data is written in the memory 21 or the next data is prepared in parallel with the processing in the neural network with the memory 21 having a double buffer structure.

Next, the operation of the L2 layer neuron will be described. When round 0 ends and 1,792 a ′ _{i, 0, q} are arranged in the memory 24A, processing in the L2 layer starts from round 1. The jth neuron in the L2 layer calculates Σ (a ′ _{i, 0, q} × w ′ _{i, q, j} ). Here, Σ represents 1,792 total sum calculations for i and q.

  Since there are 256 neurons in the L2 layer, 458,752 (= 1,792 × 256) product-sum operations must be performed in 4 [ms] after all. Therefore, the circuit of this part is operated at 114.7 [MHz].

When the calculation starts in the L2 layer in round 1, the signal input to the terminal 42A is activated at 16.384 [MHz] and the counter 23A is counted up, and 7-bit data from the memory 24A at 16.384 [MHz] Is converted to a 1-bit signal a ′ _{i, 0, q} of 74.7 [Mbps], which is 7 times faster.

Along with this operation, the signal input to the terminal 47 is made active at 114.7 [MHz], the counter 31 is counted up at 114.7 [MHz], and the 8-bit synaptic connection weight data w ′ _i, Control to output _{q and j} . The AND gate 26 multiplies the input a ′ _{i, 0, q} and w ′ _{i, q, j} to calculate 8-bit data (0 or w ′ _{i, q, j} ), and adds the data. To the device 27.

The adder 27 receives data from the AND gate 28, adds the 8-bit data output from the AND gate 26 to the data, and calculates Σ (a ′ _{i, 0, q} × w ′ _{i, q, j} ). To do. At the beginning of the sum calculation, the terminal 44 of the AND gate 28 is set to 0, and the partial sum output from the adder 27 and returned to the one-side input is set to 0. When 1,792 times of sum calculation for i and q are completed, the sum is output to the magnitude comparator 29.

The magnitude comparator 29 compares the sum with the threshold θ _j, and sets the comparison result to 1 if the sum is greater than the threshold θ _j , and sets the comparison result to 0 if the sum is smaller. The large / small comparator 29 outputs the comparison result in the form of a pulse of 114.7 [MHz]. Therefore, the signal input to the terminal 45 of the latch 30 is set to 1 at the timing when the output of the large / small comparator 29 is output, and the comparison result is held in the latch 30. As a result, the output of the L2 layer becomes a signal of 64 [Kbps].

Finally, the generation unit for the threshold θ _j will be described. At the beginning of round 1, the counter 56 outputs a count value 0 to the memory 57. The memory 57 receives the count value ₀ and reads the data at address 0, that is, the threshold offset amount δ ₀ of the neuron at the L2 layer. The memory 57 outputs the offset amount δ ₀ to the adder 58.
The adder 58, the offset [delta] ₀ of the memory 57 is output, receives a base value theta _b of supplied from a not shown register or an external threshold.

The adder 58 adds the said offset amount [delta] ₀ and the base value theta _b, and outputs the added value to the adder 59. Here, the base value θ _b is 12 bits wide, and the offset value δ ₀ is 8 bits wide. The reason why the difference between the two bit widths is 4 is that an offset amount up to about 1/16 of the base value can be given.

On the other hand, the pseudo random number generator 60 generates pseudo random numbers r _{0, v} (v is the number of rounds) and outputs the pseudo random numbers r _{0, v} to the adder 59.
The adder 59 receives the sum of the pseudo random number r _{0, v} output from the pseudo random number generator 60, the base value θ _b output from the adder 58, and the offset amount δ ₀ .

The adder 59 adds the sum of the pseudo random numbers r _{0, v} , the base value θ _b, and the offset amount δ _0, and outputs the added value θ ₀ to the magnitude comparator 29.
A signal input to the terminal 48b from a circuit (not shown) rises at the timing when the comparison by the large / small comparator 29 ends, that is, 64 [kHz], and the pseudo random number generator 60 generates new pseudo random numbers r _{1 and v} .

Along with its operation, the counter 56 counts up, the offset amount storage memory 57 of the threshold reads new offset [delta] _1. In this way, the offset amount δ _j and the pseudo random numbers r _{j, v} are updated for each neuron of the L2 layer.

Here, the subscript _v of the pseudo random numbers r _j, v will be described. As described above, when the ck input becomes active 255 times, the pseudo random number generation circuit of FIG. 17 generates the values 1 to 255 pseudo-randomly only once and returns to the initial value at the 256th time. Let this pseudo-random number sequence be R0, R1, R2, R3,.

  The value initially added to the threshold value of the 0th neuron in the L2 layer in round 1 is the initial value R0. Since there are 256 neurons in the L2 layer, the signal input to the terminal 48b becomes active 256 times, and the value added to the threshold value of the 255th neuron at the end of round 1 is also R0.

  Therefore, the value added to the threshold value of the 0th neuron in the next round 2 is R1. Eventually, when the pseudo-random number added to the threshold value of the 0th neuron is observed, the values of R0 to R254 make a round in 255 rounds.

  The same applies to pseudorandom numbers added to the thresholds of other neurons. In the case of one round, the same value is used in the 0th and 255th neurons, but in other cases, the non-overlapping values of 1 to 255 are used only once each, and if one neuron is viewed, there are 255 rounds. Thus, a value of 1 to 255 is used pseudo-randomly.

  In this way, it is possible to give a pseudo-random fluctuation that does not substantially overlap with the threshold value of each neuron (it overlaps with neurons No. 0 and No. 255). To prevent the pseudo-random numbers from overlapping between the 0th and 255th neurons, use a 9-bit or more Galois LFSR for the pseudo-random number generator, or reduce the number of neurons included in the L2 layer to 254 or less. Thus, if the number of neurons in the L2 layer is made smaller than the cycle of the pseudo random number generator and the shift amount between the two is set not to be a divisor of the cycle of the pseudo random number generator. Good.

  The main purpose of giving fluctuations to the threshold is to prevent falling into the local minimum state when changing the weight of the synaptic connection in the learning process. Further, after learning is completed, the neural network can be used with the threshold value fluctuated, but in this case, the output may not be the same for the same input data. In order to avoid this phenomenon, the signal fix may be fixed at 1 and the threshold fluctuation may be fixed at approximately the average value x'7F '.

If it is desired to make the threshold offset amount δ _{j the} same for all neurons, all the data written to the memory 57 may be the same, or the signal input to the terminal 48b may be held inactive.

Next, the bit widths of the adder 58, the adder 59, the offset memory 57, and the magnitude comparator 29 will be described. As already described, in this embodiment, the bit width of the pseudo random number generator is desirably 8 or more. If the ratio of fluctuation given to the threshold value θ _{j is} , for example, about 10% at the maximum, the bit width of θ _b needs to be 3 to 4 bits larger than the bit width of the pseudo random number generator. Therefore, in the fourth embodiment of the theta _b was 12 bits wide.

Next, assuming that an offset of about 10% at maximum is given to the threshold θ _j , the bit width of the memory 57 is set to 8. Based on the above assumptions, in this embodiment, the bit width of the adder 58 is 12, the bit width of the adder 59 is 13, and the bit width of the magnitude comparator 29 is 13. On the other hand, since the output of the adder 27 is 19 bits wide, the upper 13 bits of the adder 27 or the upper 13 bits of the minimum bit width that can represent the maximum number appearing as the sum is input to the A input of the magnitude comparator 29. .

  Alternatively, the resolution required by the magnitude comparator 29 can be determined first, and the bit width of the pseudorandom number generator 60 can be determined based on the resolution. In this case, a pseudo-random number generator 60 having a width smaller than 8 bits can be used, but if a 7-bit one is used, for example, about half of the neurons in the L2 layer have the same fluctuation.

In the fourth embodiment of the present invention, the threshold offset amount is implicitly positive or zero, but the present invention is not limited to this, and the data in the offset data memory 57 is interpreted as a two's complement expression. If the adder 58 is changed to an adder / subtracter, a positive / negative offset amount can be given to the threshold value.
In the fourth embodiment of the present invention, the threshold offset amount can be set for each L2 layer neuron. However, the present invention is not limited to this, and the L2 layer neuron in several groups having the same offset amount. , It is possible to reduce the number of data required for the memory 57 to the number of the groups.

In Example 4 of the present invention, a signal to be inputted each time comparing the sum with a threshold value theta _j in magnitude comparator 29 to the terminal 48b and to activate, the present invention is not limited thereto, the terminal 48b By keeping the signal input to the constant value, the offset amount and fluctuation amount of all neurons can be made the same.

  In the fourth embodiment of the present invention, the value of the pseudo random number is implicitly set to positive or 0. However, the present invention is not limited to this, and the pseudo random number is interpreted as a two's complement expression, and the adder 59 Is changed to an adder / subtracter, positive and negative fluctuations can be given to the threshold value.

  In the fourth embodiment of the present invention, the value of the pseudo random number generator 60 becomes x′7F ′ when the fix signal becomes 1, but the present invention is not limited to this, and any value other than 0 is possible. A value can be set as an initial value. Alternatively, if a reset signal input is added so that an initial value other than 0 is obtained when the reset signal becomes active, when the fix signal becomes 1, the value is fixed to an arbitrary value including 0. be able to. Further, when the value of the pseudo random number is interpreted as a two's complement, since the center of fluctuation becomes a value close to 0, the initial value when the fix signal becomes 1 is a value close to 0, such as x'01 '. Can be.

  In the fourth embodiment of the present invention, the 8-bit Galois LFSR is used as the pseudo-random number generator 60. However, the present invention is not limited to this, and an arbitrary-type pseudo-random number generator having an arbitrary bit width is used. However, the threshold value can be similarly fluctuated.

  In the fourth embodiment of the present invention, it has been described that all the neurons of the L1 layer are implicitly excitatory neurons, but the present invention is not limited to this. For example, the data in the synaptic connection weight data memory 25 Is replaced with an adder / subtracter, and an offset and fluctuation can be similarly applied to the threshold value for a neural network in which excitatory neurons and inhibitory neurons are mixed.

  Similarly, an offset and fluctuation can be given to the threshold value for the power neuron described in the third embodiment of the present invention. For example, in the circuit unit simulating the power neuron of FIG. 14, this can be realized by connecting the output terminal of the adder 59 of the threshold value calculation circuit 38 of FIG. 16 to the input terminal 43 of the magnitude comparator 29.

  In the fourth embodiment of the present invention, the number of neurons included in one cell is 256 in both the L1 layer and the L2 layer, but the present invention is not limited to this, and there are two or more neurons in each layer. It can be applied similarly. Further, the number of neurons in the L1 layer and the L2 layer need not be the same.

In the embodiment of the present invention, the neural network has a two-layer structure. However, the present invention is not limited to this, and each layer after the second layer is also applied to a neural network having three or more layers. Applicable to as well.
In the embodiment of the present invention, the input data of the L1 layer neuron is 4 bits wide, but the present invention is not limited to this, and can be applied to a neural network having an arbitrary bit width.

In the embodiment of the present invention, it is described that one round is 4 [ms]. However, the present invention is not limited to this, and an arbitrary time can be set.
In the embodiments of the present invention, the pulse neural network has been described. However, the present invention is not limited to this, and can be similarly applied to a neural network other than the pulse neural network.

<Effect of Embodiment 4 of Circuit Unit>
By using the technique according to the fourth embodiment of the present invention, an arbitrary offset amount and pseudo-random fluctuation can be individually given to the threshold value of each neuron in a large-scale neural network, and the neuron can have diversity. At the same time, there is an effect of preventing the learning from becoming difficult due to the local minimum during learning.

  Further, it is possible to realize a neural network that returns a response with fluctuation within a certain range with respect to exactly the same input data. Alternatively, it is possible to realize a neural network that eliminates this fluctuation and always returns the same reaction.

<Issues unique to the fifth embodiment of the circuit unit>
Embodiment 5 of the present invention has an object to provide a circuit unit for realizing a neural network having a number of neurons of 100 million or more, a feedback loop in a signal path, and operating in real time.

As an example, a three-layer pulse neural network having a feedback loop will be described with reference to FIG. FIG. 23 is a schematic diagram showing a part of a neural network having a feedback loop. The L1 layer is a data input layer. Here, for example, a neuron 230 _i (i is an integer from 1 to 1,000) that converts input data having a width of 4 bits into a pulse train having a period of 4 [ms], for example, There are 1,000. The L2 layer is an intermediate data processing layer, and there are, for example, 900 neurons 232 _j (j is an integer from 1 to 900) for processing data.

The L3 layer is a data output layer, and there are, for example, 200 neurons 236 _m (m is an integer from 1 to 200) that processes data. From each neuron 230 _{i in the} L1 layer, one output signal line 231 _i (corresponding to an axon of a nerve cell) comes out. The output signal line 231 _i branches to many places (900 at the maximum because the number of neurons 232 _j is 900) and is connected to the j-th neuron 232 _j in the L2 layer via the synapse connection 233 _{i, j} .

One output signal line 235 _k is output from the k-th neuron 232 _k in the L2 layer, and the tip of the output signal line 235 _k branches to the feedback signal to the neuron 232 _j in the L2 layer and the neuron 236 _{m in the} L3 layer. Input signal. The output signal line 235 _k is connected to the j-th neuron 232 _{j in the} L2 layer via the synapse connection 234 _{k, j} . The output signal line 235 _k is connected to the m-th neuron 236 _{m in the} L3 layer via the synapse connection 237 _{k, m} . Accordingly, the maximum number of synaptic connections of the L2 layer neuron 232 _j is 1,900 (= 1,000 + 900) per neuron.

Data a _i transmitted through the signal line 231 _i is a 1-bit signal. Synaptic connections _{233 i, j,} for example the weight data _{w i} of 8-bit _width, holds the _j, computes the product _{a i} × _{w i, j} and _{a i.}

The data b _k transmitted through the signal line 235 _k is a 1-bit signal. Synaptic connections _{234 k, j} is the weighting data _{w k} of 8-bit _width, holds the _j, computes the product _{b k} × _{w k, j} and _{b k.}

The neuron 232 _j calculates the sum of a maximum of 1,000 a _i × w _{i, j} and a maximum of 900 b _k × w _{k, j} calculated for all the synaptic connections attached thereto. Then, the neuron 232 _j may exceeds the threshold value theta value of the sum is predetermined, and outputs a 1 on its output signal line 235 _j, if the threshold is not exceeded theta, a 0 to output signal line 235 _j Output.

Signal line 235 _k toward the L3 layer from each neuron 232 _k of the L2 layer, branches number at locations (up to 200 because the number of neurons 236 _m 200). The signal line 235 _k is connected to the neuron 236 _m through the synapse connection 237 _km . Accordingly, there are a maximum of 900 synapse connections 237 _{k, m} per neuron 236 _m .

Synaptic connections _{237 k, m,} for example the weight data _{w k} of 8 bits _wide, holds _m, product _{b k} × _{w k} with _{b k,} to calculate the _m. In each neuron 236 _m , the sum of up to 900 b _k × w _{k, m} calculated at the synapses attached thereto is calculated.

When the sum value exceeds a predetermined threshold value θ, the neuron 236 _m outputs 1 to the output signal line 238 _m . When the sum value does not exceed the threshold value θ, the neuron 236 _m sets 0 to the output signal line 238 _m. Output. A series of these operations is completed within 4 [ms].

  As is apparent from the above description, the 1,000 neurons in the L1 layer are basically connected to 900 neurons in the L2 layer, and the 900 neurons in the L2 layer are also 900 neurons in the L2 layer. Since the connection is basically brute force with neurons, the total number of synaptic connections used for these connections reaches a maximum of 1.71 million (= 1,900 × 900), and the total number of wires going to these synaptic connections is also a maximum of 171. Reach 10,000.

Similarly, since 900 neurons in the L2 layer basically connect with 200 neurons in the L3 layer, the total number of synaptic connections used for these connections is a maximum of 180,000 (= 900 × 200). The total number of wires going to these synaptic connections also reaches 180,000. In an actual neural network, unnecessary synapse connections are removed depending on the use and learning results, so the output of each neuron 230 _i and neuron 232 _k has various synapse connections with which neuron 232 _j and neuron 236 _m. is there.

That is, the neuron 230 _i can selectively make a synapse connection with the neuron 232 _j , the neuron 232 _k can also selectively make a synapse connection with the neuron 236 _m, and the output of the neuron 232 _k can be selectively fed back to the neuron 232 _j. The mechanism must be technically possible.

  Even in a neural network having at most 2,100 neurons (= 1,000 + 900 + 200), the number of necessary wirings reaches a maximum of 1.89 million (= 171,000 + 180,000), and it is necessary to selectively perform them. There are 10 to 100 billion neurons in the human brain, and each neuron is said to have 1,000 to 10,000 synaptic connections. To build a neural network that has about 100 million neurons as many as the human brain and that has feedback loops between those neurons, a huge amount of wiring is required. A neural network with the scale and function cannot be realized.

  In order to solve this wiring problem, the circuit unit of the first embodiment has been described with reference to FIG. However, in the first embodiment, a so-called feedforward type neural network can be realized, but there is a problem that a neural network including a feedback loop targeted in the fifth embodiment cannot be realized. Therefore, the fifth embodiment provides a circuit unit for extending the above-described first embodiment so that an ultra large-scale neural network having a feedback loop can be constructed.

<Description of Example 5 of Circuit Unit>
The circuit unit (FIG. 5) of the first embodiment described above relates to the wiring from the L1 layer to the L2 layer, for example, but it can be easily estimated that it can be applied to the wiring from the L2 layer to the L3 layer. In this case, the wiring from the L1 layer to the L2 layer and the wiring from the L2 layer to the L3 layer can be output to separate output terminals, but in that case, the number of output terminals is two and the number of input terminals is doubled to 12 I need one.

  With recent developments in semiconductor technology, logic elements (transistors) can be made at low cost, but wirings connecting the elements are relatively more expensive than elements. In the circuit under consideration here, since the signals coming out from the two output terminals are as low as 64 [Kbps], it is technical even if the two signals are time-division multiplexed and transmitted through one signal line. No problem arises. An extra transistor is required to time-division-multiplex the signal and to restore it, but it is advantageous in terms of cost to reduce the number of wires by the time-division multiplexing of the signal.

FIG. 18A is a schematic diagram of a neural network according to the fifth embodiment of the present invention in a certain cell. One cell consists of 256 neurons 180 _i belonging to the L1 layer (i is an integer from 0 to 255), 256 neurons 182 _j belonging to the L2 layer (j is an integer from 0 to 255), and an L3 layer. It has 32 neurons 186 _m to which it belongs (m is an integer from 0 to 31).

Further, the cell includes a wiring 181 _i to neuron 182 _j of the L2 layer from the neuron 180 _i of the L1 layer, the synaptic connections _{183 i, j} to the neuron 182 _j of the L2 layer from the neuron 180 _i of the L1 layer, L2 a wiring 185 _k of the (k is from 0 255 integer) neurons ₁₈₂ k layer to neuron 182 _j from the L2 layer, synaptic connections _{184 k} to neurons 182 _j of the L2 layer from the neuron 182 _k of the L2 _layer, and _j , Synapse connection 187 _{k, m} from the L2 layer neuron 182 _k to the L3 layer neuron 186 _m , and an output terminal 188 _{m of the} L3 layer neuron 186 _m .

FIG. 18B and FIG. 18C are diagrams for explaining the format of a signal flowing between layers. As shown in FIG. 18B, data z _{i, t} from the L1 layer to the L2 layer (i is an integer from 0 to 255) and data y _{k, t} from the L2 layer to the L3 layer (k is from 0). (Integer up to 255) is output from the output terminal P0 as a signal S obtained by time division multiplexing.
Here, z _{i, t} is the t-th (t is an integer equal to or greater than 0) round output of the i-th neuron of the L1 layer. y _{k, t} is the output of the t th round of the k th neuron of the L2 layer.

  Alternatively, the L2 layer output data is temporarily stored in the memory, and after the L1 layer data is output in 2 [ms] as shown in FIG. 18C, the L2 layer data is output together. You can also In any case, the data transfer rate of the signal S is doubled as (256 [bit] +256 [bit]) ÷ 4 [ms] = 128 [Kbps]. It is.

In the present invention, the data sent from the L1 layer to the L2 layer and the data sent from the L2 layer to the L3 layer are time-division multiplexed and transmitted through one signal line, and the data sent from the L2 layer to the L3 layer is transmitted. The inter-neuron wiring system is also used as feedback data from the L2 layer to the L2 layer.
In the following description, the signal format of FIG. 18B is taken into consideration, but the present invention can be similarly applied to the signal format of FIG. 18C.

  FIG. 19 is a circuit diagram of a circuit unit of a neural network that feeds back the output of the L2 layer neuron group to the L2 layer neuron group according to the fifth embodiment of the present invention. The entire circuit of FIG. 19 corresponds to one regular hexagon (cell) in FIG. In this embodiment, each neuron is not an individual electronic circuit, but a L1 layer (256 neurons), an L2 layer (256 neurons), and an L3 layer (32 neurons) are mounted together as virtual neurons. ing.

  The circuit unit of FIG. 19 includes an 8-bit counter 20 belonging to the L1 layer, a memory 21, a pulse train modulation circuit 22, an 8-bit counter 23A, an 8-bit counter 23B, a memory 24A, a memory 24B, and a memory 25. AND gate 26, adder 27, AND gate 28, memory 69A, memory 69B, memory 70, AND gate 71, adder 72, AND gate 73, adder 74, and size comparison And a latch 78, a multiplexer 77, a memory 78, an AND gate 79, an adder 80, an AND gate 81, a magnitude comparator 82, a latch 83, and an AND gate 84. Has been.

  8-bit counter 20, memory 21, pulse train modulation circuit 22, 8-bit counter 23A, 8-bit counter 23B, memory 24A, memory 24B, memory 25, AND gate 26, adder 27, The AND gate 28 is the same as the circuit of FIG. Note that the display of the counter 31 that supplies an address to the memory 25 is omitted.

The memory 69A and the memory 69B store output data b ′ _{k, q} (7 [bit] × 256) of the L2 layer transmitted through the terminals P0 to P6. Here, q is an integer from 0 to 6 representing the input (out) force terminal number. The memories 69A and 69B are used alternately.
The memory 70 stores synaptic connection weights w ′ _{k, q, j} (8 [bit] × 256 × 7 × 256) for receiving a feedback signal from the L2 layer.

The AND gate 71 receives b′k, q output from the AND gate 84 and w ′ _{k, q, j} output from the memory 70, multiplies the b ′ _{k, q} and w ′ _{k, q, j} , The multiplied values b ′ _{k, q} × w ′ _{k, q, j} are output to the adder 72.

The adder 72 calculates the sum of k ′ _{and q} ′ of b ′ _{k, q} × w ′ _{k, q, j} output from the AND gate 71 for each neuron j in the L2 layer, and outputs the sum to the adder 74. To do. During the sum calculation, the adder 72 outputs the partial sum to the AND gate 73.
The AND gate 73 sets the partial sum that enters the adder 72 to 0 at the beginning of the total sum calculation of one neuron in the L2 layer.

  For each neuron j in the L2 layer, the adder 74 calculates the sum based on the data from the L1 layer output from the adder 27 and the sum based on the feedback data from the L2 layer output from the adder 72. Then, the sum of the data from the L1 layer and the sum of the feedback data from the L2 layer are added, and the added data is output to the magnitude comparator 75.

  The magnitude comparator 75 receives the data output from the adder 74, and outputs 1 to the latch 76 when the data is greater than the threshold value θ input from the terminal 64. On the other hand, the magnitude comparator 75 outputs 0 to the latch 76 when the data output from the adder 74 is equal to or less than the threshold value θ.

The latch 76 receives the data output from the magnitude comparator 75 and holds the data when the signal input to the terminal 65 rises.
The multiplexer 77 alternately selects the output data a ′ _{i, p} of the L1 layer and the output data b ′ _{j of the} L2 layer, and performs time division multiplexing as shown in FIG.

The memory 78 stores the synaptic connection weights w ′ _{k, q, m} (8 [bit] × 256 × 7 × 32) of the L3 layer neuron that receives the signal from the L2 layer. When the memory 78 receives a signal from a counter (not shown), the memory 78 reads the synaptic connection weight w ′ _{k, q, m} corresponding to the signal and outputs the weight to the AND gate 79.

The AND gate 79 receives the data b ′ _{k, q} output from the AND gate 84 and the synaptic connection weights w ′ _{k, q, m} output from the memory 78 _, and the b ′ _{k, q} and w ′ _{k, q,} multiplied by _m, and outputs the value _b'k after _{multiplication, q} × _{w'k, q,} the _m to the adder 80.

The adder 80, AND _b'gate 79 has an output _{k, q × w'k, q} , the _m, by adding to the calculated partial sums in the previous _{steps, Σ (b'k, q ×} w ′ _{K, q, m} ) is calculated for k and q, and the total is output to the magnitude comparator 82. Further, the adder 80 outputs the partial sum during the calculation to the AND gate 81.
The AND gate 81 sets the one-side input of the adder 80 to 0 at the beginning of the sum calculation of one neuron in the L3 layer.

The magnitude comparator 82 receives the sum output from the adder 80 and the threshold value θ input from the terminal 64, and outputs 1 to the latch 83 when the sum is larger than the threshold value θ. On the other hand, the magnitude comparator 82 outputs 0 to the latch 83 when the sum is equal to or less than the threshold value θ.
The latch 83 receives the data output from the magnitude comparator 82, holds the data when the signal input to the terminal 65 rises, and outputs the value to the terminal 67.

Although the weight of the synapse connection is positive or negative, it does not affect the effect of the present invention. Therefore, in this embodiment, only the positive data will be described. In addition, for a portion where there is no connection between neurons, the weights w ′ _{i, q, j} , w ′ _{k, q, j} and w ′ _{k, q, m} corresponding to the synapse connection are 0. To do.

  Next, the operation of this embodiment will be described. Before the processing in the neural network of FIG. 19 is started, the input data of the neurons of the L1 layer is stored in advance in the memory 21 by an arbitrary method not shown, and the weight data of the synapse connection is stored in the memory 25, the memory 70, and Assume that it is stored in the memory 78. The counter 20, the counter 23A, and the counter 23B are set to 0 beforehand by a reset signal (not shown).

  Since the counter 20 is 0 when the calculation starts, the memory 21 reads the 4-bit data at address 0 and sends it to the pulse train modulation circuit 22, which converts the data into 15-bit data. This conversion can be realized, for example, by reading data from the memory in which the data shown in FIG. 6 is written using the data sent from the memory 21 as address information.

In the first round 0, only the LSB of 15-bit data shown in FIG. 6 is transferred. The data _a'0,0 and time-division multiplexed output data _b'0 of the L2 layer, but from the output terminal P0 in the format shown in FIG. 18 (b), the output data of the round 0 in the L2 layer _b'0 Is undefined.

Although the data output from the terminal P0 is received by the adjacent cell, since the circuit is symmetrical as shown in FIG. 2B, the data of the adjacent cell can be received from the input terminals P1 to P6 together with the operation. The memory 24A stores the data a ′ _{0,0, q} from the L1 layer input from the terminals P0 to P6 at the address 0 of the memory 24A. The memory 69A stores the data b′0 _{, q} from the L2 layer at address 0 of the memory 69A, but the b′0 _{, q} is indefinite in round 0.

  Thereafter, when the signal input to the terminal 41 and the signal input to the terminal 42A become active and the counter 20 and the counter 23A become 1, the data at the first address in the memory 21 is read and sent to the pulse train modulation circuit 22. Is converted to 15-bit data, and only the LSB is sent to the terminal P0.

Then, the data from the terminals P0 to P6 are bundled to become 7-bit data, the data a ′ _{1, 0, q} from the L1 layer are stored in the first address of the memory 24A, the data b ′ _1, from the L2 layer _{, q} is stored in the first address of the memory 69A. Thus, when data transfer is performed until counters 20 and 23A exceed 255 and return to 0, round 0 ends.

  In the next round 1, the pulse train modulation circuit 22 sends out bit 1 data of 15-bit data, the transferred data is written in the L1 layer data in the memory 24B, and the output data in the L2 layer is written in the memory 69B. . In this way, data transfer is performed using the memories 24A and 24B and the memories 69A and 69B alternately.

  When the transfer of bit 14 is completed in round 14, the processing of the data stored in memory 21 is completed. When it is desired to continue the processing in the neural network, new data is written in the memory 21, or the memory 21 is made a double buffer structure and the next data is prepared in parallel with the processing in the neural network, or the memory Repeat the process using the same 21 data.

Next, the operation of the L2 layer neuron will be described. Since the data in the memory 24A is indefinite in round 0, the output of the L2 layer calculated using this data is indefinite. When round 0 ends and 1,792 a ′ _{i, 0, q} are arranged in the memory 24A, data processing in the L2 layer is performed in the next round 1.

However, since the output of the L2 layer was indefinite at round 0, the contents of the memory 69A storing this are indefinite. Therefore, if the operation of the L2 layer is performed in this state, the output of the L2 layer becomes unstable again. To prevent this, during round 1, the terminal 68 is set to 0, the output of the AND gate 84 is fixed to 0, and the feedback information from the L2 layer is ignored. With respect to data from the L1 layer, the L2 layer has to perform 1,792 product-sum operations per neuron, so the calculation is performed at a speed 1,792 times that of the L1 layer, that is, 114.7 [MHz]. In the jth virtual neuron of the L2 layer, Σ (a ′ _{i, 0, q} × w ′ _{i, q, j} ) is calculated. Here, Σ represents the sum of i and q.

The memory 24A reads out 7-bit data at 16.384 [MHz], which is 256 times 64 [kHz], and converts it into a parallel signal, thereby converting the 7-bit 114.7 [Mbps] 1-bit signal a ′ _{i, Set} to _{0, q} . Along with this operation, the corresponding 8-bit weight data w ′ _{i, q, j} is read out from the synapse connection weight memory 25 at 114.7 [MHz], and is multiplied by a ′ _{i, 0, q} by the AND gate 26. 8 bits 0 or w ′ _{i, q, j} .

The a ′ _{i, 0, q} × w ′ _{i, q, j} thus obtained is input to the adder 27 and Σ (a ′ _{i, 0, q} × w ′ _{i, q, j} ) is calculated. The signal input to the terminal 63 at the beginning of the summation is 0, and the one-side input of the adder 27 is 0. When 1,792 summation calculations for i and q are completed, the summation is sent to the magnitude comparator 75 via the adder 74, where it is compared with the threshold θ, and if the sum is greater than the threshold θ, the output is 1 If it is smaller, the output is set to 0.

Since this output appears in the form of a pulse of 114.7 [MHz], it is difficult to use as it is. Therefore, this is held in the latch 76 by an appropriate timing signal 65 to obtain a signal b ′ _j of 64 [Kbps]. That is, in round 1, L2 layer data is generated at a speed of 64 [Kbps], output from the P0 terminal, and stored in the memory 69B.

In round 2, the output data of the L2 layer stored in the memory 69B is valid. Therefore, the signal input to the terminal 68 is set to 1, and the feedback information from the L2 layer is validated. The memory 69B reads out 7-bit data at 16.384 [MHz], which is 256 times 64 [kHz], and converts it into a parallel signal, thereby converting the 7-bit 114.7 [Mbps] 1-bit signal b ′ _{k, q} .

Along with this operation, the corresponding 8-bit weight data w ′ _{k, q, j} is read out at 114.7 [MHz] from the synaptic connection weight memory 70 forming the feedback loop, and b ′ _{k, q} is read out by the AND gate 71. And 8 bits of 0 or w ′ _{k, q, j} . The AND gate 71 outputs the calculated b ′ _{k, q} × w ′ _{k, q, j} to the adder 72.

The adder 72 receives the b ′ _{k, q} × w ′ _{k, q, j} from the AND gate 71 and calculates the sum Σ (b ′ _{k, q} × w ′ _{k, q, j} ) regarding _{k and q.} . Here, the signal input to the terminal 63 at the beginning of the summation is 0, the output of the AND gate 73 is 0, and as a result, the one-side input data of the adder 72 is 0. The adder 72 outputs the sum to the adder 74 after 1,792 times of the sum calculation for k and q.

  The adder 74 adds the output of the adder 72, which is feedback information from the L2 layer, and the output of the adder 27 that has calculated the sum of data from the L1 layer, and adds the sum after addition to the magnitude comparator 75. Output.

The magnitude comparator 75 receives the sum from the adder 74, compares the sum with the threshold θ, and sets the output to 1 if the sum is greater than the threshold θ, and sets the output to 0 if the sum is smaller. The output of the large / small comparator 75 is held in the latch 76 by the timing signal input to the terminal 65 and is output to the selector 77 as a signal b ′ _j of 64 [Kbps].
In round 3 and later, the same operation as in round 2 is performed while the memories 24A and 24B and the memories 69A and 69B are alternately used.

Next, the operation of the L3 layer neuron will be described. Since the values of the memories 69A and 69B are indefinite in round 0 and round 1, the arithmetic processing cannot be performed in the L3 layer. Round 1 to confirm the output _b'j neuron L2 layer, it therefore is stored in the memory 69B, it is possible to data processing in the round 2 L3 layer.

  For the data from the L2 layer, the L3 layer must perform 1,792 product-sum operations per neuron, but the number of neurons in the L3 layer is 1/8 (= 32/256) of the L2 layer. The product-sum operation may be performed at 14.4 MHz, which is 224 times the data output speed (= 1, 792/8).

  However, since the data in the memories 69A and 69B is supplied to the AND gate 71 at 114.7 [MHz] as a feedback signal to the L2 layer, it is inconvenient to read the data at a different speed. Therefore, the processing of the L3 layer is also performed at 114.7 [MHz].

In round 2, the memory 69B reads out 7-bit data at 16.384 [MHz], which is 256 times 64 [kHz], and converts it into a parallel, which is 7 times 14.7 [Mbps]. The signals b ′ _{k and q} are output to the AND gate 79. This signal is the same as that supplied as a feedback signal to the L2 layer. Along with this operation, the synaptic connection weight memory 78 in the L3 layer reads the corresponding synaptic connection weight data w ′ _{k, q, m} at 114.7 [MHz] and outputs it to the AND gate 79. The AND gate 79 multiplies the output data b ′ _{k, q} of the L2 layer and the weight data w ′ _{k, q, m} of the synapse connection to make 8-bit 0 or w ′ _{k, q, m} .

The AND gate 79 outputs the b ′ _{k, q} × w ′ _{k, q, m} thus obtained to the adder 80. The adder 80 is received data _b'k, calculates _q × _{w'k, q, k} and q related to the sum Σ of _{m (b'k, q × w'} k, q, m) and. The signal input to the terminal 63 at the beginning of the summation is 0, the output of the AND gate 81 is 0, and the one-side input data of the adder 80 is 0. When the 1,792 sum calculation for k and q is completed, the adder 80 outputs the sum to the magnitude comparator 82.

  The magnitude comparator 82 receives the sum from the adder 80 and compares the sum with the threshold θ. The magnitude comparator 82 outputs 1 to the latch 83 if the sum is larger than the threshold θ, and outputs 0 to the latch 83 if the sum is smaller than the threshold θ.

  The latch 83 holds the value output from the magnitude comparator 82 by the timing signal input to the terminal 65 and outputs the output signal of the mth neuron in the L3 layer to the terminal 67 at 64 [Kbps]. However, since the number of neurons in the L3 layer is 32, data from the beginning of the round to the 32nd bit is effective. The operations after round 3 are the same as those of round 2.

  As described above, the output data of the L1 layer and the output data of the L2 layer are time-division multiplexed, and the data is transferred between adjacent cells using one signal line, thereby having a three-layer structure having a feedback loop. A large-scale neural network can be realized. At that time, data sent from the L2 layer to the L3 layer and feedback data from the L2 layer to the L2 layer can be made common.

  In this embodiment, the neural network has a three-layer structure. However, the present invention is not limited to this, and can be generally applied to a neural network having two or more layers. In that case, the output data from the neurons in the intermediate layer or the output layer may be time-division multiplexed on the signal line S as shown in FIG.

  In this embodiment, the output data from the L2 layer is described as being fed back to the same L2 layer, but the present invention is not limited to this. In general, output data from a certain layer A becomes input to the next layer B and also becomes feedback data to the layer C.

  Furthermore, in the present embodiment, the feedback loop is described as having only one system (from the L2 layer to the L2 layer), but the present invention is not limited to this. Generally, a neural network having a plurality of feedback loops (for example, from the L2 layer to the L2 layer and from the L4 layer to the L3 layer), or a feedback loop from a plurality of layers in one layer (for example, from the L2 layer and the L3 layer) The present invention can also be applied to a neural network having (to the L2 layer) or a neural network having a feedback loop from one layer to a plurality of layers (for example, from the L3 layer to the L2 layer and the L3 layer).

In the embodiments of the present invention, the pulse neural network has been described. However, the present invention is not limited to this.
In FIG. 19, the adder 74 is used to add the signal sum calculation result from the L1 layer and the feedback sum calculation result from the L2 layer. For example, the operation speeds of the adder 27 and the adder 72 are as follows. Is not 114.7 [MHz], but 1,793 / 1,792 times or more, the adder 74 can be omitted and the adder 27 can be substituted.

<Modification of Example 5 of Circuit Unit>
FIG. 20 is a circuit diagram of a circuit unit of a neural network that is a modification of the fifth embodiment of the present invention and feeds back the output of the L3 layer neuron group to the L2 layer neuron group. The same elements as those in the circuit of FIG. The 2-input selector 77 in FIG. 19 is replaced with a 3-input selector 90, and the outputs a ′ _{i, p} of the L1 layer, the output b ′ _{j of the} L2 layer, and the output c ′ _{m of the} L3 layer are time-division multiplexed from the output terminal P0. Output. Further, a 7 [bit] × 32 memory 91A, a memory 92B, and an AND gate 92 are added, and the output data c ′ _{m, q} of the L3 layer fed back to the L2 layer and the input of the L2 layer as the input to the L3 layer The output data b ′ _{k and q} are separated. Detailed description of the operation is omitted.

<Effect of Embodiment 5 of Circuit Unit>
Assuming that each artificial neuron in the neural network forms a synaptic connection only with neighboring neurons in the virtual space, wiring between neurons can be performed with only a small number of local signal lines. It can solve the wiring problem when realizing such a super large-scale neural network.

Furthermore, even when the neural network has a multi-layer structure and feedback loops to different layers or the same layer, the output problem of the intermediate layer is time-division multiplexed onto the local signal lines described above, so that the wiring problem can be easily solved. it can.
The output data from the intermediate layer neuron becomes the input data to the next layer and the feedback data to the same layer as itself or to other layers, but it is not necessary to transmit these separately, and the transmitted data Are commonly available.

  Further, since the feedback signal that enters the multiplication circuit with the synapse weight data is 1-bit width data, signals from several layers can be easily switched by the selector. For example, in a four-layer neural network of L1, L2, L3, and L4 layers, feedback from the L2 layer to the L2 layer is required in some applications, and from the L3 layer to the L2 layer in other applications. Suppose that feedback is needed.

  In order to realize this layer structure, the output data of the L1, L2, and L3 layers are time-division multiplexed in such a manner as to extend the signal S in FIG. Used for wiring. Then, the data of the own cell and the L1, L2, and L3 layers in the adjacent cells are all aligned in the memory of the own cell, and these are read from the memory as a 1-bit width signal.

  Therefore, if one 1-bit selector for switching data from the L2 layer and data from the L3 layer is prepared and controlled by a register in the neural network or an external signal, the feedback path can be easily switched. Even in the case of a three-layer structure without the L4 layer, the feedback loop can be switched in the same manner by preparing a memory for time division multiplexing and outputting the data of the output layer L3 to the signal line between adjacent cells and receiving the signal. it can.

  Note that the above-mentioned selector can be controlled statically to determine whether feedback from the L2 layer or feedback from the L3 layer is an alternative, but this is dynamically controlled from the L2 layer. For example, the feedback and the feedback from the L3 layer can be easily halved.

  Further, an offset and fluctuation can be given to the threshold value of the L2 layer neuron or the L3 layer neuron of the fifth embodiment of the present invention. For example, in the circuit unit of FIG. 19, if the output terminal of the adder 59 of the threshold value calculation circuit 38 of FIG. 16 is connected to the input terminal 64 of the magnitude comparator 75, an offset and fluctuation are given to the threshold value of the L2 layer neuron. be able to.

<Modification common to all embodiments>
In the second to fifth embodiments of the present invention, it is possible to realize a neural network considering the time history by inserting the circuit considering the time history shown in FIG.

In the embodiment of the present invention, the synapse connection weight data is 8 bits wide. However, the present invention is not limited to this, and can be applied to a neural network having weight data of an arbitrary bit width.
In the embodiment of the present invention, the input data of the neurons in the L1 layer has a 4-bit width, but the present invention is not limited to this, and can be applied to a neural network that handles input data having an arbitrary bit width.

  In the embodiment of the present invention, the number of neurons in the L1 layer and the number of neurons in the L2 layer included in one cell are both 256, but the present invention is not limited to this, and both the L1 layer and the L2 layer The present invention can be applied to a neural network including an arbitrary number of two or more neurons.

  As mentioned above, although embodiment of this invention was explained in full detail with reference to drawings, the concrete structure is not restricted to this embodiment, The design etc. of the range which does not deviate from the summary of this invention are included.

CN cell (polytope)
10 circuit unit 20 8-bit counter 21 memory (first storage unit)
22 Pulse train modulation circuit (output circuit)
23A 8-bit counter 23B 8-bit counter 23C 8-bit counter 24A memory 24B memory 25 memory (second storage unit)
26 ANDGATE (multiplication circuit)
27 Adder (Adder)
28 AND GATE 29 Size comparator 30 Latch 31 Counter 32 Adder / Subtracter (Adder)
33 Code storage (code information output circuit)
34 Large / small comparator (sign information output circuit)
34B AND gate (code information output circuit)
35 Memory (Power neuron information output circuit)
36 1-bit left shifter (arithmetic circuit)
37 Size comparator (power neuron information output circuit)
37B ANDGATE (power neuron information output circuit)
38 threshold calculation circuit 50 multiplier (multiplication circuit)
51 Selector 52 Multiplier 53 Memory (Third Storage Unit)
54 Parallel-to-parallel conversion circuit 55 Memory (fourth storage unit)
56 8-bit counter 57 Memory (Threshold offset storage unit)
58 12-bit adder 59 13-bit adder 60 8-bit pseudo random number generator 69A Memory 69B Memory 70 Memory (fifth storage unit)
71 ANDGATE (multiplier circuit)
72 adder 73 and gate 74 adder 75 large / small comparator 76 latch 77 two-input multiplexer 78 memory (sixth storage unit)
79 AND GATE (Multiplier circuit)
80 adder 81 AND gate 82 large / small comparator 83 latch 84 AND gate 90 3-input multiplexer 91A memory 91B memory 92 AND gate

Claims (10)

A plurality of layers, a plurality of artificial neurons existing in the layer, and a synapse connection that connects the artificial neurons and a plurality of artificial neurons existing in another layer, and the first layer of the plurality of layers This is an electronic circuit that realizes a neural network in which a product of the output data of the artificial neuron and the weight information of the synapse connection is calculated, and an output according to a result of accumulating the product is output by the artificial neuron of the second layer. And
In the virtual space of two or more dimensions, the virtual space is divided by an arbitrary number of arbitrary polytopes, and between the circuit units arranged for each polytope and the circuit units arranged in adjacent polytopes, the first Wiring for transmitting and receiving signals including output data of the artificial neurons of the layer,
The circuit unit implements a plurality of artificial neurons belonging to the first layer and a plurality of artificial neurons belonging to the second layer, and the first layer artificial neurons time-division multiplex their output data, Outputting the time-division multiplexed data to the second layer artificial neuron in the same circuit unit and the second layer artificial neuron of the circuit unit arranged in the polytope adjacent to its own polytope;
The second layer of artificial neurons in the same circuit unit includes the output data output from the first layer of artificial neurons in the same circuit unit and the first of the circuit units arranged in the polytope adjacent to its own polytope. An electronic circuit characterized by processing output data output from an artificial neuron in a layer as input data.   2. The electronic circuit according to claim 1, wherein the circuit unit sets weight information of synapse connection that does not require input of output data of the artificial neuron of the first layer to 0. 3.   The virtual space is constituted by a virtual two-dimensional plane, the polytope is constituted by a regular hexagon, and the virtual two-dimensional plane is divided by an arbitrary number of the regular hexagons. The electronic circuit described.   4. The circuit unit according to claim 1, wherein the input data of the artificial neuron in the second layer is output data of the artificial neuron in the second layer or the first layer. 5. Electronic circuit. The circuit unit includes: a first storage unit that holds input data of a first layer artificial neuron; a second storage unit that holds weight information of the synapse connection;
The first layer artificial neuron time-division-multiplexes the input data and outputs it as output data to the second layer artificial neuron in the same circuit unit, and the output data is arranged in an adjacent polytope. An output circuit for outputting to the second layer of artificial neurons,
A multiplication circuit for calculating a product of the output data and the weight information;
An adder for calculating the sum of the products as one input signal;
A magnitude comparator for determining output data of the artificial neurons of the second layer based on a comparison result between the sum and a predetermined threshold;
The electronic circuit according to claim 1, further comprising:   The circuit unit includes a first storage unit that holds input data of a first layer artificial neuron, a second storage unit that holds weight information of the synaptic connection, and an artificial neuron of the first layer. A multiplication circuit for calculating a product of output data and the weight information; an arithmetic circuit for calculating a value obtained by multiplying a product corresponding to a predetermined first layer artificial neuron by a constant among the products calculated by the multiplication circuit; An adder that calculates the sum using the value multiplied by the constant as one input signal, and a magnitude comparison that determines the output data of the artificial neuron group in the second layer based on a comparison between the sum and a predetermined threshold value The electronic circuit according to claim 1, further comprising: The circuit unit further includes a multiplier that multiplies the sum by a predetermined attenuation amount, and a third storage unit that holds the multiplied multiplication result.
The electronic circuit according to claim 5 , wherein the adder uses the multiplication result held in the third storage unit as the other input signal.   The circuit unit includes: a first storage unit that holds input data of a first layer of artificial neurons; a second storage unit that holds absolute values of synaptic connection weights; and the first layer of artificial neurons A multiplication circuit that calculates a product of the output data of the first and the absolute value of the weight, and a sign information output circuit that outputs sign information of the weight of the synapse connection indicating whether the neurons of the first layer are excitable or inhibitory; Based on the sign information, an adder that calculates the sum of the product value or the negative value of the product as one input signal, and a comparison result between the calculated sum and a predetermined threshold value, The electronic circuit according to claim 1, further comprising: a magnitude comparator that determines output data of the second layer of artificial neurons. A predetermined value predetermined for each artificial neuron in the second layer is held, a pseudo random number is calculated for each artificial neuron in the second layer, and is determined in common for the artificial neurons in the second layer electronic circuit according to any one of claims 1 to 8, characterized by further comprising a threshold value calculating circuit for adding the predetermined value and the pseudo-random number to a predetermined threshold value. A plurality of layers, a plurality of artificial neurons existing in the layer, and a synaptic connection connecting the artificial neuron and an artificial neuron existing in another layer, and the first layer of the plurality of artificial neurons a wiring system of the product of the output data and the weight information of the synaptic connections to calculate, an output corresponding to a result obtained by accumulating the product artificial neurons of the second layer to realize a neural network output,
In a two-dimensional or more virtual space, the virtual space is divided by an arbitrary polytope any number of circuit units arranged in each of the polytope, the first layer among the circuit units arranged in adjacent polytope A first wiring arranged to transmit a signal including the output data of:
A plurality of artificial neurons belonging to the first layer and a plurality of artificial neurons belonging to the second layer are mounted. The artificial neurons of the first layer time-division-multiplex their own output data, and the time-division multiplexing Output the obtained data to a second layer artificial neuron in the same circuit unit and a second layer artificial neuron in a circuit unit arranged in a polytope adjacent to its own polytope,
The second layer artificial neuron in the same circuit unit is a second wired to input output data output from the first layer artificial neuron of the circuit unit arranged in the polytope adjacent to its own polytope. And a wiring system characterized by comprising:

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