JP5434518B2 - Focus detection device - Google Patents

Description

  The present invention relates to a focus detection apparatus mounted on a photographing apparatus such as a single-lens reflex camera.

  A single-lens reflex camera is equipped with a phase difference type focus detection device as an automatic focus adjustment (AF) mechanism. In the area where the subject image of the focus detection device is projected, a plurality of line sensor groups each having line sensors arranged in parallel are two-dimensionally arranged in pairs. Each line sensor has a configuration in which a plurality of photodiodes are arranged in parallel, and a signal charge generated in each photodiode is read out as a pixel signal.

  Usually, the line sensor is a charge accumulation type sensor, and the charge accumulation time is adjusted by a monitor sensor arranged beside the line sensor (see, for example, Patent Documents 1 and 2). Since the amount of light received by each photodiode of the line sensor varies depending on the brightness distribution of the subject, the charge accumulation time of the line sensor is controlled independently.

  A monitor sensor including a photoelectric conversion element such as a photodiode detects the light intensity (light quantity) of the photodiode to be monitored in real time. When the signal output from the monitor sensor exceeds a predetermined threshold, the charge accumulation (integration) of the corresponding line sensor is terminated. This prevents the photodiode from receiving light exceeding the dynamic range and overflowing.

  The electric charge accumulated in the line sensor is temporarily stored in a memory unit such as a capacitor. When the charge accumulation of all the line sensors is completed, a series of pixel signals are output as the image signal of the subject image, and calculation processing for obtaining the defocus amount is performed.

  When a charge exceeding the saturation charge amount of the photodiode is generated by the strong light incidence, a so-called blooming phenomenon occurs in which the charge overflows from the photoelectric conversion element and flows out to the adjacent pixels. The same problem also occurs when charges generated in the photodiode after transferring the charges leak to the charge storage portion.

  In order to prevent such blooming, an address type imaging device such as a CMOS sensor is provided with a control switch for discharging unnecessary charges generated in the photoelectric conversion unit, that is, an anti-blooming gate (ABG) (see Patent Document 3). .

  During the exposure period, the ABG is in an OFF state, and the accumulated charge is not discharged due to the ABG serving as a barrier. Unnecessary charges generated by excessive light are discharged to the drain or the like through the ABG barrier. When the accumulated charge is transferred, ABG is switched to the ON state. Therefore, unnecessary charges generated after the charge transfer are discharged as they are through the ABG and are prevented from flowing out to the adjacent pixels.

JP 2006-145792 A JP 2004-272238 A JP 2004-111590 A

  As described above, the charge accumulation time of the photoelectric conversion element of each line sensor varies depending on the brightness distribution of the subject, and it is necessary to detect both a very bright part and a dark part of the subject. Therefore, a very wide dynamic range is required for the photoelectric conversion element of the focus detection device. This is greatly different from an image sensor such as the cited document 2 in which the charge accumulation time of each photoelectric conversion element is constant.

  Therefore, the line sensor used in the focus detection apparatus must be configured so that charge leakage is minimized when the amount of light is extremely small, and unnecessary charges can be sufficiently discharged when the amount of light is excessive. That is, in order to enable focus detection with a wide dynamic range, the barrier of charge outflow by a charge discharge gate such as ABG must be set more precisely.

  The focus detection apparatus of the present invention includes a plurality of line sensors arranged in a projection area of a subject image, a plurality of monitor sensors arranged on the side of the plurality of line sensors, respectively, for monitoring the amount of light received by the corresponding line sensors, Image signal output means for outputting an image signal of the subject image based on the electric charge accumulated in the line sensor. For example, the focus detection device is applied to a photographing device such as a single-lens reflex camera. The line sensor is configured by an address-type image sensor such as a CMOS sensor.

  The line sensor according to the present invention includes a photoelectric conversion element such as a photodiode, a charge storage unit that stores charges accumulated in the photoelectric conversion element, and a charge transfer gate that transfers charges accumulated in the photoelectric conversion element to the charge storage unit. And a charge discharging gate for discharging charges accumulated in the photoelectric conversion element. The charge discharge gate forms an electrical barrier for charge outflow during the exposure period. For example, a charge discharge gate composed of a transistor or the like is provided on the opposite side of the charge storage portion with respect to the photoelectric conversion element. Is set to the closed state.

  In the present invention, the electrical barrier of the charge discharge gate of the line sensor is determined based on a predetermined condition. That is, when the number of charges discharged from the charge discharge gate is the maximum illuminance, the number of charges generated in the photoelectric conversion element is larger than the number of charges generated in the photoelectric conversion element, and the charge corresponding to the saturation charge amount of the charge storage portion is The threshold voltage of the charge discharge gate and the depletion voltage of the photoelectric conversion element are determined so as to be smaller than the number of charges generated in the photoelectric conversion element when it is stored in the conversion element.

  Here, the threshold voltage indicates the potential of the charge discharge gate that defines an electrical barrier for charge outflow, and the depletion voltage indicates the potential of the photoelectric conversion element when no charge is accumulated. The maximum illuminance and the minimum illuminance are determined in advance according to the performance characteristics of the line sensor.

  In the present invention, the number of charges flowing out from the charge discharge gate that forms an electrical barrier during the exposure period is set to be appropriate for both very strong light and weak light. Even when the exposure amount is such that overflow occurs, unnecessary charges are sufficiently discharged through the unnecessary charge discharging gate, so that blooming can be prevented, and when the amount of light is very small, it flows out. Since the number of charges is sufficiently small, the charge accumulation period of the line sensor can be terminated in an appropriate period, and focus detection with a wide dynamic range is performed.

  It is desirable to suppress the number of charges flowing out as much as possible when the illuminance is low. Therefore, when the illuminance is at a minimum and the charge corresponding to the saturation charge amount in the charge storage portion is accumulated in the photoelectric conversion element, 1/10 of the number of charges generated in the photoelectric conversion element, and further 1/100 It is preferable to determine the threshold voltage of the charge discharge gate and the depletion voltage of the photoelectric conversion element so as to satisfy the following.

For example, the depletion voltage is set so as to satisfy the following expression.

ΔV _MEMmax ≦ V _rst − (V _PD0 + ΔV _FD )

However, the photodiode voltage corresponding to the saturation charge amount of the charge storage portion is _represented by ΔV _MEMmax , the _depletion voltage is _represented by V _PD0 , the reset voltage is represented by V _rst , and the FD output voltage that is a desired voltage in the floating diffusion (FD) is represented by ΔV _FD. .

Further, the depletion voltage _VPD0 is set so as to satisfy the following expression. However, the saturation charge amount of the charge storage capacitor is Q _MEMS , the photodiode voltage when the charge is accumulated by the saturation charge amount Q _MEMS is V _PDQ , and the saturation charge amount of the photodiode is Q _PDM .

Q _PDM ≧ Q _MEMS × V _PD0 / (V _PD0 −V _PDQ )

  A focus detection apparatus line sensor according to another aspect of the present invention includes a photoelectric conversion element, a charge storage unit that stores charges accumulated in the photoelectric conversion element, and transfers charges accumulated in the photoelectric conversion element to the charge storage unit. A charge transfer gate, a pixel signal readout circuit that outputs the accumulated charge transferred to the charge storage unit as a pixel signal, and a charge discharge gate that discharges the charge accumulated in the photoelectric conversion element, and is discharged from the charge discharge gate When the maximum number of charges is larger than the number of charges generated in the photoelectric conversion element at the maximum illuminance, and the charge corresponding to the saturation charge amount of the charge storage portion is accumulated in the photoelectric conversion element at the minimum illuminance In this case, the threshold voltage of the charge discharge gate and the depletion voltage of the photoelectric conversion element are determined so as to be smaller than the number of charges generated in the photoelectric conversion element.

  As described above, according to the present invention, it is possible to perform focus detection with a wide dynamic range while suppressing blooming.

It is a typical internal block diagram of the digital camera which is this embodiment. It is the figure which showed the board | substrate arrangement | positioning of a focus detection part. It is a block diagram of a focus detection part. It is the figure which showed the connection relation of a line sensor, a monitor sensor, and an AGC circuit. It is an electric circuit diagram of a pixel signal readout circuit for line sensors. FIG. 6 is a schematic cross-sectional view of the pixel signal readout circuit of FIG. 5. It is an electric circuit diagram of a monitor sensor. It is the figure which showed the state in which the electric charge was accumulate | stored in the photodiode by receiving the light from a to-be-photographed object. It is the figure which showed the state from which an electric charge is transferred from a photodiode. It is the figure which showed the state from which the unnecessary charge is discharged | emitted from the photodiode. It is the figure which showed the reset state of the floating diffusion. It is the figure which showed the reset state of the floating diffusion. It is the figure which showed the charge transfer from a charge storage capacity to a floating diffusion. It is the figure which showed the charge transfer from a charge storage capacity to a floating diffusion. It is the figure which showed the relationship between the number of electric charges which flow out (leak) from a photodiode exceeding an anti-blooming gate (ABG), and a photodiode voltage. It is the figure which showed the electric charge outflow at the time of maximum illumination intensity. It is the figure which showed the electric charge outflow at the time of minimum illumination intensity. It is the figure which showed the relationship between the depletion voltage and the maximum voltage of charge storage capacity.

  Hereinafter, the present embodiment will be described with reference to the drawings.

  FIG. 1 is a schematic internal configuration diagram of a digital camera according to the present embodiment.

  The single-lens reflex digital camera 10 includes a main body 12 and an interchangeable lens 14 that can be attached to and detached from the main body 12. Inside the main body 12, a pentagonal roof prism (hereinafter referred to as a pentaprism) 16, a quick return mirror 18, a focal plane. An image sensor 22 such as a shutter 20 and a CCD is provided.

  A system control circuit 30 including a ROM 36, a RAM 37, and a CPU 38 controls the photographing operation of the camera 10, and outputs control signals to the peripheral control circuit 32, the display unit 33, the AF module 24, the photometric IC 23, the EEPROM 39, and the like. The peripheral control circuit 32 controls the exposure mechanism such as the focal plane shutter 20, the diaphragm (not shown), the image sensor 22, and acquires lens information from the lens memory 13.

  When the camera 10 is turned on by operating a power button (not shown), the photographing mode is set. The light passing through the photographic optical system 15 is guided toward the pentaprism 16 by the quick return mirror 18, and a subject image is formed on the focus plate 17. The user visually recognizes the subject image through a finder window (not shown). When a release button (not shown) is half-pressed for photographing, the photometry IC 23 arranged near the pentaprism 16 detects the brightness of the subject according to the TTL photometry method. The AF module 24 disposed below the quick return mirror 18 detects the in-focus state according to the phase difference method.

  A part of the light passing through the photographing optical system 15 passes through the quick return mirror 18 and is guided to the AF module 24 by the sub mirror 19. The AF module 24 includes a condenser lens 26, a separator lens 27, a field mask 29, and a focus detection unit 40. The AF module 24 includes a field mask 29 disposed at a position (conjugate surface) equivalent to the imaging surface (light receiving surface of the image sensor 22). The divided subject image is re-imaged on the focus detection unit 40 by the separator lens 27. The focus detection unit 40 outputs an image signal of a subject image projected as a pair.

  The system control circuit 30 performs defocus amount and focus adjustment based on the image signal sent from the AF module 24. That is, a control signal is output to the AF motor driver 34 according to the defocus amount detected by the AF module 24 and the direction of the focus shift. The AF motor 35 shifts the focusing lens in the photographing optical system 15 based on the drive signal from the AF motor driver 34. A series of focus detection and lens driving are performed until the in-focus state is reached.

  When focus adjustment is performed in the release half-pressed state and the brightness of the subject is detected, the system control circuit 30 calculates and determines an exposure value, that is, a shutter speed and an aperture value. When the release button is fully pressed, a series of recording operation processing is executed. That is, the subject image is formed on the image sensor 22 by the operations of the quick return mirror 18, the diaphragm, and the shutter 20, and an image signal for one frame is output from the image sensor 22 to the signal processing circuit 25. In the signal processing circuit 25, digital image data is generated, and the image data is stored in the EEPROM 39.

  FIG. 2 is a diagram illustrating a substrate arrangement of the focus detection unit.

  The focus detection unit 40 is configured by an integrated substrate on which a plurality of CMOS type line sensors are arranged. On the surface of the focus detection device 40, line sensor groups EA1 and EA2 are installed in the vertical direction of the substrate along the vertical direction of the subject image, and the line sensor groups EB1 and EB2 are set in the horizontal direction of the substrate along the horizontal direction of the subject image. is set up. The line sensor groups EA1, EA2, and EBA1, EB2 face each other across the center of the substrate.

  The imaging optical system including the field mask 29, the condenser lens 26, and the separator lens 27 forms two sets of subject image pairs by pupil division, the projection area where the line sensor groups EA1 and EA2 are arranged, and the line sensor group EB1. A pair of subject images are formed on the projection area where EB2 is arranged.

  Each line sensor group is composed of a plurality of line sensors arranged in the left-right or up-down direction at predetermined intervals, and the line sensors in the line sensor groups EA1, EA2 are arranged in parallel in the left-right direction, and the line sensors in the line sensor groups EB1, EB2 Are in parallel along the vertical direction. Each line sensor includes a plurality of photodiodes and a pixel signal readout circuit (both not shown here).

  The line sensor group EA1 includes nine line sensors LSA1 to LSA9, and functions as a reference line sensor. On the other hand, the line sensors LSA11 to LSA19 constituting the line sensor group EA2 function as reference line sensors. Similarly, the line sensors LSB1 to LSB5 constituting the line sensor group EB1 function as reference sensors, and the line sensors LSB6 to LSB10 constituting the line sensor group EB2 function as reference line sensors.

  Vertical shift registers VSR1 to VSR9 and VSS1 to VSS5 for charge transfer are installed on the side of the line sensors LSA1 to LSA9 of the line sensor group EA1 and the line sensors LSB1 to LSB5 of the line sensor group EB1, and the line sensor groups EA2 and EB2 The vertical shift registers VSR11 to VSR19 and VSS6 to VSS10 are similarly arranged for the respective line sensors.

  In the line sensor groups EA1 and EB1, a series of monitor sensors LMA1 to LMA9 and LMB1 to LMB5 are arranged on the corresponding line sensor side. Each of the monitor sensors LMA1 to LMA9 and LMB1 to LMB5 has a configuration in which a plurality of minute sensors are arranged in parallel along the line sensor, and the corresponding line sensor region is divided into a plurality of areas for monitoring.

  The monitor sensors LMA1 to LMA9 are arranged in a line along the side surfaces of the line sensors LSA1 to LSA9, respectively, receive the same light amount (light intensity) received by the corresponding line sensor, and a signal corresponding to the light amount is used as a monitor signal. Output. Monitor sensors LMB1 to LMB5 also output monitor signals to monitor the amount of light received by line sensors LSB1 to LSB5.

  Further, OB (Optical Black) monitor sensors OBA1 to OBA9 and OBB1 to OBB5 for detecting dark current components are arranged beside each monitor sensor of the line sensor groups EA1 and EB1, and the detected dark current components are Based on this, the monitor signal output from the monitor sensor is corrected.

  The AGC circuit 42 compares the monitor signal value sequentially output from each monitor sensor with a threshold value, and controls the integration time of the line sensor by auto gain control. The threshold value is an index value for determining whether or not the amount of light necessary for focus detection is incident on the target line sensor, and is set to prevent the line sensor from overflowing.

  When the monitor signal value exceeds the threshold value, a monitor signal indicating completion of integration is sent to the logic circuit 44. The logic circuit 44 outputs a control signal for terminating the charge accumulation (integration) of the corresponding line sensor, that is, the line sensor to be monitored. When the control signal is transmitted to the line sensor, the charge accumulation ends and the charge is temporarily stored in the line sensor.

  The charge accumulation time of the line sensor is independently controlled for each monitoring target area of the licensor, and the charge accumulation time of each line sensor is adjusted according to the light intensity distribution of the subject. When the charge accumulation of all the line sensors is completed, the pixel signals are sequentially read out by the vertical shift register of each line sensor and the horizontal shift registers of the column circuits 45 and 46 having a charge transfer function. As a result, the accumulated charge is subjected to voltage conversion and amplification processing in a pixel signal readout circuit (not shown here) of each line sensor, and a pixel signal is output.

  A series of pixel signals read from each line sensor is subjected to noise removal processing and amplification processing in the column circuits 45 and 46. The series of pixel signals is sent to the system control circuit 30 as an image signal of the subject image. In the system control circuit 30, the phase difference is detected based on the image signal of the pair of line sensors, and the defocus amount is obtained.

  FIG. 3 is a block diagram of the focus detection unit. FIG. 4 is a diagram illustrating a connection relationship between the line sensor, the monitor sensor, and the AGC circuit. The control of the charge accumulation time (integration time) of the line sensor will be described with reference to FIGS.

  In FIG. 3, only the line sensor pairs LSA5 and LSA15 extending along the vertical direction, the line sensor pairs LSB3 and LSB8 extending along the horizontal direction, and the monitor sensors LMA5 and LMB3 corresponding thereto are shown, and the other lines Sensors and monitor sensors are omitted. Further, in FIG. 4, the line sensor and the monitor sensor are illustrated in an arrangement different from the actual arrangement illustrated in FIG. 2 for easy understanding of the charge accumulation end timing of the line sensor.

  The line sensor LSA5 has a configuration in which photodiode pairs facing each other across the line sensor pixel signal readout circuit PSA5 are arranged in the vertical direction, and charges are read from each photodiode by the line sensor pixel signal readout circuit. Similarly, the other line sensors LSA15, LSB3, and LSB8 have a configuration in which a pair of photodiodes facing each other across the pixel signal readout circuits PSA15, PSB3, and PSB8 are arranged in parallel.

  The monitor sensor LMA5 arranged beside the line sensor LSA5 has a configuration in which a plurality of minute sensors having photodiodes are arranged in the vertical direction, and is accumulated by a monitor sensor pixel signal readout circuit (not shown here). The charge is read out. The monitor sensor LSB3 arranged beside the line sensor LSB3 has the same configuration.

The AGC circuit 42 _HS detects whether or not the voltage level of the monitor signal output from the monitor sensor LMB3 exceeds a threshold value, and outputs a monitor signal notifying the end of charge accumulation (integration) to the logic circuit 44 when the threshold value is reached. . The charge accumulation time (integration time) of the line sensor LSB3 to be monitored is adjusted by the AGC circuit _42HS . The threshold value of the AGC circuit 42 _HS is set to a value that takes into consideration the dynamic range of the line sensor LSB 3, and is set by the VMS signal from the logic circuit 44. The AGC circuit 42 _V5 that monitors the monitor sensor LMA5 has the same configuration.

  In FIG. 4, one line sensor LSB3 is illustrated. The monitor sensor LMB3 at the opposite position is composed of a plurality of minute sensors each having a photodiode, and here, for convenience, it is assumed to be composed of three minute sensors M1 to M3, M4 to M6, and M7 to M9. .

  As described above, the line sensor LSB3 has a configuration in which a large number of photodiode pairs are arranged, and the micro sensors M1 to M9 of the monitor sensor LMB3 perform monitoring on a region of a predetermined number of assigned photodiodes. Yes.

Here, three distance measuring zones SZ1 to SZ3 are defined for the line sensor LSB3, and the AGC circuit 42 _HS is a group of monitor sensors connected to the monitor sensors M1 to M3, M4 to M6, and M7 to M9, respectively. 42H ₃₁ , 42H ₃₂ , and 42H ₃₃ , which adjust the integration times of the distance measurement zones SZ1 to SZ3, respectively. The monitor sensor groups 42H ₃₁ , 42H ₃₂ , and 42H ₃₃ detect the output signals from the micro sensors M1 to M3, M4 to M6, and M7 to M9, respectively, so that three monitor sensor detections are performed in accordance with the ranging zones SZ1 to SZ3. The units AGC1 to AGC3, AGC4 to AGC6, and AGC7 to AGC9 are provided.

  Taking the distance measuring zone SZ1 of the line sensor LSB3 as an example, when a pair of subject images by pupil division is projected onto the focus detection unit 40, charges are accumulated in the distance measuring zone SZ1 of the line sensor LSA1 and the monitor sensors M1 to M3. Is done. The amounts of light input to the three microsensors M1 to M3 differ depending on the brightness distribution of the subject, and therefore the timings at which the monitor sensor detection units AGC1 to AGC3 output monitor signals that notify the end of integration are different.

  For example, when strong light is incident on the micro sensors M1 of the monitor sensors M1 to M3, but the light incident on the micro sensors M2 and M3 is weak, the voltage value of the monitor signal input to the detection unit AGC1 is detected by the detection units AG2 and AG3. First, the monitor signal that exceeds the threshold and notifies the end of charge accumulation is output to the logic circuit 44.

  When the logic circuit 44 receives the end signal from the detection unit AGC1, the logic circuit 44 ends the charge accumulation in the distance measuring zone of the line sensor LSB3. The charges accumulated in each photodiode in the distance measuring zone SZ1 of the line sensor LSB3 are temporarily stored in a charge accumulation capacitor (not shown here). Even when the detection unit AGC2 or the detection unit AGC3 outputs the monitor signal for completion of integration earliest, the charge accumulation in the distance measuring zone SZ1 of the line sensor LSB3 is similarly ended.

  Such charge accumulation of the line sensor is performed in the same manner for the distance measuring zones SZ2 and SZ3 of the line sensor LSB3. That is, when a monitor signal exceeding the threshold is output in any of the micro sensors M4 to M6 and M7 to M9, the charge accumulation in the distance measuring zones SZ2 and SZ3 of the line sensor LSB3 is terminated at that time.

  When charge accumulation of all the line sensors is completed (or a predetermined time elapses before that), a pixel signal is output from each line sensor. Pixel signals output from the line sensor groups EA1 and EA2 (see FIG. 2) in the vertical direction are transferred to the column circuit 46 (see FIGS. 2 and 3). On the other hand, pixel signals output from the line sensor groups EB1 and EB2 in the left-right direction are transferred to the column circuit 45.

  In the column circuits 45 and 46, noise removal and amplification processing are performed on the pixel signals that are output. As a result, the image signals corresponding to the pair of subject images for the line sensor groups EA 1 and EA 2 are offset by the offset circuit 64 and then output to the system control circuit 30 through the output switching circuit 66. On the other hand, the image signals corresponding to the pair of subject images for the line sensor groups EB 1 and EB 2 are offset by the offset circuit 62 and then output to the system control circuit 30 through the output switching circuit 68.

  The system control circuit 30 controls the operation of the logic circuit 44 and selectively detects the monitor signal from each AGC circuit. In the monitor output selection circuit 56, the monitor signal designated by the system control circuit 30 is output and sent from the output switching circuit 68 to the system control circuit 30. The OB monitor signal selectively output from the OB monitor output selection circuit 52 is sent to the system control circuit 30 via the output switching circuit 66. Note that the reference potentials of the output signals of the OB monitor signal and the monitor signal are shifted by the level shift circuits 53 and 55, respectively.

  When the charge accumulation of the line sensor is finished, the logic circuit 44 outputs a signal notifying the end of charge accumulation to the system control circuit 30 through the selection circuit 58. When charge accumulation of all line sensors is completed, a signal notifying completion of charge accumulation is sent to the system control circuit 30 through the selection circuit 60. The system control circuit 30 controls the integration time of each line sensor and the gain of the AGC circuit based on these monitor signals and end signals.

  FIG. 5 is an electric circuit diagram of the line sensor pixel signal readout circuit. FIG. 6 is a schematic cross-sectional view of the pixel signal readout circuit of FIG. FIG. 7 is an electric circuit diagram of the monitor sensor.

  FIG. 5 shows a circuit configuration relating to a pair of photodiodes 120Aj and 120Bj in the line sensor LSB3 and a line sensor pixel signal readout circuit 130j connected thereto. The photodiode pairs 120Aj and 120Bj are both connected to the line sensor pixel signal readout circuit 130j.

  The pixel signal readout circuit 130j for the line sensor includes anti-blooming gates (ABG) 121A and 121B for controlling the sweeping of unnecessary charges, charge storage capacitors (MEM) 124A and 124B for temporarily storing charges, a photodiode pair 120Aj, Transfer gates (TG) 122A and 122B are provided for transferring the charges accumulated in 120Bj to the charge storage capacitors 124A and 124B.

  Furthermore, the line sensor pixel signal readout circuit 130j includes a charge detection mechanism based on an FDA (Floating Diffusion Amplifier), and a floating diffusion (FD) 125 into which charges are injected and a floating charge that transfers the accumulated charges in the charge accumulation capacitors 124A and 124B. Diffusion gates (FDG) 123A and 123B, a reset gate (RG) 26, a source follower amplifier 127, and a selection gate 128 are provided.

FIG. 6 shows a substrate cross section of the focus detection unit 40 in the vicinity of the photodiode 120Aj. A p-type layer (p-well) is formed on an n-sub substrate, and a pn junction photodiode 120Aj is formed thereon. Further, a buried photodiode is formed by forming a p ⁺ layer on the surface of the photodiode 120Aj. The charge storage capacitor 124A has a similar MOS diode configuration.

  An opening (not shown) is provided above the photodiode 120Aj, and light other than the photodiode 120Aj is prevented from entering by covering a portion excluding the opening with a light shielding film.

  The anti-blooming gate (ABG) 121A, the transfer gate (TG) 122A, the floating diffusion gate (FDG) 123A, and the reset gate (RG) 124A are each configured by a transistor having a charge transfer electrode (gate electrode) disposed on the surface. Each pulse signal is input in accordance with the charge read timing.

By opening / closing the transfer gate (TG) 122A and the floating diffusion gate (FDG) 123A, charges are transferred to the charge storage capacitor 124A and the floating diffusion (FD) 125 composed of n ⁺ layers. Further, by opening / closing the anti-blooming gate (ABG) 121A, unnecessary charges of the photodiode 120Aj are swept out to the power supply VDDA serving as a drain through the n ⁺ layer 129.

  FIG. 7 shows a minute sensor 140m that monitors the photodiode 120Aj. The monitor sensor pixel signal readout circuit 144 connected to the photodiode 142 includes an anti-blooming gate (ABG) 151, a transfer gate (TG) 152, a reset gate (RG) 154, a charge storage capacitor (MEM) 153, and a source. A follower amplifier 155 is provided.

  When light from the subject reaches the line sensor, a signal charge (pixel signal) is generated by photoelectric conversion of the photodiodes 120Aj and 120Bj, and the charge is accumulated according to the amount of light. On the other hand, the signal charge generated in the photoelectric conversion unit 142 of the monitor sensor 140m is output to the AGC circuit shown in FIGS.

  When the monitor signal exceeds the threshold value, the charge accumulation of the photodiode 120Aj ends, and the accumulated charge is temporarily transferred to the charge storage capacitors 123A and 123B through the transfer gates 122A and 122B. The accumulated charges are stored in the charge accumulation capacitors 123A and 123B, respectively, until the charge accumulation of the other photodiode pairs is completed.

  When the charge accumulation of the other line sensors is completed, the charges generated in the photodiodes 120Aj and 120Bj and respectively stored in the charge storage capacitors 123A and 123B are separately or mixed and injected into the floating diffusion (FD) 125. The Then, a pixel signal (voltage signal) is output by the source follower amplifier 127. When the pixel signal is output, the floating diffusion 124 is reset by the operation of the reset gate 126.

  Next, a flow from charge generation to pixel signal readout will be described with reference to FIGS. 8 to 14 show the potential state of each component of the substrate in accordance with the circuit cross section shown in FIG.

FIG. 8 is a diagram showing a state where charges are accumulated in the photodiode upon receiving light from the subject. It represents depletion voltage when charge in the photodiode 120Aj is not stored in V _PD0, the substrate surface of the focus detector 40 and the reference voltage 0.

  During charge accumulation, the anti-blooming gate (ABG) 121A and the transfer gate (TG) 122A are at a low level, and charges are accumulated in the photodiode 120Aj. The ABG 121A is set to a low level and an OFF state so that charges are not discharged through the ABG 121A during charge accumulation. A voltage Vt at the low level of the ABG 121A (hereinafter referred to as a threshold voltage) Vt becomes an electrical barrier during charge accumulation to prevent charge leakage, while overcoming the unnecessary charge generated by excessive light exceeds the barrier of the ABG 121A. It is set to discharge sufficiently.

  FIG. 9 is a diagram showing a state where charges are transferred from the photodiode. When the charge accumulation of the photodiode 120Aj is completed, the transfer gate (TG) 122A is set to the high level, that is, the ON state. As a result, the charge accumulated in the photodiode 120Aj is temporarily stored in the charge storage capacitor 124A.

  FIG. 10 is a diagram showing a state in which unnecessary charges are discharged from the photodiode. When the charge is transferred to the charge storage capacitor 124A, the ABG 121A goes high so that blooming does not occur. Thereby, unnecessary charges generated in the photodiode 120Aj are discharged.

  11 and 12 are diagrams showing the reset state of the floating diffusion. By switching the reset gate (RG) 126 to the high level, the potential of the floating diffusion 125 is reset to the initial state, and the reset gate (RG) 126 is set to the low level again to detect the reset voltage Vrst.

  13 and 14 are diagrams showing charge transfer from the charge storage capacitor to the floating diffusion. By setting the floating diffusion gate (FDG) 125 to a high level, the charges stored in the charge storage capacitor 124A are transferred to the floating diffusion (FD) 125. Then, by switching the floating diffusion gate (FDG) 125 to the low level again, the voltage change of the floating diffusion (FD) 125 is detected as the voltage of the pixel signal.

  FIG. 15 is a diagram showing the relationship between the number of charges that flow out (leak) from the photodiode beyond the anti-blooming gate (ABG) and the photodiode voltage. FIG. 16 is a diagram illustrating the charge outflow at the time of the maximum illuminance. FIG. 17 is a diagram illustrating the outflow of charge at the minimum illuminance. The threshold voltage setting of the anti-blooming gate (ABG) will be described with reference to FIGS.

In the graph shown in FIG. 15, the horizontal axis represents the photodiode voltage V _PD (V), and the vertical axis represents the number of leaked electrons from the anti-blooming gate (ABG) (hereinafter referred to as the number of outflow charges) LQ (e− / s). and then graphs the relationship between the photo-diode voltage V _PD and the outlet charge number LQ. Photodiode voltage V _PD, when no charge is accumulated, i.e. depletion voltage V _PD0 when light is not irradiated becomes the maximum, gradually decreases the photodiode voltage V _PD in accordance with the light intensity increases.

The photodiode voltage V _PD and the number LQ of outflow charges have an exponential relationship, and the number LQ of outflow charges increases as the photodiode voltage V _PD (accumulated charge) increases. When the threshold voltage Vt of the anti-blooming gate (ABG) and the depletion voltage V _PD0 are determined, the relationship between the photodiode voltage V _PD and the number LQ of outflow charges follows the straight line Ls shown in FIG. That outflow charge number LQ at a certain photodiode voltage _{V PD} is determined by a straight line Ls.

Here, the straight line Ls is defined when the depletion voltage V _PD0 = 1V, the saturation charge photodiode voltage (hereinafter referred to as saturation photodiode voltage) V _PDQ = 0V, and the threshold voltage Vt is Vts (= 0.5 V). Is done. The straight line Ls indicating the relationship between the photodiode voltage V _PD and the number LQ of outflow charges changes the slope (proportional magnitude) and intercept of the line by changing the performance characteristics of the line sensor, the depletion voltage V _PD0 , and the threshold voltage Vts. .

  Since the threshold voltage Vt indicates the size of the barrier when the charge exceeds the anti-blooming gate (ABG), the number LQ of outflow charges also changes depending on the size of the threshold voltage Vt. When the threshold voltage Vt increases, the electric charge does not easily exceed the barrier of the floating diffusion gate (ABG), and the number LQ of outflow charges decreases. Conversely, when the threshold voltage Vt is set to a small value, charges easily leak from the floating diffusion gate (ABG).

FIG. 16 shows the charge accumulated in the photodiode due to very strong light. When the charge is accumulated to near the saturation charge amount _{QPDm of the} photodiode by strong light, the charge is likely to overflow from the photodiode. Therefore, it is necessary to set a threshold voltage Vt that allows the charge to flow out through the anti-blooming gate (ABG) without leaking to the transfer gate (TG).

On the other hand, FIG. 17 shows the charge accumulated in the photodiode due to very weak light. Even when the light intensity is low, some of the charge flows out beyond the barrier of the floating diffusion gate (ABG). If the outflow charge number LQ is not suppressed as much as possible when the light is weak, even if the charge is accumulated in the photodiode up to the vicinity of the threshold voltage of the AGC circuit, the charge flows out at a pace exceeding the number of charges generated in the photodiode, No charge is accumulated until the number of charges corresponding to the threshold value of the AGC circuit. That is, it is necessary to suppress the number of charges that leak in a situation where charges corresponding to the saturation charge amount _QMEMS of the charge storage capacitor (MEM) are stored in the photodiode.

As described above, when the illuminance is very large, the excessive charge generated must be sufficiently discharged, and when the illuminance is very small, the number of leaked charges must be sufficiently small. Therefore, the threshold voltage Vt, set to a value based on the number of charges Q _min generated in the photodiode when the charge number Q _max and minimum illuminance generated in the photodiode at the maximum illumination intensity.

  However, the maximum illuminance is a limit illuminance that allows linear output of the photodiode, and is determined in advance by the performance characteristics of the photodiode. The minimum illuminance indicates the limit illuminance that can be photoelectrically converted, and is similarly defined by the performance characteristics of the photodiode.

In the straight line Ls in FIG. 15, the number of charges flowing out through the anti-blooming gate (ABG) at the maximum illuminance is equal to the number of generated charges Q _max . As described above, when the threshold voltage Vts of the straight line Ls is further reduced, the number of outflow charges increases, so that the straight line Ls moves upward. Accordingly, by setting a threshold voltage Vt smaller than the threshold voltage Vts of the straight line Ls, surplus charges generated at the maximum illuminance are discharged through the anti-blooming gate (ABG) and do not flow into the charge storage capacitor or the like.

  On the other hand, when considering the limit of the threshold voltage Vt at the minimum illuminance, it is necessary to set the threshold voltage Vt that becomes the limit when the charge is accumulated in the photodiode by the amount of saturation charge of the charge storage capacitor. When the light intensity is very small, the saturation charge amount QMEMs of the charge storage capacitor is reached over a long exposure period. In this situation, if the accumulated charge of the photodiode leaks through the ABG more than the number of charges generated in the photodiode, it will not be possible to transfer the accumulated charge indefinitely under the condition of the minimum illuminance.

Therefore, when the photodiode voltage V _PD is the saturation photodiode voltage V _PDQ corresponding to the saturation charge amount Q _MEMS of the charge storage capacitor (MEM) (see FIG. 15), the number of charges Q at the minimum illuminance generated in the photodiode. _The number of charges leaking out compared to _min must be sufficiently small.

The straight line Lm shown in FIG. 15 is determined according to the threshold voltage Vtm and the depletion voltage V ′ _PD0 , and the number LQ of outflow charges when the photodiode voltage V _PD is the saturated photodiode voltage V _PDQ is the minimum illuminance. equal to the generated charge number _{Q min.} Therefore, by setting a threshold voltage Vt that is higher than the threshold voltage Vtm of the straight line Lm, the number of leaked charges can be made smaller than the number of generated charges.

A region TR sandwiched between the straight line Lm and the straight line Ls satisfies the conditions required for the maximum illuminance and the minimum illuminance. Therefore, the depletion voltage V _{PD0 of} the photodiode and the threshold voltage V _t of the anti-blooming gate (ABG) may be determined so that the proportional relationship between the photodiode voltage V _PD and the number LQ of outflow charges falls within the region TR.

However, in order to ensure a wide dynamic range, the outflow charge number LQ when the minimum illuminance, it is desirable to keep the following 1/100 of generating charge number Q _min. In this case, the depletion voltage V _{PD0 of} the photodiode and the threshold voltage V _{t of the} anti-blooming gate (ABG) so as to fall within the region TS sandwiched between the straight line Ln and the straight line Ls in which the number LQ of the outflow charges is 1/100 times. Is set.

The threshold voltage Vt of the anti-blooming gate (ABG) and the depletion voltage V _PD0 of the photodiode set based on such conditions satisfy both the prevention of the occurrence of anti-blooming and the securing of a wide dynamic range. On the other hand, the house in the substrate detector of the focus detection unit 40 is required to have a depletion voltage V _PD0 that satisfies the conditions described below.

FIG. 18 is a diagram showing the relationship between the depletion voltage and the maximum voltage of the charge storage capacitor. The voltage ΔV _MEMmax corresponding to the saturation charge amount of the charge storage capacitor, the _depletion voltage V _PD0 , the reset voltage V _rst, and the FD output voltage ΔV _FD must satisfy the following relational expression. However, the FD output voltage ΔV _FD indicates a desired voltage in the floating diffusion (FD).

ΔV _MEMmax ≦ V _rst − (V _PD0 + ΔV _FD ) (1)

(1) requests that there is a potential difference [Delta] V _G shown in FIG. 18, so as to satisfy the above equation (1), the depletion voltage is set.

Furthermore, the depletion voltage _VPD0 is set so as to satisfy the following expression. However, the saturation charge amount of the charge storage capacitor is Q _MEMS , the photodiode voltage when the charge is accumulated by the saturation charge amount Q _MEMS is V _PDQ , and the saturation charge amount of the photodiode is Q _PDM .

Q _PDM ≧ Q _MEMS × V _PD0 / (V _PD0 −V _PDM ) (2)

The equation (2) indicates that the saturated charge amount Q _PDM of the photodiode is sufficiently larger than the saturated charge amount Q _MEMS of the charge storage capacitor (MEM), that is, the photodiode can store charges sufficiently compared to the charge storage capacitor. It is determined whether or not.

  As described above, according to the present embodiment, the cross-shaped line sensor groups EA1, EA2, EB1, and EB2 including a plurality of line sensors are formed on the substrate surface of the focus detection unit 40 of the AF module 24, and the line sensor group. Monitor sensors MA1 to MA9 and MB1 to MB5 for monitoring incident light of the line sensors are arranged beside each of the line sensors EA1 and EA2.

  In each of the plurality of photodiodes and line sensor pixel signal readout circuits constituting each line sensor, an anti-blooming gate (ABG) that discharges surplus charges by switching control is provided near the photodiodes, and charges are accumulated in the photodiodes. During this time, the anti-blooming gate (ABG) becomes a barrier against charge leakage.

The threshold voltage Vt of the anti-blooming gate and the depletion voltage V _PD0 of the photodiode are those of the outflow charge number LQ discharged through the anti-blooming gate (ABG) rather than the generated charge number Q _max at the maximum illuminance. as many, and the number of outflow charges LQ is smaller than the number of charges Q _min to be at the minimum illuminance occurs in a state of being charge accumulated in the saturated charge amount Q _MEMS only photodiodes of the charge storage capacitor (MEM) Stipulated.

  In the case of focus detection, unlike image sensors, the charge accumulation time of each line sensor is controlled separately, and it is necessary to detect luminance changes such as edge portions even with low light intensity, so a wide dynamic lens is required. Is done. According to the present embodiment, blooming does not occur even when the dynamic range of the line sensor is set sufficiently wide, the accumulated charge of the photodiode is output regardless of the light intensity, and the luminance level of each pixel can be output with high accuracy. It becomes possible.

  The distance measurement may be configured to measure multiple points or only the center of the screen, and the number of line sensors, the number of line sensor groups, and the arrangement direction of the line sensors are arbitrary. Further, the present invention may be applied to a camera other than a single-lens reflex camera, or may be applied to a photographing apparatus having a camera function such as a mobile phone.

10 SLR digital camera 24 AF module (focus detection device)
40 Focus detection unit 120Aj, 120Bj Photodiode (photoelectric conversion element)
121A Anti-blooming gate (charge discharge gate)
122A transfer gate 124A charge storage capacity (charge storage unit)
Vt threshold voltage V _PD0 depletion voltage

Claims (7)

A plurality of line sensors arranged in the projection area of the subject image;
A plurality of monitor sensors arranged on the side of the plurality of line sensors, respectively, for monitoring the amount of light received by the corresponding line sensors;
Image signal output means for outputting an image signal of a subject image based on charges accumulated in the plurality of line sensors,
The line sensor is an address-type image sensor, and includes a photoelectric conversion element, a charge storage unit that stores charges accumulated in the photoelectric conversion element, and a charge accumulated in the photoelectric conversion element in the charge storage unit. A charge transfer gate for transferring, and a charge discharge gate for discharging charge accumulated in the photoelectric conversion element,
The number of charges discharged from the charge discharge gate is larger than the number of charges generated in the photoelectric conversion element when the line sensor has the maximum illuminance, and is the minimum illuminance of the line sensor . Depletion of the threshold voltage of the charge discharge gate and the photoelectric conversion element so that the charge corresponding to the saturation charge amount is smaller than the number of charges generated in the photoelectric conversion element when the charge is stored in the photoelectric conversion element. A focus detection apparatus characterized in that a voltage is determined. When the electric charge corresponding to the saturation charge amount of the charge storage portion is accumulated in the photoelectric conversion element at the minimum illuminance, the number of electric charges discharged from the charge discharge gate is generated in the photoelectric conversion element. The focus detection apparatus according to claim 1, wherein a threshold voltage of the unnecessary charge discharge gate and a depletion voltage of the photoelectric conversion element are determined so as to be 1/10 or less of the number of charges. The focus detection apparatus according to claim 1, wherein the depletion voltage satisfies the following expression.

ΔV _MEMmax ≦ V _rst − (V _PD0 + ΔV _FD ) (1)

However, the photoelectric conversion element is a photodiode, the photodiode voltage corresponding to the saturation charge amount of the charge storage portion is ΔV _MEMmax , the _depletion voltage is V _PD0 , the reset voltage is V _rst , and the desired voltage in the floating diffusion (FD) The FD output voltage is expressed as ΔV _FD . The focus detection apparatus according to claim 1, wherein the depletion voltage V _PD0 satisfies the following expression.

Q _PDM ≧ Q _MEMS × V _PD0 / (V _PD0 −V _PDQ ) (2)

However, the photoelectric conversion element is a photodiode, the saturation charge amount of the charge storage capacitor is Q _MEMS , the photodiode voltage when the charge is accumulated by the saturation charge amount Q _MEMS is V _PDQ , and the saturation charge amount of the photodiode is Q _PDM .   An imaging device comprising the focus detection device according to claim 1. A line sensor for focus detection which is an address type image sensor,
A photoelectric conversion element;
A charge storage unit for storing charges accumulated in the photoelectric conversion element;
A charge transfer gate for transferring the charge accumulated in the photoelectric conversion element to the charge storage unit;
A pixel signal readout circuit that outputs the accumulated charge transferred to the charge storage unit as an image transfer signal;
A charge discharge gate for discharging charges accumulated in the photoelectric conversion element,
The number of charges discharged from the charge discharge gate is larger than the number of charges generated in the photoelectric conversion element when the line sensor has the maximum illuminance, and is the minimum illuminance of the line sensor . Depletion of the threshold voltage of the charge discharge gate and the photoelectric conversion element so that the charge corresponding to the saturation charge amount is smaller than the number of charges generated in the photoelectric conversion element when the charge is stored in the photoelectric conversion element. A focus detection line sensor characterized in that a voltage is determined. The number of outflow charges L _Q flowing out of the photoelectric conversion element beyond the charge discharge gate is represented by the vertical axis and the voltage V _PD of the photoelectric conversion element is represented by the horizontal axis, and the number of outflow charges L _Q and the photoelectric conversion element voltage V _PD In the graph showing the relationship, when the proportional relationship between the photoelectric conversion element voltage V _PD and the outflow charge number L _Q is the maximum illuminance of the line sensor, the number of charges generated in the photoelectric conversion element becomes equal to the outflow charge number L _Q. and the straight line Ls, the number of charges generated in the photoelectric conversion element when the minimum illuminance of the line sensors to fit in region TR sandwiched between the equal linear Lm outflow charge number L _Q, the discharge gate The focus detection apparatus according to claim 1, wherein a threshold voltage and a depletion voltage of the photoelectric conversion element are determined.

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