JP5419111B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a technique that is effective when used in a device including a plurality of functional blocks such as a one-chip microcomputer and a system LSI and including a step-down power supply circuit that steps down an external power supply.

  As an example of a large scale integrated circuit in which two step-down circuits for operation and standby are provided, and power consumption during standby is reduced by stopping the operation step-down circuit during standby. Japanese Laid-Open Patent Publication No. 02-244488 is disclosed as an example of a semiconductor integrated circuit device in which power efficiency is improved by properly using two types of step-down circuits (series type and switching type) depending on the operation mode.

Japanese Patent Laid-Open No. 02-244488 JP 2001-21640 A

  In a recent system LSI such as a one-chip microcomputer, the threshold voltage of a MOSFET (insulated gate field effect transistor) tends to decrease as the operating voltage decreases. However, when the threshold voltage is lowered, there arises a problem that the leakage current due to the subthreshold characteristic increases. Therefore, it is the simplest and most effective to partially turn off the circuit power supply during standby. However, Patent Document 1 is for a memory and does not support an operation mode of a microcomputer or the like. Further, neither of Patent Documents 1 and 2 considers the case where the step-down circuit is completely stopped during standby to drop the internal power supply voltage (output of the step-down circuit). In view of this, the present invention has been made by studying a step-down circuit that can cope with internal power-off.

  An object of the present invention is to provide a semiconductor integrated circuit device with reduced current consumption. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. The semiconductor device includes an external terminal, a first step-down circuit that receives the external power supply voltage supplied from the external terminal and outputs a first internal voltage lower than the external power supply voltage from the first output terminal, and the external power supply voltage. Receiving a first mode in which a second internal voltage lower than the external power supply voltage is output from the second output terminal; and a second mode in which a third internal voltage lower than the first and second internal voltages is output from the second output terminal. A second step-down circuit whose mode is switched, a first internal circuit including a first static RAM connected to the first output terminal and supplied with a ground voltage as a low power supply voltage, and connected to the second output terminal And a second internal circuit including a second static RAM to which the ground voltage is supplied as a lower power supply voltage. During standby, the second step-down circuit is controlled to the second mode, and the first internal voltage is supplied from the first step-down circuit as the high-level power supply voltage of the first internal circuit, so that the memory of the first static RAM is stored. The contents are retained, and the third internal voltage is supplied from the second step-down circuit as the high power supply voltage of the second internal circuit, and the stored contents of the second static RAM are lost .

  Power consumption in the standby mode and sleep mode can be greatly reduced.

1 is a block diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention. FIG. 2 is a block diagram illustrating an example of a step-down power supply circuit for an analog circuit in FIG. 1. FIG. 2 is a block diagram illustrating an example of a step-down power supply circuit for a digital circuit in FIG. 1. FIG. 2 is a block diagram illustrating an example of the reference voltage generation circuit of FIG. 1. FIG. 4 is a circuit diagram showing an embodiment of the step-down circuits 31 and 32 of FIG. 3. FIG. 3 is a circuit diagram showing an embodiment of the step-down circuit 21 of FIG. 2. FIG. 4 is a circuit diagram showing an embodiment of the step-down circuit 30 of FIG. 3. FIG. 3 is a circuit diagram showing an embodiment of the step-down circuit 20 of FIG. 2. FIG. 2 is a state transition diagram showing an embodiment of the one-chip microcomputer of FIG. 1. It is explanatory drawing of the operation state of the pressure | voltage fall circuit corresponding to the operation state of the microcomputer of FIG. It is a block diagram which shows one Example of the smoothing capacity | capacitance CA of FIG. It is a circuit diagram showing one embodiment of a level-up conversion circuit used in the present invention. It is a circuit diagram which shows another Example of the level-up conversion circuit used for this invention. It is a circuit diagram which shows another Example of the level-up conversion circuit used for this invention. It is a block diagram which shows another Example of the semiconductor integrated circuit device based on this invention. FIG. 16 is a block diagram showing an embodiment of the digital circuit step-down circuits 33 to 36 and the digital circuit 50 of FIG. 15. FIG. 16 is a circuit diagram illustrating an example of the level-down conversion circuit of FIG. 15. FIG. 16 is an explanatory diagram of an operation state of the step-down circuit corresponding to the operation state of the microcomputer of FIG. 15. FIG. 16 is a chip layout diagram showing an embodiment of the microcomputer of FIG. 15.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention. The semiconductor integrated circuit device shown in the figure is directed to a system LSI including a one-chip microcomputer or CPU. In the figure, 1 is a semiconductor integrated circuit chip, E is an external power supply which is a power supply potential as a first reference potential, and the voltage value is, for example, 3.3 V (volts). The semiconductor integrated circuit chip 1 has two power terminals, VCC and VCCI, and a ground potential (fourth reference potential) of a circuit such as 0 V (volts) as external terminals receiving the power potential supplied from the external power source. Three ground terminals are provided: VSSA, VSSD, and VSSI. The power supply terminal VCCI and the ground terminal VSSI are used as dedicated terminals for supplying the reference voltage generation circuit 10 with the operating voltage VDDI and the ground potential VSSI. Of the remaining two ground terminals, the ground terminal VSSA is used to supply a ground potential to the analog circuit step-down power supply circuits 20 and 21 and the analog circuit 40. The other ground terminal VSSD is used to supply a ground potential to the step-down power supply circuits for digital circuits 30 to 32, the digital circuit 50, and a state control circuit 60 described later. Although not shown, a power supply voltage terminal VCCQ and a ground terminal VSSQ are also provided for the input / output circuit.

  Reference numeral 10 denotes a reference voltage generation circuit which operates by receiving the power supply voltage VDDI supplied from the external terminal and the circuit ground potential VSSI, and includes a constant voltage generation circuit such as a known bandcap circuit (BGR). The reference voltages VREFA and VREFDA that are considered to be substantially constant without depending on the fluctuation of the external power supply voltage VCCI or the temperature fluctuation are formed. The voltage value of the reference voltage VREFA is, for example, 1.25 V (volts), and the voltage value of the reference voltage VREFD is, for example, 1.5 V (volts). In this embodiment, it is desirable to use independent power supply terminals VCCI and VSSI as shown in FIG. 1 as a countermeasure against power supply noise of the reference voltage generation circuit 10. In the case where it is unavoidable to share with other power supply terminals VCC, it is desirable to separate the power supply wiring from other circuits. In other words, a dedicated power supply line is provided to which only the reference voltage generation circuit 10 is connected from the electrode pad corresponding to the power supply terminal VCC.

  Reference numerals 20 and 21 denote step-down power supply circuits for analog circuits, which receive the reference voltage VREFA and form an internal voltage VDDA (second reference potential) for the analog circuit 40. The voltage value of internal voltage VDDA is set to, for example, 2.5 V (volts). The analog circuit step-down power supply circuits 20 and 21 operate by receiving a power supply voltage VCC supplied from an external terminal and a circuit ground potential VSSA. CA is an on-chip smoothing capacitive element (hereinafter also referred to as on-chip smoothing capacitor), and is between the output terminals (VDDA) of the analog circuit step-down power supply circuits 20 and 21 and the circuit ground potential VSSA. Provided.

  Reference numerals 30 to 32 denote step-down power supply circuits for digital circuits, which receive the reference voltage VREFD and form an internal voltage VDDD (third reference potential) for the digital circuit 50. The voltage value of internal voltage VDDD is set to 1.5 V (volt), for example. The digital circuit step-down power supply circuits 30 to 32 operate in response to a power supply voltage VCC supplied from an external terminal and a circuit ground potential VSSD. CD is an external smoothing capacitive element (hereinafter also referred to as an off-chip smoothing capacitor), and is connected to the output terminals (VDDD) of the step-down power supply circuits 30 to 32 for digital circuits through external terminals for connection. .

  Reference numeral 40 denotes an analog circuit, which includes, for example, a PLL (Phase Locked Loop) circuit, a DLL (Delay Locked Loop) circuit, an AD converter, a DA converter, and the like. VDDA and VSSA are used as the power source. Reference numeral 50 denotes a digital circuit, which includes a logic circuit such as a CPU and a memory circuit such as a ROM (Read Only Memory) and a RAM (Random Access Memory). VDDD and VSSD are used as the power source. A state control circuit 60 controls the operation state of the semiconductor integrated circuit 1 in accordance with the output signal S of the digital circuit 50 and the interrupt request signal IRQ, reset signal / RES, and standby signal / STBY signal input from the outside. VCC and VSSD are used as the power source. A level-up conversion circuit 70 converts the output signal S (VDDD level) of the digital circuit 50 into a VCC level corresponding to the operating voltage of the state control circuit 60.

  In the semiconductor integrated circuit device of this embodiment, a plurality of step-down power supply circuits 20, 21 and 30 to 32 are provided for the analog circuit 40 and the digital circuit 50, respectively, and correspond to the operating states of the analog circuit 40 and the digital circuit 50. The power consumption is reduced by turning off part or all of the power. This means that not only the operating voltage of the analog circuit 40 and the digital circuit 50 in the non-operating state is cut off, but also the operating current that forms the output voltage of the step-down power supply circuits 20, 21, and 30 to 32 corresponding thereto. Blocked.

  The state control circuit 60 is operated by the external power supply VCC instead of the internal power supply. Thus, when the analog circuit and the digital circuit do not operate, the current supply capability of the corresponding ones of the step-down power supply circuits 20, 21, and 30 to 32 is reduced to reduce the power consumption. The step-down power supply circuits 20 and 21 for analog circuits use on-chip smoothing capacitors CA, and the step-down circuit power supplies 30 to 32 for digital circuits use off-chip smoothing capacitors CD. The reason why the smoothing capacitor CA for the analog circuit is on-chip is to improve the frequency characteristics. In other words, when an off-chip smoothing capacitor is used, a parasitic inductance of a bonding wire or package is added, and the influence thereof can be prevented. Since the smoothing capacitor CD for digital circuits is required to support a large peak current rather than a frequency characteristic, it has a large capacitance value, for example, 0.1 μF to 1 μF, off-chip.

  FIG. 2 shows a block diagram of an embodiment of the step-down power supply circuit for the analog circuit of FIG. Reference numeral 20 denotes a circuit block as a standby voltage step-down circuit, which has a small current supply capability and reduces power consumption. This step-down circuit 20 is always operated. However, the speed is increased by inputting the enable signal EN1. Reference numeral 21 denotes a circuit block as a step-down circuit for operation, which has a large current supply capability and increases power consumption. The step-down circuit 21 is activated by the enable signal EN1 to form the internal voltage VDDA with the large current supply capability. Further, when the step-down circuit 21 is deactivated by the enable signal EN1, its own operating current is cut off, the output operation of the internal voltage VDDA is stopped, and the output high impedance state is set. The output terminals of the step-down circuits 20 and 21 as the two circuit blocks are connected to each other.

  FIG. 3 shows a block diagram of an embodiment of the step-down power supply circuit for digital circuit of FIG. Reference numeral 30 denotes a standby voltage step-down circuit, in which the current supply capability is set small to reduce power consumption. The step-down circuit 30 is always operated when the input terminal for the enable signal is connected to the power supply voltage VCC. Nos. 31 and 32 have a large current supply capacity and increase power consumption. These step-down circuits 31 and 32 are activated by enable signals EN2 and EN3, respectively, to form the internal voltage VDDD with the large current supply capability. Further, when the step-down circuits 31 and 32 are inactivated by the enable signals EN2 and EN3, their own operating currents are cut off, the output operation of the internal voltage VDDD is stopped, and the output high impedance state is established. . The output terminals of the step-down circuits 30 to 32 as the three circuit blocks are connected to each other.

  FIG. 4 shows a block diagram of an embodiment of the reference voltage generating circuit of FIG. A silicon band gap circuit (BGR) 11 generates a stable voltage VBGR independent of the power supply voltage VCC and temperature. As long as the circuit can generate a stable voltage, for example, a circuit for extracting a threshold voltage difference of MOSFETs may be used instead of the band gap circuit. In the figure, reference numeral 12 denotes a differential amplifier, which is supplied with a reference voltage VBGR at its inverting input terminal (−) and drives a P-channel type output MOSFET MP0. The source and substrate (back gate) of the MOSFET MP0 are connected to the power supply voltage VCC, and a tapped resistor string 13 is provided between the drain and the circuit ground potential VSSI. The divided voltage at a predetermined tap of the resistor string 13 is supplied to the non-inverting input (+) of the amplifier 12 and is controlled in a negative feedback loop so as to coincide with the reference voltage VBGR.

  The amplifier 12, the tapped resistor string 13, and the MOSFET MP0 constitute a trimming circuit. The output voltage VREF can be adjusted by changing the extraction of the resistance tap of the resistor string 13 with tap. TRIM is a trimming signal whose signal level is the power supply voltage VDDD level. BIE is a burn-in enable signal, and the voltage level is VDDD. The signals TRIM and BIE are output by a CPU as will be described later in the digital circuit 50. Reference numerals 14 and 15 denote level-up conversion circuits which convert the VDDD level input signal to the VCC level.

  Reference numeral 16 denotes a decoder, and the operating voltage is composed of VCC and VSSD. When the signal BIE is at a low level (normal time), the TRIM signal is decoded to generate a resistance tap selection signal. When the BIE signal is at a high level (burn-in), the tap at the highest position is always selected regardless of the TRM signal. As a result, the reference voltage VREF becomes higher than normal (1.5 V or 2.5 V). When the microcomputer is in a reset state (described later), the outputs of the level-up conversion circuits 14 and 15, that is, the converted signals TRIM and BIE are fixed at a low level. At this time, it is preferable that the decoder 16 selects a default value (for example, the center tap of the resistor string).

In this embodiment, the level-up conversion circuits 14 and 15 are placed in front of the decoder 16 (input side), but may be placed after the decoder 16 (output side). In that case, the operating voltage of the decoder 16 is set to VDDD and VSSD. However, it is desirable to place them before the decoder 16 (input side) because the number of level-up conversion circuits 14 and 15 can be reduced. That is, when the signal TRIM is n bits, the number of level-up conversion circuits 14 may be n, but when the signal TRIM is provided on the rear stage side, the number is increased to 2 ⁿ .

  FIG. 5 shows a circuit diagram of an embodiment of the step-down circuits 31 and 32 of FIG. VREFD is a reference voltage. EN is an enable signal, and the signal level has an amplitude like VCC and VSS. When the signal level is high (VCC), the step-down circuit is activated. SHORT is a short circuit signal, and the signal level is set to an amplitude such as VCC and VSS, and when the signal level is high level (VCC), MOSFET MN1 is turned on. This signal SHORT is used when the internal power supply VDDD is set to 0 V when the step-down circuit is deactivated due to the enable signal having a low level. Although not used in the embodiment of FIGS. 1 and 3 (always low level), it is used in the embodiment of FIG. VCCQ is a power supply terminal for an input / output circuit, and the voltage level is the same as VCC. VSSQ is a ground terminal for an input / output circuit.

  CS1 is a current source, and includes MOSFETs Q6 to Q9. When the enable signal EN is at a high level, the N-channel MOSFET Q9 is turned off, the P-channel MOSFETs Q7 and Q8 are turned on, and the diode-shaped N-channel MOSFET Q6 is turned on. A current is supplied to cause the MOSFET Q6 and MOSFETs Q5 and Q10 in the form of a current mirror to operate as a current source. When enable signal EN is at a low level, N-channel MOSFET Q9 is turned on, and P-channel MOSFETs Q7 and Q8 are turned off. While the current is cut off, the gates and sources of the MOSFETs Q6, Q5, and Q10 are short-circuited by turning on the MOSFET Q9 to turn them off. In this way, the operating currents of the differential amplifier DA1 and the output circuit described below are cut off from the low level of the enable signal EN.

  DA1 is a differential amplifier, and includes N-channel differential MOSFETs Q1 and Q2, the current source MOSFET Q5 provided between the source and the ground terminal VSSD of the circuit, the drains of the MOSFETs Q1 and Q2, and the power supply terminal VCC. It is composed of an active load circuit composed of P-channel MOSFETs Q3 and Q4 in the form of a current mirror provided therebetween. MP1 is a P-channel output MOSFET. The output signal of the differential amplifier is supplied to the gate, and constitutes an output circuit together with the current source MOSFET Q10 provided on the drain side. MP2 is a P-channel MOSFET, and is provided between the gate and source of the output MOSFET MP1. When the enable signal EN is supplied to the gate of the MOSFET MP2, the output MOSFET MP1 is forcibly turned off (output high impedance state) when the signal EN is at a low level.

  MN1 is an N-channel MOSFET, and when the signal SHORT is supplied to the gate and the signal SHORT is at a high level, VDDD and VSSD are short-circuited. That is, VDDD is forcibly extracted to the VSSD level. ESD is an electrostatic breakdown protection element circuit, and includes a diode, a protection MOSFET, and resistors R1 and R2. Since the VDDD terminal becomes an external terminal for externally attaching the smoothing capacitor CD, it is desirable to provide the ESD and take measures against electrostatic breakdown.

  FIG. 6 shows a circuit diagram of an embodiment of the step-down circuit 21 of FIG. VREFA is a reference voltage. EN is an enable signal, and the signal level has an amplitude like VCC and VSS. When the signal level is high (VCC), the step-down circuit is activated. BIE2 is a burn-in enable signal, and the signal level is set to VCC and VSSA. As a method of performing the burn-in, there is a method of directly connecting an external power source and an internal power source in addition to the method of increasing the reference voltage described above with reference to FIG. That is, the external power supply VCC is directly applied to the internal circuit. When the signal BIE2 becomes high level, the N-channel MOSFET MN2 is turned on, the gate of the P-channel MOSFET MP3 is changed to low level, and the power supply voltage VCC and the output voltage VDDA are directly connected. EN is an enable signal, the signal levels are VCC and VSSA, and the step-down circuit is activated when it is at a high level (VCC).

  DA2 is a differential amplifier, and differential MOSFETs Q1 and Q2 and current source MOSFET Q5 similar to those described above are used. The drain current of the differential MOSFET Q1 includes a diode-type P-channel MOSFET Q11 and a P-channel MOSFET Q12 in the form of a current mirror, a die-automatic N-channel MOSFET Q13 that receives the drain current of the P-channel MOSFET Q12, and an N-type in the form of current mirror Output through channel MOSFET Q16. The drain current of the differential MOSFET Q2 is output through a P-channel MOSFET Q14 in the form of a diode and a P-channel MOSFET Q15 in the form of a current mirror. The difference between the drain current of the P-channel MOSFET Q15 and the drain current of the N-channel MOSFET Q16 drives the output MOSFET MP3. In this differential amplifier DA2, the output signal of an AND gate circuit G1 that receives the output signal of the inverter circuit INV2 that receives the signal EN and the signal BIE2 is transmitted to the gate of the MOSFET Q5. It is activated when the signal EN is high and the signal BIE2 is low and not burn-in. When the signal EN is at a low level or the signal BIE2 is at a high level, the MOSFET Q5 is turned off to stop the amplification operation, and the P-channel MOSFETs Q17 and Q18 are turned on to stop the operation of the current mirror circuit.

  DIV1 is a voltage dividing circuit, and by feeding back half the output voltage VDDA to the differential amplifier DA2, the output voltage VDDA becomes twice the reference voltage VREFA. RC and CC are phase compensation resistors and capacitors. The digital step-down circuit shown in FIG. 5 has a large smoothing capacitor connected to the outside, so the above phase compensation is not necessary, but the analog step-down circuit has a phase compensation circuit added to prevent oscillation. It is good to do.

  MP3 is a P-channel output MOSFET, and the voltage dividing circuit DIV1 is provided as a load circuit. MP4 is a P-channel MOSFET that receives an output signal from an OR gate circuit G2 that receives the signal EN and the signal BIE2, and is turned on when both the signal EN and the signal BIE2 are at a low level (logic 0). The gate of the output MOSFET MP3 is set to the high level, and the output MOSFET MP3 is turned off (output high impedance state). MN2 is an N-channel MOSFET, and when the signal BIE2 is at a high level, the gate of the output MOSFET MP3 is set to a low level, and the output voltage VDDA is raised as the power supply voltage VCC.

  FIG. 7 shows a circuit diagram of an embodiment of the step-down circuit 30 of FIG. VREFD is a reference voltage, EN is an enable signal, and signal amplitudes are VCC and VSSD. This circuit is activated when the signal EN is at a high level. Although not used in the embodiment of FIG. 1 (always set to high level), it is used in the embodiment of FIG. SHORT is an output short circuit signal, and the signal amplitude is VCC and VSSD. Used when the internal voltage VDDD is set to 0V. Although not used in the embodiment of FIG. 1 (always low level), it is used in the embodiment of FIG.

  CS2 is a current source and includes circuit elements Q6 to Q9 similar to the current source CS1 of FIG. 5, but is set so that the current value is smaller than that of the current source CS1. DA3 is a differential amplifier and includes circuit elements Q1 to Q5 similar to those in FIG. MP5 is a P-channel output MOSFET, MP6 is a P-channel MOSFET, and is turned on when the signal EN is at a low level, the output MOSFET MP5 is turned off by setting the gate of the output MOSFET MP5 to a high level, and an output high impedance state And MN3 is an N-channel MOSFET. When the signal SHORT is at a high level, the MOSFET MN3 is turned on to short-circuit VDDD and VSSD.

  FIG. 8 shows a circuit diagram of an embodiment of the step-down circuit 20 of FIG. VREFA is a reference voltage. DA4 is a differential amplifier, which comprises active MOSFETs Q3 and Q4 and MOSFETs Q21 and Q22, which are composed of differential MOSFETs Q1 and Q2, a current source MOSFET Q5 and a current mirror circuit similar to those described above. EN is an enable signal, and signal amplitudes are VCC and VSSA. When the signal EN is at a high level, the MOSFET Q21 is turned on, and the current flowing through the differential amplifier DA4 increases by adding the current formed by the MOSFET Q22 to the steady current formed by the MOSFET Q5 corresponding to the constant voltage VRR. Speeded up.

  BIE2 is a burn-in enable signal, and the signal amplitude is VCC and VSSA. When the signal BIE2 becomes high level, the output signal of the inverter circuit INV3 becomes low level, the P channel MOSFET Q23 is turned on, and the differential amplifier DA4 is stopped. DIV2 is a voltage dividing circuit. The output voltage VDDA is divided into VDDA / 2 by MOSFETs Q24 and Q25, and fed back to the gate of the differential MOSFET Q2, thereby forming an output voltage VDDA that is twice the reference voltage VREFA. . MP7 is a P-channel output MOSFET, and the voltage dividing circuit DIV2 constitutes a load circuit.

  FIG. 9 shows a state transition diagram of an embodiment of the one-chip microcomputer shown in FIG. The program execution state is a state in which the CPU is executing a program. This program execution state consumes a large amount of current. The sleep mode shifts to the sleep mode when the CPU executes a sleep command. In this sleep mode, current consumption is small. The software standby mode shifts to the software standby mode when the CPU executes a sleep instruction (the transition to the sleep mode is distinguished by a specific register value). In this software standby mode, the current consumption is even smaller than in the sleep mode. The hardware standby mode shifts to the hardware standby mode when the external signal / STBY becomes low level. The current consumption in the hardware standby mode is equal to or smaller than that in the software standby mode. The reset state shifts to the reset state when the external signal / RES becomes low level. In this reset state, the internal circuit is reset.

  When an interrupt occurs in the program execution state, sleep mode, or software standby mode (when IRQ in FIG. 1 becomes high level), the exception processing state shifts to the exception processing state. Further, when / RES becomes high level (reset release) in the reset state, the state shifts to the exception processing state. The CPU executes an exception handling program. When the exception processing is completed and the CPU executes an RTE (Return from Exception) instruction, the program returns to the program execution state.

  FIG. 10 is an explanatory diagram of the operation state of the step-down circuit corresponding to the operation state of the microcomputer shown in FIG. In each of the program execution state, the reset state, and the exception handling state, all circuits of the reference voltage generation circuit 10, analog circuit step-down circuits 20 and 21, and digital circuit step-down circuits 30, 31, and 32 are operated. . In the sleep mode, one step-down circuit 32 of the digital step-down circuits is stopped. In the software standby mode and the hardware standby mode, the step-down circuit 21 in the analog step-down circuit and the step-down circuits 31 and 32 in the digital step-down circuit are stopped. The reference voltage generation circuit and step-down circuits 20 and 30 are always operated. By operating / stopping the step-down circuits 20, 21, and 30 to 33 according to the current consumption of the internal circuit in each operation state, the current consumption of the step-down circuit as a whole can be reduced. When the step-down circuit is stopped, the current consumed by the differential amplifier and the output circuit constituting the step-down circuit is cut off as described above, so that the current consumption in the power supply circuit is significantly reduced.

  FIG. 11 shows a configuration diagram of one embodiment of the smoothing capacitor CA of FIG. FIG. 11A illustrates a planar configuration, and FIG. 11B illustrates a cross-sectional configuration taken along line a-a ′ of FIG. 100 is a P-type semiconductor substrate, 101 is an n-well, and 102 is a p-well. Reference numeral 103 denotes an element isolation insulating film, reference numeral 104 denotes an n + diffusion layer that constitutes one electrode of the smoothing capacitor CA, and reference numeral 105 denotes a p + diffusion layer, which is used to apply a bias voltage to the p well 102. Reference numeral 106 denotes polysilicon, which constitutes the other electrode of the smoothing capacitor CA. Reference numeral 107 denotes a contact hole on the n + diffusion layer, and reference numeral 108 denotes a contact hole on the p + diffusion layer. Reference numeral 109 denotes a contact hole on polysilicon. Reference numerals 110, 111, and 112 denote metal wiring layers.

  Among the metal wiring layers, 110 is one electrode of the smoothing capacitor CA, and 112 is the other electrode. Although not shown in the figure, the left and right metal wiring layers 110 are connected via an upper wiring layer. Reference numeral 111 denotes a wiring for grounding the substrate. The smoothing capacitor CA of this embodiment is characterized in that a capacitor having a relatively small voltage dependency as compared with a MOS capacitor can be obtained. Therefore, it can also be used as the phase compensation capacitor CC of FIG.

  FIG. 12 is a circuit diagram showing one embodiment of the level-up conversion circuit used in the present invention. This level-up conversion circuit is used as the level-up conversion circuit 70 in FIG. 1 and the level-up conversion circuits 14 and 15 in FIG. The level-up conversion circuit LCU of this embodiment converts the VDDD level input signal in to the VCC level output signal out. That is, the VDDD level input signal in is supplied to the gates of the N-channel MOSFETs Q34 and Q39 and the P-channel MOSFETs Q33 and Q38. Further, an inverted signal of the input signal in formed by the inverter circuit INV4 at the VDDD level is supplied to the gates of the N-channel MOSFETs Q31 and Q37 and the P-channel MOSFETs Q30 and Q36. The power supply voltage VCC is supplied to the CMOS inverter circuit composed of the MOSFETs Q30 and Q31 through the P-channel MOSFET Q32. Similarly, the CMOS inverter circuit composed of MOSFETs Q33 and Q34 is also supplied with the power supply voltage VCC through the P-channel MOSFET Q35.

  The CMOS inverter circuit composed of the MOSFETs Q36 and Q37 is supplied with the output voltage of the CMOS inverter circuit composed of the MOSFETs Q30 and Q31 as an operating voltage. The CMOS inverter circuit composed of the MOSFETs Q38 and Q39 is supplied with the output voltage of the CMOS inverter circuit composed of the MOSFETs Q33 and Q34 as the operating voltage. The output signal of the CMOS inverter circuit composed of the MOSFETs Q36 and Q37 and the output signal of the CMOS inverter circuit composed of the MOSFETs Q38 and Q39 are transmitted to the gates of the P-channel MOSFETs Q35 and Q32. Then, the reset signal / RES is input to the gate circuit G3, and the output signal out is formed through the gate circuit G3. The gate circuit G3 and the inverter circuits INV5 and INV6 are operated with the power supply voltage VCC. By providing such an output control circuit, the output out is fixed to the high level when the reset signal / RES is at the low level. As shown in FIG. 9, when the microcomputer is in the reset state, the control signal can be fixed to the default state.

  FIG. 13 is a circuit diagram showing another embodiment of the level-up conversion circuit used in the present invention. The input signal in is supplied to the gate of the N-channel MOSFET Q40 through a CMOS switch composed of an N-channel MOSFET Q44 and a P-channel MOSFET Q45 controlled by the reset signal / RES. The input signal in passed through the CMOS switches (Q44, Q45) is inverted by the inverter circuit INV8 and supplied to the gate of the N-channel MOSFET Q41. Between the drains of these N-channel MOSFETs Q40 and Q41 and the power supply voltage VCC, P-channel MOSFETs Q42 and Q43 whose gates and drains are cross-connected are provided. The reset signal / RES is supplied to the gate of the P-channel MOSFET Q46 provided between the gate of the N-channel MOSFET Q40 and the power supply voltage VCC, and the reset signal inverted by the inverter circuit INV7 is connected to the gate of the N-channel MOSFET Q41. It is supplied to the gate of an N-channel MOSFET Q47 provided between the circuit and the ground potential. The drain output of the MOSFET Q40 is output as an output signal out through the inverter circuit INV9. Also in this embodiment, when the reset signal / RES is at a low level, the input signal in is blocked from being input to the level conversion unit, and the N-channel MOSFET Q40 is forcibly turned on and the MOSFET Q41 is turned off to turn off the inverter circuit INV9. The passed output signal out is fixed at a high level.

  FIG. 14 is a circuit diagram showing still another embodiment of the level-up conversion circuit used in the present invention. The input signal in is supplied to the source of the N-channel MOSFET Q50 whose gate is supplied with the low-level power supply voltage VDDD and the gate of the N-channel MOSFET Q51. Between the drains of these MOSFETs Q50 and Q51 and the power supply voltage VCC, P-channel MOSFETs Q53 and Q54 in which the gate and the drain are cross-connected are provided. An N-channel MOSFET Q52 that receives a reset signal / RES is provided between the source of the N-channel MOSFET Q51 and the ground potential of the circuit. Further, a P-channel MOSFET Q55 to which the reset signal / RES is supplied to the gate is provided between the drain of the MOSFET Q51 and the power supply voltage VCC. An output signal obtained from the drain of the MOSFET Q51 is output as an output signal out through the inverter circuit INV10. Also in this embodiment, when the reset signal / RES is at low level, the MOSFET Q52 is turned off to stop the level conversion operation of the input signal in, and the MOSFET Q55 is turned on to fix the output signal out through the inverter circuit INV9 to low level. To do.

  FIG. 15 is a block diagram showing another embodiment of the semiconductor integrated circuit device according to the present invention. The semiconductor integrated circuit device shown in the figure is directed to a system LSI including a one-chip microcomputer or CPU. The difference from the embodiment of FIG. 1 is that the internal power supply for the digital circuit is partially turned off in the standby mode (software standby and hardware standby). VDDN is an internal voltage for the digital circuit, and 33 to 36 are step-down circuits for the digital circuit, which generate power supplies VDDD and VDDN for the digital circuit 50. The voltage values of VDDD and VDDN are the same, for example, a low voltage such as 1.5V. The power supply voltages of the step-down circuits 33 to 35 are VCC and VSSD. The step-down circuits 33 to 35 of this embodiment set the internal voltage VDDD to 0 V in the standby mode. In contrast, the internal voltage VDDN is maintained even in the standby mode.

  Reference numeral 50 denotes a digital circuit, which includes a RAM (Random Access Memory), a ROM (Read Only Memory), a register, a logic circuit, and the like as described below. The digital circuit 50 is supplied with VDDD and VSSD or VDDN and VSSD according to the function. Reference numeral 60 denotes a state control circuit. Unlike the embodiment of FIG. 1, the power supply uses VDDN and VSSD. Therefore, it can be constituted by a fine device having a low breakdown voltage.

  Reference numerals 80 and 81 denote level-up conversion circuits, which can be realized by the circuits shown in FIGS. The enable signals EN1 to EN4 for the step-down circuit and the output short circuit signal SHORT are converted from the VDDN level to the VCC level. Reference numerals 90 to 92 denote level down conversion circuits which convert VCC level input signals IRQ, / RES, / STBY to VDDN level and supply them to the state control circuit 60. SW is a switch, which is turned off in the standby mode and turned on in other cases. By providing this switch SW, the smoothing capacitor CD can be shared by VDDD and VDDN.

  In this embodiment, (1) a step-down power supply for a digital circuit is provided with two systems of VDDD and VDDN, and VDDD is turned off in accordance with the operating state, whereby a leakage current flows in a circuit using VDDD as a power supply. Disappear. That is, not only the power consumption of the step-down circuit itself but also the power consumption corresponding to the leakage current can be reduced. The CMOS circuit theoretically stops the consumption current when the input signal does not change, but the leakage current (sub-current) flowing between the source and drain when the MOSFET is turned off due to the miniaturization of the MOSFET and the lower threshold voltage. Threshold leakage current and the like) and gate leakage current cannot be ignored, but in this embodiment, power consumption in the digital circuit itself can be reduced. (2) The state control circuit 60 is operated by the always-on internal power supply VDDN. Thereby, even in the standby mode, it is possible to deal with the interrupt request signal IRQ, the reset signal / RES, and the standby signal / STBY from the outside.

  FIG. 16 is a block diagram showing one embodiment of the digital circuit step-down circuits 33 to 36 and the digital circuit 50 shown in FIG. Reference numeral 33 denotes a standby VDDN step-down circuit whose current supply capability is set small and power consumption is reduced. The specific configuration of the step-down circuit 33 is constituted by a circuit as shown in FIG. 7, for example. However, the enable signal EN is connected to the power supply voltage VCC and used as a constant operation. Therefore, the output short-circuit signal SHORT and related circuits can be omitted. Reference numeral 34 denotes an operating VDDN step-down circuit whose current supply capability is set large and power consumption is also increased. The specific configuration of the step-down circuit 34 is configured by a circuit as shown in FIG. 5, for example. It is activated by the enable signal EN2. The output short circuit signal SHORT is not used (connected to VSSD). The output terminals of the step-down circuits 33 and 34 are connected to form the internal voltage VDDN.

  Reference numeral 35 denotes a standby VDDD step-down circuit whose current supply capability is set small and power consumption is also reduced. The specific configuration of the step-down circuit 35 is configured by a circuit as shown in FIG. 7, for example. Unlike the step-down circuit 33, it is activated by the enable signal EN3. VDDD is grounded by the output short signal SHORT. Reference numeral 36 denotes an operating VDDD step-down circuit, which has a large current supply capability and increases power consumption. The specific configuration of the step-down circuit 36 is constituted by a circuit as shown in FIG. 5, for example. It is activated by the enable signal EN4. VDDD is grounded by the output short signal SHORT. The output terminals of the step-down circuits 35 and 36 are connected to form the internal voltage VDDD. The two output voltages VDDN and VDDD are selectively connected by a switch SW.

  The digital circuit 50 is composed of a CPU 51, a RAM 54, and a ROM 55, although not particularly limited. The CPU includes a logic circuit 52 and a register 53. VDDD and VSSD are used as power sources for the logic circuit 52, and VDDN and VSSD are used as power sources for the RAM 54 and the register 53. As a result, the storage contents of the RAM 54 and the register 53 are held by VDDN even during standby. A register or RAM whose stored contents may be lost may be supplied with the internal voltage VDDD. However, the registers and RAM for storing the operation state of the microcomputer must be the internal voltage VDDN that is always supplied as described above. The ROM 55 and the logic circuit 52 use internal voltages VDDD and VSSD. Although the power is turned off during standby, the contents are not lost because the ROM 55 is a nonvolatile memory. There is no problem because the logic circuit 52 may be supplied with power in the operating state. Reference numeral 56 denotes a data bus.

  FIG. 17 is a circuit diagram showing one embodiment of the level down conversion circuits 90-92 shown in FIG. Between the drains of the N-channel MOSFETs Q56 and Q57 that receive the input signal in and the inverted signal from the inverter circuit INV11 and the power supply voltage VDDN, P-channel MOSFETs Q58 and Q59 whose gates and drains are cross-connected are provided. As a result, the VCC level input signal in is converted to the VDDN level output signal out. Although an inverter using VDDN as a power source may be used, in this circuit, the P-channel MOSFET can be configured with a fine device having a low withstand voltage.

  FIG. 18 is an explanatory diagram of the operation state of the step-down circuit corresponding to the operation state of the microcomputer shown in FIG. In this embodiment, in the program execution state, the reset state, and the exception processing state, all the step-down circuits are in the operating state. In the sleep mode, among the digital step-down circuits, the step-down circuits 34 and 36 with large current consumption are stopped. In the software standby mode and the hardware standby mode, the step-down circuit 21 in the analog step-down circuit and the step-down circuits 34, 35, and 36 in the digital step-down circuit are stopped. When the step-down circuits 35 and 36 are stopped, VDDD is turned off (blocked state). The reference voltage generation circuit and the step-down circuits 20 and 33 are always in operation. The current consumption as a whole can be reduced by operating / stopping the step-down circuit according to the magnitude of the current consumption of the internal circuit in each operation state and further turning off part of the internal power supply in the standby mode.

  FIG. 19 shows a chip layout of an embodiment of the microcomputer shown in FIG. In the figure, each circuit block and the like are shown in conformity with the actual geometric arrangement in the semiconductor chip. 1 is an LSI chip, 2 is a bonding pad, 3 is an I / O area, and is an area where input / output circuits are mainly arranged. Reference numeral 4 denotes an area where circuits 34 and 36 having a large current supply capability are arranged in the digital circuit step-down circuit. These step-down circuits 34 and 36 are distributed in the I / O area around the chip and supply wiring to the digital circuit 50 occupying most of the core area (area inside the I / O area). Impedance is reduced.

  Reference numeral 5 denotes an area in which the analog circuit step-down circuits 20 and 21 are arranged, and is arranged in the vicinity of the analog circuit 40, the VCC, and the VSSA pad. Reference numeral 6 denotes an area in which the level down conversion circuits 90 to 92 are arranged, which is arranged in the vicinity of the signals IRQ, / RES, and / STBY pads. Reference numeral 7 denotes an area in which the reference voltage generation circuit 10 and the step-down circuits 33 and 35 are arranged, and is arranged in the vicinity of the VCCI and VSSI pads in order to prevent power supply noise used in the reference voltage generation circuit 10. Although not shown, dedicated power supply terminals VCCQ and VSSQ are appropriately provided for the input / output circuit, particularly for the output circuit.

  In a semiconductor integrated circuit device such as a system LSI including a microcomputer or a CPU, the internal power supply of each circuit block can be turned on / off corresponding to the operation mode, and current consumption in the sleep mode and standby mode can be reduced. With such a configuration, power consumption during standby and sleep can be reduced, in other words, since it is not affected by leakage current, lower voltage (lower threshold voltage) and higher performance can be achieved. That is, in response to low power consumption modes such as sleep mode and standby mode such as a microcomputer, the leakage current as a whole can be reduced by turning off the internal power supply of the circuit block that does not operate in the mode and turning off the step-down circuit itself. Can be greatly reduced. As a result, the threshold voltage of the MOSFET can be lowered as compared with the prior art, and a low-speed and high-speed circuit can be obtained.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, in the embodiment shown in FIGS. 1 and 15, the analog internal power supply VDDA always outputs a voltage, but the analog internal power supply may be turned off depending on the operation mode. The power consumption corresponding to the leakage current of the analog circuit can be further reduced. The specific configurations of the step-down circuit and the level conversion circuit can take various embodiments. The present invention can be widely used for semiconductor integrated circuit devices including a central processing unit CPU or a microprocessor.

  The present invention can be widely used for a semiconductor device including a step-down power supply circuit that steps down an external power supply.

DESCRIPTION OF SYMBOLS 1 ... LSI chip, 2 ... Bonding pad, 3 ... I / O area, 4 ... Digital circuit step-down circuit area, 5 ... Analog circuit step-down circuit area, 6 ... Level conversion circuit area, 7 ... Reference voltage generation circuit area,
DESCRIPTION OF SYMBOLS 10 ... Reference voltage generation circuit, 11 ... Band gap circuit, 20, 21 ... Step-down circuit for analog circuit, 30-32 ... Step-down circuit for digital circuit, 40 ... Analog circuit, 50 ... Digital circuit, 60 ... State control circuit, 70 ... Level-up conversion circuit, CD ... External smoothing capacitor, CA ... On-chip smoothing capacitor,
12 ... Differential amplifier, 13 ... Tapped resistor string, 14, 15 ... Level-up conversion circuit, 16 ... Decoder,
CS1, CS2 ... current source, DA1-DA4 ... differential amplifier, ESD ... electrostatic breakdown prevention element, DIV1-DIV2 ... voltage divider circuit, RC, CC ... phase compensation circuit,
33 to 36: step-down circuit for digital circuit, 80, 81 ... level up conversion circuit, 90 to 92 ... level down conversion circuit, SW ... switch,
DESCRIPTION OF SYMBOLS 100 ... p-type semiconductor substrate 101 ... n well 102 ... p well 103 ... Insulating film for element isolation 104 ... n + diffusion layer 105 ... p + diffusion layer 106 ... polysilicon 107 ... contact hole on n + diffusion layer 108 ... contact hole on p + diffusion layer, 109 ... contact hole on polysilicon, 110-112 ... metal wiring layer,
MP0 to MP7... P channel MOSFET, MN1 to MN3... N channel MOSFET, Q1 to Q55.

Claims (11)

An external terminal,
A first step-down circuit that receives an external power supply voltage supplied from the external terminal and outputs a first internal voltage lower than the external power supply voltage from a first output terminal;
A first mode for receiving the external power supply voltage and outputting a second internal voltage lower than the external power supply voltage from a second output terminal; and a third internal voltage lower than the first and second internal voltages from the second output terminal. A second step-down circuit that is switched to the second mode for outputting
A first internal circuit including a first static RAM connected to the first output terminal and supplied with a ground voltage as a low power supply voltage;
A second internal circuit including a second static RAM connected to the second output terminal and supplied with the ground voltage as a lower power supply voltage;
During standby, the second step-down circuit is controlled to the second mode, and the first internal voltage is supplied from the first step-down circuit as the high-level power supply voltage of the first internal circuit, so that the memory of the first static RAM is stored. The contents are retained, the third internal voltage is supplied from the second step-down circuit as the high-level power supply voltage of the second internal circuit, and the stored contents of the second static RAM are lost.
When controlled to the second mode, the second step-down circuit outputs the third internal voltage to the higher power supply voltage of the second internal circuit . The semiconductor device according to claim 1,
During normal operation, the second step-down circuit is controlled to the first mode, and the first internal voltage is supplied from the first step-down circuit as a high-level power supply voltage of the first internal circuit. The stored contents are held, and the second internal voltage is supplied from the second step-down circuit as the high power supply voltage of the second internal circuit, and the stored contents of the second static RAM are held. apparatus. The semiconductor device according to claim 1,
The semiconductor device according to claim 3, wherein the third internal voltage is the ground voltage. The semiconductor device according to claim 1 or 2,
A third mode connected to the first output terminal and receiving the external power supply voltage to output the first internal voltage from the third output terminal; and a fourth mode for setting the third output terminal to a high impedance state. A third step-down voltage circuit to be switched;
During the normal operation, the third step-down circuit is controlled to the third mode, the first internal voltage is supplied from the first and third step-down circuits as the high-level power supply voltage of the first internal circuit, and the second The second internal voltage is supplied from the second step-down voltage circuit as the high level power supply voltage of the internal circuit. During the standby , the third voltage step-down circuit is controlled to the fourth mode, and the high level power supply voltage of the first internal circuit The semiconductor device, wherein the first internal voltage is supplied from the first step-down circuit, and the third internal voltage is supplied from the second step-down circuit as a higher power supply voltage of the second internal circuit. The semiconductor device according to claim 4,
The semiconductor device according to claim 1, wherein a current supply capability of the third step-down circuit is set higher than a current supply capability of the first step-down circuit. An external terminal,
A first step-down circuit that receives an external power supply voltage supplied from the external terminal and outputs a first internal voltage lower than the external power supply voltage from a first output terminal;
A first mode for receiving the external power supply voltage and outputting a second internal voltage lower than the external power supply voltage from a second output terminal; and a third internal voltage lower than the first and second internal voltages from the second output terminal. A second step-down circuit that is switched to the second mode for outputting
A first internal circuit including a first static RAM connected to the first output terminal and supplied with a ground voltage as a low power supply voltage;
A second internal circuit including a second static RAM connected to the second output terminal and supplied with the ground voltage as a lower power supply voltage;
During standby, the second step-down circuit is controlled to the second mode, and the first internal voltage is supplied from the first step-down circuit as the high-level power supply voltage of the first internal circuit, so that the memory of the first static RAM is stored. The contents are retained, the third internal voltage is supplied from the second step-down circuit as the high-level power supply voltage of the second internal circuit, and the stored contents of the second static RAM are lost .
A fifth mode connected to the second output terminal and receiving the external power supply voltage to output the second internal voltage from the fourth output terminal; and a sixth mode for setting the fourth output terminal to a high impedance state. further comprising a fourth step-down circuit is switched,
During the normal operation, the fourth step-down circuit is controlled to the fifth mode, the first internal voltage is supplied from the first step-down circuit to the high-level power supply voltage of the first internal circuit, and the second internal circuit Is supplied with the second internal voltage from the second and fourth step-down circuits,
At the time of the standby, the fourth step-down circuit is controlled to the sixth mode, the first internal voltage is supplied from the first step-down circuit to the high power supply voltage of the first internal circuit, and the second internal circuit The semiconductor device according to claim 1, wherein the third internal voltage is supplied from the second step-down circuit to the high power supply voltage. An external terminal,
A first step-down circuit that receives an external power supply voltage supplied from the external terminal and outputs a first internal voltage lower than the external power supply voltage from a first output terminal;
A first mode for receiving the external power supply voltage and outputting a second internal voltage lower than the external power supply voltage from a second output terminal; and a third internal voltage lower than the first and second internal voltages from the second output terminal. A second step-down circuit that is switched to the second mode for outputting
A first internal circuit including a first static RAM connected to the first output terminal and supplied with a ground voltage as a low power supply voltage;
A second internal circuit including a second static RAM connected to the second output terminal and supplied with the ground voltage as a lower power supply voltage;
During standby, the second step-down circuit is controlled to the second mode, and the first internal voltage is supplied from the first step-down circuit as the high-level power supply voltage of the first internal circuit, so that the memory of the first static RAM is stored. The contents are retained, the third internal voltage is supplied from the second step-down circuit as the high-level power supply voltage of the second internal circuit, and the stored contents of the second static RAM are lost .
A fifth mode connected to the second output terminal, receiving the external power supply voltage and outputting the second internal voltage from the fourth output terminal; and sixth mode outputting the third internal voltage from the fourth output terminal. further comprising a fourth step-down circuit mode and is switched,
During the normal operation, the fourth step-down circuit is controlled to the fifth mode, the first internal voltage is supplied from the first step-down circuit to the high-level power supply voltage of the first internal circuit, and the second internal circuit Is supplied with the second internal voltage from the second and fourth step-down circuits,
At the time of the standby, the fourth step-down circuit is controlled to the sixth mode, the first internal voltage is supplied from the first step-down circuit to the high power supply voltage of the first internal circuit, and the second internal circuit 3. The semiconductor device according to claim 1, wherein the third internal voltage is supplied from the second and fourth step-down circuits to the high power supply voltage. The semiconductor device according to claim 6 or 7,
The current supply capability of the fourth step-down circuit is set higher than the current supply capability of the second step-down circuit. The semiconductor device according to any one of claims 6 to 8 ,
The second internal circuit includes a nonvolatile memory and a logic circuit. The semiconductor device according to any one of claims 6 to 9 ,
It said first, second, fourth buck circuit, the semiconductor device characterized in that it comprises at least the current source circuit and a differential amplifier. The semiconductor device according to claim 1,
The second internal circuit includes a nonvolatile memory and a logic circuit .

Images