JP5413060B2 - Memory diagnostic method and memory circuit - Google Patents

Description

  The present invention relates to a diagnostic method and a memory circuit for a memory in which a frame received from a network is written.

  In a transmission apparatus that transmits LAN frames such as Ethernet (registered trademark), frame data received from a network is written in a memory for each user by an input interface unit. Under the control of the scheduler, the frame data is read from the memory and supplied to the switching unit, and a cross-connect process is performed according to the destination. The cross-connected frame data is sent from the output interface unit to the network. As described above, the memory of the transmission apparatus is always accessed by transmission frame processing, and the frequency of access to the memory is high. Also, one memory space is divided and used by a plurality of users.

  FIG. 1 is a block diagram showing an example of a conventional memory circuit. The LAN frame (input data) is supplied to the write control unit 1. The write controller 1 sets the input data in units of words, generates a write address by changing the use area for each user, and writes the input data in the memory 2 in units of words. The read control unit 3 generates a read address and reads data from the memory 2, and the read data is supplied to a subsequent circuit.

  Start the failure diagnosis program to diagnose the memory, detect the failure address in the memory, store it in the register, and when the address to access the memory matches the failure address, replace the memory by the selector with the repair register A method of performing memory failure relief by replacing the memory failure address with a relief register by selecting is conventionally known (see, for example, Patent Document 1).

JP 2000-181806 A

  As a general memory check method, there is a check method using a parity code or an error correction code (ECC), which has the following disadvantages. Since the parity check is an even or odd check, an error cannot always be detected by probability theory. The ECC check requires redundant bits for checking, and increases the memory capacity and circuit scale.

  Conventionally, in a transmission apparatus, only memory diagnosis is performed in a shipping test, and it is difficult to perform memory diagnosis in an operational state after shipping because of time constraints. For this reason, even if a memory failure occurs due to secular change, the memory failure cannot be detected. Further, there is a problem that the diagnosis for the unused memory space is not sufficient.

  The disclosed memory circuit is intended to automatically detect a failure in the entire memory during operation.

A memory circuit according to an embodiment of the disclosure is a memory circuit that writes a frame received from a network to a memory allocated with an area for each user, reads out frame data of each user from the memory, and supplies the frame data to a subsequent circuit.
Test address generation by sequentially changing the test address for testing the memory in an empty time slot that includes a frame-to-frame gap , a frame leading preamble and a frame start demarcation point received from the network Means,
Saving means for saving data read from the test address of the memory;
Test writing means for writing test data to the test address of the memory;
Test read means for reading test data from the test address of the memory;
Determination means for determining the presence or absence of a failure by comparing the test data read by the test reading means with reference data held in advance;
Write back means for writing back the data saved in the save means to the test address of the memory.

  According to this embodiment, it is possible to automatically detect a failure of the entire memory during operation.

It is a block diagram of an example of the conventional memory circuit. It is a block diagram of one Embodiment of a transmission apparatus. 1 is a configuration diagram of an embodiment of a memory circuit. It is a figure which shows the gap between LAN frames. It is a flowchart of one Embodiment of a memory check process. It is a figure which shows the signal timing chart of a memory check. It is a figure which shows the signal timing chart of a memory check. It is a figure which shows one Embodiment of a failure memory management table. It is a figure which shows the example of the failure memory management table when a user area | region fails.

  Embodiments will be described below with reference to the drawings.

<Configuration of transmission device>
FIG. 2 shows a configuration diagram of an embodiment of the transmission apparatus. In FIG. 2, the interface unit 10 is provided with a plurality of optical transceivers 11-0 to 11-7. Each of the optical transceivers 11-0 to 11-7 is supplied with an optical signal from the network and is converted into an electric signal. The LAN frame coming from the network has a VLAN tag composed of TPID (tag protocol identifier: 0x8100) and tag control information. The tag control information includes a 3-bit user priority and a 12-bit VID (virtual LAN identifier).

  The LAN frames output from the optical transceivers 11-0 to 11-7 are supplied to the MAC processing unit 12, and MAC processing such as termination of the MAC address is performed. Thereafter, the LAN frame is supplied to the priority control unit 13.

  The frame identification unit 14 in the priority control unit 13 identifies the VID of the LAN frame, supplies the identified VID to the read / write control unit 16, and supplies the LAN frame to the policer 15. The policer 15 limits the flow rate of the LAN frame.

  The read / write control unit 16 generates a write address of the memory according to the VID, and the input LAN frame is written in an area according to the VID of the memory 17 by the write address. The scheduler 18 adjusts the reading order.

  The read / write control unit 16 generates a read address according to the adjustment of the scheduler 18 and supplies the read address to the memory 17, and the LAN frame is read from the area designated by the read address of the memory 17. The LAN frame read from the memory 17 is supplied to the switch fabric unit 30 via the interface unit 20. When the read / write control unit 16 detects a failure in the memory 17, it notifies the failure memory management unit 19 of the failure information, and the failure information is held and managed by the failure memory management unit 19.

  The switch fabric unit 30 performs cross-connect processing on the LAN frame according to the destination, and the cross-connected LAN frame is transmitted from the optical transceiver 36 of the interface unit 35 corresponding to the destination to the network.

  The CPU unit 40 performs flow entry setting and monitoring for the CPUs 21, 31, and 37 of the interface unit 10, the switch fabric unit 30, and the interface unit 35, respectively.

<Configuration of transmission device>
FIG. 3 shows a block diagram of an embodiment of a memory circuit. This memory circuit corresponds to the read / write control unit 16 and the memory 17 in FIG. In FIG. 3, the LAN frame (input data) from the terminal 50 is supplied to the write control unit 51.

  The write control unit 51 is instructed by the fault memory management unit 19 or the CPU 21 for the use area for each user, and generates the write address by using the input data in units of words and changing the use area for each user. The input data and the write address are supplied to the memory 54 via the data selector 52 and the address selector 53, and the input data is written to the memory 54 in units of words. The memory 54 corresponds to the memory 17 in FIG.

  In addition, the read control unit 55 generates a read address. The read address is supplied to the memory 54 via the address selector 56, and the data read from the memory 54 is supplied from the terminal 57 to the subsequent circuit. The read data is supplied to a temporary flip-flop (temp-FF) 58 and a test read control / check unit 62. The temporary flip-flop 58 supplies the stored data to the data selector 52.

  An empty time slot instruction signal is supplied to the terminal 60 from the frame identification unit 14, and this empty time slot instruction signal is supplied to the test write control unit 61, the data selector 52, and the address selectors 53 and 56, respectively.

  The test write control unit 61 generates test data 0xAA, 0x55 (0x indicates a hexadecimal display) during an empty time slot, and also generates a write address using a built-in address counter. Also, the test write control unit 61 causes the data selector 52 to select test data (output of the test write control unit 61) in the first time slot of the empty time slot, and save data (temporary flip-flop 58 in the fifth time slot. A selection signal for selecting the output of the output. The selection signal is supplied to the data selector 52. The test data and the write address are supplied to the memory 54 via the data selector 52 and the address selector 53, and the test data or saved data is written to the memory 54 in units of words.

  Note that the test data 0xAA is a binary value “1010”, that is, a first value alternating with 1, 0, and the test data 0x55 is a binary value “0101”, ie, a second value where 0, 1 is alternating. Yes, by writing two test data 0xAA and 0x55 at the same address and comparing the test data read from the address with each of the reference data 0xAA and 0x55, two checks are performed, so that one address of the memory 54 is accurate. Fault detection can be performed.

  In addition, the test read control and check unit 62 generates a read address by an address counter built in the empty time slot. The read address is supplied to the memory 54 via the address selector 56, and the test data is read from the memory 54 and supplied to the test read control and check unit 62. The test read control and check unit 62 compares the test data read from the memory 54 with reference data 0xAA and 0x55 stored in advance, and if there is a mismatch, the failure information including the check result and the read address (test address) Is notified to the fault / failure memory management unit 19.

<Gap between LAN frames>
FIG. 4 shows a gap between LAN frames. There is at least 12 bytes of IFG (Interframe Gap) between the LAN frame and the preceding LAN frame. The LAN frame starts with a 7-byte preamble and a 1-byte SFD (Start Frame Delimiter), followed by a variable-length LAN frame (payload area) of up to 9600 bytes. . Therefore, the memory 54 is checked using a total of 20 bytes of IFG, preamble, and SFD as empty time slots.

<Memory check processing>
FIG. 5 shows a flowchart of an embodiment of a memory check process executed by the memory circuit in an empty time slot. In FIG. 5, in step S <b> 1, a test address that is a read address and a write address generated by the test write control unit 61 and the test read control / check unit 62 is set as the head address of the memory 54. At this time, 0xAA is set as test data.

  In step S2, the read address from the test read control and check unit 62 is supplied to the memory 54, and the data read from the memory 54 is written into the temporary flip-flop 58 and saved.

  Next, the test data (0xAA or 0x55) from the test write control unit 61 is written to the write address of the memory 54 in step S3. The test read control / check unit 62 and the test write control unit 61 are synchronized, and the read address and the write address are the same. Then, the read address from the test read control / check unit 62 is supplied to the memory 54, and the test data read from the memory 54 is supplied to the test read control / check unit 62.

  In step S4, the test read control and check unit 62 compares the test data read from the memory 54 with the reference data (0xAA or 0x55) held in advance and is normal (match), the process proceeds to step S5, and the abnormal If (mismatch), the process proceeds to step S6.

  In step S5, the write address from the test write control unit 61 and the saved data of the temporary flip-flop 58 are supplied to the memory 54, and the saved data is written back to the same address as when the memory 54 was saved.

  In step S6, the test read control and check unit 62 notifies the failure information to the failure failure memory management unit 19, and the failure memory management unit 19 sets an area determined to be a failure in the failure memory management table as an unused area.

  After execution of step S5 or S6, it is determined whether or not the test data used immediately before in step S7 is 0xAA. If the immediately preceding test data is 0xAA, 0x55 is set as test data in step S8, and the process proceeds to step S2. If the immediately preceding test data is 0x55, 0xAA is set as test data in step S9, and the read address and write address as test addresses are incremented by 1, and the process proceeds to step S2.

<Signal timing chart>
6 and 7 show signal timing charts of the memory check. Between the LAN frames shown in FIG. 6 (B), there is an empty time slot for 20 clocks shown in FIG. 6 (C) at a high level. Note that the clock in FIG. 6C is a clock that indicates one byte period of the LAN frame in one cycle based on the 100 MHz system clock shown in FIG. 6A.

  In the period of empty time slots for 20 clocks, the write control unit 51 stops generating addresses (counting normal addresses) as shown in FIG. As shown in FIGS. 6E and 6F, the test write control unit 61 and the test read control / check unit 62 set the test addresses (that is, the write address and the read address) to 0, 1 during this empty time slot. , 2 and 3 times. 6A to 6J, the time axis (horizontal axis) is enlarged.

  Then, the generation period of each test address shown in FIG. 6 (F) is divided into 6 time slots from No. 0 to No. 5 shown in FIG. 6 (G).

  In the time slot 0, data is read from the test address of the memory 54 and saved in the temporary flip-flop 58 as shown in FIG.

  In the first time slot, test data 0xAA is written to the test address of the memory 54 as shown in FIG.

  In the second time slot, as shown in FIG. 6H, the test data is read from the test address of the memory 54 and compared with the reference data 0xAA by the test read control and check unit 62.

  In the third time slot, test data 0x55 is written to the test address of the memory 54 as shown in FIG.

  In the fourth time slot, as shown in FIG. 6H, the test data is read from the test address of the memory 54 and compared with the reference data 0x55 by the test read control and check unit 62.

  In the fifth time slot, the saved data of the temporary flip-flop 58 is written back to the test address of the memory 54 as shown in FIG.

  In FIG. 6, since test data that matches the reference data is read from the test address of the memory 54 and no failure is detected, the check result output from the test read control and check unit 62 is as shown in FIG. Maintain a low level indicating no failure.

  In this way, a check is made for one address in the memory 54, and three test addresses in the memory 54 are checked in an empty time slot period of 20 clocks.

  FIG. 6 shows a case where there is no failure in the memory 54, whereas FIG. 7 shows a case where there is a failure in the memory 54. Between the LAN frames shown in FIG. 7B, there is an empty time slot for 20 clocks shown at a high level in FIG. 7C.

  In the period of empty time slots for 20 clocks, the write control unit 51 stops generating addresses (counting normal addresses) as shown in FIG. As shown in FIGS. 7E and 7F, the test write control unit 61 and the test read control / check unit 62 set the test addresses (that is, the write address and the read address) to 300, 301 during this empty time slot. , 302 and counts up three times. 7A to 7J, the time axis (horizontal axis) is shown enlarged.

  The generation period of each test address shown in FIG. 7F is divided into 6 time slots from No. 0 to No. 5 shown in FIG.

  In the 0th time slot of the test address 300, data is read from the test address of the memory 54 and saved in the temporary flip-flop 58 as shown in FIG.

  In the first time slot of the test address 300, the test data 0xAA is written to the test address of the memory 54 as shown in FIG.

  In the second time slot of the test address 300, as shown in FIG. 7H, the test data 0xAA is read from the test address in the memory 54 and compared with the reference data 0xAA by the test read control and check unit 62.

  In the third time slot of the test address 300, test data 0x55 is written to the test address of the memory 54 as shown in FIG.

  In the fourth time slot of the test address 300, the test data 0x15 is read from the test address in the memory 54 and compared with the reference data 0x55 by the test read control and check unit 62, as shown in FIG.

  In the fifth time slot of the test address 300, the saved data of the temporary flip-flop 58 is written back to the test address of the memory 54 as shown in FIG.

  Although the test data 0x55 is written to the test address of the memory 54 in the third time slot of FIG. 7 (I), the test data 0x15 is read from the test address of the memory 54 in the fourth time slot of FIG. Since no failure is detected, the check result output from the test lead control and check unit 62 becomes a high level indicating that there is a failure in the fifth time slot as shown in FIG.

  FIG. 8 shows an embodiment of a fault memory management table built in the fault memory management unit 19. In FIG. 8, reflecting the check result of FIG. 7, the memory diagnosis result for the user area of the address 300-3FF in the memory 54 is abnormal. As described above, when a part of the memory area used for each user is abnormal, the area is not assigned to the user as an unused area.

  FIG. 9 shows an example of a fault memory management table when the user area of the address 000-0FF used for the user flow-0 has failed. If it is determined that the used memory space (user area) is abnormal, the memory space is set as an unused area, and an alternative address 500-5FF, for example, is assigned to the user flow-0 again as a used area.

  Thus, by storing the determination result of whether the user area is valid or invalid (normal or abnormal) and the user flow-No information in the fault memory management table of the fault memory management unit 19, the memory space for each user can be managed. It becomes possible to use a normal memory space.

  It is assumed that a LAN frame (payload area after SFD) is stored as a precondition for using the memory 54. Therefore, the memory area where the diagnosis result is abnormal is not used, and the data already stored in the abnormal memory area is discarded. Then, the next input data is stored in a new memory space and processed normally.

In this way, failure detection of the entire memory can be performed automatically during operation, and if there is an abnormality, that area is not released to the user and is treated as unused, and the memory space is in a normal area. By inputting the input data, the reliability of the memory circuit can be ensured.
(Appendix 1)
In a memory circuit that writes a frame received from a network to a memory assigned an area for each user, reads out frame data of each user from the memory, and supplies the frame data to subsequent circuits.
Test address generating means for sequentially generating a test address for testing the memory in an empty time slot including an inter-frame gap of a frame received from the network;
Saving means for saving data read from the test address of the memory;
Test writing means for writing test data to the test address of the memory;
Test read means for reading test data from the test address of the memory;
Determination means for determining the presence or absence of a failure by comparing the test data read by the test reading means with reference data held in advance;
Write-back means for writing back the data saved in the save means to the test address of the memory;
A memory circuit comprising:
(Appendix 2)
In the memory circuit according to attachment 1,
It comprises failure memory management means for managing a user area including an address determined to be a failure by the determination means as a failure area and allocating another non-failure area to the user assigned to the failure area. Memory circuit.
(Appendix 3)
In the memory circuit according to attachment 2,
2. The memory circuit according to claim 1, wherein the test data is a first value in which 1, 0 alternates and a second value in which 0, 1 alternates.
(Appendix 4)
In a memory diagnostic method for diagnosing a memory circuit that writes a frame received from a network to a memory assigned an area for each user, reads out frame data of each user from the memory, and supplies the frame data to a subsequent circuit,
A first step of sequentially generating a test address for testing the memory in an empty time slot including an inter-frame gap of a frame received from the network;
A second step of saving data read from the test address of the memory;
A third step of writing test data to the test address of the memory;
A fourth step of reading test data from the test address of the memory;
A fifth step of comparing the test data read out in the fourth step with reference data stored in advance to determine the presence or absence of a failure;
A sixth step of writing back the data saved in the second step to the test address of the memory;
A memory diagnostic method comprising repeating the first to sixth steps.
(Appendix 5)
In the memory diagnosis method according to appendix 4,
A memory diagnostic method, comprising: managing a user area including an address determined to be a failure in the fifth step as a failure area, and allocating another non-failure area to the user assigned to the failure area.
(Appendix 6)
In the memory diagnosis method according to appendix 5,
The test data is a first value in which 1, 0 alternates and a second value in which 0, 1 alternates,
In the first step, the second to seventh steps are executed using the first value test data, and the second to seventh steps are executed using the second value test data. A memory diagnostic method, wherein the test address is changed.
(Appendix 7)
In the memory circuit described in Appendix 3,
2. The memory circuit according to claim 1, wherein the empty time slot is a period including the interframe gap, a preamble at the beginning of the frame, and a frame start demarcation point.
(Appendix 8)
In the memory diagnosis method according to appendix 6,
The memory diagnosis method according to claim 1, wherein the empty time slot is a period including the interframe gap, the preamble at the beginning of the frame, and the frame start demarcation point.

10 Interface unit 10
11-0 to 11-7 Optical transceiver 12 MAC processing unit 13 Priority control unit 14 Frame identification unit 15 Policer 16 Read / write control unit 17 Memory 18 Scheduler 19 Fault memory management unit 20 Interface unit 30 Switch fabric unit 40 CPU unit 51 Write control unit 52, data selector 53, 56 address selector 54 memory 55 read control unit 58 temporary flip-flop 61 test write control unit 62 test read control and check unit

Claims (6)

In a memory circuit that writes a frame received from a network to a memory assigned an area for each user, reads out frame data of each user from the memory, and supplies the frame data to subsequent circuits.
Test address generation by sequentially changing the test address for testing the memory in an empty time slot that includes a frame-to-frame gap , a frame leading preamble and a frame start demarcation point received from the network Means,
Saving means for saving data read from the test address of the memory;
Test writing means for writing test data to the test address of the memory;
Test read means for reading test data from the test address of the memory;
Determination means for determining the presence or absence of a failure by comparing the test data read by the test reading means with reference data held in advance;
Write-back means for writing back the data saved in the save means to the test address of the memory;
A memory circuit comprising: The memory circuit of claim 1, wherein
It comprises failure memory management means for managing a user area including an address determined to be a failure by the determination means as a failure area and allocating another non-failure area to the user assigned to the failure area. Memory circuit. The memory circuit according to claim 2.
2. The memory circuit according to claim 1, wherein the test data is a first value in which 1, 0 alternates and a second value in which 0, 1 alternates. In a memory diagnostic method for diagnosing a memory circuit that writes a frame received from a network to a memory assigned an area for each user, reads out frame data of each user from the memory, and supplies the frame data to a subsequent circuit,
A first step of generating by sequentially changing test addresses for testing the memory in an empty time slot which is a period including an inter-frame gap of a frame received from the network, a preamble at the beginning of a frame, and a frame start demarcation point When,
A second step of saving data read from the test address of the memory;
A third step of writing test data to the test address of the memory;
A fourth step of reading test data from the test address of the memory;
A fifth step of comparing the test data read out in the fourth step with reference data stored in advance to determine the presence or absence of a failure;
A sixth step of writing back the data saved in the second step to the test address of the memory;
A memory diagnostic method comprising repeating the first to sixth steps. The memory diagnostic method according to claim 4,
A memory diagnostic method, comprising: managing a user area including an address determined to be a failure in the fifth step as a failure area, and allocating another non-failure area to the user assigned to the failure area. The memory diagnostic method according to claim 5,
The test data is a first value in which 1, 0 alternates and a second value in which 0, 1 alternates,
In the first step, the second to seventh steps are executed using the first value test data, and the second to seventh steps are executed using the second value test data. A memory diagnostic method, wherein the test address is changed.

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