JP5412769B2 - Flash memory control device, flash memory control method, and flash memory control program - Google Patents

Description

  The present invention relates to a flash memory control device, and particularly eliminates the need to change the interface with firmware connected to the flash memory control device even when the block configuration and / or page configuration inside the flash memory is changed due to the expansion of the memory capacity. An object of the present invention is to provide a flash memory control device that can inherit the above.

  The flash memory is composed of a page that is an aggregate of a plurality of data and a plurality of blocks in which a plurality of pages are integrated. In addition, the flash memory has a characteristic that the write and read operations are accessed in units of pages, and the erase operation is accessed in units of blocks.

  The flash memory may need to be replaced from the mounted device due to the circumstances of the flash memory manufacturer, for example, due to lack of warranty or the end of production. In many cases, this replacement can be used only because a flash memory having the same capacity as that before the replacement has not already been distributed to the market due to rapid technological progress.

  Because the flash memory may have different numbers of blocks and pages per block due to the difference in memory capacity, the block number and page number identified by the address information inside the flash memory input from the outside are the same before and after this replacement. May be different. For this reason, in the case of the above-described replacement with a flash memory having a different number of pages per block, the flash memory erases up to a block that is not an erase target before the replacement in the erase process performed in units of blocks. Have

In order to solve this problem, a semiconductor memory device as a conventional flash memory control device includes a memory cell array in which electrically rewritable memory cells are arranged in a matrix, and a memory cell gate electrode. In a semiconductor memory device having a word line as a selection signal line, the number of memory cell pages simultaneously selected at the time of writing is variable, and each memory cell page includes a memory cell sharing a different word line (For example, refer to Patent Document 1).
Japanese Patent Laid-Open No. 2003-141883

  However, in the conventional flash memory control device, the number of blocks and the number of pages per block can be changed by an operation in the manufacturing stage, but cannot be changed by an operation on the user side. For this reason, the conventional flash memory control device has a problem that a user side firmware correction is required at the interface part with the flash memory, and the burden on the user side is heavy because of the large number of work steps for the firmware correction.

  The present invention has been made to solve the above-described problems. By converting the address information input to the flash memory, it is not necessary to modify the firmware on the user side, and the firmware resource can be used regardless of the generation of the flash memory. An object of the present invention is to provide a flash memory control device that can be inherited.

  The flash memory control device disclosed in the present application controls access to the flash memory after the change when the flash memory storing rewritable electrical data is changed to a flash memory having a different number of pages in block units. In the flash memory control device, the address information receiving means for receiving the address information in the flash memory, and whether to convert the received address information to the flash memory after the change based on an external input Determination means for determining whether or not information conversion calculation means for converting address information as correction address information based on the determination result, and when the information conversion is executed, based on the correction address information The flash memory is accessed.

  In this manner, the flash memory control device disclosed in the present application determines whether or not the determination unit converts the address information received by the address information reception unit by an external input to the changed flash memory. Since the information conversion operation means converts the address information as corrected address information based on the determination result, the address of the firmware which is the user side interface to the flash memory when the flash memory is newly replaced Without changing information, the same block of the flash memory can be accessed before and after the replacement, and write, read, and erase processes can be executed, and firmware resources can be inherited regardless of the generation of the flash memory.

  Further, the flash memory control device disclosed in the present application is provided with an adjusting unit that adjusts the access timing when the changed flash memory is accessed using the correction address information, as necessary. As described above, the flash memory control device disclosed in the present application adjusts the access timing to the flash memory when the adjustment unit uses the correction address information. This eliminates the need for additional work for synchronizing with the flash memory, and can be easily introduced without extra costs and work man-hours.

  Further, in the flash memory control device disclosed in the present application, the information conversion means uses a bit shift operation for information conversion of the address information as necessary. As described above, in the flash memory control device disclosed in the present application, since the information conversion unit uses a bit shift operation for information conversion of the address information, the flash memory before and after the replacement using a simpler operation method is used. On the other hand, access to the same block can be realized, and computational resources can be used effectively.

  The flash memory control device disclosed in the present application is mounted with the flash memory control device integrated with the flash memory, if necessary. As described above, since the flash memory control device disclosed in the present application is integrated with the flash memory, the flash memory control device has no additional work for firmware corresponding to the old version of flash memory. Addressing can be performed, and by maintaining backward compatibility, it can be easily introduced without extra costs and work man-hours.

  Further, the flash memory control device disclosed in the present application is mounted on a communication device as necessary. Thus, since the flash memory control device disclosed in the present application is mounted on the communication device, the effect of the modification or renewal of the communication device due to the renewal of the flash memory is suppressed. The usable period of the communication device can be extended, and the operation cost related to this communication apparatus can be reduced.

(First embodiment of the present invention)
Hereinafter, a flash memory control device according to a first embodiment of the present invention will be described with reference to FIGS. 1 is a block diagram showing a configuration of a flash memory control device according to a first embodiment of the present invention, FIG. 2 is a flowchart of the flash memory control device described in FIG. 1, and FIG. 3 is described in FIG. FIG. 4 shows an example of bit arrangement in the flash memory of the flash memory control device described in FIG. 1, and FIG. 5 shows a flash memory control device shown in FIG. FIG. 6 shows an example of the address shift calculation of the flash memory controller described in FIG. 1, FIG. 7 shows an example of the address shift result of the flash memory controller shown in FIG. Shows another example of the address shift calculation of the flash memory control device shown in FIG.

  Referring to FIG. 1, the flash memory control device according to the present embodiment is based on address information receiving means 1 for receiving address information in the flash memory 100 as command / data / address signal A from external input information 200, and input from the outside. Shift determination unit 2 as a determination means for determining whether or not to convert the received address information to the flash memory after the change, and the received address information is information based on the determination result. A shift circuit 3 serving as an information conversion calculation unit that generates correction address information by conversion, and an adjustment unit that adjusts the access timing when the changed flash memory is accessed using the correction address information. And a timing adjustment circuit 4.

  In addition, the shift determination unit 2 can receive a state setting signal B corresponding to the state of a state setting pin for setting the presence / absence of a bit shift and a bit shift method from the external input information 200. Further, the timing adjustment circuit 4 receives / CE, / RE, / WE, CLE, ALE, / WP, RY_ / BY as the control signal C from the external input information 200.

  The flash memory 100 includes an I / O register buffer 101 that temporarily stores an I / O bit signal from the outside as an interface with the outside, and a control circuit 102 that receives the control signal C. The flash memory 100 generates a memory cell array as a storage area, a row address decoder and column address data for controlling the memory cell array, a data register / sense amplifier for temporarily storing data, and a high voltage. A high voltage generation circuit, a command register for outputting input information from the I / O register buffer 101 to the control circuit 102 based on the input control signal C, and an input from the I / O register buffer 101 An address register that temporarily holds address information and a status register that holds a status indicating a current state in the I / O register buffer 101 based on an input from the control circuit 102 are provided.

The operation of the flash memory control device according to this embodiment based on the above configuration will be described below. First, as shown in FIG. 2, the flash memory 100 is replaced with a new flash memory 100 (S1).
For example, as shown in FIG. 3, it is assumed that the flash memory 100 is replaced from a 64M flash memory to a 256M flash memory. By this replacement, the number of pages per block is changed from 16 pages to 32 pages.

  In addition, as shown in FIG. 4A, for example, the bit arrangement in the flash memory is an I / O bit [7: 0] which is an 8-bit bit signal when the number of pages per block is 16 pages. Is defined for each cycle of the first cycle, the second cycle, and the third cycle. For example, the intra-block page address corresponds to bits A09 to A12 of the second cycle, that is, I / O bits [3: 0].

  In addition, as shown in FIG. 4B, the intra-block page address is the same as the bits A09 to A13 in the second cycle, that is, the I / O bit [4], even when the number of pages per block is 32 pages. : 0]. As described above, before and after the replacement, the arrangement of the page address in the block is different when the number of pages per block is 16 pages and 32 pages.

  The address information receiving means 1 receives the address information inside the flash memory 100 (S2). As this address information, the same command data address signal A as used for the flash memory 100 before the replacement is used. The command data address signal A can include address information as an 8-bit signal.

  The shift determination unit 2 receives a state setting signal B corresponding to the pin state of the state pin (S3). The state setting signal B can be provided as a 3-bit signal as shown in FIG. 5, and the bit shift operation method for the command / data / address signal A is defined in detail. For example, when the state setting signal B is set to “000”, the bit shift operation is not performed. When the state setting signal B is set to “011”, the bit shift operation is performed, and an odd number in the block is set. The address information is set only for the page.

  The shift determination unit 2 determines whether to perform a bit shift operation on the address information based on the state setting signal B (S4). When the bit shift operation is performed by this determination, the shift circuit 3 performs the bit shift operation according to the state setting signal B (S5).

  For example, as shown in FIG. 6, the shift circuit 3 has the following procedure when the setting of the state setting signal B is “011” and the address information is arranged only for odd pages in the block. A bit shift operation is performed on the address information.

  First, the shift circuit 3 shifts I / O [6: 0] of the second cycle up to 1 bit in the input address information (S101). The shift circuit 3 inserts a bit value 0 into I / O [0] (S104). The shift circuit 3 transmits the bit information at this time to the I / O register buffer 101, and latches I / O [7] of the address second cycle at this time.

  Next, the shift circuit 3 shifts the I / O [6: 0] of the third cycle up by 1 bit (S102). The shift circuit 3 inserts the latched second cycle I / O [7] into I / O [0] (S103). The shift circuit 3 transmits the bit information at this time to the I / O register buffer 101. The shift circuit 3 discards the third cycle I / O [7] because it is not used (S105).

  Next, the timing adjustment circuit 4 adjusts the transmission timing of the control signal C in order to synchronize with the timing of transmitting the shifted address to the I / O register buffer 101 (S6). The timing adjustment circuit 4 transmits the shifted address to the control circuit 102 at the adjusted timing, and accesses the flash memory (S7).

  Further, when the bit shift operation is not performed according to the determination of S4, the timing adjustment circuit 4 uses the input address information directly to access the flash memory as in S7. Note that the shift circuit 3 outputs data without shifting in the case of outputting data from the flash memory, for example, in the case of read processing.

  The shift circuit 3 can configure an address arrangement using odd pages as shown in FIG. 7 by the bit shift operation. With this configuration, the shift circuit 3 can perform processing without changing the address information from the firmware while maintaining the block number even when the 64M flash memory is replaced with the 256M flash memory. Even in the block batch erasing process in the erasing process, a normal erasing process can be performed without any inconvenience.

  As described above, the flash memory control device according to the present embodiment, when a flash memory is newly replaced, the flash memory before and after the replacement without changing the firmware address information which is an interface on the user side to the flash memory. The same block of memory can be accessed to perform write, read, and erase processing, and firmware resources can be inherited regardless of the generation of the flash memory.

  For example, as shown in FIG. 8, the shift circuit 3 has the following setting when the setting of the state setting signal B is “100” and the address information is arranged only for the even pages in the block. The bit shift operation is performed on the address information by the following procedure.

  First, the shift determination unit 2 detects that the state setting signal B from the state pin is “011” as in S3 of FIG. 2, and arranges address information only for even pages in the block. Determine what to do. Based on this determination, the shift circuit 3 shifts I / O [6: 0] of the second cycle up to 1 bit in the input address information (S201).

  The shift circuit 3 inserts a bit value 1 into I / O [0] (S204). The shift circuit 3 transmits bit information at this time to the I / O register buffer 101, and latches I / O [7] of the address second cycle at this time.

Next, the shift circuit 3 shifts the I / O [6: 0] of the third cycle up by 1 bit (S202). Further, the shift circuit 3 inserts the latched second cycle I / O [7] into I / O [0] (S203). The shift circuit 3 transmits the bit information at this time to the I / O register buffer 101. The shift circuit 3 discards I / O [7] in the third cycle because it is not used (S205). The subsequent processing is performed in the same manner as the processing after S6 in FIG.
As described above, since the bit shift operation is used, access to the same block can be realized with respect to the flash memory before and after the replacement by a simple operation method, and the calculation resources can be effectively used.

(Other embodiments of the present invention)
Hereinafter, a flash memory with an address control function using a flash memory control device according to another embodiment of the present invention will be described with reference to FIG. FIG. 9 is a block diagram showing a configuration of a flash memory control device according to another embodiment of the present invention.

  The flash memory with an address control function according to the present embodiment is similar to FIG. 1 describing the first embodiment, the address information receiving unit 1, the shift determination unit 2, the shift circuit 3, and the The timing adjustment circuit 4 is further provided, and the flash memory 100 is integrated and formed.

  As described above, since the flash memory control device is integrated with the flash memory, it can be addressed without additional work even for firmware corresponding to the old version of flash memory. Can be easily introduced without extra costs and man-hours.

  The flash memory control device in the first and other embodiments can also be mounted on a communication device. As described above, since the flash memory control device is mounted on the communication device, the present flash memory control device suppresses the influence of the modification or renewal of the communication device due to the renewal of the flash memory, and the usable period of this communication device. The operating cost associated with this communication apparatus can be reduced.

  In the first and other embodiments, the shift determination unit 2 accepts the state setting signal B corresponding to the pin state of the state pin, but the state is determined by using a command that replaces the state pin. It is also possible to accept the state setting signal B without a pin.

  Note that the device on which the flash memory targeted by the above embodiments is mounted is not limited to a communication device, and can be widely applied to devices that require memory. The shift circuit 3 performs the bit shift operation as the information conversion operation means. However, the operation method for converting the address information is not limited to this bit shift operation. It can also be implemented using a combination of logical operations, logical product, negation, and exclusive logical sum.

[Appendix] The following appendices are further disclosed with respect to the embodiment including the above examples.
(Supplementary Note 1) In a flash memory control device that controls access to a flash memory after the change when the flash memory storing rewritable electrical data is changed to a flash memory having a different number of pages in units of blocks Address information receiving means for receiving address information in the flash memory, and determination means for determining whether or not to convert the received address information to the flash memory after the change, based on an external input And information conversion operation means for generating corrected address information by converting the received address information based on the determination result, and when the information conversion is executed, based on the corrected address information A flash memory control device for accessing the flash memory.

(Supplementary note 2) The flash memory control device according to supplementary note 1, further comprising an adjusting unit that adjusts a timing of the access when the changed flash memory is accessed using the correction address information.

(Supplementary note 3) The flash memory control device according to Supplementary note 1 or 2, wherein the information conversion means uses a bit shift operation for the information conversion.

(Supplementary Note 4) A flash memory with an address control function in which the flash memory control device according to Supplementary Notes 1 to 3 is mounted integrally with the flash memory.

(Supplementary note 5) A flash memory-mounted communication device in which the flash memory control device according to any one of Supplementary notes 1 to 4 is mounted on a communication device.

(Supplementary note 6) In a flash memory control method for controlling access to a flash memory after the change when the flash memory storing electrical data in a rewritable manner is changed to a flash memory having a different number of pages in block units An address information receiving step for receiving address information in the flash memory, and a determination step for determining whether or not to convert the received address information to the flash memory after the change based on an external input And an information conversion calculation step for generating corrected address information by converting the received address information based on the determination result, and when the information conversion is executed, based on the corrected address information A flash memory control method for accessing the flash memory.

(Supplementary note 7) The flash memory control method according to supplementary note 6, further comprising an adjustment step of adjusting the access timing when the flash memory after the change is accessed using the correction address information.

(Supplementary note 8) The flash memory control method according to supplementary note 1 or 7, wherein the information conversion step uses a bit shift operation for the information conversion.

(Supplementary note 9) The flash memory control method according to supplementary notes 6 to 8, which is mounted integrally with the flash memory.

(Supplementary Note 10) When the flash memory that stores electrical data in a rewritable manner is changed to a flash memory in which the number of pages in other block units is different, the computer functions to control access to the flash memory after the change In the flash memory control program to be executed, address information receiving means for receiving address information in the flash memory, whether to convert the received address information to the flash memory after the change based on an external input When the information conversion is performed based on the correction address information, the computer functions as an information conversion calculation unit that converts the address information as correction address information based on the determination result. Access the flash memory Flash memory control program.

(Supplementary note 11) The flash memory control program according to supplementary note 10, which causes a computer to function as an adjustment unit for adjusting the access timing when the flash memory after the change is accessed using the correction address information.

(Supplementary note 12) The flash memory control program according to supplementary note 10 or supplementary note 11, wherein the information conversion means uses a bit shift operation for the information conversion.

(Supplementary note 13) The flash memory control program according to supplementary notes 10 to 12, which is integrated with the flash memory and mounted.

(Supplementary note 14) A flash memory-installed communication program in which the flash memory control program according to supplementary notes 10 to 13 is installed in the communication program.

1 is a block diagram showing a configuration of a flash memory control device according to a first embodiment of the present invention. 1 is a flowchart of a flash memory control device of a flash memory control device according to a first embodiment of the present invention. Example of flash memory replacement in the flash memory control device according to the first embodiment of the present invention Example of bit arrangement in flash memory of flash memory control device according to first embodiment of present invention Setting example of state setting signal of flash memory control device according to first embodiment of the present invention Example of address shift calculation of flash memory control device according to first embodiment of present invention Example of an address shift result of the flash memory control device according to the first embodiment of the present invention Another example of address shift calculation of the flash memory control device according to the first embodiment of the present invention The block diagram which shows the structure of the flash memory control apparatus which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Address information reception means 2 Shift determination part 3 Shift circuit 4 Timing adjustment circuit 100 Flash memory 101 I / O register buffer 102 Control circuit 200 External input information A Command data address signal B Status setting signal C Control signal

Claims (6)

In the flash memory control device for controlling access to the flash memory after the change when the flash memory storing the electrical data in a rewritable manner is changed to a flash memory having a different number of pages in other block units,
Address information receiving means for receiving address information in the flash memory;
Determining means for determining whether to convert the received address information to the flash memory after the change based on an external input;
Based on the determination result, the received address information is information-converted using a bit shift operation, and information conversion calculation means for generating corrected address information,
A flash memory control device that accesses the flash memory based on the correction address information when the information conversion is executed. The flash memory control device according to claim 1,
A flash memory control device comprising adjustment means for adjusting the access timing when the changed flash memory is accessed using the correction address information. 3. A flash memory with an address control function, wherein the flash memory control device according to claim 1 or 2 is mounted integrally with the flash memory. The flash memory control device according to any one of claims 1 to 3, wherein the flash memory control device is mounted on a communication device. In the flash memory control method for controlling access to the flash memory after the change when the flash memory storing the rewritable electrical data is changed to a flash memory having a different number of pages in other block units,
An address information receiving step for receiving address information in the flash memory;
A determination step of determining whether to convert the received address information to the flash memory after the change based on an input from the outside;
An information conversion calculation step of generating corrected address information by converting the received address information using bit shift calculation based on the determination result;
A flash memory control method for accessing the flash memory based on the correction address information when the information conversion is executed. Flash memory control that allows the computer to function to control access to the flash memory after the change when the flash memory that stores electrical data in a rewritable manner is changed to a flash memory with a different number of pages for each block. In the program
Address information receiving means for receiving address information in the flash memory;
Determining means for determining whether to convert the received address information to the flash memory after the change, based on an external input;
Based on the determination result, the received address information is information-converted using a bit shift operation, and a computer is caused to function as information conversion operation means for generating corrected address information ,
A flash memory control program for accessing the flash memory based on the correction address information when the information conversion is executed.