JP5411065B2 - Reference clock restoration method, packet multiplexer, packet separator, and transmission system - Google Patents

Description

  The present invention relates to a transmission system in which a transmission side transmits a plurality of types of signals simultaneously using a reference clock using a single transmission medium, a method for restoring the reference clock, a packet multiplexing device for the transmission system, and a packet separation device for the transmission system. Is.

  When transmitting / receiving digital video signals, audio signals, and data signals via a transmission line such as a communication system that assumes handling of an error-prone environment or a broadcasting system such as multi-channel digital broadcasting, generally MPEG ( A standard called Moving Picture Experts Group) -2 Systems is used (see, for example, Non-Patent Document 1). In MPEG-2 Systems, when part 1 encodes video, part 3 encodes audio, and part 1 multiplex transmits part 2 and part 3 signals, the received signals are synchronized. Multiple encoding schemes that can be reproduced have been standardized. Regarding encoding of a video signal having a large data capacity, the MPEG system (MPEG-1: ISO / IEC 11172, MPEG-2: ISO / IEC 13818) compresses the original video digital data in order to reduce the capacity. In addition to H.) recently. The H.264 / AVC system (ISO / IEC 14496-10) has also been put into practical use.

  These compressed digital signals such as video signals, audio signals, and data signals are transferred to TS (Transport Stream) packets having a fixed length of 188 bytes to which a 4-byte header specified in MPEG-2 Systems is added. Stored and distributed. In the digital broadcasting system, a total of 204-byte TS packets subjected to FEC (Forward Error Correction) using a 16-byte Reed-Solomon code are used.

  In addition to the compressed video / audio digital signal, the TS packet also stores a control signal such as a data signal, program scheduling information, and PCR (Program Clock Reference).

  In digital broadcasting, the STC of the receiving side decoding unit is synchronized with the 27 MHz STC (System Time Clock), which is the reference clock of the transmitting side coding unit, using the time interval between the PCR value and the TS packet storing the PCR. Yes. Here, the PCR is composed of 42 bits and is composed of a counter value counted at 27 MHz.

  MPEG-2 Systems stipulates that the PCR (transmission interval) is 100 msec or less and the jitter is 500 nsec or less in order for the receiving side decoder PLL (Phase Lock Loop) to operate correctly and stabilize STC synchronization. .

  By the way, when TS packets are transmitted on an IP (Internet Protocol) network such as IPTV, a plurality of TS packets are stored and transmitted in one IP packet in order to improve transmission efficiency. At this time, since invalid data existing between TS packets before storage is deleted, time interval information between TS packets disappears. For this reason, for the purpose of restoring time interval information between TS packets, a TTS (Timer) in which a linear 32-bit counter value counted by a 27 MHz clock of the STC is added to a TS packet as a 4-byte time stamp when the TS packet is stored. -Stamped TS) is standardized (see, for example, Non-Patent Document 2).

  On the other hand, in the IP network, fluctuations occur in the IP packet arrival time interval due to congestion. Furthermore, since the IP network is asynchronous, different processing clocks are used in the devices in the network. In each apparatus, in order to absorb different processing clocks, IFG (Inter Frame Gap) between IP packets is inserted and extracted. Therefore, in the IP network, fluctuations in the IP packet interval also occur due to insertion / extraction of IFG.

  As described above, in a normally used IP network, it is difficult to transmit while maintaining the IP packet interval. Therefore, when normal TS packets are distributed over an IP network, fluctuations in the IP packet interval occur, and it is difficult to correctly reproduce video, audio, and data signals.

  However, if the adaptive clock method is used, the time interval of IP packets can be preserved (see, for example, Non-Patent Document 3). This is done in the manner described below. That is, the time stamp counted at the processing clock frequency of the transmission side apparatus is stored in the IP packet and transmitted. An IP packet having a fluctuating packet interval transmitted through the IP network is buffered in the receiving apparatus, and the fluctuation is absorbed. Then, the transmission side apparatus and the reception side apparatus can be synchronized by adapting the processing clock frequency of the reception side apparatus to the processing clock frequency of the transmission side apparatus based on the counter value of the time stamp stored in the IP packet. . At this time, if the frequency of the clock of the transmission side apparatus and the frequency of the clock of the reception side apparatus reproduced by the time stamp are different, the capacity of the buffer increases or decreases. In the receiving side apparatus, it is possible to synchronize with the clock of the transmitting side apparatus by adjusting the reproduction clock frequency counted by the time stamp so that the capacity of the buffer becomes constant.

  In order to restore TS packets on the IP network, the IP packet time interval is saved, the IP packet is buffered, and the TS packet stored in the IP packet is clocked based on the time information at the time of input. It is necessary to output from the IP packet in the buffer.

  Even in this case, it is possible to synchronize the processing clock of the receiving apparatus with the processing clock of the transmitting apparatus by using the adaptive clock method for TS packets.

  Specifically, in the transmission side apparatus, the TS packet is given a time stamp value counted using a processing clock synchronized with the clock frequency of the STC, and stored in the IP packet as a TTS packet. The TTS packet is buffered at the receiving device. Then, the transmission side apparatus and the reception side apparatus can be synchronized by adapting the processing clock frequency of the reception side apparatus to the processing clock frequency of the transmission side apparatus based on the counter value of the time stamp stored in the TTS packet. . At this time, if the frequency of the clock of the transmission side apparatus is different from the frequency of the clock of the reception side apparatus reproduced by the time stamp, the capacity of the buffer increases or decreases. By adjusting the reproduction clock frequency counted by the time stamp so that the capacity of the buffer is constant in the reception side device, the processing clock of the reception side device can be synchronized with the processing clock of the transmission side device. .

  Since the adaptive clock method is performed for one IP or TS packet stream, a clock of a plurality of TS packet streams that multiplex and transmit a plurality of video, audio, and data signals using the adaptive clock method. In the case of reproduction, it is necessary to perform adaptive clock synchronization in each receiving apparatus or decoder after separating each stream.

  Therefore, as shown in FIG. 1, when a broadcasting station having one reference clock 203 transmits a plurality of video, audio, and data signals by a plurality of encoders 202, the transmitting side 200 transmits all STCs generated from the reference clock 203. Therefore, the receiving side 250 reproduces the same STC by the corresponding decoder 252 by the adaptive clock method. In FIG. 1, the layer 2 switch 205 determines a relay destination based on a MAC (Media Access Control) address included as destination information in the packet, and performs a relay operation.

ISO / IEC 13818-1 ARIB STD-B24 Volume 2 R. P. Singh, S.H. H. Lee, “Adaptive clock synchronization schemes for real-time traffic in broadband packet networks” in Proc. 8th European Conf. on Electrotechnics, 1988, pp 84-88.

  However, the adaptive clock method separates all transmitted video, audio, and data signal TS packet streams, and then restores the clock in each decoder for the number of streams to be transmitted. There is a problem that the configuration on the receiving side becomes redundant, for example, the number of decoders is required. This tendency becomes more prominent as the number of flowing streams increases.

  Furthermore, since the adaptive clock method performs buffering, there is a problem that a delay occurs and the real-time property of the video is impaired.

  Therefore, in order to solve the above problem, the present invention broadcasts TS packets from HE (Head-End) upstream of the distribution network, and does not generate fluctuation due to congestion as in a normal IP network, and When transmitting on the receiving side a plurality of types of signals distributed from the transmitting side having one reference clock when transmitting by an asynchronous communication network in which the cause of fluctuations other than congestion is only IFG insertion / extraction An object of the present invention is to provide a reference clock recovery method, a packet multiplexing device, a packet separation device, and a transmission system in which a plurality of decoders on the receiving side can be synchronized with the STC of each encoder on the transmitting side with a single clock recovery unit. And

  In order to achieve the above object, a reference clock restoration method according to the present invention includes a packet fluctuation detection unit of a packet separation device in an IP network that attempts to absorb a difference in processing clock between devices by inserting / extracting an IFG in a transmission frame. Based on the IFG insertion / removal information obtained by the above, the processing frequency of the packet multiplexer and the processing clock of the packet separator are synchronized by changing the clock frequency in the packet separator.

  Specifically, in the reference clock restoration method according to the present invention, a plurality of fixed-length packet parts are arranged on the transmission side so as to sandwich a fixed-length interframe gap (IFG), and based on the reference clock, When the transmission frame transmitted by performing packet multiplexing processing for storing a signal in the packet part is temporarily stored in the buffer at the receiving side, the transmission frame is stored so that the storage amount of the buffer is within a predetermined range. The IFG is inserted and removed, and the reference clock on the receiving side is synchronized with the reference clock on the transmitting side by controlling the frequency based on the insertion and removal information of the IFG.

  When the transmission frame output from the packet multiplexer is received, the processing clocks of the packet multiplexer and the packet separator differ from each other. Therefore, the packet separator absorbs the clock deviation by inserting and removing the IFG. This reference clock restoration method controls the frequency of the processing clock on the reception side based on this IFG insertion / extraction information and synchronizes with the reference clock on the transmission side.

  Accordingly, when receiving a plurality of types of signals distributed from a transmission side having one reference clock on the reception side, the present invention allows a plurality of decoders on the reception side to be connected to the transmission side in a single clock recovery unit. A reference clock recovery method that can be synchronized with the STC of each encoder can be provided.

  In the reference clock restoration method according to the present invention, the IFG insertion / extraction information indicates the number of the packet parts from the packet part immediately before the IFG in which the insertion / extraction has occurred to the packet part immediately before the IFG in which the next insertion / extraction has occurred. It is a time interval in which insertion / extraction of the IFG approximated by using occurs.

  This reference clock restoration method can approximate the time interval at which IFG insertion / extraction occurs even when the instant at which IFG insertion / extraction cannot be detected accurately.

  The packet multiplexing apparatus according to the present invention is based on a transmission frame generation unit that generates a transmission frame by arranging a plurality of fixed-length packet units so as to sandwich a fixed-length interframe gap (IFG), and a reference clock, A packet switching unit that performs packet multiplexing processing for storing a signal in the packet part of the transmission frame generated by the transmission frame generation unit and transmits the transmission frame in which the signal is stored in the packet part.

  This packet multiplexing apparatus forms a transmission frame in which IFGs that can be inserted and removed are arranged between packet parts based on a reference clock, and performs multiplexing processing by storing signals in the packet parts. If the IFG is inserted / removed on the receiving side, the processing clock deviation between the packet multiplexer and the packet separator can be absorbed.

  Accordingly, when receiving a plurality of types of signals distributed from a transmission side having one reference clock on the reception side, the present invention allows a plurality of decoders on the reception side to be connected to the transmission side in a single clock recovery unit. It is possible to provide a packet multiplexer capable of transmitting a transmission frame that can be synchronized with the STC of each encoder.

  The packet switching unit of the packet multiplexing apparatus according to the present invention determines the number of the packet units to be stored in the signal based on the transmission rate of the signal.

  This packet multiplexing apparatus can flexibly cope with multiplexing of video, audio or data signal packets having different transmission rates.

  Meanwhile, the packet separation device according to the present invention temporarily stores the transmission frame from the packet multiplexing device in a buffer in a physical layer, and the IFG of the transmission frame so that the storage amount of the buffer is within a predetermined range. Is a packet fluctuation detection unit that detects the location where the packet is inserted and removed in the buffer of the physical layer by measuring the packet interval, and the frequency is controlled based on the IFG insertion / extraction information output by the packet fluctuation detection unit. A clock control unit that synchronizes a reference clock with a reference clock of the packet multiplexer, and a reference clock that is controlled by the clock control unit, and is stored from the packet unit of the transmission frame that is output from the buffer An output destination switching unit that extracts a signal and outputs the signal for each type of the signal.

  When receiving a transmission frame transmitted from the packet multiplexer, this packet separator detects IFG fluctuation caused by a difference in processing clock between the packet multiplexer and the packet separator, and The reference clock is restored and output.

  Therefore, when receiving a plurality of types of signals distributed from the transmission side having one reference clock on the reception side, the packet separation apparatus transmits a plurality of reception side decoders using a single clock recovery unit. It is possible to provide a packet separation device that can be synchronized with the STC of each encoder on the side.

  The clock control unit of the packet separation device according to the present invention approximates using the number of the packet parts from the packet part immediately before the IFG in which insertion / extraction has occurred to the packet part immediately before the IFG in which the next insertion / extraction has occurred. The time interval at which the IFG is inserted / removed is used as the IFG insertion / removal information.

  Even when the instant at which IFG insertion / removal cannot be accurately detected, the present packet separation apparatus can approximate the time interval at which IFG insertion / removal occurs.

  A transmission system according to the present invention includes the packet multiplexing device and the packet separation device.

  The transmission system includes the packet multiplexing device and the packet separation device. Accordingly, when receiving a plurality of types of signals distributed from a transmission side having one reference clock on the reception side, the present invention allows a plurality of decoders on the reception side to be connected to the transmission side in a single clock recovery unit. A transmission system that can be synchronized with the STC of each encoder can be provided.

  In the present invention, when receiving a plurality of types of signals distributed from a transmitting side having one reference clock on the receiving side, a plurality of decoders on the receiving side are connected to each code on the transmitting side by a single clock recovery unit. A reference clock restoration method, a packet multiplexing device, a packet separation device, and a transmission system that can be synchronized with the STC of the receiver can be provided.

It is a figure explaining the transmission system using an adaptive clock method. (A) It is a figure explaining the structure of a transmission frame. (B) It is a figure explaining the structure of a packet part. It is a figure explaining the reference clock decompression | restoration method based on this invention. It is a figure explaining the transmission system concerning the present invention. It is a figure explaining the packet multiplexing apparatus which concerns on this invention. (A) It is a figure explaining the structure of a transmission frame. (B) It is a figure explaining the structure of a packet part. It is a figure explaining the packet separation apparatus which concerns on this invention. It is a figure explaining the outline | summary of the IFG insertion / extraction space | interval calculation method.

  Embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments described below are examples of the present invention, and the present invention is not limited to the following embodiments. In the present specification and drawings, the same reference numerals denote the same components.

  The transmission system of the present embodiment includes a packet multiplexing device and a packet separation device. The transmission system, for example, broadcasts TS packets from HE (Head-End) upstream of the distribution network, does not cause fluctuation due to congestion as in a normal IP network, and causes of fluctuations other than congestion are IFG This is applied to the case where transmission is performed by an asynchronous Ethernet (registered trademark) network in which only insertion / extraction is performed.

  The packet multiplexing device includes: a transmission frame generation unit that generates a transmission frame by arranging a plurality of fixed-length packet units so as to sandwich a fixed-length IFG; and the transmission frame generated by the transmission frame generation unit based on a reference clock A packet switching unit that performs packet multiplexing processing for storing a signal in the packet unit and transmits the transmission frame in which the signal is stored in the packet unit.

  The packet multiplexing apparatus has a port for inputting an external clock, and has a function of performing processing such as multiplexing with a reference clock generated by multiplying the frequency of the input clock (multiplication ratio: A). Further, the packet multiplexing apparatus has a function of internally generating a transmission frame as shown in FIG. 2A composed of a fixed-length packet part (91, 92) and a fixed-length IFG 93. In this transmission frame, packet portions and IFGs 93 are alternately arranged. The packet portion of the transmission frame is a header packet portion 91 or a content packet portion 92 that stores a signal to be transmitted. FIG. 2B illustrates the structure of this packet part. The packet part includes a preamble, an SFD (Start Frame Delimiter) (“Preamble + SFD” in the figure), a destination address (“DA” in the figure), a source address (“SA” in the figure), a VLAN (Virtual LAN) tag header (in the figure). "VLAN"), length and type ("Type / Length" in the figure), data ("Payload" in the figure), and FCS (Frame Check Sequence).

  The preamble is a signal for allowing the interface connected to the LAN to recognize the start of transmission frame transmission and to give synchronization timing. The SFD indicates that the destination address part starts from the next bit. For example, the preamble is 7 bytes and the SFD is 1 byte.

  The destination address is the MAC address of the interface of the station that is the destination. For example, the destination address is 6 bytes. The source address is the MAC address of the interface that transmitted the transmission frame. For example, the transmission address is 6 bytes.

  As the VLAN tag header, a tag header for VLAN used by the switching hub is designated (for example, refer to IEEE 802.1Q). In this embodiment, a multiplex number for multiplexing signals is described. For example, the VLAN tag header is 4 bytes.

  The length and type specify the length and type of the signal stored in the next data field. For example, the length and type are 2 bytes. In the data, a signal to be transmitted is stored. The FCS receives a value for detecting an error in the transmission frame. For example, the value is a CRC (Cyclic Redundancy Check) value calculated from each field of destination address, source address, length / type, and data. Similarly, the reception side calculates the CRC, and if it does not match the value of the FCS field, it determines that an error has occurred and discards the transmission frame. For example, FCS is 4 bytes.

  At this time, the packet part is a header packet part and a content packet part, and the transmission frame is composed of one header packet part and a plurality of content packet parts (number: M). A unique number (multiplex number) indicating position information in the transmission frame is defined in the VLAN field in the header packet part and each content packet part.

  A signal in which a plurality of TTS packets are stored is output from each encoder, and stored in a content packet portion having a predetermined multiplex number in the packet multiplexer. At this time, the packet switching unit determines the number of the packet units to be stored in the signal based on the transmission rate of the signal. By assigning a plurality of multiplexing numbers to high-speed video, audio and data signals, it is possible to flexibly cope with multiplexing of video, audio and data signals having different transmission rates.

  On the other hand, the packet separation device temporarily stores the transmission frame from the packet multiplexing device in a buffer of the physical layer, and the IFG of the transmission frame is stored in the physical layer so that the storage amount of the buffer is within a predetermined range. The packet fluctuation detection unit that detects the portion inserted / extracted in the buffer by measuring the packet interval, and the reference clock by controlling the frequency based on the IFG insertion / extraction information output by the packet fluctuation detection unit A clock control unit that synchronizes with a reference clock of the packet multiplexing device, and a reference clock that is controlled by the clock control unit, takes out a signal stored from the packet part of the transmission frame output from the buffer, And an output destination switching unit that outputs each signal type.

  The packet separator receives the transmission frame transmitted from the packet multiplexer and restores the processing clock frequency in the packet multiplexer by detecting the IFG fluctuation caused by the difference in processing clock with the packet multiplexer. In addition, the reference clock of the packet multiplexer is restored and output.

  When the transmission frame output from the packet multiplexer is received, the processing clocks of the packet multiplexer and the packet separator differ from each other. Therefore, the packet separator absorbs the clock deviation by inserting and removing the IFG. For example, IEEE 802.3 stipulates that the expansion and contraction of the IFG is performed in units of 4 bytes in the physical layer. In this operation, a packet is buffered in a clock deviation absorption buffer in the physical layer, a time change of the buffer amount is monitored, and control is performed so that the buffer does not fail.

  For example, when the processing clock frequency of the packet multiplexer is higher than that of the packet separator, the buffer in the packet separator overflows. Therefore, the packet separator sets an overflow threshold in the buffer, and exceeds the threshold 4 Delete byte IFG.

  On the other hand, when the processing clock frequency of the packet multiplexer is lower than that of the packet separator, the buffer underflows. Therefore, the packet separator sets an underflow threshold value in the buffer, and if the threshold value falls below the threshold, the 4-byte IFG Insert.

  FIG. 3 is a processing flow for explaining the reference clock restoration method of this embodiment. This reference clock restoration method is as follows. When a packet is input to the packet separator (step S01), the packet fluctuation detection unit determines whether or not the interval from the previous packet is a set value (step S02). The packet fluctuation detection unit can determine whether the IFG has been inserted or removed by observing the interval from the previous packet. When the packet fluctuation detection unit determines that the interval from the previous packet is a set value, the clock control unit does not adjust the clock frequency (step S03). When the interval with the previous packet changes, the packet fluctuation detection unit determines whether the interval has increased (step S04). When the interval is shortened, that is, when 4-byte IFG deletion is detected, the clock control unit increases the processing clock frequency of the packet separation device (step S06). On the other hand, when the interval is increased, that is, when insertion of 4-byte IFG is detected, the clock control unit decreases the processing clock frequency of the packet separation device (step S05). Thus, the reference clock restoration method of this embodiment can synchronize the processing clock frequencies of the packet multiplexer and the packet separator.

  Further, when the packet multiplexer generates the processing clock by multiplying the reference clock input from the input port by the multiplication factor A, the packet separation device multiplies the processing clock by the reciprocal 1 / A of the multiplication factor A. The reference clock may be output from the packet separator to a plurality of decoders. Since the processing clock generated by the packet multiplexer is generated by multiplying the reference clock by A, the clock generated by multiplying the processing clock restored by the packet separator by 1 / A is input to the packet multiplexer. It will be synchronized with the reference clock.

  This clock synchronization method is only possible by detecting the expansion / contraction of the IFG between the packet parts in the transmission frame, and it is not necessary to perform control using buffer monitoring as in the adaptive clock method. For this reason, this clock synchronization method can reduce the time until clock synchronization associated with the clock recovery processing of a packet.

  Further, the packet separation device detects the multiplex number written in the VLAN field in the content packet portion of the received transmission frame, and if it is a number to be separated, the packet separation device sends the signal in the content packet portion to a predesignated port. Multiplexed signals can be separated by outputting them.

  The packet multiplexing device and the packet separation device according to the present embodiment can receive only one clock recovery process even when a broadcasting station or the like having one reference clock transmits a plurality of video, audio, and data signals to a remote place. The plurality of decoders can use STCs corresponding to the STCs of the individual encoders on the transmission side, and there is no need to install a plurality of clock recovery devices on the reception side.

(Example)
FIG. 4 is a diagram illustrating the transmission system 301 of the present embodiment. The transmission system 301 includes a packet multiplexing device 201 on the transmission side 200 and a packet separation device 251 on the reception side 250. The transmission side 200 includes a broadcast station having N encoders 202 that operate with one common reference clock 203 and a packet multiplexing apparatus 201. The receiving side 250 includes a packet separator 251 and N decoders 252 that operate on a reference clock 253 output from the packet separator 251.

  The transmission system 301 transmits all video, audio, and data signals to a remote station to a remote station having N encoders 202 operating with one common reference clock 203, and decodes them with each encoder 202. The purpose is to synchronize the STC of the device 252.

  For example, the interface between the encoder 202 and the packet multiplexer 201 is 1GE (one Gigabit Ethernet (registered trademark)), the interface between the decoder 202 and the packet separator 251 is 1GE, and the interface between the packet multiplexer and the packet separator is 10GE (Ten Gigabit Ethernet (registered trademark)).

  The encoder 202 stores and outputs a plurality of TS packets in one packet (for example, Ethernet (registered trademark) packet). At this time, a TTS with a time stamp is used for the TS packet in order to hold the time interval of the TS packet. The clock frequency used for the time stamp is 27 MHz generated from the reference clock.

  The packet multiplexer 201 generates a transmission frame as shown in FIG. The packet multiplexing device 201 multiplexes the packet output from each encoder 202 into the content packet portion in the transmission frame having a predetermined multiplex number, and outputs the transmission frame. For example, as specified in IEEE 802.3, 10GE internal processing is 64-bit parallel processed using a reference clock 203 having a frequency of 156.25 MHz.

  The packet multiplexer 201 receives the reference clock 203 used by the encoder 202, and generates a 10GE processing clock by multiplying the reference clock 203. In broadcasting, video and audio signals are transmitted without being disturbed, and the reference clock 203 is required to have a highly accurate frequency. In the case of digital broadcasting, a 10 MHz clock using a rubidium oscillator is generally used as the reference clock 203. Therefore, also in this embodiment, the frequency of the reference clock 203 is 10 MHz.

  FIG. 5 is a diagram for explaining the packet multiplexer 201. The packet multiplexing device 201 includes a transmission frame generation unit 12 that generates a transmission frame by arranging a plurality of fixed-length packet units so as to sandwich a fixed-length IFG, and the transmission generated by the transmission frame generation unit 12 based on a reference clock 203. A packet switching unit that performs packet multiplexing processing for storing a signal in the packet part of the frame and transmits the transmission frame in which the signal is stored in the packet part.

  The packet multiplexer 201 includes a multiplexer 10 that multiplexes video, audio, and data signals input from a 1GE port into a transmission frame, and a clock converter that generates a processing clock of the multiplexer from an externally input reference clock 203. Have 20.

  The frequency conversion unit 21 of the clock conversion unit 20 multiplies the input reference clock 203 and sends the clock to the multiplexing unit 10 as a processing clock. When the input reference clock 203 is 10 MHz and the processing clock of the multiplexing unit 10 is 156.25 MHz, the multiplication factor A is 156.25 / 10 = 125/8.

  Multiplexer 10 receives each packet storing video, audio and data signals sent from each encoder 202. The packet switching unit 14 mounts each packet at a fixed position of the transmission frame generated by the transmission frame generation unit 12 and performs multiplexing.

  First, the multiplex standby unit 15 buffers a packet for each port until a content packet unit designated in advance is output from the transmission frame generation unit 12. The multiplex number identifying unit 13 identifies the multiplex number described in the VLAN field of each content packet part of the transmission frame output from the transmission frame generating unit 12. At this time, if the identified multiplex number is written in the multiplex position table 11 and matches a multiplex number that differs for each port, the multiplex number identifying unit 13 sends the multiplex waiting unit 15 corresponding to that port to the subsequent multiplex number. Instructs the number assigning unit 16 to output a packet.

  The multiplex number assigning unit 16 assigns a designated multiplex number to the VLAN field to the packet transmitted from the multiplex standby unit 15. The packet replacing unit 14 replaces the packet part of the transmission frame output from the multiple number identifying unit 13 with a packet having the same multiple number that has arrived from the multiple number assigning unit 16. By performing this process on a plurality of packet streams, a plurality of packets are multiplexed into a transmission frame.

  The transmission frame output from the packet switching unit 14 is sent to the subsequent packet separator.

  FIG. 6A is a diagram for explaining a transmission frame structure transmitted by the packet multiplexer 201. The transmission frame is composed of one header packet part 91 and a plurality of content packet parts 92. FIG. 6B illustrates the structure of the header packet unit 91 and the content packet unit 92. The header packet portion 91 and the content packet portion 92 have fixed sizes of 336 bytes and 1536 bytes, respectively, and the IFG 93 between these packets is a multiple of the IFG insertion / extraction processing performed in units of 4 bytes as described above. There are 64 bytes.

  The number of content packet units 92 in the transmission frame may be freely set according to the number of video, audio and data signals to be transmitted, or the transmission capacity. In this example, the case of 781 will be described. When one video, audio, or data signal stream is assigned to one content packet unit 92 in a transmission frame, the stream is about 10 Mbps. If a plurality of content packet sections 92 are allocated, digital terrestrial broadcasting 1ch (about 17 Mbps), BS digital broadcasting 1ch (about 23 Mbps), and video, audio and data signals having a transmission rate exceeding 100 Mbps with higher definition. Can be handled flexibly.

  FIG. 7 is a diagram for explaining the packet separation device 251. The packet separation device 251 temporarily stores the transmission frame from the packet multiplexing device in a physical layer buffer, and the IFG of the transmission frame is stored in the physical layer buffer so that the storage amount of the buffer is within a predetermined range. The packet fluctuation detecting unit 32 for detecting the position inserted and removed by measuring the packet interval, and the reference clock signal by controlling the frequency based on the IFG insertion / extraction information output from the packet fluctuation detecting unit 32 The clock control unit 41 synchronized with the reference clock 201 and the reference clock controlled by the clock control unit 41 are used to extract the signal stored from the packet part of the transmission frame output from the buffer, and the signal type And an output destination switching unit 34 for outputting each time.

  The packet separation device 251 includes a physical layer chip (not shown), a separation position table 31, a packet fluctuation detection unit 32, a multiplex number identification unit 33, an output destination switching unit 34, and a multiplex number deletion unit 35. A reference clock generation unit 40 having a clock control unit 41, a clock adjustment unit 42, and a frequency conversion unit 43.

  The transmission frame output from the packet multiplexer 201 is input to the packet fluctuation detection unit 32. Since the processing clock used in the separation unit 30 is not synchronized with the processing clock of the packet multiplexing device 201 when the packet separation device 251 is activated, the physical layer chip uses the IFG of the transmission frame so as to eliminate the difference in the processing clock. Insert and remove. Therefore, the packet part interval of the received transmission frame, that is, the arrival time of the packet fluctuates.

  The packet fluctuation detection unit 32 detects the fluctuation of the packet arrival time. Specifically, the packet fluctuation detection unit 32 measures the interval between the received packet unit and the packet unit that arrives immediately before, and detects that the value is not the packet unit interval specified in advance. In this case, IFG insertion / extraction information is sent to the clock control unit 41 at the subsequent stage. Here, the IFG insertion / extraction information is information that the IFG has been inserted or deleted, information on the number of insertion / extraction bytes, and time information from when the previous insertion / extraction occurred until the current insertion / extraction occurred. These are the three.

  The clock control unit 41 controls the frequency of the processing clock output from the clock adjustment unit 42 based on the IFG insertion / extraction information transmitted from the packet fluctuation detection unit 32. Specifically, in the case of IFG insertion / extraction information indicating that an IFG has been inserted, the processing clock frequency of the packet separation device 251 is assumed to be larger than the processing clock frequency of the packet multiplexing device 201, and thus the clock control unit 41. Decreases the frequency of the processing clock output from the clock adjustment unit 42. On the other hand, in the case of IFG insertion / extraction information indicating that the IFG has been deleted, since the processing clock frequency of the packet separation device 251 is assumed to be smaller than the processing clock frequency of the packet multiplexing device 201, the clock control unit 41 The frequency of the processing clock output from the adjustment unit 42 is increased. The amount of increase or decrease in the frequency of the processing clock performed by the clock adjustment unit 42 may be a constant value or a variable value.

  FIG. 8 is a diagram for explaining an IFG insertion / extraction interval calculation method. Since the header packet part in the transmission frame is very small compared to the number of content packet parts, it can be ignored in calculating the frequency adjustment amount of the processing clock.

The time (T _interval [sec]) from the time when the previous insertion / extraction occurs to the time when this insertion / extraction occurs and the frequency difference (Δf [Hz]) between the processing clocks of the packet multiplexer 201 and the packet separator 251 The relationship is sought as follows.

IFG insertion / extraction is performed by IEEE. According to 802.3, it occurs in units of 4 bytes in 10GE. In other words, the time interval at which IFG insertion / extraction occurs is the time until the buffer reaches the threshold again from the storage amount that is 4 bytes away from the threshold at which the buffer storage amount overflows or underflows. Therefore, the time interval T _interval at which IFG insertion / extraction occurs is
T _interval = 4 × 8 / (| Δf | × 8 × 8)
= 1 / (2 × | Δf |) (1)
It becomes.

Δf is | Δf | = 1 / (2 × T _interval ) (2)
It becomes.

On the other hand, if Δf is the processing clock (f _tx [Hz]) of the packet multiplexer and the processing clock (f _rx [Hz]) of the packet separator, Δf = f _tx −f _rx (3)
It can be expressed as.

  However, since the packet fluctuation detection unit 32 has only a function of counting the number of IFG bytes, it cannot accurately detect the moment when the IFG insertion / extraction occurs. Therefore, the packet separator 251 pays attention to the packet immediately before the IFG where the IFG insertion / extraction occurs, and approximates the time interval at which the IFG insertion / extraction occurs using the number of packets between the packets. Specifically, the clock control unit 41 uses the number of packet parts from the packet part immediately before the IFG in which insertion / extraction has occurred to the packet part immediately before the next IFG to generate an approximate IFG insertion / extraction time interval. Is IFG insertion / extraction information.

In the transmission frame in the transmission system 301, the number of bytes between the content packet parts is 1600 bytes. Therefore, when there is no IFG insertion / extraction, the content packet part interval T _p received by the packet separation device 251 is:
T _p = (1600 × 8) / ((f _rx ) × 8 × 8)
= 200 / f _rx (4)
It becomes.

Here, the number of packets (N _interval ) existing while the IFG generated in the packet separator 251 is inserted / removed is calculated using the equations (1) and (4):
N _interval
= T _interval / T _p
= (1 / (2 × | Δf |)) / (200 / f _rx )
= F _rx / (| Δf | × 400) (5)
It becomes.

Therefore, the frequency difference | Δf | of the processing clock between the packet multiplexer 201 and the packet separator 251 is
| Δf | = f _rx / (N _interval × 400) (6)
It becomes.

For _{example, f rx} Ethernet because it is defined as the frequency of the following error ± 100ppm than 156.25MHz than standard (registered _trademark), and can be approximated to 156.25MHz to _{f rx,}
| Δf | ≒
(156.25 × 10 ⁶ ) / (N _interval × 400) (7)
It becomes.

Further, since N _interval is the number of content packet copies, the actual detection is a natural number N _interval '. Therefore,
N _interval '= [N _interval ] (8)
It becomes.

Here, since the processing clock frequency falls within a range of ± 100 ppm according to IEEE 802.3, the minimum value that N _interval can take is when the processing clock deviation between the packet multiplexer 201 and the packet separator 251 is 200 ppm. It becomes. The value of N _interval at that time is 12.76 ··, and the portion after the decimal point can be considered as an error with respect to the value of N _interval .

Therefore, the equation (8) can be approximated as follows.
N _interval '= N _interval (9)
Accordingly, the frequency difference between the processing clocks of the packet multiplexing apparatus 201 and the packet separation apparatus 251 can be expressed by the following expression using the expressions (7) and (9).
| Δf | ≒
(156.25 × 10 ⁶ ) / (N _interval '× 400) (10)
Furthermore, by using the code identifier Flag,
Δf = f _tx −f _rx
= Flag × (156.25 × 10 ⁶ ) / (N _interval '× 400)
(11)
It can be.

From the above, f _rx is
f _rx
= F _tx
-Flag × (156.25 × 10 ⁶ ) / (N _interval '× 400)
(12)
And Flag is
Flag
= (F _tx -f _rx ) × (N _interval '× 400) / (156.25 × 10 ⁶ ) (13)
It becomes. The size of the flag is defined to be 1, and the parameter N _interval 'in the equation (13) always takes a positive value from the equation (5). Therefore, the size of the flag is 1, and the sign is ( _ftx− f _rx ).

When the packet fluctuation detection unit 32 detects the insertion of IFG, it means that the deviation absorption buffer related to the processing clock frequency difference in the packet separator 251 has underflowed. That is, since F _rx > f _tx , Flag = −1 from the equation (13). When Flag = −1, the clock control unit 41 performs processing for increasing the clock frequency of the clock adjustment unit 42, and synchronizes the processing clock of the packet separation device 251 with the processing clock of the packet multiplexing device 201.

On the other hand, when the packet fluctuation detection unit 32 detects the deletion of the IFG, it means that the deviation absorption buffer related to the processing clock frequency difference in the packet separation device 251 has overflowed. That is, since f _rx <f _tx , Flag = + 1 from the equation (13). In the case of Flag = + 1, the clock control unit 41 performs a process of reducing the clock frequency of the clock adjustment unit 42 and synchronizes the processing clock of the packet separation device 251 with the processing clock of the packet multiplexing device 201.

As described above, the clock control unit 41 can adjust the clock frequency of the packet separation device 251 using the IFG insertion / extraction information. The processing clock f _rx converges to the processing clock f _tx of the packet multiplexer 201 by performing this frequency adjustment every time an IFG is inserted or removed.

Further, the processing clock (156.25 MHz) adjusted by the clock adjustment unit 42 is also output to the subsequent frequency conversion unit 43. The frequency conversion unit 43 generates a reference clock frequency of 10 MHz using a PLL or the like. At this time, the multiplication factor is 1 / A, which is the reciprocal of the multiplication factor A used in the packet multiplexer 201, and the processing clock f _rx adjusted by the clock adjustment unit 42 is synchronized with the processing clock f _tx of the packet multiplexer 201. In consideration of the fact that the adjustment is performed, the reference clock output from the frequency conversion unit 43 is synchronized with the reference clock input to the packet multiplexer 201.

  On the other hand, the packet fluctuation detection unit 32 outputs the transmission frame to the multiplex number identification unit 33 as it is. The multiplex number identification unit 33 determines the multiplex number of the received content packet part based on the information in the separation position table 31 indicating which output port the signal stored in each content packet part in the transmission frame should be output to. Identify ports that should be recognized and output. At this time, if the multiplex number identified by the multiplex number identifying unit 33 is not included in the information of the separation position table 31, the signal of the content packet unit is deleted.

  After identifying the output port, the multiplex number identifying unit 33 simultaneously transmits the signal of the content packet unit to be output to the designated port and the output destination port information to the output destination switching unit 34 in the subsequent stage. The output destination switching unit 34 switches the output destination based on the information, and outputs the signal of the content packet unit to each output port. The signal output from the output port is input to the subsequent multiplex number deletion unit 35.

  In the multiplex number deletion unit 35, the packet multiplex device 201 deletes the multiplex number information given to the VLAN field of the content packet of the video, audio and data signals, and the same packet as the packet input to the packet multiplex device 201 is obtained. Restore.

  As described above, the separation unit 30 separates the video, audio, and data signal packets and outputs them from the designated port.

  In the present embodiment, the case where the packet interval is 1600 bytes has been described. However, when a fixed-length transmission frame having a packet interval other than 1600 bytes is created, “400 (= 1600/4)” in the above formula is used. The described method only changes with the number of packet interval bytes / 4, and the calculation method does not change.

  This is used when a broadcasting station having one reference clock delivers a plurality of video, audio and data signals. Further, if the present invention is used, it is possible to restore one reference at each relay station even when video, audio, and data signals are distributed via a plurality of relay stations at the time of distribution.

10: Multiplexer 11: Multiplex position table 12: Transmission frame generator 13: Multiplex number identification unit 14: Packet replacement unit 15: Multiplex standby unit 16: Multiplex number assigning unit 20: Clock converter 21: Frequency converter 30: Separation Unit 31: Separation position table 32: Packet fluctuation detection unit 33: Multiplex identification unit 34: Output destination switching unit 35: Multiplex number deletion unit 40: Reference clock generation unit 41: Clock control unit 42: Clock adjustment unit 43: Frequency conversion Part 91: Header packet part 92: Content packet part 93: IFG
150: Transmission path 200: Transmission side 201: Packet multiplexer 202: Encoder 203: Reference clock 250: Reception side 251: Packet separation device 252: Decoder 253: Reference clock 301: Transmission system

Claims (7)

On the sending side,
A plurality of fixed-length packet parts are arranged so as to sandwich a fixed-length inter-frame gap (IFG: Inter Frame Gap), and the transmission frame transmitted by performing packet multiplexing processing for storing a signal in the packet part based on a reference clock ,
On the receiving side,
When temporarily storing in the buffer,
The IFG of the transmission frame is inserted / removed so that the storage amount of the buffer falls within a predetermined range, and the frequency is controlled based on the insertion / removal information of the IFG to synchronize the receiving-side reference clock with the transmitting-side reference clock The reference clock recovery method.   Insertion / extraction of the IFG approximated using the number of packet parts from the packet part immediately before the IFG in which the insertion / extraction has occurred to the packet part immediately before the IFG in which the next insertion / extraction has occurred. The method of claim 1, wherein the time interval is a time interval. A transmission frame generation unit that generates a transmission frame by arranging a plurality of fixed-length packet units so as to sandwich a fixed-length interframe gap (IFG),
Based on a reference clock, a packet multiplex process for storing a signal in the packet part of the transmission frame generated by the transmission frame generation part, and a packet replacement part for transmitting the transmission frame storing the signal in the packet part;
A packet multiplexing device.   4. The packet multiplexing apparatus according to claim 3, wherein the packet replacement unit determines the number of the packet units to be stored in the signal based on a transmission rate of the signal. 5. The transmission frame from the packet multiplexer according to claim 3 or 4 is temporarily stored in a buffer of a physical layer, and the IFG of the transmission frame is stored in the physical layer so that a storage amount of the buffer is within a predetermined range. A packet fluctuation detection unit for detecting a portion inserted and removed in the buffer by measuring a packet interval;
A clock control unit that controls the frequency and synchronizes the reference clock with the reference clock of the packet multiplexer based on the IFG insertion / extraction information output by the packet fluctuation detection unit;
Using a reference clock controlled by a clock control unit, an output destination switching unit that extracts a signal stored from the packet unit of the transmission frame output from the buffer and outputs the signal for each type of the signal;
A packet separating apparatus.   The clock control unit is a time at which the insertion / extraction of the IFG approximated using the number of the packet parts from the packet part immediately before the IFG in which insertion / extraction has occurred to the packet part immediately before the IFG in which the next insertion / extraction has occurred. 6. The packet separation device according to claim 5, wherein the interval is used as information on insertion / extraction of the IFG. The packet multiplexing device according to claim 3 or 4,
The packet separator according to claim 5 or 6,
Including transmission system.

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