JP5407542B2 - Bias adjustment circuit, amplifier, and transmission / reception circuit - Google Patents

Description

  The present invention relates to a bias circuit, and more particularly to a bias circuit technique that can adjust the gain of an amplifier to a specific value regardless of variations in manufacturing characteristics and temperature changes.

  In a wireless transmission / reception circuit, there is a bias circuit as a circuit that determines a DC operating point of a high-frequency amplifier or mixer. The gain of high-frequency amplifiers and mixers (hereinafter referred to as “amplifiers” as a representative) changes greatly due to variations in manufacturing characteristics and temperature changes. For this reason, if the gain of the amplifier is larger than a desired value, for example, the subsequent circuit is saturated in the receiving circuit, and the signal cannot be received correctly. Conversely, if the gain is too small than the desired value, the signal is buried in the noise of the receiver, and the signal cannot be received correctly. Therefore, it is desirable to use a bias circuit that can adjust the gain of the amplifier to a desired value in accordance with variations in characteristics and changes in temperature. As an example, a circuit that makes the transistor transconductance (hereinafter referred to as Gm) constant is fixed. A technique called “Gm circuit” is already known.

However, the conventional “constant Gm circuit” cannot be adjusted with high accuracy when manufactured by a recent submicron process. FIG. 9 shows an example of a conventional “constant Gm circuit” (see Non-Patent Document 1). In general, in the “constant Gm circuit”, the size of the transistors 51, 52, 53, and 54 used is increased in order to reduce the current error. On the other hand, in a circuit that operates at a high frequency in a radio transceiver, it is required to reduce the size in order to obtain good high frequency characteristics. However, since the effect of channel length modulation increases when the size is reduced, there is a problem that the operating point differs greatly between the bias circuit and the transistor of the amplifier, making it difficult to keep Gm constant.
As a countermeasure, when the size of the “constant Gm circuit” is reduced, the value of the resistor 55 and the voltage drop caused by the resistor must be reduced. In recent submicron processes, There was a problem that it was greatly affected by the characteristic error of the resistor.

In Patent Document 1, in a differential amplifier, a tail current source is set so that a current difference when a voltage difference is given to a differential pair becomes a specific value for the purpose of suppressing variation in gain of the resistive load differential amplifier. A technique for adjusting the above is disclosed. Specifically, a certain voltage difference is given to the gates of the transistors constituting the differential pair, and the bias current is adjusted so that the drain current difference becomes a specific value. By making this change in bias current proportional to the tail current source of the differential amplifier, the Gm of the differential amplifier can be arbitrarily adjusted.
Japanese Patent Application Laid-Open No. 2004-228688 discloses a technique for applying a specific minute current to a single transistor and adjusting the voltage difference to a specific value for the purpose of adjusting the gain of the amplifier without depending on transistor variations. There is. This will be specifically described with reference to FIG. First, FIG. 11 shows a state in which the switch 61 is off and the switch 62 is on. In this state, the current Id flows through the transistor 64, and the gate voltage becomes Vg. Charge is accumulated in the capacitor 63 by the voltage difference between Vg and Vc. Next, FIG. 12 shows a state in which the switch 61 is turned on and the switch 62 is turned off. A large amount of current flows through the transistor 64 by ΔId, and the gate voltage increases by ΔVg. Further, a voltage larger by ΔVc is inputted to the positive input 66 of the comparator 65. Since the charge corresponding to the voltage difference between Vg and Vc is accumulated in the capacitor 63, the comparison result between ΔVg and ΔVc is the output of the comparator 65 after all. When the controller 67 is used based on the result of the comparator 65 and the current Id is adjusted so that ΔVg and ΔVc are equal, the Gm of the transistor 64 becomes ΔId / ΔVc.

However, the prior art disclosed in Patent Document 1 is similar to the present invention in that the gain is made constant by adjusting the bias so that the ratio between the constant current difference and the constant voltage difference is certainly constant. However, the problem that the error becomes large due to the variation of the transistors in the sub-micron process described above cannot be solved. This is because the voltage difference of the differential pair is greatly affected by variations in manufacturing of the transistors, and high accuracy cannot be obtained.
In addition, since the prior art disclosed in Patent Document 2 can adjust the gain using a single transistor, Gm can be adjusted to a constant value without depending on transistor variations, so that the amplifier can be adjusted. Gain can be adjusted. However, there is a problem that the gain of the amplifier cannot be adjusted with higher accuracy due to the accuracy of the current difference ΔId and the voltage difference ΔVc.
The present invention has been made in view of such a problem, and when the transistor of the duplication circuit and the transistor of the bias circuit have the same size and a minute current is applied to the transistor of the bias circuit, the applied current and the changed gate voltage Bias circuit that can accurately adjust the gain of the amplifier without being affected by manufacturing variations even in the sub-micron process by adjusting the bias current so that the ratio to The purpose is to provide.

In order to solve such a problem, the present invention provides a bias adjustment circuit capable of adjusting the gain of an amplifier to a specific value, a first bias current setting circuit for setting a bias current, and the first A second bias current setting circuit having the same configuration as that of the first bias current setting circuit , a gate voltage of the transistor constituting the first bias current setting circuit, and a gate voltage of the transistor constituting the second bias current setting circuit. comprising of a constant multiplication circuit to a constant multiple of the difference, a comparator for comparing the reference voltage calculated value by the constant multiplication circuit, an integrator for integrating the result of comparison by the comparator, wherein the integrator The value integrated by the detector is fed back to the first bias current setting circuit and the second bias current setting circuit, and the second bias current setting circuit Characterized in that supplied to the amplifier gate voltage of the transistor constituting the road as a bias voltage.
According to a second aspect of the present invention, there is provided a bias adjustment circuit capable of adjusting the gain of the amplifier to a specific value, a first bias current setting circuit for setting a bias current, and a second bias having the same configuration as the first bias current setting circuit. A bias current setting circuit, a constant multiplication circuit for multiplying a difference between a gate voltage of a transistor constituting the first bias current setting circuit and a gate voltage of a transistor constituting the second bias current setting circuit by a constant, A comparator that compares the value calculated by the constant multiplier circuit with a reference voltage; and an integrator that integrates the result of comparison by the comparator; and the value integrated by the integrator is the first integrated value. Feedback to the bias current setting circuit and the second bias current setting circuit, and the first bias current setting set based on the integrated value Multiple of the path of current, or the current of the second bias current setting circuit which is set based on the integrated value, and supplying to said amplifier as the bias current.
According to a third aspect of the present invention, the comparator has a function of holding a comparison result by the comparator.
According to a fourth aspect of the present invention, the constant multiplication circuit includes a function that allows a multiple of the constant multiplication circuit to be changed.
According to a fifth aspect of the present invention, an amplifier includes the bias adjustment circuit according to any one of the first to fourth aspects.
According to a sixth aspect of the present invention, a transmission / reception circuit includes the amplifier according to the fifth aspect.

According to the present invention, the bias current is adjusted so that the ratio between the current difference and the voltage difference in a single transistor becomes a specific value, and the voltage difference between the bias circuit and the replica circuit having the same configuration is amplified by the constant multiplier circuit. By reducing the effects of comparator errors and noise and reference voltage errors, the effect of noise is reduced by the integrator, and the steady state error is reduced by feeding back the output result of the integrator to the bias current. Even in the submicron process, the gain of the amplifier can be adjusted to a desired value with high accuracy without being affected by variations in transistors. Further, since the integrator output is always fed back to the bias current, the bias can be changed following a sudden temperature change, and the gain of the amplifier can be kept constant.
In addition, by implementing an integration function with a digital circuit, a bias state can be maintained, and a bias circuit capable of maintaining a constant gain with low power consumption can be operated.
Further, the gain of the amplifier can be easily changed by making the constant of the constant multiplier circuit variable. In order to change the constant of the constant multiplier circuit, it is only necessary to change the value of the resistor, but this can generally be implemented more easily and accurately than in the case of changing the reference constant current or constant voltage. .
The amplifier can adjust the gain to an arbitrary value by adjusting the bias current with high accuracy even in the sub-micron process.
Further, the transmission / reception circuit can make the gain constant in the high-frequency circuit and can perform high-performance transmission / reception with a wide dynamic range.

It is a circuit diagram which shows the structure of the bias circuit of this invention. It is a figure which shows the specific example of a bias circuit, a duplication circuit, and a difference constant multiplication circuit. It is a figure which shows the specific example of the circuit which produces the voltage difference (DELTA) Vc used as a reference | standard. FIG. 3 is a diagram illustrating an example of a switched capacitor integrating circuit as an example of the integrating circuit 10; FIG. 3 is a diagram illustrating an example of an analog integration circuit as an example of the integration circuit 10. It is a figure which shows the example using a digital integration circuit as an example of an integration circuit. It is a figure which shows the example which biases the transistor 29 of the amplifier 28 by the bias circuit of this invention. It is a figure which shows the simulation result of the bias circuit of this invention. It is a figure which shows the structure of the conventional constant Gm circuit. It is a figure of the example of a circuit which adjusts Gm with the conventional single transistor. FIG. 11 is a simplified diagram of a period during which charges are charged in FIG. 10. FIG. 11 is a simplified diagram of a period for comparing voltage differences in FIG. 10.

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings. However, the components, types, combinations, shapes, relative arrangements, and the like described in this embodiment are merely illustrative examples and not intended to limit the scope of the present invention only unless otherwise specified. .
An embodiment of the present invention will be described. Specifically, it has the following characteristics when comparing the increase in the gate voltage of the transistor of the bias circuit when a constant current is applied and the reference voltage. That is, as shown in FIG. 1, a replica circuit 2 (second bias current setting circuit) of the bias circuit 1 (first bias current setting circuit) is prepared, and the gate voltage of the transistor 11 of the bias circuit 1 is Then, the difference between the gate voltage of the transistor 12 of the replica circuit 2 is multiplied by a constant by the constant multiplier circuit 5 and then compared with the reference voltage 9 by the comparator 13, so that the error of the reference voltage 9, the error of the comparator 13, noise This is characterized in that the influence of the noise of the comparator 13 is integrated, and the result of the comparator 13 is integrated by the integrator 10 and fed back, thereby reducing the influence of the noise of the comparator 13 and eliminating the stationary error.

FIG. 1 is a circuit diagram showing the configuration of the bias circuit of the present invention. The bias circuit 100 includes a bias circuit 1 that supplies a bias current to an amplifier (not shown), a duplication circuit 2 that includes a transistor 12 having the same size as the bias circuit 1, and a gate voltage of the transistor 11 that constitutes the bias circuit 1. A subtracting circuit 4 for calculating a difference from the gate voltage of the transistor 12 constituting the replica circuit 2, a constant multiplying circuit 5 for multiplying the output of the subtracting circuit 4 by a constant, and a gate voltage difference multiplied by a constant by the constant multiplying circuit 5. A comparator 13 that compares with the reference voltage 9 and an integrator 10 that integrates the result of comparison by the comparator 13 are provided. Then, the value integrated by the integrator 10 is fed back to the bias circuit 1 and the replica circuit 2, and the bias current of the replica circuit 2 is supplied to the amplifier to adjust the gain of the amplifier.
That is, it is assumed that the bias circuit 1 and the duplicating circuit 2 are composed of transistors of the same size. A constant current 3 can be applied to the bias circuit 1 via the switch 7. The gate voltage of the transistor 11 of the bias circuit 1 and the gate voltage of the transistor 12 of the replication circuit 2 are multiplied by a constant N by taking the difference. The configuration of the comparator 13, the capacitor 6, the switch 8, and the reference voltage 9 is the same as the technique shown in FIG.

First, consider a state in which the switch 7 is off and the switch 8 is on. Since the bias circuit 1 and the replica circuit 2 have the same configuration, the gate voltage difference between the transistors 11 and 12 is only an error caused by manufacturing variations. Then, consider a state in which the switch 7 is turned on and the switch 8 is turned off. A current ΔId is applied from the constant current source 3 to the transistor 11 of the bias circuit 1. It is assumed that the gate voltage of the transistor 11 increases by ΔVg. The output obtained by taking the difference from the replica circuit and multiplying by a constant N is increased by N * ΔVg as compared with the previous case. At the same time, the reference voltage 9 is raised by ΔVc. Since the switch 8 is off, the comparator 13 compares the magnitudes of N * ΔVg and ΔVc in consideration of the electric charge accumulated in the capacitor 6. Then, the integrator 10 integrates the difference between N * ΔVg and ΔVc.
That is, the bias current is adjusted so that the ratio between the current difference and the voltage difference in a single transistor becomes a specific value, and the voltage difference between the bias circuit 1 and the replica circuit 2 having the same configuration is amplified by the constant multiplier circuit 5. Thus, the error of the comparator 13 and the influence of the noise and the error of the reference voltage 9 are reduced, the influence of the noise is reduced by the integrator 10, and the output result of the integrator 10 is fed back to the bias current to reduce the steady-state error. In the submicron process, the gain of the amplifier can be adjusted to a desired value with high accuracy without being affected by variations in transistors. Further, since the output of the integrator 10 is always fed back to the bias current, the bias can be changed following a sudden temperature change, and the gain of the amplifier can be kept constant.

FIG. 2 is a diagram showing a specific example of the bias circuit 1, the duplication circuit 2, and the constant multiplication circuit 5. The same components will be described with the same reference numerals as in FIG. The constant multiplier circuit 5 includes resistors 21 and 22 and an amplifier 23. The multiple is determined by the ratio of the resistors 21 and 22.
FIG. 3 is a diagram showing a specific example of a circuit for generating a reference voltage difference ΔVc. Although a voltage difference is created by passing a current through the resistor (the voltage difference between the node 34 and the node 35 is used), the resistance value generally varies greatly, and adjustment is necessary. That is, the current is adjusted so that the voltage drop due to the current flowing through the resistor 31 is equal to the constant voltage 33, and the current is passed through the resistor 32 to obtain a voltage difference.
FIG. 4 is a diagram illustrating an example of a switched capacitor integrating circuit as an example of the integrating circuit 10. The integration circuit 10 is configured by the switches 14 and 16, the capacitors 15 and 17, and the amplifier 18. When the switches 8 and 16 are on, the switch 14 is off, and when the switches 8 and 16 are off, the switch 14 is on.

FIG. 5 is a diagram illustrating an example of an analog integration circuit as an example of the integration circuit 10. The resistor 24, the capacitor 25, and the amplifier 26 constitute an integrating circuit.
FIG. 6 is a diagram illustrating an example in which a digital integration circuit is used as an example of the integration circuit. The output of the comparator 13 is digitized and integration is realized by the logic circuit 27.
FIG. 7 is a diagram showing an example in which the transistor 29 of the amplifier 28 is biased by the bias circuit of the present invention. The amplifier stage transistor 29 of the amplifier 28 has the same transistor length as the transistors 11 and 12 of the bias circuit 1 and the replica circuit 2, and the gate voltage of the transistor 12 can be used.
FIG. 8 is a diagram showing a simulation result of the bias circuit of the present invention. FIG. 8 shows the output result of the integration circuit 10, which shows that it converges stably to a desired bias point as time passes.

  As described above, according to the present invention, the bias current is adjusted so that the ratio between the current difference and the voltage difference in a single transistor becomes a specific value, and the voltage difference from the duplicate circuit 2 having the same configuration as the bias circuit 1 is achieved. Is amplified by the constant multiplier circuit 5 to reduce the influence of errors of the comparator 13 and noise and the error of the reference voltage 9, the influence of noise is reduced by the integrator 10, and the output result of the integrator 10 is bias current. Therefore, the steady-state error can be reduced, and the gain of the amplifier 28 can be accurately adjusted to a desired value without being affected by transistor variations even in the sub-micron process. Furthermore, since the output of the integrator 10 is always fed back to the bias current, the bias can be changed following a sudden temperature change, and the gain of the amplifier 28 can be kept constant.

In addition, by implementing an integration function in the digital circuit 27, a bias state can be maintained, and a bias circuit that can maintain a constant gain with low power consumption can be operated.
Further, by making the constant of the constant multiplication circuit 5 variable, the gain of the amplifier 28 can be easily changed. In order to change the constant of the constant multiplication circuit 5, it is sufficient to change the value of the resistor. However, this is generally easier and more accurate than when changing the reference constant current or constant voltage. it can.
The amplifier 28 can adjust the gain to an arbitrary value by adjusting the bias current with high accuracy even in the sub-micron process.
Further, by using the bias adjustment circuit of the present invention for the transmission / reception circuit, the gain can be made constant in the high-frequency circuit, and high-performance transmission / reception with a wide dynamic range is possible.

  1 bias circuit, 2 replication circuit, 3 constant current, 4 subtraction circuit, 5 constant multiplication circuit, 6 capacity for storing steady state error, 7 switch, 8 comparator feedback switch, 9 reference voltage input to comparator, 10 integration circuit , 11 Bias circuit transistor, 12 Duplicate circuit transistor

JP 2007-184688 A Japanese Patent Application No. 2009-001014 Thomas H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits Second Edition”, Cambridge University Press, pp. 325-328

Claims (6)

In the bias adjustment circuit that can adjust the gain of the amplifier to a specific value,
A first bias current setting circuit for setting a bias current ;
A second bias current setting circuit having the same configuration as the first bias current setting circuit ;
A constant multiplication circuit for multiplying a difference between a gate voltage of a transistor constituting the first bias current setting circuit and a gate voltage of a transistor constituting the second bias current setting circuit by a constant;
A comparator that compares the value calculated by the constant multiplication circuit with a reference voltage;
And a integrator for integrating the result of comparison by the comparator,
The value integrated by the integrator is fed back to the first bias current setting circuit and the second bias current setting circuit, and the gate voltage of the transistors constituting the second bias current setting circuit is used as a bias voltage. A bias adjustment circuit which is supplied to the amplifier .   In the bias adjustment circuit that can adjust the gain of the amplifier to a specific value,
  A first bias current setting circuit for setting a bias current;
  A second bias current setting circuit having the same configuration as the first bias current setting circuit;
  A constant multiplication circuit for multiplying a difference between a gate voltage of a transistor constituting the first bias current setting circuit and a gate voltage of a transistor constituting the second bias current setting circuit by a constant;
  A comparator that compares the value calculated by the constant multiplication circuit with a reference voltage;
  An integrator for integrating the results compared by the comparator,
  The value integrated by the integrator is fed back to the first bias current setting circuit and the second bias current setting circuit, and the first bias current setting circuit is set based on the integrated value. A bias adjustment circuit, wherein a current of the second bias current setting circuit set based on a constant multiple of the current or the integrated value is supplied to the amplifier as a bias current. The comparator bias adjustment circuit according to claim 1 or 2, characterized in that it comprises a function of holding the comparison result by the comparator. 3. The bias adjustment circuit according to claim 1, wherein the constant multiplication circuit has a function of changing a multiple of the constant multiplication circuit. An amplifier comprising the bias adjustment circuit according to any one of claims 1 to 4 . A transmission / reception circuit comprising the amplifier according to claim 5 .

Images