JP5402752B2 - Compiling device and compiling program - Google Patents

Description

  The present invention relates to a compiling device that obtains source code and creates an object code that can be executed by a processor, and a compiling program that is executed in the arithmetic processing device and operates the arithmetic processing device as a compiling device.

  Source code, which is a program written in a programming language used when a programmer creates a program, cannot be executed by a computer processor as it is. In order to cause the program to be executed by the processor, it is necessary to convert the source code into an object code that can be executed by the processor and takes into consideration the structure of the processor. In this compilation, a register allocation process is performed. This register allocation processing is an operation of allocating variables to real registers by allocating an unlimited number of virtual registers to which variables appearing in the compiler intermediate language are allocated to a small number of real registers.

  However, depending on the processor, the real registers are divided into multiple groups, and even real registers belonging to different groups can be shared. However, if another group of real registers is used within one instruction, There is a delay in the execution of instructions than when using real registers.

  In addition, depending on the register allocation result, even a processor having a plurality of arithmetic units may have a dependency due to reading and writing of registers, and parallel processing may be greatly limited.

  There is a proposal for a contrivance for parallel processing in a system in which the correspondence between an arithmetic unit and a register is completely fixed, which can be used only by that arithmetic unit and cannot be used by other arithmetic units. In contrast, this case targets a processor of a type that has a plurality of arithmetic units and a plurality of registers and can use any of the plurality of registers regardless of the arithmetic unit of the plurality of arithmetic units. It is said. There is no compile ingenuity to speed up arithmetic processing when using this type of processor.

JP-A-9-62636

  An object of the compiling apparatus and the compiling program disclosed in the present disclosure is to increase the speed of arithmetic processing in the above type of processor.

  The compiling device of the present disclosure obtains source code and compiles object code that can be executed by a processor having a plurality of registers and a plurality of arithmetic units that perform arithmetic processing using the plurality of registers. Device.

  The compiling device of the present disclosure includes a source code acquisition unit, an unrolling unit, a register allocation unit, an object code generation unit, and an object code output unit.

  The source code acquisition unit acquires source code.

  The unrolling unit unrolls the loop described in the source code into a plurality of instruction groups.

  The register allocation unit allocates registers to variables appearing in a plurality of instruction groups generated by the unrolling unit.

  The object code generation unit generates an object code based on the register allocation result in the register allocation unit.

  The object code output unit outputs the object code generated by the object code generation unit.

  Here, the register allocation unit includes a first allocation unit. The first assigning unit assigns each register group to the plurality of instruction groups when the plurality of registers are grouped into a plurality of register groups. Then, for each of the plurality of instruction groups, the first assigning unit assigns all of the individual variables excluding the common variables used in common to the plurality of instruction groups among the variables appearing in the instruction group. Are assigned only to the registers constituting one register group assigned to.

  Further, the compile program of the present case is a program that is executed by an arithmetic processing device that executes the program and causes the arithmetic processing device to operate as the compile device of the present case.

  According to the compiling device and the compiling program of the present disclosure, it is possible to increase the speed of arithmetic processing in a processor having a plurality of arithmetic units and a plurality of registers that can be shared by the plurality of arithmetic units.

It is a basic lineblock diagram of the compilation device of a 1st embodiment of this case. It is a conceptual diagram of the processor by which execution of the object code created with the compiling apparatus of FIG. 1 is scheduled. It is a figure which shows the procedure of the process performed with the compilation apparatus of 2nd Embodiment. It is a figure which shows an example of the source code stored in the source file. It is a figure which shows the code described by the intermediate language produced | generated by the parsing process. It is a flowchart of an unrolling process. FIG. 6 is a diagram illustrating a state in which a code described in the intermediate language illustrated in FIG. 5 is unrolled. It is a flowchart which shows the process in which the variable in a loop is classified into a register group in a register allocation process. FIG. 8 is a diagram illustrating an array S in which variables (virtual registers) are distributed in the example illustrated in FIG. 7. It is a figure which shows the real register classified into the register group number N (here N = 2). It is a figure which shows the content of the arrangement | sequence B (n). It is a flowchart of a register allocation process. It is a flowchart of a register allocation step. It is a flowchart of a reference operand allocation step. It is a flowchart of a definition operand allocation step. It is a flowchart of an evacuation / restoration instruction generation step. It is the figure which showed the allocation result to a real register. 11 is an example of a register group in place of FIG. It is a figure which shows the content of the arrangement | sequence B (n) instead of FIG. It is the figure which showed the result of the allocation to a real register in the premise shown in FIG. 18, FIG. It is a figure which shows the process result of FIG.12 S34 when the state of FIG. 20 arises. It is a figure which shows the register put together into one group. Here is an example of using registers without grouping for unrolled instructions. It is a figure which shows an example when a register is used without grouping about the unrolled instruction. It is explanatory drawing of a processor. It is a figure which shows the example which does not produce a delay in execution of an instruction | indication. It is a figure which shows the example which produces the delay in execution of an instruction | indication. It is a figure which shows an example with low parallelism. It is a figure which shows an example with high parallelism.

  Hereinafter, an embodiment of the present case will be described.

  FIG. 1 is a basic configuration diagram of a compiling device according to the first embodiment of the present invention. The compiling device 10 is a device that obtains source code and creates object code that can be executed by a processor. However, the object code created by the compiling apparatus 10 is an object code executed by a processor having a plurality of registers and a plurality of arithmetic units that execute arithmetic processing using the plurality of registers. Therefore, this object code is not intended to be executed by the processor 21 shown in FIG.

  FIG. 2 is a conceptual diagram of a processor that is scheduled to execute an object code created by the compiling apparatus of FIG.

  The processor 21 shown in FIG. 1 is a processor that executes the OS 30 and the compile program 40 shown in FIG. On the other hand, the processor 50 shown in FIG. 2 is a processor responsible for executing the object code created by the compiling device 40 shown in FIG.

  The object code created by the compiling device 40 is written in, for example, a CD (Compact Disk optical disc) or the like, and is installed in an arithmetic processing device or computer having the processor shown in FIG. 2 and different from the arithmetic processing device in FIG. Is done. This object code is executed by a processor of the installation destination computer or computer.

  The processor 50 shown in FIG. 2 includes a plurality of (two in the example shown in FIG. 2) arithmetic units 51a and 51b that can be shared by the plurality of arithmetic units 51a and 51b. N) registers 52a, 52b,..., 52n.

  Returning to FIG. 1, the description will be continued.

  The compiling device 10 includes hardware 20 of an arithmetic processing device, an operating system (Operating System OS) 30 executed on the hardware 20, and a compiling program 40 executed under the management of the OS 30. .

  The hardware 20 includes a processor 21, a memory 22, an input device 23, and an output device 24.

  In the processor 21, the OS 30 and the compile program 40 are executed.

  The memory 22 is responsible for storing data.

  The input device 23 constituting the hardware 20 includes a keyboard / mouse operated by a user of the compiling device 10, a CD / DVD drive that is driven by loading a portable recording medium such as a CD / DVD, and the like. It includes a receiving device for receiving information from the outside via a communication line (not shown).

  Furthermore, the output device 24 includes an image display device that displays an image, a speaker that outputs sound, and a transmission device that transmits information to the outside.

  The OS 30 controls execution of a program (here, the compile program 40) that operates on the hardware 20.

  The compile program 40 includes a source code acquisition unit 41, an unrolling unit 42, a register allocation unit 43, an object code generation unit 44, and an object code output unit 45. Each of these units 41 to 45 is a name of a program part here, but is also a name indicating each component of the compiling apparatus 10 as a function when the program part is executed by the processor 21.

  The source code acquisition unit 41 acquires source code. This source code may be input by the user from the input device 23, or may be the source code stored on the CD or DVD installed. Alternatively, it may be input from outside via a communication line.

  The unrolling unit 42 unrolls a loop described in the source code into a plurality of instruction groups. A specific example will be described later.

  The register allocation unit 43 allocates registers to variables that appear in a plurality of instruction groups generated by the unrolling unit 42. The register allocation unit 43 includes a first allocation unit 431, a comparison unit 432, a memory save / restore code insertion unit 433, and a second allocation unit 434.

  The first assigning unit 431 assigns each register group when the plurality of registers 52a, 52b,..., 52n constituting the processor 50 shown in FIG. Assign to each. Then, for each of the plurality of instruction groups, the first assigning unit 431 assigns all of the individual variables except for the common variables used in common to the plurality of instruction groups among the variables appearing in the instruction group. Allocation is made only to registers constituting one register group assigned to the group.

  Further, the comparison unit 432 operates when it is impossible to allocate all the individual variables to the registers by the first allocation unit 431. The comparison unit 432 is a ratio of the number of reference times of all variables that cannot be assigned to a register in the first allocation unit 431 among all variables appearing in the plurality of instruction groups to the overall program length. And the threshold value are compared.

  The memory save / restore code insertion unit 433 operates when the comparison unit 432 determines that the ratio is less than the threshold value. The memory saving / restoring code insertion unit 433 saves the memory in the memory 22 of the variable that cannot be allocated to the register, instead of allocating the variable to the register that cannot be allocated in the first allocation unit 431. A code for instructing restoration from 22 is inserted.

  The second allocation unit 434 operates when the comparison unit 432 determines that the ratio is equal to or greater than the threshold value. The second allocation unit 434 assumes that any of a plurality of registers 52a, 52b,..., 52n (see FIG. 2) before grouping can be used in any of a plurality of instruction groups. All variables appearing in multiple instruction groups are assigned to registers.

  Further, the object code generation unit 44 generates an object code based on the register allocation result in the register allocation unit 43.

  Further, the object code output unit 45 outputs the object code generated by the object code generation unit 44. The output here may be any output, such as writing to a portable recording medium such as a CD, or transmitting to the outside via a communication line.

  This is the end of the general description of the first embodiment, and a more specific second embodiment will be described below.

  FIG. 3 is a diagram illustrating a procedure of processes executed by the compiling apparatus according to the second embodiment. The process shown here is a process realized by executing the compile program as the second embodiment under the hardware 20 and the OS 30 shown in FIG. Since the hardware and OS of the arithmetic processing unit are not different from those shown in FIG. 1, reference will be made to FIG. 1 as necessary. The object code created in the second embodiment is also an object code executed by the processor 50 having the configuration shown in FIG.

  In FIG. 3, a source file 60 and an object file 80 are shown.

  The source file 60 stores source code written in a program language for source code.

  The object file 80 stores object codes described in a program language (such as an assembler) for object codes that can be executed by the processor 50 shown in FIG.

  Also, in FIG. 3, as a compile process 70 executed by the compile apparatus of the second embodiment, a syntax analysis process 71, an unrolling process 72, a register allocation process 73, an instruction scheduling process 74, and a code generation process 75 are provided. It is shown.

  The correspondence with the first embodiment described above is as follows.

  The process of receiving the source file 60 indicated by the arrow A in FIG. 3 corresponds to the source code acquisition unit 41 in FIG. The parsing process 71 serves as a pre-process for the next unrolling process 72, and the combined process of the parsing process 71 and the unrolling process 72 corresponds to the unrolling unit 42 in FIG. Further, the register allocation process 73 corresponds to the register allocation unit 43. The instruction scheduling process 74 plays a role of pre-processing of the next code generation process 75, and the combination of the instruction scheduling process 74 and the code generation process 75 is the object code generation unit 44 in FIG. Corresponding to Furthermore, the process of outputting the object file 70 in which the object code generated by the code generation process 75 indicated by the arrow B is filed corresponds to the object code output unit 45 of FIG.

  Here, an outline of the process 70 shown in FIG. 3 will be described. Then, a detailed specific example will be described.

  In the parsing process 71, the received source file 60 is parsed and converted into an intermediate language. In this intermediate language, an unlimited number of virtual registers are used, and virtual registers are assigned to the appearing variables. Therefore, it is not necessary to distinguish between a virtual register and a variable here, and in the following, these terms may be used without distinction unless otherwise specified.

  After the parsing process 71 is performed, an unrolling process 72 is performed. In this unrolling process 72, the loop in the program converted into the intermediate language is unrolled into a plurality of instruction groups.

  In the register allocation processing 74, a real register (register 52a shown in FIG. 2) that can actually be used as a variable (virtual register) in a code written in an intermediate language, including a plurality of instruction groups generated by the unrolling processing 72. , 52b,..., 52n) are allocated.

  In the instruction scheduling process 75, instruction scheduling is performed so as to increase the degree of parallelism of the processes in the plurality of computing units 51a and 51b (see FIG. 2).

  In the code generation process 75, an object code is generated in accordance with the scheduling in the instruction scheduling process 74.

  Hereinafter, the various processes 71 to 75 shown in FIG. 3 will be specifically described.

  FIG. 4 is a diagram illustrating an example of source code stored in a source file. In this embodiment, there is an interest in the loop portion of the program, and only the portion related to the loop is illustrated here.

  (1) In the line, it is defined that the variables I and N are integers.

  (2) The line defines that array A (10), array B (10), variable C, array D (10), and variables t1, t2, and t3 are all real numbers.

  (2) Between the line (n) and the line (n) (part indicated by reference numeral (a)), specific numerical values are defined for N, A (10), B (10), and C. To do.

  The (n) line is the start point of the loop. The process from the (n + 1) line to the (n + 4) line is performed until I = N while I is incremented by 1 with I = 1 as an initial value. Is shown to be repeated.

  The (n + 1) th row indicates that A (I) and C are added and stored in t1.

  The (n + 2) line indicates that B (I) should be subtracted from t1 and stored in t2.

  The (n + 3) line indicates that A (I) and t2 should be multiplied and stored in t3.

  The (n + 4) line indicates that B (I) should be divided by t3 and stored in D (I).

  The (n + 5) line represents the end point of the loop.

  Here, a specific example will be described based on the source code shown in FIG.

  FIG. 5 is a diagram showing a code written in an intermediate language generated by the syntax analysis process 71.

  PRn (n = 1, 2,...) Appearing in FIG. 5 and in each figure described below represents a virtual register.

  In FIG. 5, A (I), B (I), D (I) mean an arrangement on the memory, and A (I), B (I) (I = 1, 2,... It is assumed that the array numerical value in the memory is stored in N) before the portion shown in FIG. Further, it is assumed that the value of N is also defined before the portion shown in FIG. 5 and that the value of C is also defined and associated with the virtual register PR2.

  The (1) line of the code in FIG. 5 indicates that 1 should be substituted for I.

  The (2) line is the start point of the loop, and is the return point from the (11) line when the condition described in the (11) line is satisfied.

  The (3) line indicates that the contents of A (I) on the memory should be stored in the virtual register PR1.

  (4) The line indicates that the contents of PR1 (corresponding to A (I)) and the contents of PR2 (corresponding to C) should be added and stored in PR3 (corresponding to t1). .

  The (5) line indicates that the contents of B (I) on the memory should be stored in the virtual register PR4.

  (6) The line indicates that the content of PR4 (corresponding to B (I)) should be subtracted from the content of PR3 (corresponding to t1) and stored in PR5 (corresponding to t2). .

  (7) Line 7 indicates that the contents of PR1 (corresponding to A (I)) and PR5 (corresponding to t2) are multiplied and stored in PR6 (corresponding to t3).

  (8) Line 8 indicates that the content of PR4 (corresponding to B (I)) should be divided by the content of PR6 (corresponding to t3) and stored in PR7 (corresponding to D (I)). Has been.

  The (9) line indicates that the contents of PR7 should be stored in D (I) on the memory.

  (10) Line 1 shows that I is incremented by adding 1 to I again.

  It is indicated that the (11) line should return to LABEL ((2) line) if I <N + 1.

  In the parsing process 71 shown in FIG. 3, as an example, the source code shown in FIG. 4 is converted into a code expressed in an intermediate language shown in FIG.

  FIG. 6 is a flowchart of the unrolling process. FIG. 7 is a diagram showing a state where the code written in the intermediate language shown in FIG. 5 is unrolled.

  Here, only the unrolled portion is of interest, and FIG. 7 shows only the portion corresponding to the (3) to (9) rows in FIG. Actually, for example, after the portion shown in FIG. 7, processing corresponding to (10) and (11) is executed (however, 4 is added to I in the processing corresponding to (10)). Such processing is added.

  In FIG. 7, four loops shown in FIG. 5 are developed. When the unrolling process 72 (see FIG. 3) is executed, a development number is embedded in each instruction. However, in FIG. 7, for the sake of easy understanding, the expansion numbers are arranged in the instructions separately from the instructions.

  When comparing the (3) to (9) lines in FIG. 5 and FIG. 7, in FIG. 7, the instruction group consisting of the respective instructions in the (3) to (9) lines in FIG. Each expansion number of 1-4 is attached | subjected about the instruction group. Further, the virtual register number (n of PRn) is changed so that variables appearing in the instruction groups of the expansion numbers 1 to 4 are assigned to different virtual registers for the expansion numbers 1 to 4, respectively. However, in each of the expansion numbers 1 to 4, PR2 (corresponding to C in FIG. 4), which is a common variable (a virtual register used in common) commonly used in the instruction groups of the expansion numbers 1 to 4. Is commonly used in all the development numbers 1 to 4.

  The unrolling process 72 is demonstrated based on the flowchart of FIG.

  Here, first, 1 is set in the counter (step S11), the original instruction (here, line (3) in FIG. 5) is copied (step S12), and the counter (here, 1) is used as the expansion number. (Step S13). In step S14, it is determined whether or not there are instructions remaining in the loop. Here, since the (3) line in FIG. 5 has only been copied and the (4) to (9) lines remain, the process returns to step S12, and this time for the (4) line in FIG. Steps S12 and S13 are performed. Similarly, the processes in steps S12 and S13 are sequentially repeated for the lines (5) to (9). When the processes of steps S12 and S13 are completed up to the (9) th line, the process proceeds to step S15 via step S14, and the counter is counted up. In step S16, it is determined whether or not the counter exceeds the number of expansions (here, 4), and steps S12 to S15 are repeated until the number of expansions exceeds four. If it is determined in step S16 that the number of expansions exceeds 4, the process proceeds to step S17, and a variable (virtual register) referred to by the copied instruction is renamed for each expansion. However, a variable (virtual register) (PR2 in the example shown in FIG. 5) that is commonly used in each of the expansion numbers 1 to 4 is left without being renamed.

  By the above unrolling process, the code of FIG. 5 is unrolled to the code of FIG.

  FIG. 8 is a flowchart showing processing for classifying variables in a loop into register groups in the register allocation processing 73. The process of FIG. 8 is a preparatory process for the process of assigning variables to registers (see FIG. 12).

  Here, the registers that can be used by the processor 50 (see FIG. 2) that is supposed to execute the object code generated by the compilation here are grouped into a plurality of register groups. The number N of register groups to be grouped is determined from the number of usable registers and the number of unrolling expansions L (here, L = 4) (step S21). N is 2 or more and L or less. Here, N = 2.

  Next, areas of the arrays S (N + 1) and B (N + 1) are secured (step S22). Here, the array S (N + 1) is an array for classifying variables (virtual registers) for each register group. The array B (N + 1) is an array for classifying registers (real registers) for each group. The reason why the number of arrays is not N (the number of register groups) but N + 1 is to classify common variables used in common across a plurality of development numbers separately from the register groups. Here, a set of all variables (virtual registers) appearing in the loop is assumed to be V.

  In step S23, an arbitrary variable (virtual register) v in the set V of variables (virtual registers) is extracted. Then, it is determined whether or not the instruction in which the variable v appears is an instruction belonging to the same expansion number, that is, whether or not the variable v is a variable that appears only in an instruction within a certain expansion number. (Step S24). If all the instructions in which the variable v appears are instructions belonging to the same expansion number, the variable v is distributed to the array S by the expansion number in which the variable v appears. Here, since the number of expansions is 4 and the number of register groups N is 2, the variables (virtual registers) of expansion numbers 1 and 3 are distributed to S (1), and the expansion numbers 2 and 4 are distributed to S (2). Variables (virtual registers) are distributed.

  If it is determined in step S24 that v appears across instructions with a plurality of expansion numbers, the process proceeds to step S26, and the variable v is added to the array S (N + 1).

  After the above processing is executed for all the variables v in the set V, an array B (n) corresponding to the array S (n) is created. Here, B (n) means a set of registers belonging to the nth register group. B (N + 1) is a special set, which is a set of registers including all the registers belonging to each register group.

  Further, in step S28, the entire instruction group is searched to check how many registers are required for saving / restoring to the memory, and a necessary number of registers are reserved.

  FIG. 9 is a diagram illustrating an array S in which variables (virtual registers) are distributed in the example illustrated in FIG.

  In S (1), a variable (virtual register) that appears only in the instruction group with expansion number 1 and a variable (virtual register) that appears only in the instruction group with expansion number 3 are distributed. In addition, a variable (virtual register) that appears only in the instruction group with expansion number 2 and a variable that appears only in the instruction group with expansion number 4 are distributed to S (2). Furthermore, a variable (virtual register) that commonly appears in a group of instructions having a plurality of expansion numbers is distributed to S (3).

  FIG. 10 is a diagram showing the real registers classified into the register group number N (N = 2 in this case).

  Here, there are 12 usable registers R0 to R11 (n = 12 in FIG. 2), R0 to R5 are divided into group 1, and R6 to R11 are divided into group 2.

  FIG. 11 is a diagram showing the contents of the array B (n).

  In B (1), R0 to R3 are distributed as registers that can be used for definition reference (calculation) between registers, and R4 and R5 are reserved registers for saving / restoring to / from memory. Further, R6 to R7 are distributed to B (2) as registers that can be used for definition reference between registers, and R10 and R11 are reserved as registers. Further, all registers R0 to R11 are arranged in B (3). Of all these registers, R10 and R11 are set as reserved registers, and usable registers are R0 to R9.

  FIG. 12 is a flowchart of register allocation processing.

  In the register allocation process 73 shown in FIG. 3, the register allocation process shown in FIG. 12 is executed following the pre-process shown in FIG.

  Here, first, when an arbitrary variable v is included in S (n) (see FIG. 9), only register B (n) (see FIG. 11) can be used, and register allocation is executed. Registers for saving and restoring are reserved separately, and here, only the “usable registers” shown in FIG. 11 are allocated.

  In step S32, it is determined whether or not “usable registers” have been assigned to all variables. When the “usable registers” can be assigned to all the variables, the register assignment process ends. If registers cannot be allocated to all variables using only "usable registers", then whether the total number of times the variables could not be allocated is sufficiently small for the entire program It is determined whether or not (step S33). Specifically, the total number of reference times of variables that could not be assigned for all of the expansion numbers 1 to 4 is counted, and the ratio of the number of reference times to the number of steps of the entire program is compared with a threshold, and the ratio Is less than the threshold or greater than or equal to the threshold. If the ratio is less than the threshold value, that is, if the total number of references to variables that could not be allocated is sufficiently small relative to the overall program size, the process proceeds to step S34, and if not, the process proceeds to step S35. .

  In step S34, using the reserved register (see FIG. 11), an instruction for saving and restoring the variable that could not be allocated to the register is generated in the memory, and the allocation process is terminated.

  On the other hand, in step S35, register allocation is executed assuming that all registers can be used for an arbitrary variable v. However, as in the case of step S31, the save / restore register is reserved separately.

  In step S36, it is determined whether or not the register can be allocated to all variables in step S35. If the register can be allocated to all the variables, the register allocation process ends. If the register cannot be assigned to all variables, an instruction to save and restore to the variable memory that could not be assigned to the register is generated using the reserved register (step S37).

  FIG. 13 is a flowchart of the register allocation step. This register allocation step is executed in both step S31 and step S35 of FIG. 12, but the process flow is the same. However, the number of registers that can be used for allocation differs between step S31 and step S35.

  According to the flow of FIG. 13, the unrolled instructions as shown in FIG. 7 are viewed in order from the top (step S41), the allocation of reference operands (step S42), and the allocation of definition operands (step S43) are all performed. This command is executed (step S44).

Here, the reference operand is a variable on the left side of the instruction. For example, ADD R1, R0 ⇒ R2 in expansion number 1
The variables (virtual registers) R1 and R0 in FIG. Also, the variable on the right side of the instruction, here R2, is the definition operand.

  FIG. 14 is a flowchart of the reference operand allocation step (step S42 in FIG. 13).

  Here, the reference operand of the instruction is checked (step S51), and it is determined whether or not the reference operand is the last reference that has no reference after the instruction. If it is the last reference, the reference operand is assigned to the reference operand. The registered register is released (step S53). This process is performed for all reference operands (step S54).

  FIG. 15 is a flowchart of the definition operand assignment step (step S43 in FIG. 13).

  Here, the definition operand of the instruction is examined (step S61), and it is determined whether or not the definition operand is assigned to the register (step S62). If the definition operand has been assigned to a register, the next definition operand is checked (step S66). If the definition operand has not been assigned to a register, whether or not there are remaining registers not assigned to variables. It is checked (step S63). If there is a surplus register that is not assigned to a variable, the surplus register is assigned to the definition operand (step S64). On the other hand, if there is no surplus register, the definition operand (variable) is assigned to the set SPILL. It is added (step S65). This set SPILL is a set of variables (virtual registers) that could not be assigned to registers. The above processing is performed for all definition operands.

  FIG. 16 is a flowchart of the save / restore instruction generation step (step S34 and step S37 in FIG. 12).

  Here, an arbitrary variable v is extracted from the set SPILL that could not be assigned a register (step S37).

  Next, a temporary area M on the memory is determined for the variable v (step S72).

  Further, an instruction to store in the temporary area M is generated for the definition of the variable v. As a register for storing used in this instruction, a register reserved for saving and restoring is used (see FIG. 11).

  Next, an instruction to load the register from the temporary area M with respect to the reference of the variable v is generated (step S74). Again, a register reserved for saving and restoring is used as a register for loading.

  The above processing is performed for all variables in the set SPILL (step S75).

  FIG. 17 is a diagram showing the result of allocation to real registers. FIG. 17 shows the allocation result when the variables appearing in the unrolled instruction shown in FIG. 7 are assigned to the registers on the assumption that the number of registers shown in FIG. 10 exists.

  In FIG. 17, for each expansion number, all variables appearing only in the instruction group of that expansion number are assigned to registers belonging to one group. However, for the two instructions marked with “x” in FIG. 17, both group 1 and group 2 shown in FIG. 10 are referred to. If the number of instructions marked with x increases, there is a risk that processing parallelization may be hindered or the processing speed may be reduced. However, in the example shown in FIG. It stays.

  Next, an example in which there are not enough registers will be described.

  FIG. 18 shows an example of a register group in place of FIG.

  In FIG. 10, each group has six registers, but in FIG. 18, there are only five registers in each group.

  FIG. 19 is a diagram showing the contents of the array B (n) instead of FIG. In FIG. 19, the number of “usable registers” is reduced as compared with FIG.

  FIG. 20 is a diagram showing the result of the allocation to the actual register (step S31 in FIG. 12) based on the assumptions shown in FIGS.

  There are not enough registers to be assigned to the variables (virtual registers), and the variables (virtual registers) marked with a star in the figure remain without being assigned to the registers.

  FIG. 21 is a diagram illustrating a processing result in step S34 in FIG. 12 when the state in FIG. 20 occurs in step S31 in FIG.

  Instructions for saving / restoring to / from the memory are inserted in the portions marked with Δ in the figure.

  The process of saving / restoring to memory takes a lot of time compared to data movement between registers, but when the frequency is low, it is parallelized by inserting the process of saving / restoring to / from memory. It is not necessary to increase the factors that hinder.

  Next, an example of step S35 in FIG. 12 will be described. In this step S35, the registers are allocated on the assumption that the registers are grouped into one group without being grouped, and the registers in the one group can be used by instructions of all the expansion numbers.

  FIG. 22 is a diagram illustrating registers grouped into one group.

  FIG. 23 shows an example in which a register is used without grouping an unrolled instruction as shown in FIG.

  Here, registers are assigned to all variables without performing the process of saving to the memory / restoring from the memory. This means that when the number of processes for saving to the memory / restoring from the memory is too large, the parallel processing is given up and assigned to the register. That is, the same registers are assigned over the expansion numbers 1 to 4, and it is difficult to perform parallel processing with a plurality of arithmetic units. For example, since the eighth LOAD has a register dependency with the immediately preceding STORE, these instructions cannot be executed in parallel.

  In FIG. 23, the same registers are reused in order to reduce the number of registers to be used as much as possible. In order to improve the parallelism of processing as much as possible, it may be assigned to use different registers as much as possible.

  FIG. 24 is a diagram showing an example when registers are used without grouping the unrolled instructions as shown in FIG. Here, however, it is devised to use as different registers as possible. For example, in the definition of the fourth instruction SUB, since R2 is released, R2 can be used again as shown in FIG. 23, but R4 is assigned in FIG. As a result of using a different register as much as possible, the eighth LOAD in FIG. 24 can be executed simultaneously with the STORE and DIV above it. However, since the register group is not taken into consideration here, many instructions on which the register group (see FIG. 18) depends are generated as indicated by the crosses in FIG. For this reason, the parallelism is low as compared with the case where the instruction for saving / restoring to / from the memory shown in FIG. 21 is inserted.

  Next, advantages of the above embodiment will be described.

  FIG. 25 is an explanatory diagram of a certain processor.

  The processor shown here has three arithmetic units A, B, and C and three register groups A, B, and C. The arithmetic unit A can directly refer to the register group A, but the other register groups B and C cannot be directly referred to, and it takes time to refer to them. The same applies to the other arithmetic units B and C and the register group. In this case, if a register belonging to a plurality of register groups depends on one instruction, it takes time to execute the instruction.

  FIG. 26 is a diagram illustrating an example in which a delay is not caused in the execution of an instruction.

  Here, the registers of the register group A are a1, a2, a3,..., And the registers of the register group B are b1, b2, b3,.

  In the instruction sequence shown in FIG. 26, all registers in register group A are used, so that no instruction delay occurs.

  FIG. 27 is a diagram illustrating an example of causing a delay in the execution of an instruction.

  The instruction sequence shown in FIG. 27 includes a register group A register and a register group B register together, and a delay occurs in the execution of the instruction.

  In the above-described embodiment, since the grouped registers are used as much as possible, elements that cause a delay in execution of instructions are minimized, and high-speed processing is possible.

  Another advantage of this embodiment is parallelism. Even if the register group as shown in FIG. 25 does not exist on the hardware and all the registers can be referred to evenly, the parallelism can be improved by grouping the registers as in this embodiment. Processing speed is improved.

  FIG. 28 is a diagram illustrating an example of low parallelism.

  Here, the allocation processing is performed without grouping the registers, and as a result, the LOAD instruction on the (5) line can be executed only after the register r1 is released on the (3) line. That is, the LOAD instruction on the (5) line can be executed only simultaneously with the STORE instruction on the (4) line.

  FIG. 29 is a diagram illustrating an example of high parallelism.

  Here, the registers are grouped, so that the instructions on the (1) line and (5) line can be executed in parallel.

  In the above-described embodiment, parallelism is improved because the grouped registers are used as much as possible. Therefore, the processing speed is improved by parallel processing using a plurality of arithmetic units even if the processor is not a hardware grouped processor as shown in FIG.

10, 40 Compile device 20 Hardware 21, 50 Processor 22 Memory 23 Input device 24 Output device 30 Operating system (OS)
40 Compile Program 41 Source Code Acquisition Unit 42 Unrolling Unit 43 Register Allocation Unit 44 Object Code Generation Unit 45 Object Code Output Unit 51a, 51b Calculator 52a, 52b, 52n Register 60 Source File 70 Compile Process 71 Parsing Process 72 Unrolling Processing 73 Register allocation processing 74 Instruction scheduling processing 75 Code generation processing 80 Object file 431 First allocation unit 432 Comparison unit 433 Memory save / restore code insertion unit 434 Second allocation unit

Claims (5)

A compiling device that obtains source code and creates an object code that can be executed by a processor having a plurality of registers and a plurality of arithmetic units that perform arithmetic processing using the plurality of registers,
A source code acquisition unit for acquiring source code;
An unrolling unit for unrolling a loop described in the source code into a plurality of instruction groups;
A register allocation unit that allocates registers to variables that appear in the plurality of instruction groups generated by the unrolling unit;
An object code generation unit that generates an object code based on a register allocation result in the register allocation unit;
An object code output unit that outputs the object code generated by the object code generation unit,
The register allocating unit assigns each register group when the plurality of registers are grouped into a plurality of register groups to each of the plurality of instruction groups, and each of the plurality of instruction groups appears in the instruction group. Including a first allocation unit that allocates all of the individual variables, except for the common variable used in common to the plurality of instruction groups, among the variables to only the registers constituting one register group allocated to the instruction group. Compile device characterized by this.   If the register allocation unit cannot allocate all of the individual variables to the register by the first allocation unit, the register of the variable that cannot be allocated by the first allocation unit 2. The compiling device according to claim 1, further comprising a memory saving / restoring code insertion unit for inserting a code for instructing saving and restoring of the variable to / from the memory instead of allocation to the variable.   When the register allocation unit is unable to allocate all the individual variables to the register by the first allocation unit, the plurality of instruction groups before being grouped in any of the plurality of instruction groups The compiling apparatus according to claim 1, further comprising a second allocation unit that allocates all the variables appearing in the plurality of instruction groups to the register, assuming that any of the registers can be used. When the register allocation unit cannot allocate all the individual variables to the register by the first allocation unit, the first allocation of all the variables appearing in the plurality of instruction groups. A comparison unit that compares the ratio of the number of reference times of all variables for which allocation of registers was impossible in the part to the length of the entire program and a threshold value;
When the comparison unit determines that the ratio is less than the threshold value, instead of allocating the variable to the register, the first allocating unit cannot allocate the register, A memory save / restore code insertion unit for inserting a code for instructing save and restore from the memory;
When the comparison unit determines that the ratio is equal to or greater than the threshold, any of the plurality of registers before being grouped can be used in any of the plurality of instruction groups. The compiling apparatus according to claim 1, further comprising: a second allocation unit that allocates all variables appearing in the plurality of instruction groups to the registers. In a processor having a plurality of arithmetic units that are executed by an arithmetic processing unit that executes a program, obtains a source code, and executes arithmetic processing while using the plurality of registers and the plurality of registers A compiling program that operates as a compiling device for creating executable object code,
The arithmetic processing unit;
A source code acquisition unit for acquiring source code;
An unrolling unit for unrolling a loop described in the source code into a plurality of instruction groups;
A register allocation unit that allocates registers to variables that appear in the plurality of instruction groups generated by the unrolling unit;
An object code generation unit that generates an object code based on a register allocation result in the register allocation unit;
An object code output unit that outputs the object code generated by the object code generation unit,
The register allocating unit assigns each register group when the plurality of registers are grouped into a plurality of register groups to each of the plurality of instruction groups, and each of the plurality of instruction groups appears in the instruction group. Compilation including a first allocation unit that allocates all of individual variables except for a common variable used in common to the plurality of instruction groups among variables to only a register constituting one register group allocated to the instruction group A compile program which is operated as a device.

Images