JP5399538B2 - Touch panel controller, integrated circuit using the same, touch panel device, and electronic device - Google Patents

Description

  The present invention relates to a touch panel controller for controlling a touch panel including a sense line, M drive lines, and M capacitances respectively formed between the sense lines and the M drive lines, and The present invention relates to an integrated circuit, a touch panel device, and an electronic device used.

  Capacitance detection circuit for detecting a distribution of capacitance values of a capacitance matrix formed between M drive lines and L sense lines as a device for detecting capacitance values distributed in a matrix However, this is disclosed in Patent Document 1. In the capacitance detection device, when the touch panel is touched with a finger or pen, the capacitance value of the capacitance is reduced at the touched position, and by detecting the change in the capacitance value, The touch position with the touch panel by a finger or a pen is detected.

  FIG. 13 is a schematic diagram showing a configuration of the touch panel device 51 disclosed in Patent Document 1. As shown in FIG. FIG. 14 is a diagram illustrating mathematical formulas for estimating the capacity by driving the touch panel system 51 with an orthogonal code sequence. The touch panel system 51 includes a touch panel 52 and a touch panel controller 53. The touch panel 52 has drive lines DL1 to DL4, sense lines SL1 to SL4, and capacitances C11 to C44 arranged at positions where the drive lines DL1 to DL4 and the sense lines SL1 to SL4 intersect. .

  The touch panel controller 53 is provided with a drive unit 54. The drive unit 54 drives the drive lines DL1 to DL4 based on the 4 × 4 orthogonal code sequence shown in Expression 7 of FIG. The element of the orthogonal code sequence is either “1” or “−1”. If the element is “1”, the drive unit 54 applies the voltage Vdrive, and if the element is “−1”, −Vdrive is applied. Here, the voltage Vdrive may be a power supply voltage, but may be a voltage other than the power supply voltage.

  In this specification, “orthogonal code sequence” means that a code sequence N = (di1, di2,..., DiN) (i = 1,..., M) having a code length N satisfies the following conditions. It shall be said.

  An example of an “orthogonal code sequence” is a Hadamard matrix generated by a sylvester method.

  The Hadamard matrix by the Sylvester method creates a basic unit of 2 rows × 2 columns as a basic structure. The upper right, upper left, and lower left bits of the basic unit are the same, and the lower right is an inversion of these bits.

  Next, the above-described 2 × 2 basic elements are combined as four blocks in the upper right, upper left, lower right, and lower left to create a code of a bit array of 4 rows × 4 columns. Here, as in the creation of the 2 × 2 basic unit, the lower right block is bit-inverted. The code of the bit arrangement of 8 rows × 8 columns and 16 rows × 16 columns is generated in the same procedure. These matrices satisfy the above-described definition of the “orthogonal code sequence” of the present invention. The orthogonal code sequence of 4 rows × 4 columns shown in FIG. 14 is a 4 rows × 4 columns Hadamard matrix by the Sylvester method.

  Here, the Hadamard matrix refers to a square matrix whose elements are either 1 or −1 and whose rows are orthogonal to each other. That is, any two rows of the Hadamard matrix represent vectors that are perpendicular to each other.

  As the “orthogonal code sequence” according to the present invention, a matrix obtained by arbitrarily extracting N rows from an M-order Hadamard matrix can be used (where N ≦ M). As described below, a Hadamard matrix by a method other than the Sylvester method can also be applied to the present invention.

  The Nth order Hadamard matrix by the Sylvester method is a power of M = 2, but if M is a multiple of 4, there is an expectation that a Hadamard matrix exists, for example, when M = 12, and M There is a Hadamard matrix when = 20. Hadamard matrices obtained by methods other than these Sylvester methods can also be used as orthogonal code sequences according to the present embodiment.

  The touch panel system 51 includes four amplifiers 55 arranged at positions corresponding to the sense lines SL1 to SL4, respectively. The amplifier 55 receives and amplifies the linear sums Y1, Y2, Y3, and Y4 along the capacitance sense line driven by the driving unit 54.

  For example, in the first drive among the four times of the 4 rows × 4 columns orthogonal code sequence, the drive unit 54 applies the voltage Vdrive to all the drive lines DL1 to DL4. Then, for example, the measured value Y1 from the sense line SL3 expressed by the following formula 5 is output from the amplifier 55. In the second drive, the voltage Vdrive is applied to the drive lines DL1 and DL3, and -Vdrive is applied to the remaining drive lines DL2 and DL4. Then, the measured value Y2 from the sense line SL3 expressed by the following equation 6 is output from the amplifier 55.

  Next, in the third drive, the voltage Vdrive is applied to the drive lines DL1 and DL2, and −Vdrive is applied to the remaining drive lines DL3 and DL4. Then, the measured value Y3 from the sense line SL3 is output from the amplifier 55. Thereafter, in the fourth drive, the voltage Vdrive is applied to the drive lines DL1 and DL4, and −Vdrive is applied to the remaining drive lines DL2 and DL3. Then, the measured value Y4 from the sense line SL3 is output from the amplifier 55.

  Here, the capacitances C31 to C34 shown in FIG. 13 are indicated by C1 to C4 in the formulas 7 to 9 in FIG. In FIG. 14, the measurement values Y1 to Y4 are omitted from the coefficient (−Vdrive / Cint) to simplify the notation.

  Then, as shown in Equation 8, the capacitances C1 to C4 are estimated as shown in Equation 9 by taking the inner product of the measured values Y1, Y2, Y3, and Y4 and the orthogonal code sequence as shown in Equation 8. Can do.

  15 is a circuit diagram showing the configuration of another conventional touch panel device 98, and FIG. 16 is a waveform diagram showing the operation of another touch panel device 98. As shown in FIG. 17 is a circuit diagram showing the operation of another touch panel device 98, and FIG. 18 is a waveform diagram showing another operation of the other touch panel device 98.

  The problem of the touch panel described in Patent Document 1 will be described with reference to FIGS. Here, for simplicity, the number of drive lines is four and the number of sense lines is one.

  The touch panel device 98 includes a touch panel 97, a drive unit 92, an analog integrator 95, and an inner product calculation circuit 93. The drive unit 92 includes switches S1 to S4 connected to the drive lines DL1 to DL4, respectively.

  The analog integrator 95 has an operational amplifier 99 with one input coupled to the sense line and the other input coupled to a reference voltage Vref. The output of the operational amplifier 99 is coupled to the sampling switch Samp. Between the output of the operational amplifier 99 and one input of the operational amplifier 99, an integration capacitor Cint and a reset switch Rst are arranged in parallel with each other.

  The drive line DL1 and the drive line DL3 are all given a code sequence whose code is “−1”, and the drive line DL2 and the drive line DL4 are all given a code sequence which is “1”. For the sake of simplicity, as shown in FIG. 15, if the switches S1 to S4 are “ON”, the corresponding drive line is connected to the power supply voltage VDD, and if “OFF”, the corresponding drive line is grounded. Suppose that Further, it is assumed that the reference voltage Vref of the analog integrator 95 is given by VDD / 2.

  First, a period during which the analog integrator 95 is reset when the reset switch Rst is “ON” will be described with reference to FIG. This period is hereinafter referred to as period a starting from time T91 and ending at time T92. The signal corresponding to the reset switch Rst rises from off to on at time T91 when the period a starts, and falls from on to off at time T92 when the period a ends. During this period a, the switch S1 is off and grounded, and the switch S2 is on and coupled to the power supply voltage VDD. Switch S3 is off and grounded, and switch S4 is on and coupled to power supply voltage VDD. The sampling switch Samp is off.

  As shown in FIG. 17, in the period a, the voltage of the sense line SL is biased to the reference voltage Vref (= VDD / 2) by the analog integrator 95 that has been reset. Since the drive lines DL1 and DL3 are grounded and the drive lines DL2 and DL4 are connected to the power supply voltage VDD, the charges Q11a, Q12A, Q13A, and Q14A stored in the capacitances C11, C12, C13, and C14 are respectively ,

Given in.

  Next, a period in which the switch Rst is “off” and the output signal of the analog integrator 95 is read will be described with reference to FIGS. 15 and 16. Hereinafter, this period is referred to as period b starting from time T93 and ending at time T96.

  The reset switch Rst is off from time T93 to time T96. The switch S1 turns from off to on at time T93 when the period b starts, and turns off from on at time T96 when the period b ends. The switch S2 turns from on to off at time T93, and turns from off to on at time T96. The switch S3 turns from off to on at time T93, and turns off from on at time T96. The switch S4 turns from on to off at time T93, and turns from off to on at time T96. Then, the sampling switch Samp turns from off to on at time T94, and turns from on to off at time T95.

  In the period b, if the gain of the operational amplifier 99 of the analog integrator 95 is sufficiently large, the voltage of the sense line SL becomes substantially equal to Vref (= VDD / 2). Since the drive lines DL2 and DL4 are grounded and the drive lines DL1 and DL3 are connected to the power supply voltage VDD, the charges Q11b, Q12b, Q13b, and Q14b stored in the capacitances C11, C12, C13, and C14 are respectively ,

Given in.

  When shifting from the period a to the period b, it is necessary to charge the electrostatic capacitance C11 and the electrostatic capacitance C13, so that the electric charge of (VDD · C11 + VDD · C13) is supplied from the power supply voltage VDD. The electric charges of the electrostatic capacitance C12 and the electrostatic capacitance C14 are discharged to the ground GND. Further, since it is necessary to charge the capacitance C12 and the capacitance C14 when the period b is shifted to the period a, the electric charge of (VDD · C12 + VDD · C14) is supplied from the power supply voltage VDD. The electric charges of the electrostatic capacitance C11 and the electrostatic capacitance C13 are discharged to the ground GND. That is, if the time taken from time T91 to time T97, which is one cycle of operation (cycle from period a through period b to period a), is T, the current Icycle consumed in one cycle is supplied from the power supply voltage VDD. Given by dividing the total amount of charge to be divided by time T;

It becomes.

Patent No. 4927216 (Registered on February 17, 2012)

  However, in the configuration shown in FIGS. 15 to 18 described above, from the power supply voltage VDD (VDD · C11 + VDD · C13) in order to charge the capacitance C11 and the capacitance C13 when the period a is shifted to the period b. And the charge from the power supply voltage VDD to (VDD · C12 + VDD · C14) is charged to charge the capacitance C12 and the capacitance C14 when the period b is shifted to the period a. It is necessary to supply.

  For this reason, when the capacitance values of the capacitances C11, C12, C13, and C14 of the touch panel 97 are increased, or the period for driving the touch panel 97 is shortened, or the voltage that drives the capacitance of the touch panel 97 (FIGS. 15 to FIG. 15). When the power supply voltage VDD) in the example shown by 18 increases, the drive current for driving the drive line increases. Further, when the number of drive lines and sense lines of the touch panel 97 increases, the current consumption of the touch panel increases. Therefore, there is a problem that current consumption of the touch panel controller increases.

  An object of the present invention is to provide a touch panel controller capable of reducing power consumption, an integrated circuit using the same, a touch panel device, and an electronic apparatus.

  In order to solve the above problems, a touch panel controller according to the present invention includes a sense line, M drive lines, and M static lines formed between the sense lines and the M drive lines, respectively. A touch panel controller for controlling a touch panel including a capacitance, wherein the M capacitances are driven in parallel based on N M-dimensional vectors, and a linear sum signal of charges accumulated in the capacitances A drive circuit that outputs a value along the sense line, and an inner product operation circuit that estimates the value of the M capacitances by an inner product operation of the linear sum signal and the N M-dimensional vectors, The drive circuit includes a switch for short-circuiting at least two of the M drive lines.

  According to this feature, at least two of the M drive lines are short-circuited by the switch. For this reason, the electric charge accumulated in the capacitance connected to the shorted drive line can be redistributed to each capacitance through the shorted drive line. Therefore, the drive power of the drive line can be reduced. As a result, the power consumption of the touch panel controller can be reduced.

  The touch panel controller according to the present invention preferably further includes a control circuit that generates a short-circuit control signal for controlling the switch based on the N M-dimensional vectors.

  According to the above configuration, the switch for short-circuiting at least two of the M drive lines is controlled by the short-circuit control signal generated based on the N M-dimensional vectors. At least two are short-circuited by the switch. For this reason, the electric charge accumulated in the capacitance connected to the shorted drive line can be redistributed to each capacitance. Therefore, the drive power of the drive line can be reduced. As a result, the power consumption of the touch panel controller can be reduced.

  The touch panel controller according to the present invention further includes an analog integrator that analog-integrates the linear sum signal and supplies the signal to the inner product operation circuit, and the switch is configured to drive the drive based on a reset period during which the analog integrator is reset. It is preferable to short the line.

  According to the above configuration, the drive line is short-circuited based on the reset period during which the analog integrator is reset. For this reason, the voltage of the sense line connected to the analog integrator is biased by the reset analog integrator, and the electric charge accumulated in the capacitance connected to the shorted drive line is transferred to each capacitance. Can be redistributed. Therefore, the drive power of the drive line can be further reduced.

  In the touch panel controller according to the present invention, it is preferable that the switch starts a short circuit of the drive line based on the start of the reset period.

  According to the above configuration, the short circuit of the drive line is started based on the start of the reset period. For this reason, the voltage on the sense line connected to the analog integrator is biased by the reset analog integrator, and the charge accumulated in the capacitance connected to the shorted drive line is restored to each capacitance. Can be allocated. Therefore, the drive power of the drive line can be further reduced.

  In the touch panel controller according to the present invention, it is preferable that the switch starts a short circuit of the drive line based on the end of the reset period.

  According to the above configuration, the short circuit of the drive line is started based on the end of the reset period. At this time, the voltage of the sense line connected to the analog integrator is substantially equal to Vref (= VDD / 2). And the electric charge accumulate | stored in the electrostatic capacitance connected to the shorted drive line is redistributed to each electrostatic capacitance, and the drive power of a drive line can be made smaller.

  The integrated circuit according to the present invention is characterized by integrating the touch panel controller according to the present invention.

  According to this feature, at least two of the M drive lines of the touch panel controlled by the touch panel controller are short-circuited by the switch. For this reason, the electric charge accumulated in the capacitance connected to the shorted drive line can be redistributed to each capacitance. Therefore, the drive power of the drive line can be reduced. As a result, an integrated circuit that can reduce the power consumption of the touch panel controller can be provided.

  The touch panel device according to the present invention includes the touch panel controller according to the present invention and a touch panel controlled by the touch panel controller.

  According to this feature, at least two of the M drive lines of the touch panel controlled by the touch panel controller are short-circuited by the switch. For this reason, the electric charge accumulated in the capacitance connected to the shorted drive line can be redistributed to each capacitance. Therefore, the drive power of the drive line can be reduced. As a result, the power consumption of the touch panel device can be reduced.

  An electronic apparatus according to the present invention includes the touch panel controller according to the present invention and a touch panel controlled by the touch panel controller.

  According to this feature, at least two of the M drive lines of the touch panel controlled by the touch panel controller are short-circuited by the switch. For this reason, the electric charge accumulated in the capacitance connected to the shorted drive line can be redistributed to each capacitance. Therefore, the drive power of the drive line can be reduced. As a result, power consumption of the electronic device can be reduced.

  In the touch panel controller according to the present invention, at least two of the M drive lines are short-circuited by a switch. For this reason, the electric charge accumulated in the capacitance connected to the shorted drive line can be redistributed to each capacitance through the shorted drive line. Therefore, the drive power of the drive line can be reduced. As a result, the power consumption of the touch panel controller can be reduced.

1 is a circuit diagram showing a configuration of a touch panel device according to Embodiment 1. FIG. It is a wave form diagram which shows operation | movement of the said touchscreen apparatus. It is a circuit diagram for demonstrating operation | movement of the said touchscreen apparatus. It is another circuit diagram for demonstrating operation | movement of the said touchscreen apparatus. It is a schematic diagram for demonstrating operation | movement of the said touchscreen apparatus. It is another schematic diagram for demonstrating operation | movement of the said touchscreen apparatus. It is a schematic diagram for demonstrating operation | movement of the conventional touch panel apparatus. 6 is a circuit diagram showing a configuration of a touch panel device according to Embodiment 2. FIG. It is a wave form diagram which shows operation | movement of the said touchscreen apparatus. It is a block diagram which shows the structure of the control circuit and code sequence generation circuit which were provided in the said touch panel apparatus. It is a wave form diagram which shows operation | movement of the said control circuit and a code series production | generation circuit. 6 is a block diagram illustrating a configuration of a mobile phone according to Embodiment 3. FIG. It is a circuit diagram which shows the structure of the conventional touch panel apparatus. It is a figure for demonstrating operation | movement of the said touchscreen apparatus. It is a circuit diagram which shows the structure of the other conventional touch panel apparatus. It is a wave form diagram which shows operation | movement of the said other touch panel apparatus. It is a circuit diagram which shows operation | movement of the said other touch panel apparatus. It is a wave form diagram which shows other operation | movement of said other touch panel apparatus.

  Hereinafter, embodiments of the present invention will be described in detail.

(Embodiment 1)
(Configuration of touch panel device 8)
FIG. 1 is a circuit diagram showing a configuration of touch panel device 8 according to the first embodiment. The touch panel device 8 includes a touch panel 7 and a touch panel controller 1. Here, for the sake of brevity, the touch panel 7 will be described as having four drive lines and one sense line.

  The touch panel 7 has drive lines DL1 to DL4, a sense line SL, and capacitances C11 to C14 formed at positions where the drive lines DL1 to DL4 and the sense line SL intersect.

  The touch panel controller 1 has a drive circuit 2. The drive circuit 2 drives the capacitances C11 to C14 in parallel based on the N four-dimensional vectors, and analogizes the linear sum signal of the charges accumulated in the capacitances C11 to C14 along the sense line SL. Output to the integrator 5.

  The analog integrator 5 has an operational amplifier 9 having one input coupled to the sense line SL and the other input coupled to a reference voltage Vref. The output of the operational amplifier 9 is coupled to the sampling switch Samp. Between the output of the operational amplifier 9 and one input of the operational amplifier 9, an integration capacitor Cint and a reset switch Rst are arranged in parallel with each other. The analog integrator 5 integrates the linear sum signal output along the sense line SL and supplies it to the inner product arithmetic circuit 3.

  The inner product calculation circuit 3 estimates the values of the capacitances C11 to C14 by the inner product calculation of the linear sum signal supplied from the analog integrator 5 and N four-dimensional vectors.

  The drive circuit 2 has a switch S1p for supplying the power supply voltage VDD to the drive line DL1 based on N number of four-dimensional vectors (code series), and a ground GND for supplying the drive line DL1 based on the code series. A switch S1n arranged in parallel with the switch S1p, a switch S2p for supplying the power supply voltage VDD to the drive line DL2 based on the code sequence, and a switch for supplying the ground GND to the drive line DL2 based on the code sequence A switch S2n arranged in parallel with S2p, a switch S3p for supplying the power supply voltage VDD to the drive line DL3 based on the code sequence, and a switch S3p for supplying the ground GND to the drive line DL3 based on the code sequence And switch S3n arranged in parallel with A switch S4p for supplying the power supply voltage VDD to the drive line DL4 based on the column, and a switch S4n arranged in parallel with the switch S4p for supplying the ground GND to the drive line DL4 based on the code sequence ing.

  The drive circuit 2 is provided with short-circuit switches S1s to S4s for short-circuiting the drive lines DL1 to DL4, respectively. One ends of the short-circuit switches S1s to S4s are connected to the drive lines DL1 to DL4, respectively, and the other ends of the short-circuit switches S1s to S4s are coupled to each other.

  The touch panel controller 1 has a control circuit 6. The control circuit 6 controls the drive circuit 2 and the analog integrator 5 based on the N four-dimensional vectors.

  Here, for the sake of simplicity, the drive lines DL1 and DL3 are given code sequences whose codes are all “−1”, and the drive lines DL2 and DL4 are all given code sequences that are “1”. ing. For simplicity, as shown in FIG. 1, if the switch S1 is “ON”, that is, if the switch S1p is ON and the switch S1n is OFF, the drive line SL1 is connected to the power supply voltage VDD, and the switch S2 Is ON, that is, if the switch S2p is on and the switch S2n is off, the drive line SL2 is connected to the power supply voltage VDD. If the switch S3 is “on”, that is, if the switch S3p is on and the switch S3n is off, the drive line SL3 is connected to the power supply voltage VDD, and if the switch S4 is “on”, that is, the switch S4p is If the switch S4n is off and the switch S4n is off, the drive line SL4 is connected to the power supply voltage VDD.

  If the switch S1 is “off”, that is, if the switch S1p is off and the switch S1n is on, the drive line SL1 is connected to the ground GND, and if the switch S2 is “off”, that is, the switch S2p is off. If the switch S2n is on, the drive line SL2 is connected to the ground GND. If the switch S3 is “off”, that is, if the switch S3p is off and the switch S3n is on, the drive line SL3 is connected to the ground GND, and if the switch S4 is “off”, that is, the switch S4p is off. If the switch S4n is on, the drive line SL4 is connected to the ground GND.

  Further, it is assumed that the reference voltage Vref is given by VDD / 2.

  The touch panel controller 1 shown in FIG. 1 includes switches S1s to S4s that short-circuit a plurality of drive lines in addition to the conventional configuration shown in FIG. The switches S1s to S4s are controlled by control signals corresponding to the switches S1s to S4s, respectively. The switches S1p to S4p connected between the drive line and the power source are controlled by control signals corresponding to the switches S1p to S4p, respectively. It is assumed that the switches S1n to S4n connected between the drive line and the ground are controlled by control signals corresponding to the switches S1n to S4n, respectively.

  The touch panel controller 1 can be configured by an integrated circuit in which the touch panel controller 1 is integrated.

(Operation of touch panel device 8)
FIG. 2 is a waveform diagram showing the operation of the touch panel device 8, and shows an example of a timing diagram of these control signals.

  First, at time T1 when the period c starts, when the switch Rst is turned on from off, the switches S1p, S1n, S2p, S2n, S3p, S3n, S4p, and S4n are all off, and the short-circuit switches S1s to S4s are From off to on. At time T2 when the period c ends and the period a starts, the switches S1n, S3n, S2p, and S4p are turned on from off, and the short-circuit switches Sis to S4s are turned on from off.

  Next, at time T3 when the period a ends and the period d starts, the reset switch Rst is turned from on to off, the switches S1n, S3n, S2p, and S4p are turned from on to off, and the short-circuit switches S1s to S4s are turned off. To turn on. Thereafter, at time T4 when the period d ends and the period b starts, the switches S1p, S3p, S2n, and S4n are turned on from the off state, and the short-circuit switches S1s to S4s are turned on from the off state.

  At time T5, the sampling switch Samp is turned on from off. Next, at time T6 when the period b ends, the switches S1p, S3p, S2n, S4n and the sampling switch Samp are turned off from on.

  Thereafter, when the switch Rst is turned from OFF to ON at the time T7 when the period c starts, the switches S1p, S1n, S2p, S2n, S3p, S3n, S4p, and S4n are all off, and the short-circuit switches S1s to S4s are off. Will be on. Thereafter, the same operation is repeated.

  Thus, the short-circuit switches S1s to S4s short-circuit the drive lines DL1 to DL4 based on the time T1 to time T3 in the reset period in which the analog integrator 5 is reset. That is, the short-circuit switches S1s to S4s start short-circuiting the drive lines DL1 to DL4 from time T1 when the reset period starts. Then, the short-circuit switches S1s to S4s start short-circuiting the drive lines DL1 to DL4 from time T3 when the reset period ends.

  In the example shown in FIG. 2, after the value of the signal corresponding to the reset switch Rst of the analog integrator 5 is changed, the short-circuit switches S1s to S4s that short-circuit the drive lines are turned on. The period when the reset switch Rst of the analog integrator 5 is “ON” and the short-circuit switches S1s to S4s are “ON” is the period c, the reset switch Rst of the analog integrator 5 is “OFF”, and the short-circuit switches S1s to S4 The operation will be described with a period d in which S4s is “ON”. In the period a and the period b, the same operation as the above-described conventional configuration is performed.

  3 and 4 are circuit diagrams for explaining the operation of the touch panel device 8. 5 and 6 are schematic views for explaining the operation of the touch panel device 8. FIG. 7 is a schematic diagram for explaining the operation of the conventional touch panel device.

  First, the operation in the period c will be described with reference to FIGS. Here, the period b has shifted to the period c. In the period c, the voltage of the sense line SL is biased to the reference voltage Vref (= VDD / 2) by the reset analog integrator 5. Since all the drive lines DL1 to DL4 are short-circuited, the charges Q11b, Q12b, Q13b, and Q14b stored in the capacitances C11, C12, C13, and C14 are transferred to the capacitances C11, C12, C13, and C14. Distributed. If the total charge is Qc,

It becomes. The voltage Vshort of the shorted drive line is

Given in. Therefore, the charge stored in each capacitance is

It becomes.

  The operation in the period d will be described with reference to FIGS. 4, 5, and 6. Here, the period a is shifted to the period d. In the period d, if the gain of the operational amplifier 9 of the analog integrator 5 is sufficiently large, the voltage of the sense line SL becomes substantially equal to the reference voltage Vref (= VDD / 2).

  Since all the drive lines DL1 to DL4 are short-circuited, the charges Q11a, Q12a, Q13a, and Q14a stored in the electrostatic capacitors C11, C12, C13, and C14 are transferred to the electrostatic capacitors C11, C12, C13, and C14. Distributed. If the total charge is Qd,

It becomes. The voltage Vshort of the shorted drive line is

Given in. Therefore, the charges stored in the respective capacitances C11, C12, C13, and C14 are

It becomes.

  Next, with reference to FIG. 5 and FIG. 6, consider the case of transition from period c to period a. Considering the capacitance C11,

ΔQ11ca is

Thus, the charge of ΔQ11ca is discharged to the ground GND. The same operation is performed for the capacitance C13.

  Next, consider the capacitance C12.

Is

Thus, the charge of ΔQ12ca is supplied from the power supply voltage VDD. The same operation is performed for the capacitance C14.

  Next, consider the case of transition from period d to period b. Considering the capacitance C11,

Thus, the charge transfer amount ΔQ11db is

Thus, the charge of ΔQ11db is supplied from the power supply voltage Vdd. The same operation is performed for the capacitance C13.

  Next, consider the capacitance C12.

ΔQ12db is

Thus, the charge of ΔQ12db is discharged to the ground GND. The same operation is performed for the capacitance C14.

  In the transition from the period a to the period d and the transition from the period b to the period c, only charge distribution is performed, so that supply of charge from the power supply voltage Vdd and discharge to the ground GND are not performed. . The total amount of charge supplied from the power supply voltage Vdd in one cycle of operation is

If the capacitances C11, C12, C13, and C14 are all equal, the total amount of charges is

Given in. That is, if the time taken for one cycle of operation is T, the current Icycle consumed in one cycle is

It becomes.

  Referring to FIGS. 5, 6, and 7, in the first embodiment, a period c for short-circuiting drive lines SL <b> 1 to SL <b> 4 is provided during the transition from period b to period a, and during the transition from period a to period b. A period d for short-circuiting the drive lines SL1 to SL4 is provided. For this reason, the charges of the capacitances C11 to C44 are redistributed in the period c and the period d.

  In the conventional configuration shown in FIGS. 17 and 7, assuming that the capacitances C11, C12, C13, and C14 are all equal, the current Icycle old consumed in one cycle is

Thus, the current consumption can be halved compared to the conventional configuration.

  In the first embodiment, an example is shown in which all four drive lines are short-circuited, but the present invention is not limited to this. Two or three drive lines may be short-circuited.

(Embodiment 2)
(Configuration of touch panel device 8A)
FIG. 8 is a circuit diagram showing a configuration of touch panel device 8A according to the second embodiment. The same reference numerals are given to the same components as those described above. Therefore, detailed description of these components will not be repeated.

  The touch panel device 8A includes a touch panel controller 1A. The touch panel controller 1A includes a code sequence generation circuit 10 and a control circuit 6A.

  Here, for the sake of simplicity, as in the first embodiment, if the switches S1 to S4 are “ON”, the drive line is connected to the power supply voltage VDD, and if it is “OFF”, the drive line is grounded. Further, it is assumed that the reference voltage Vref is given by VDD / 2.

  In the touch panel controller 1 shown in FIG. 1, for the sake of simplicity, the drive lines DL1 and DL3 are all given a code sequence whose signs are “−1”, and the drive lines DL2 and DL4 are all “1”. Is given a code sequence. However, in the second embodiment, it is assumed that a code sequence that repeats “−1, 1” is given to the drive line DL1, and a code sequence that repeats “1, −1” is given to the drive line DL2. For the drive lines DL3 and DL4, as in the example of FIG. 1, a code sequence that is all “−1” is given to the drive line DL3, and a code sequence that is all “1” is given to the drive line DL4.

  FIG. 9 is a waveform diagram showing the operation of the touch panel device 8A. First, at time T1 when the period c starts, when the switch Rst is turned on from off, the switches S1p, S2n, S3p, S3n, S4p, and S4n are all off, and the switches S1n and S2p are on. The short-circuit switches S1s to S2s are off, and the short-circuit switches S3s to S4s are turned on from off. At time T2 when the period c ends and the period a starts, the switches S3n and S4p are turned on from off and the short-circuit switches S3s and S4s are turned off from on.

  Next, at time T3 when the period a ends and the period d starts, the reset switch Rst is turned from on to off, the switches S1n, S3n, S2p, and S4p are turned from on to off, and the short-circuit switches S1s to S4s are turned off. To turn on. Thereafter, at time T4 when the period d ends and the period b starts, the switches S1p, S3p, S2n, and S4n are turned on from the off state, and the short-circuit switches S1s to S4s are turned on from the off state.

  At time T5, the sampling switch Samp is turned on from off. Next, at time T6 when the period b ends, the switches S3p and S4n and the sampling switch Samp are turned off from on.

  Thereafter, at time T7 when the period c starts, when the switch Rst is turned on from off, the switches S1n, S2p, S3p, S3n, S4p, and S4n are all off, and the switches S1p and S2n are on. The short-circuit switches S3s to S4s are turned on from off. The short-circuit switches S1s and S2s are off. Thereafter, the same operation is repeated.

  As described above, when the drive line DL1 and the drive line DL2 shift from the period b to the period c to the period a, the connection destination of the drive lines DL1 and DL2 in the period b and the period a does not change. In the period c, the short-circuit switches S1s and S2s are turned on to prevent short-circuiting. In this case, since the connection destination of the drive line in the period b and the period a does not change between the electrostatic capacity C11 and the electrostatic capacity C12, there is no charge movement between the electrostatic capacity C11 and the electrostatic capacity C12. Therefore, power is not consumed by transition from period b → period c → period a.

  FIG. 10 is a block diagram showing the configuration of the control circuit 6A and the code sequence generation circuit 10 provided in the touch panel device 8A. FIG. 11 is a waveform diagram showing operations of the control circuit 6A and the code sequence generation circuit 10.

  The code sequence generation circuit 10 generates a code sequence of N four-dimensional vectors. The control circuit 6A receives one-dimensional portions of the four-dimensional vectors generated by the code sequence generation circuit 10 and generates drive line control signals each delayed by one clock, and outputs from the delay circuit 11 And four short-circuit control signal generation circuits 12 that respectively receive one-dimensional portions of the four-dimensional vectors generated by the code sequence generation circuit 10 and generate drive line short-circuit control signals.

  In this way, a drive line control signal obtained by delaying the signal output from the code sequence generation circuit 10 by the delay circuit 11 is applied to each drive line. As shown in FIG. 11, the short-circuit control signal generation circuit 12 outputs “−1” if the output signal from the code sequence generation circuit 10 and the output signal from the delay circuit 11 match, and if they do not match. “1” is output. When the output signal from the short-circuit control signal generation circuit 12 is “1”, the respective drive lines are not short-circuited in the next clock period c. If the output signal from the short-circuit control signal generation circuit 12 is “−1”, each drive line is short-circuited in the period c of the next clock.

  Thus, the power consumption of the touch panel controller can be further suppressed by adaptively controlling the short-circuiting switch in accordance with the code form of the code sequence given to the drive line.

(Embodiment 3)
FIG. 12 is a block diagram showing a configuration of mobile phone 100 according to Embodiment 3. In FIG. A mobile phone 100 that is an example of an electronic device equipped with a touch panel controlled by an integrated circuit in which the touch panel controller of the present invention is integrated will be described with reference to FIG.

  The cellular phone 100 includes a CPU 110, a RAM 112, a ROM 111, a camera 113, a microphone 114, a speaker 115, an operation key 116, a display panel 118, a display control circuit 109, and a touch panel system 101. . Each component is connected to each other by a data bus.

  CPU 110 controls the operation of mobile phone 100. The CPU 110 executes a program stored in the ROM 111, for example. The operation key 116 receives an instruction input from the user to the mobile phone 100. The RAM 112 volatilely stores data generated by executing a program by the CPU 110 or data input via the operation keys 116. The ROM 111 stores data in a nonvolatile manner.

  The ROM 111 is a ROM capable of writing and erasing, such as an EPROM (Erasable Programmable Read-Only Memory) or a flash memory. Although not shown in FIG. 12, the mobile phone 100 may be configured to include an interface (IF) for connecting to another electronic device by wire.

  The camera 113 captures a subject in response to the operation of the operation key 116 by the user. The image data of the photographed subject is stored in the RAM 112 or an external memory (for example, a memory card). The microphone 114 receives user's voice input. The mobile phone 100 digitizes the input voice (analog data). Then, the mobile phone 100 sends the digitized voice to a communication partner (for example, another mobile phone). The speaker 115 outputs a sound based on, for example, music data stored in the RAM 112.

  The touch panel system 101 includes a touch panel 102 and a touch panel controller 103 (integrated circuit). The CPU 110 controls the operation of the touch panel system 101. For example, the CPU 110 executes a program stored in the ROM 111. The RAM 112 stores data generated by the execution of the program by the CPU 110 in a volatile manner. The ROM 111 stores data in a nonvolatile manner.

  The display panel 118 displays images stored in the ROM 111 and the RAM 112 by the display control circuit 109. The display panel 118 may be superimposed on the touch panel 102 or may incorporate the touch panel 102.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  The present invention relates to a touch panel controller for controlling a touch panel including a sense line, M drive lines, and M capacitances respectively formed between the sense lines and the M drive lines, and It can be used for the used integrated circuit, touch panel device, and electronic equipment.

DESCRIPTION OF SYMBOLS 1 Touch panel controller 2 Drive circuit 3 Inner product calculation circuit 5 Analog integrator 6 Control circuit 7 Touch panel 8 Touch panel apparatus 9 Operational amplifier 10 Code sequence generation circuit 11 Delay circuit 12 Short circuit control signal generation circuit

Claims (8)

A touch panel controller that controls a touch panel including a sense line, M drive lines, and M capacitances formed between the sense lines and the M drive lines, respectively.
A drive circuit for driving the M capacitances in parallel based on N M-dimensional vectors and outputting a linear sum signal of charges accumulated in the capacitances along the sense lines;
An inner product operation circuit that estimates the value of the M capacitances by an inner product operation of the linear sum signal and the N M-dimensional vectors,
The touch panel controller, wherein the drive circuit includes a switch for short-circuiting at least two of the M drive lines.   The touch panel controller according to claim 1, further comprising a control circuit that generates a short-circuit control signal for controlling the switch based on the N M-dimensional vectors. An analog integrator that analog-integrates the linear sum signal and supplies it to the inner product arithmetic circuit;
The touch panel controller according to claim 1, wherein the switch short-circuits the drive line based on a reset period in which the analog integrator is reset.   The touch panel controller according to claim 3, wherein the switch starts a short circuit of the drive line based on the start of the reset period.   The touch panel controller according to claim 3, wherein the switch starts a short circuit of the drive line based on the end of the reset period.   An integrated circuit, wherein the touch panel controller according to claim 1 is integrated. A touch panel controller according to claim 1;
A touch panel device comprising: a touch panel controlled by the touch panel controller. A touch panel controller according to claim 1;
An electronic device comprising: a touch panel controlled by the touch panel controller.

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