JP5393410B2 - Baseband signal stretching circuit - Google Patents

Description

  The present invention relates to an extension circuit for a baseband signal transmitted in a communication system in which a plurality of nodes are connected via a wired transmission path.

  As an example of a conventional baseband signal extending circuit, there is a repeater (see, for example, Non-Patent Document 1 below). A repeater terminates and generates a physical layer on a transmission line, that is, when a signal in an electrically deteriorated state is received, it is reshaped and transmitted, and the signal transmission source device (transmission node) Repeaters relay (reshape and transfer) signals between the receiver and the receiving device (receiving node), thereby realizing signal transmission to a farther receiving node. It is also possible to arrange a plurality of repeaters between the transmission node and the reception node.

  However, a repeater is a circuit (apparatus) that relays a signal in the middle of a transmission path, and has a configuration independent of a transmission node and a reception node. Therefore, if there is no equipment such as a power source at the place where the signal is placed, it is impossible to extend the signal transmission distance using a repeater.

  In such a case, conventionally, extension of the signal transmission distance has been realized by an extension circuit in which, for example, an amplifier circuit is applied to the transmission node side and an equalizer circuit is applied to the reception node side. In this stretching circuit, the amplifier circuit receives the transmission signal output from the transmission node, amplifies this signal, and sends it to the transmission line. The equalizer circuit receives the signal sent from the amplifier circuit to the transmission line, and equalizes this signal with a cable to compensate the cable attenuation characteristic and passes it to the receiving node.

  In general, the frequency characteristic of the transmission line is determined by the cable characteristic to be applied, and thus has, for example, a √f characteristic and becomes an LPF (Low Pass Filter) characteristic that passes a low-frequency component.

  Further, for example, a bridged T-type constant resistance circuit shown in Non-Patent Document 2 below can be applied to the equalizer circuit, and has an HPF (High Pass Filter) characteristic that allows a high-frequency component to pass.

“Theory and Implementation of High-Speed Ethernet (registered trademark)” (p.119, ASCII Publishing) “Submarine Cable Communication System” (p.240, published by IEICE)

  However, the conventional baseband signal stretching circuit (stretching circuit comprising an amplifier circuit on the transmission node side and an equalizer circuit on the reception node side) has the following problems.

  For example, when the output signal from the transmitting node is a 10BASE-T signal, the 10BASE-T signal is added to the end of the 10BASE-T signal while the main signal frequency band is approximately 5 MHz to 8 MHz. The band of a signal called Start of Idle (hereinafter referred to as SOI) is a low frequency of about 50 kHz.

  In general, an equalizer circuit realizes a function of suppressing an amplitude variation between frequency bands of a main signal by applying an inverse characteristic to a frequency characteristic of a transmission line. At this time, the cut-off frequency fc of the equalizer circuit is generally set in the vicinity of the occupied frequency band of the main signal. For this reason, the low-frequency gain far from the cutoff frequency fc cannot secure a sufficient attenuation characteristic than the low-frequency characteristic of the equalizer circuit. Therefore, considering the loss of the transmission line and the loss of the equalizer circuit in total, the gain on the high-frequency side is obtained. Compared to this, the gain is large. In other words, since the attenuation amount of the high frequency component is larger than the attenuation amount of the low frequency component on the same transmission line, the level difference between the main signal and the SOI signal on the receiving node side increases as the transmission distance increases. Normal communication (reception) will not be possible.

  The present invention has been made in view of the above, and obtains a baseband signal stretching circuit capable of maintaining normal communication even when a signal composed of a plurality of types of components having greatly different frequencies is transmitted over a long distance. With the goal.

  In order to solve the above-described problems and achieve the object, the present invention provides a baseband signal extension applied to a communication system in which a signal transmission side node and a reception side node are connected via a wired transmission line. A transmission processing means for amplifying a signal output from a transmission node, which is a node on the transmission side, and transmitting the amplified signal to a transmission line; and receiving the signal transmitted to the transmission line, wherein the received signal has a frequency When two or more components having different bands are included, the level of each signal component is suppressed by an attenuation amount corresponding to the frequency band, and further, the frequency characteristics of the transmission path are reduced with respect to the received signal after the suppression. And receiving processing means for outputting to a receiving node which is a node on the receiving side after executing a corresponding compensation process.

  According to the present invention, it is possible to improve the communication quality when a signal is transmitted over a long distance, and it is possible to extend the transmission distance capable of maintaining normal communication more than before.

FIG. 1 is a diagram showing a configuration example of Embodiment 1 of a baseband signal extending circuit according to the present invention. FIG. 2 is a diagram illustrating a configuration example of the equalizer circuit. FIG. 3 is a diagram illustrating an example of frequency characteristics of the SOI suppression circuit. FIG. 4 is a diagram illustrating a configuration example of the SOI suppression circuit. FIG. 5 is a diagram showing a configuration example of a baseband signal extending circuit according to the second embodiment of the present invention. FIG. 6 is a diagram illustrating a configuration example of a third embodiment of a baseband signal extending circuit according to the present invention. FIG. 7 is a diagram illustrating a configuration example of the SOI deletion circuit. FIG. 8 is a diagram illustrating a configuration example of the SOI addition circuit. FIG. 9 is a diagram showing a configuration example of a fourth embodiment of a baseband signal extending circuit according to the present invention.

  Embodiments of a baseband signal stretching circuit (hereinafter simply referred to as a stretching circuit) according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a diagram showing a configuration example of Embodiment 1 of a baseband signal extending circuit according to the present invention. FIG. 1 also shows a transmission-side node and a reception-side node that perform signal transmission using an extension circuit.

  As shown in FIG. 1, the extension circuit of the present embodiment is arranged in the vicinity of the transmission circuit 1 arranged in the vicinity of the node 101 which is the transmission side node and the node 102 which is the node in the reception side. The reception processing unit 2 is configured, and the transmission processing unit 1 and the reception processing unit 2 are connected by a transmission line 100. The transmission processing unit 1 includes an amplifier circuit 11, amplifies the output signal from the node 101 by the amplifier circuit 11, and sends it to the transmission line 100. The reception processing unit 2 includes an SOI suppression circuit 21 and an equalizer circuit 22, and after the SOI suppression circuit 21 performs level adjustment of a signal received via the transmission line 100, the equalizer circuit 22 performs cable equalization.

  Hereinafter, the detailed operation of the extending circuit of the present embodiment will be described with reference to FIG. In this embodiment, as an example, an operation when a 10BASE-T signal including a main signal and an SOI signal is transmitted from the node 101 to the node 102 will be described.

  When transmitting a signal (10BASE-T signal) from the node 101 to the node 102, the signal output from the node 101 is input to the transmission processing unit 1, and the amplifier circuit 11 of the transmission processing unit 1 receives the input from the node 101. The signal is amplified and output to the transmission line 100. The signal sent to the transmission line 100 is input to the reception processing unit 2, and the SOI suppression circuit 21 of the reception processing unit 2 individually suppresses each signal component with a different attenuation amount for each component of the input signal. A reception signal composed of each signal component after suppression is input to the equalizer circuit 22, and the equalizer circuit 22 equalizes the input signal with a cable and outputs it to the node 102. The equalizer circuit 22 is a circuit similar to that provided in a conventional extending circuit (see Non-Patent Document 2 above), and has an HPF characteristic that allows a high-frequency component to pass through. The equalizer circuit 22 can be realized by a circuit including resistors 31 to 34, a capacitor 35, and a coil 36 as shown in FIG.

  The details of the signal suppression operation in the SOI suppression circuit 21 will be described. The SOI suppression circuit 21 has, for example, the HPF characteristic shown in FIG. 3, which is a high-frequency gain in the occupied frequency band of the main signal generated from the LPF characteristic of the transmission line 100 and the HPF characteristic of the equalizer circuit 22 and the SOI signal. This is a characteristic determined in consideration that the difference in the low-frequency gain in the occupied frequency band is close to zero.

  Specifically, the gain for the main signal is determined by combining the LPF characteristic of the transmission line 100 and the HPF characteristic of the equalizer circuit 22. As already described, the gain in the occupied frequency band of the main signal (high frequency signal) and the gain in the occupied frequency band of the SOI signal (low frequency signal) have the relationship of the following equation (1).

(Gain in main signal occupied frequency band) <(Gain in SOI signal occupied frequency band)
... (1)

  Therefore, in the extending circuit according to the present embodiment, the gain difference is absorbed by the operation of the SOI suppression circuit 21. That is, the SOI suppression circuit 21 realizes the above function by having an HPF characteristic that suppresses the gain in the occupied frequency band of the SOI signal.

  The gain in the occupied frequency band of the SOI signal is determined by combining the LPF characteristic of the transmission line 100, the HPF characteristic of the equalizer circuit 22, and the HPF characteristic of the SOI suppression circuit 21. As described above, the method for determining each parameter (cutoff frequency, attenuation characteristic, etc.) of the SOI suppression circuit 21 is such that the gain in the occupied frequency band of the main signal is the same as the gain in the occupied frequency band of the SOI signal. decide.

  The SOI suppression circuit 21 can be realized by a general integration circuit including a capacitor 41 and a resistor 42 as shown in FIG.

  As described above, in the extending circuit according to the present embodiment, the SOI signal that is a low frequency component included in the signal received from the transmission side node via the transmission path is brought closer to the level of the main signal that is the high frequency component. It was decided to perform cable equalization after suppression. That is, the cable equalization is performed after suppressing the SOI signal with the attenuation amount determined based on the frequency characteristic of the transmission line and the frequency characteristic of the circuit (equalizer circuit) that performs cable equalization. Thereby, the communication quality in the case of transmitting a signal over a long distance can be improved, and the transmission distance capable of maintaining normal communication can be extended as compared with the conventional case.

Embodiment 2. FIG.
FIG. 5 is a diagram illustrating a configuration example of the extending circuit according to the second embodiment. In FIG. 5, the same components as those of the extending circuit of the first embodiment (see FIG. 1) are denoted by the same reference numerals. In the present embodiment, description of the same components as those in Embodiment 1 is omitted.

  As illustrated, the extending circuit of the present embodiment includes a transmission processing unit 1a and a reception processing unit 2a. The transmission processing unit 1a includes an amplifier circuit 11 and an SOI suppression circuit 12, and the reception processing unit 2a includes an equalizer circuit 22. The SOI suppression circuit 12 performs the same processing as the SOI suppression circuit 21 of the reception processing unit 2 described in the first embodiment.

  That is, in the extending circuit of the present embodiment, the processing performed by the SOI suppression circuit 21 of the reception processing unit 2 in the extending circuit of the first embodiment (the high-frequency signal included in the input signal to the node 102 on the receiving side). The transmission side (transmission processing unit 1a) performs a process of suppressing the SOI signal, which is a low frequency signal, so that the level and the level of the low frequency signal are the same.

  The method for setting and realizing each parameter (cutoff frequency, attenuation characteristic, etc.) of the SOI suppression circuit 21 is the same as that of the SOI suppression circuit 21 of the first embodiment.

  As described above, in the extension circuit according to the present embodiment, in the transmission processing unit 1a arranged in the vicinity of the transmission side node, the amplification process of the signal output from the transmission side node and the low frequency included in the signal are performed. Signal (SOI signal) level suppression processing is performed so that the level of the high-frequency signal and the level of the low-frequency signal included in the signal transmitted from the transmission-side node become the same when reaching the reception-side node. did. Thereby, the communication quality in the case of transmitting a signal for a long distance can be improved similarly to the extending | stretching circuit of Embodiment 1 mentioned above.

Embodiment 3 FIG.
Next, the extending circuit according to the third embodiment will be described. In the first and second embodiments, the circuit that suppresses the SOI signal so that the level difference between the high-frequency component (main signal) and the low-frequency component (SOI signal) in the signal input to the reception-side node is small. In this embodiment, a stretching circuit that realizes normal communication during long-distance transmission will be described by a method different from those in the first and second embodiments.

  FIG. 6 is a diagram illustrating a configuration example of the extending circuit according to the third embodiment. In FIG. 6, the same components as those of the extension circuit (see FIG. 1) of the first embodiment are denoted by the same reference numerals. In the present embodiment, description of the same components as those in Embodiment 1 is omitted.

  As illustrated, the extending circuit of the present embodiment includes a transmission processing unit 1b and a reception processing unit 2b. The transmission processing unit 1b includes an amplifier circuit 11, an SOI deletion circuit 13 and a parallel / serial conversion circuit 14 disposed in the preceding stage, and the reception processing unit 2b includes an equalizer circuit 22 and a serial circuit disposed in the subsequent stage. / Parallel conversion circuit 23 and SOI addition circuit 24.

  The SOI deletion circuit 13 receives the signal (10BASE-T signal) output from the node 101 and deletes the SOI signal included therein. The parallel / serial conversion circuit 14 converts a parallel signal that is an output signal from the SOI deletion circuit 13 into a serial signal.

  The serial / parallel conversion circuit 23 converts a serial signal that is an output signal from the equalizer circuit 22 into a parallel signal. The SOI addition circuit 24 adds an SOI signal to the output signal from the serial / parallel conversion circuit 23.

  Hereinafter, the detailed operation of the extending circuit of the present embodiment will be described with reference to FIG. Similar to the first embodiment, the operation when the node 101 is a transmitting node and the node 102 is a receiving node will be described.

  An output signal (10BASE-T signal) from the node 101 is input to the transmission processing unit 1b, and the SOI deletion circuit 13 of the transmission processing unit 1b deletes the SOI signal included in the signal input from the node 101. Specifically, the input 10BASE-T signal is terminated, and the SOI signal is deleted from the 10BASE-T signal to generate an MII (Media Independent Interface) signal. In general, an MII signal in a system that transmits a 10BASE-T signal is a parallel signal that does not include an SOI signal. The SOI deletion circuit 13 further performs framing by inserting a synchronization pattern into the MII signal and outputs the result to the parallel / serial conversion circuit 6.

  The parallel / serial conversion circuit 6 converts the signal output from the SOI deletion circuit 13 from a parallel signal to a serial signal, and then outputs the signal to the amplifier circuit 11. The amplifier circuit 11 amplifies the input signal from the parallel / serial converter circuit 6 and sends it to the transmission line 100.

  The signal sent from the transmission processing unit 1b to the transmission line 100 is input to the reception processing unit 2b, and the equalizer circuit 22 of the reception processing unit 2b equalizes the input signal with a cable and outputs it to the serial / parallel conversion circuit 23. Here, as described above, since the transmission processing unit 1b transmits the signal to the transmission line 100 after deleting the SOI signal by the SOI deletion circuit 13, the transmission processing unit 1b reaches the reception processing unit 2b via the transmission line 100. The signal is a signal including only the main signal (high frequency signal). Therefore, the reception processing unit 2b only needs to correct the occupied frequency band of the main signal. For example, the conventional equalizer circuit (see FIG. 2) shown in the first embodiment can be applied.

  The serial / parallel conversion circuit 23 converts the serial signal input from the equalizer circuit 22 into a parallel signal, and outputs the converted signal to the SOI addition circuit 24. After establishing frame synchronization, the SOI addition circuit 24 identifies a preamble, data, and the like, adds an SOI signal to generate an MDI (Media Dependent Interface) signal, and outputs it to the node 102 as a 10BASE-T signal.

  Details of the SOI deletion circuit 13 will be described. FIG. 7 is a diagram illustrating a configuration example of the SOI deletion circuit 13. The SOI deletion circuit 13 includes a 10BASE-T termination circuit 131, a scramble circuit 132, and a pattern insertion circuit 133.

  In the SOI deletion circuit 13, the output signal (10BASE-T signal) from the node 101 is input to the 10BASE-T termination circuit 131. When a 10BASE-T signal is input, the 10BASE-T termination circuit 131 terminates the signal and generates and outputs an MII signal that is a signal compliant with MII. As the MII signal, a parallel data signal obtained by deleting the SOI signal from the 10BASE-T signal is output. The MII signal is an NRZ signal obtained by decoding the Manchester code implemented by the 10BASE-T signal. Therefore, depending on the data, “0” or “1” data may continue. When considering clock recovery on the receiving side, continuous data of “0” or “1” should be avoided. Therefore, the scramble circuit 132 scrambles and rearranges the output data signal from the 10BASE-T termination circuit 131 so that the same code continuation of data is eliminated (so that the number of places where the same code continues is reduced). The output data (scrambled MII signal) from the scramble circuit 132 is input to the pattern insertion circuit 133. The pattern insertion circuit 133 receives an idle period (interval in which an idle signal is disposed) and an SOI period (SOI) other than the data period. For example, a unique word such as a “01” pattern is inserted into a section where the signal is arranged so that frame synchronization can be easily performed on the receiving side. Further, by making the occupied frequency band of these sections the same as the occupied frequency band of the main signal, the main signal and the unique word that have reached the receiving side are set to the same level (normal communication is realized).

  Next, details of the SOI addition circuit 24 will be described. FIG. 8 is a diagram illustrating a configuration example of the SOI addition circuit 24, and the SOI addition circuit 24 includes a frame synchronization circuit 241, a descrambling circuit 242, and a 10BASE-T generation circuit 243.

  In the SOI addition circuit 24, the frame synchronization circuit 241 receives the signal output from the serial / parallel conversion circuit 23 in the previous stage, and the unique word included in the signal, that is, the SOI deletion circuit included in the transmission processing unit 1b. The unique pattern, the preamble pattern, and the like input by the 13 pattern insertion circuits 133 are detected to establish frame synchronization. The descrambling circuit 242 detects a data interval based on the synchronization establishment result in the frame synchronization circuit 241, and further performs processing (decoding) opposite to the scramble processing (rearrangement) performed by the scramble circuit 132 of the SOI deletion circuit 13. Scramble processing) to return each data to the original order. As a result, the MII signal output from the 10BASE-T termination circuit 131 of the SOI deletion circuit 13 is restored. The 10BASE-T generation circuit 243 performs Manchester code conversion, addition of an SOI signal, and the like on the MII signal output from the descrambling circuit 242 according to the specification of the 10BASE-T signal, and generates a 10BASE-T signal.

  As described above, in the extension circuit of the present embodiment, the transmission processing unit amplifies after deleting the low frequency and known signal (corresponding to the SOI signal) included in the output signal from the transmission side node. The reception processing unit restores the signal output from the node on the transmission side by adding the signal (SOI signal) deleted by the transmission processing unit to the reception signal from the transmission channel. Output to the node. Thereby, the communication quality in the case of transmitting a signal over a long distance can be improved similarly to the extension circuit shown in the previous embodiment. Further, since the signal sent to the transmission line is only the main signal and the occupied frequency band is limited, a general equalizer circuit can be applied.

Embodiment 4 FIG.
FIG. 9 is a diagram illustrating a configuration example of the extending circuit according to the fourth embodiment. In FIG. 9, the same components as those of the extending circuit of the first embodiment (see FIG. 1) are denoted by the same reference numerals. In the present embodiment, description of the same components as those in Embodiment 1 is omitted.

  As illustrated, the extending circuit of the present embodiment includes a transmission processing unit 1c and a reception processing unit 2c. The transmission processing unit 1c includes an amplification circuit 11, and an SOI and idle detection circuit 15 and a pattern insertion circuit 16 arranged in the preceding stage. The reception processing unit 2c includes an equalizer circuit 22 and a frame arranged in the subsequent stage. Synchronizing circuit 25, SOI and idle adding circuit 26 are included.

  The SOI and idle detection circuit 15 receives a signal (10BASE-T signal) output from the node 101 and detects an SOI interval and an idle interval included therein. The pattern insertion circuit 16 inserts a unique word into the section (SOI section, idle section) detected by the SOI and idle detection circuit 15.

  The frame synchronization circuit 25 establishes frame synchronization of the received signal. SOI and idle addition circuit 26 inserts an SOI signal and an idle signal into the input signal.

  Hereinafter, the detailed operation of the extending circuit of the present embodiment will be described with reference to FIG. Similar to the first embodiment, the operation when the node 101 is a transmitting node and the node 102 is a receiving node will be described.

  An output signal (10BASE-T signal) from the node 101 is input to the transmission processing unit 1c, and the SOI and idle detection circuit 15 of the transmission processing unit 1c has an SOI section (SOI signal disposed) of the signal input from the node 101. ) And idle sections (sections where idle signals are arranged) are detected. The pattern insertion circuit 16 inserts a unique word such as a “01” pattern by applying an analog adder / subtractor or the like to the SOI section and the idle section indicated by the detection result in accordance with the detection result in the SOI and idle detection circuit 15. To do. That is, the SOI signal and the idle signal included in the signal output from the node 101 are replaced with a unique word. Note that the occupied frequency bands in the SOI section and the idle section are set to be the same as the occupied frequency band of the main signal. The amplifier circuit 11 amplifies the input signal from the pattern insertion circuit 16 and sends it to the transmission line 100.

  The signal sent from the transmission processing unit 1c to the transmission line 100 is input to the reception processing unit 2c, and the equalizer circuit 22 of the reception processing unit 2c equalizes the input signal with a cable and outputs the signal to the frame synchronization circuit 25. Here, as described above, the transmission processing unit 1c replaces the SOI signal (SOI section) with a unique word in the pattern insertion circuit 16, and the occupied frequency band in this section becomes the same as the occupied frequency band of the main signal. Therefore, the reception processing unit 2c only needs to correct the occupied frequency band of the main signal. For example, the conventional equalizer circuit (see FIG. 2) shown in the first embodiment can be applied.

  The frame synchronization circuit 25 detects a unique word included in the input signal from the equalizer circuit 22 and establishes frame synchronization. The SOI and idle addition circuit 26 detects an SOI interval and an idle interval based on the synchronization establishment result in the frame synchronization circuit 25, further inserts an SOI signal in the SOI interval, inserts an idle signal in the idle interval, The 10BASE-T signal output from the node 101 on the transmission side is restored. The restored 10BASE-T signal is output to the node 102.

  As described above, in the extension circuit of the present embodiment, the transmission processing unit outputs a low-frequency and known signal (corresponding to an SOI signal) and an idle signal included in the output signal from the transmission-side node. After replacing with a unique word of the same occupied frequency band as the signal, it is amplified and transmitted to the transmission line, and the reception processing unit replaces the unique word replaced with the transmission processing unit with the original signal (SOI signal and idle signal). Thus, the signal output from the transmitting node is restored and output to the receiving node. Thereby, the communication quality in the case of transmitting a signal over a long distance can be improved similarly to the extension circuit shown in the previous embodiment. Since the signal sent to the transmission line is a main signal and a unique word in the same occupied frequency band, and the occupied frequency band is limited, a general equalizer circuit is used as in the extension circuit of the third embodiment. Applicable.

  In each of the embodiments described above, the case where the 10BAST-T signal is transmitted has been described. However, the extension circuit shown in each embodiment has a signal that is the same as the 10BASE-T signal, that is, the frequency band is greatly different. The present invention can be applied to any system that transmits a signal composed of a plurality of types of components (signals).

  As described above, the baseband signal extending circuit according to the present invention is useful for long-distance data transmission, and in particular, a communication system for transmitting signals including a plurality of types of components having greatly different frequency bands through a wired transmission line. This is suitable for extending the non-relay transmission distance.

1, 1a, 1b, 1c Transmission processing unit 2, 2a, 2b, 2c Reception processing unit 11 Amplification circuit 12, 21 SOI suppression circuit 13 SOI deletion circuit 14 Parallel / serial conversion circuit 15 SOI and idle detection circuit 16, 133 Pattern insertion Circuit 22 Equalizer circuit 23 Serial / parallel conversion circuit 24 SOI addition circuit 25, 241 Frame synchronization circuit 26 SOI and idle addition circuit 31, 32, 33, 34, 42 Resistor 35, 41 Capacitor 36 Coil 100 Transmission path 101, 102 Node 131 10BASE-T termination circuit 132 scramble circuit 242 descrambling circuit 243 10BASE-T generation circuit

Claims (12)

A baseband signal extension circuit applied to a communication system in which a signal transmission side node and a reception side node are connected via a wired transmission line,
Transmission processing means for amplifying a signal output from a transmission node which is the transmission side node and sending it to a transmission line;
When a signal sent to the transmission path is received and the received signal includes two or more components having different frequency bands, the level of each signal component is suppressed by an attenuation amount corresponding to the frequency band, and Receiving processing means for outputting to the receiving node which is a node on the receiving side, after performing compensation processing according to the frequency characteristics of the transmission path for the received signal after the suppression,
A baseband signal extending circuit comprising: a baseband signal extending circuit; A signal output from the transmission node is a 10BASE-T signal,
The reception processing means includes
An SOI suppression circuit for suppressing an SOI signal included in the received 10BASE-T signal;
An equalizer circuit that performs compensation processing according to the frequency characteristics of the transmission path on the 10BASE-T signal after the SOI signal is suppressed;
The baseband signal extending circuit according to claim 1, further comprising: The baseband signal extension circuit according to claim 2, wherein the SOI suppression circuit suppresses the SOI signal so as to be at the same level as a main signal included in the received 10BASE-T signal. A baseband signal extension circuit applied to a communication system in which a signal transmission side node and a reception side node are connected via a wired transmission line,
When the signal output from the transmission node which is the transmission-side node is amplified, and the amplified signal includes two or more components having different frequency bands, each of the signals included in the amplified signal Transmission processing means for suppressing the level of the signal component with an attenuation amount corresponding to the frequency band and sending it to the transmission line;
A reception processing means for receiving a signal sent to the transmission path, performing a compensation process according to the frequency characteristic of the transmission path on the received signal, and outputting the received signal to a reception node that is a node on the reception side;
A baseband signal extending circuit comprising: a baseband signal extending circuit; A signal output from the transmission node is a 10BASE-T signal,
The transmission processing means includes
An amplification circuit for amplifying the 10BASE-T signal output from the transmission node;
An SOI suppression circuit for suppressing an SOI signal included in the amplified signal;
The baseband signal extending circuit according to claim 4, further comprising: The said SOI suppression circuit suppresses the SOI signal contained in the said amplified signal so that the main signal and SOI signal contained in the signal which the said receiving node receives may become the same level. A baseband signal stretching circuit as described. 7. The baseband signal according to claim 2, wherein the SOI suppression circuit suppresses the SOI signal with an attenuation amount based on a frequency characteristic of the transmission line and a frequency characteristic of the equalizer circuit. Drawing circuit. The baseband signal extending circuit according to claim 2, 3, 5, 6, or 7, wherein the SOI suppression circuit is configured by an integrating circuit. A baseband signal extending circuit applied to a communication system for transmitting a 10BASE-T signal,
Of the SOI signal and main signal included in the output signal from the transmission node that is the node on the signal transmission side, the SOI signal is replaced with a signal in the same frequency band as the main signal, and the signal after execution of the replacement processing is amplified. Transmission processing means for sending to the transmission line,
After receiving the signal sent to the transmission line and performing compensation processing according to the frequency characteristic of the transmission line on the received signal, the signal replaced by the transmission processing means is replaced with an SOI signal. A reception processing means for outputting to a receiving node which is a receiving side node;
A baseband signal extending circuit comprising: a baseband signal extending circuit; The transmission processing means includes
An SOI deletion circuit for generating an MII (Media Independent Interface) signal by deleting an SOI signal included in an output signal from the transmission node, and further adding a signal in the same frequency band as the main signal;
A parallel / serial conversion circuit that converts an output signal from the SOI deletion circuit, which is a parallel signal, into a serial signal;
An amplifier circuit for amplifying an output signal from the parallel / serial converter circuit;
With
The reception processing means includes
An equalizer circuit that performs compensation processing according to frequency characteristics of the transmission path on the received signal;
A serial / parallel conversion circuit for converting an output signal from the equalizer circuit into a parallel signal;
Of the signal components included in the output signal from the serial / parallel conversion circuit, an SOI addition circuit that replaces the signal added by the SOI deletion circuit with an SOI signal;
The baseband signal extending circuit according to claim 9, further comprising: The SOI deletion circuit includes:
A 10BASE-T termination circuit for removing the SOI signal from the output signal from the transmission node;
A scramble circuit that scrambles the output signal from the 10BASE-T termination circuit;
A pattern insertion circuit for adding a fixed pattern signal in the same frequency band as the main signal to the output signal from the scramble circuit;
With
The SOI addition circuit includes:
A frame synchronization circuit for establishing frame synchronization of a signal output from the serial / parallel conversion circuit;
A descrambling circuit for descrambling the signal after frame synchronization is established;
An SOI addition circuit for adding an SOI signal to an output signal from the descrambling circuit;
The baseband signal extending circuit according to claim 10, further comprising: The transmission processing means includes
An SOI and idle detection circuit for detecting an arrangement section of an SOI signal and an idle signal included in an output signal from the transmission node;
A pattern insertion circuit that replaces the signal of the detected section with a fixed pattern signal in the same frequency band as the main signal;
An amplifier circuit for amplifying an output signal from the pattern insertion circuit;
With
The reception processing means includes
An equalizer circuit that performs compensation processing according to frequency characteristics of the transmission path on the received signal;
A frame synchronization circuit for establishing frame synchronization of the signal output from the equalizer circuit;
An SOI and idle addition circuit for adding an SOI signal and an idle signal to a signal after frame synchronization is established;
The baseband signal extending circuit according to claim 9, further comprising:

Images