JP5384843B2 - Method for manufacturing piezoelectric element structure and piezoelectric element structure - Google Patents

Method for manufacturing piezoelectric element structure and piezoelectric element structure Download PDF

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JP5384843B2
JP5384843B2 JP2008070921A JP2008070921A JP5384843B2 JP 5384843 B2 JP5384843 B2 JP 5384843B2 JP 2008070921 A JP2008070921 A JP 2008070921A JP 2008070921 A JP2008070921 A JP 2008070921A JP 5384843 B2 JP5384843 B2 JP 5384843B2
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靖和 二瓶
竜児 塚本
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本発明は、基板上に複数の圧電素子を備えてなる圧電素子構造体の製造方法および圧電素子構造体に関するものである。   The present invention relates to a method for manufacturing a piezoelectric element structure including a plurality of piezoelectric elements on a substrate, and a piezoelectric element structure.

電界印加強度の増減に伴って伸縮する圧電性を有する圧電体と、圧電体に対して所定方向に電界を印加する電極とを備えた圧電素子が、インクジェット式記録ヘッドに搭載されるアクチュエータ等として使用されている。   A piezoelectric element including a piezoelectric body having piezoelectricity that expands and contracts as the electric field application intensity increases and decreases and an electrode that applies an electric field to the piezoelectric body in a predetermined direction is used as an actuator mounted on an ink jet recording head. It is used.

圧電体材料としては、チタン酸ジルコン酸鉛(PZT)等のペロブスカイト構造を有する複合酸化物が知られている。かかる材料は電界無印加時において自発分極性を有する強誘電体であり、従来の圧電素子では、強誘電体の分極軸に合わせた方向に電界を印加することで、分極軸方向に伸びる「圧電効果」を利用することが一般的である。   As a piezoelectric material, a composite oxide having a perovskite structure such as lead zirconate titanate (PZT) is known. Such a material is a ferroelectric material having spontaneous polarization when no electric field is applied. In a conventional piezoelectric element, by applying an electric field in a direction corresponding to the polarization axis of the ferroelectric material, the piezoelectric material extends in the direction of the polarization axis. It is common to use “effect”.

圧電体の自発分極を電界印加方向と一致させるため、従来、圧電体に対して分極処理が施されている。分極処理としては、圧電体の上下に電極を形成し、その電極間に電界を印加する方法が一般的である。   In order to make the spontaneous polarization of the piezoelectric body coincide with the electric field application direction, the piezoelectric body has been conventionally subjected to polarization treatment. As the polarization treatment, a method of forming electrodes on the upper and lower sides of a piezoelectric body and applying an electric field between the electrodes is generally used.

また、特許文献1には、分極処理とともに圧電体の耐熱性を向上させるため、圧電体に互いに逆向きの電界を交互に印加して分極を行う方法が提案されている。   Patent Document 1 proposes a method of performing polarization by alternately applying electric fields in opposite directions to the piezoelectric body in order to improve the heat resistance of the piezoelectric body together with the polarization treatment.

一方、圧電素子として、基板上にスパッタ法により成膜された圧電体膜を備えたものが知られており、スパッタ法により成膜された圧電体膜は、分極処理を行うことなく、成膜直後の状態で基板側から膜表面に向かう自発分極を有するものとなる(図3参照)ことが知られている。   On the other hand, a piezoelectric element having a piezoelectric film formed on a substrate by sputtering is known, and the piezoelectric film formed by sputtering is formed without performing polarization treatment. It is known that it has spontaneous polarization from the substrate side to the film surface in the state immediately after (see FIG. 3).

基板上にスパッタ法により成膜される圧電体膜を圧電素子として利用する場合、予め下部電極層が形成された基板上に、圧電体膜を成膜し、圧電体膜上に上部電極層を形成する。このような、基板側から膜表面に向かう(下部電極層側から上部電極層側に向かう)自発分極を有する圧電体膜を備えた圧電素子構造体を実用化する場合、駆動時の電界の向きを自発分極の向きと一致させるために、上部電極を下部電極より高い電位とする必要がある。したがって、(1)上部電極側を接地電位とし、下部電極側をアドレス電極として正電位とする、あるいは、(2)下部電極側を接地電位とし、上部電極側をアドレス電極として負電位として駆動させる必要がある。(1)の場合、基板側の電極である下部電極を個別電極とする必要があり、(2)の場合、負電圧用の駆動ICが必要となる。
特開2007−258597号公報
When a piezoelectric film formed by sputtering on a substrate is used as a piezoelectric element, a piezoelectric film is formed on a substrate on which a lower electrode layer has been formed in advance, and an upper electrode layer is formed on the piezoelectric film. Form. When a piezoelectric element structure having a piezoelectric film having spontaneous polarization from the substrate side toward the film surface (from the lower electrode layer side to the upper electrode layer side) is put into practical use, the direction of the electric field during driving In order to match the direction of spontaneous polarization, the upper electrode needs to have a higher potential than the lower electrode. Therefore, (1) the upper electrode side is set as a ground potential and the lower electrode side is set as a positive potential using the address electrode, or (2) the lower electrode side is set as the ground potential and the upper electrode side is driven as the negative potential using the address electrode. There is a need. In the case of (1), the lower electrode, which is an electrode on the substrate side, needs to be an individual electrode, and in the case of (2), a driving IC for negative voltage is required.
JP 2007-258597 A

しかしながら、下部電極の個別電極とする場合、製造プロセスが複雑になるという問題があり、負電圧駆動を行うための負電圧駆動用ICは正電圧駆動用ICと比較してサイズが大きく、負電圧駆動用ICを備えるためにこれを備える装置全体のサイズが大きくなってしまう、また1枚のウェハから製造可能な素子数をICサイズに合わせて減らす必要が生じること、さらには、負電圧駆動用IC自体も正電圧用と比較して高価であることからコスト高となるという問題がある。   However, when the lower electrode is an individual electrode, there is a problem that the manufacturing process is complicated, and the negative voltage driving IC for performing negative voltage driving is larger in size than the positive voltage driving IC, and thus the negative voltage driving IC is negative. Since the drive IC is provided, the size of the entire apparatus including the drive IC is increased, the number of elements that can be manufactured from one wafer needs to be reduced according to the IC size, and further, for the negative voltage drive. Since the IC itself is more expensive than the positive voltage, there is a problem that the cost is increased.

そこで、下部電極層を素子毎の個別電極とはせず、複数の素子で共通のベタ電極とし、かつ、正電圧駆動ドライバICを利用可能とすることが望まれる。そのためには、圧電体膜の自発分極を反転さればよい。この自発分極を反転させるための反転分極処理としては、従来の分極処理と同様に、圧電体を挟む上下電極間に電圧を印加して行う方法を適用することが考えられる。また、圧電素子構造体において、複数の圧電素子の圧電体膜の自発分極の反転分極は一括して分極を行うことが望ましく、その場合、各圧電体膜の電極間にそれぞれ電圧を印加して多数の素子の圧電体膜について一括分極反転を行うこととなる。   Therefore, it is desired that the lower electrode layer is not a separate electrode for each element, but a solid electrode common to a plurality of elements and a positive voltage driver IC can be used. For this purpose, the spontaneous polarization of the piezoelectric film may be reversed. As the reversal polarization process for reversing the spontaneous polarization, it is conceivable to apply a method in which a voltage is applied between the upper and lower electrodes sandwiching the piezoelectric body, similarly to the conventional polarization process. In addition, in the piezoelectric element structure, it is desirable that the reversal polarization of the spontaneous polarization of the piezoelectric films of a plurality of piezoelectric elements is performed in a lump. In this case, a voltage is applied between the electrodes of each piezoelectric film. The collective polarization inversion is performed on the piezoelectric films of a large number of elements.

しかしながら、本発明者らの実験によれば、圧電素子構造体に対して、上述の一括分極反転処理を施した場合、電圧印加時の膜破壊による素子欠陥率は15−30%程度と非常に高く、現実的には実用化できないという問題が生じた。   However, according to the experiments by the present inventors, when the above-described collective polarization reversal process is performed on the piezoelectric element structure, the element defect rate due to film breakdown at the time of voltage application is as high as about 15-30%. The problem was that it was expensive and could not be practically used.

一般に、電圧印加時における膜破壊は、電圧印加時に組成欠陥や構造欠陥など相対的に抵抗が低い部分、もしくは表面欠損部や気孔部など形状的に電荷がたまりやすい部分をトリガーとして始まることが知られている。圧電体膜に連続的に電界を印加し続けると、トリガー部分の電荷集中箇所において発熱が生じ、局所的に温度が高くなる。この局所的に温度が高くなった部分において、急激に抵抗が下がることにより、電荷集中による破壊に至ると考えられる。   In general, it is known that film breakdown at the time of voltage application starts with a part having relatively low resistance such as a composition defect or a structural defect, or a part where charge tends to be accumulated, such as surface defects or pores, at the time of voltage application. It has been. If an electric field is continuously applied to the piezoelectric film, heat is generated at the charge concentration portion of the trigger portion, and the temperature locally increases. It is considered that the breakdown due to the charge concentration is caused by the sudden drop in resistance at the part where the temperature is locally increased.

圧電素子構造体の分極処理においては、複数の素子に共通のベタ電極である下部電極と、素子毎に設けられる上部電極との間に、一括して電圧を印加する。全電荷量は電極面積が大きくなればなるほど大きくなるものであり、複数の素子に対して一括して電圧を印加するためにトータル電極面積が大きくなり、電荷集中による破壊が生じやすくなる。このため、複数の素子を均一に反転させることが難しく、欠陥率が非常に高く、実用化が困難であった。   In the polarization processing of the piezoelectric element structure, a voltage is collectively applied between a lower electrode that is a solid electrode common to a plurality of elements and an upper electrode provided for each element. The total amount of charges increases as the electrode area increases. Since the voltage is applied to a plurality of elements at once, the total electrode area increases, and breakdown due to charge concentration tends to occur. For this reason, it is difficult to invert a plurality of elements uniformly, the defect rate is very high, and practical application is difficult.

本発明は、上記事情を鑑みてなされたものであり、多数の圧電素子を備えた圧電素子構造体において、圧電体膜の自発分極の向きが上部電極層側から下部電極層側に向かう向きである、実用化可能な圧電素子構造体の製造方法を提供することを目的とするものである。   The present invention has been made in view of the above circumstances, and in a piezoelectric element structure including a large number of piezoelectric elements, the direction of spontaneous polarization of the piezoelectric film is directed from the upper electrode layer side to the lower electrode layer side. An object of the present invention is to provide a method for manufacturing a practical piezoelectric element structure.

本発明の圧電素子構造体の製造方法は、基板上に、下部電極層、圧電体膜および上部電極層がこの順に積層されてなる多数の圧電素子を備えた圧電素子構造体を製造する圧電素子構造体の製造方法において、
前記圧電体膜をスパッタ法により成膜し、
該成膜により自発分極が前記下部電極層から前記上部電極層に向かう向きとなっている圧電体膜に対し、該圧電体膜の抗電界以上の大きさの、前記上部電極層から前記下部電極層に向かう電界をパルス印加することを特徴とする。
The method for manufacturing a piezoelectric element structure of the present invention includes a piezoelectric element for manufacturing a piezoelectric element structure including a plurality of piezoelectric elements in which a lower electrode layer, a piezoelectric film, and an upper electrode layer are laminated in this order on a substrate. In the manufacturing method of the structure,
The piezoelectric film is formed by sputtering,
With respect to the piezoelectric film in which spontaneous polarization is directed from the lower electrode layer toward the upper electrode layer by the film formation, the upper electrode layer has a magnitude greater than the coercive electric field of the piezoelectric film and the lower electrode. It is characterized by applying a pulse of an electric field directed to the layer.

前記圧電体膜が、少なくともPbを含むペロブスカイト型酸化物であることが望ましい。   The piezoelectric film is preferably a perovskite oxide containing at least Pb.

なお、前記電界のパルス印加における電圧印加時間Aと、非電圧印加時間Bとの比B/Aが1以上であることが望ましく、さらには、比B/Aが10以上であることが望ましい。   Note that the ratio B / A between the voltage application time A and the non-voltage application time B in the pulse application of the electric field is preferably 1 or more, and more preferably, the ratio B / A is 10 or more.

本発明の圧電素子構造体は、基板上に、下部電極層、スパッタ法により成膜された圧電体膜及び上部電極層がこの順に積層されてなる多数の圧電素子を備えた圧電素子構造体であって、
該圧電素子構造体における圧電素子の欠陥率が1%以下であり、
前記圧電体膜の自発分極が前記上部電極層から前記下部電極層に向かう向きであることを特徴とする。
The piezoelectric element structure of the present invention is a piezoelectric element structure including a plurality of piezoelectric elements in which a lower electrode layer, a piezoelectric film formed by sputtering and an upper electrode layer are laminated in this order on a substrate. There,
The defect rate of the piezoelectric element in the piezoelectric element structure is 1% or less,
The spontaneous polarization of the piezoelectric film is directed from the upper electrode layer toward the lower electrode layer.

ここで、欠陥率は、欠陥が生じた圧電素子数/圧電素子構造体に設けられた全圧電素子数(=欠陥が生じた上部電極チャンネル数/素子全体の上部電極チャンネル数)である。   Here, the defect rate is the number of piezoelectric elements in which a defect has occurred / the total number of piezoelectric elements provided in the piezoelectric element structure (= the number of upper electrode channels in which a defect has occurred / the number of upper electrode channels in the entire element).

前記圧電体膜が、少なくともPbを含むペロブスカイト型酸化物であることが望ましい。   The piezoelectric film is preferably a perovskite oxide containing at least Pb.

本発明の圧電素子構造体の製造方法によれば、圧電体膜をスパッタ法により成膜し、該成膜により自発分極が下部電極層から上部電極層に向かう向きとなっている圧電体膜に対し、該圧電体膜の抗電界以上の大きさの、上部電極層から下部電極層に向かう電界をパルス印加するので、周期的に冷却時間がとられるため、発熱を抑制することができ、従来、分極時の電圧印加に伴う発熱により破壊されていた圧電体膜の破壊を抑制し、連続電界印加による分極方法を用いる場合と比較して、クラックやボイドといった圧電素子の欠陥率を抑制することができ、実用化可能な圧電素子構造体を得ることができる。   According to the method for manufacturing a piezoelectric element structure of the present invention, a piezoelectric film is formed by sputtering, and the spontaneous polarization is directed to the upper electrode layer from the lower electrode layer by the film formation. On the other hand, since the electric field directed from the upper electrode layer to the lower electrode layer is applied with a pulse having a magnitude greater than the coercive electric field of the piezoelectric film, the cooling time can be taken periodically, so that heat generation can be suppressed. This suppresses the destruction of the piezoelectric film that has been destroyed by the heat generated by voltage application during polarization, and suppresses the defect rate of piezoelectric elements such as cracks and voids compared to the case of using the polarization method by applying a continuous electric field. Thus, a piezoelectric element structure that can be put to practical use can be obtained.

本発明の圧電素子構造体は、基板上に、下部電極層、スパッタ法により成膜された圧電体膜及び上部電極層がこの順に積層されてなる多数の圧電素子を備えた圧電素子構造体であって、圧電素子の欠陥率が1%以下であり、圧電体膜の自発分極が上部電極層から下部電極層に向かう向きであることから、圧電アクチュエータなどの実用用途に有効である。   The piezoelectric element structure of the present invention is a piezoelectric element structure including a plurality of piezoelectric elements in which a lower electrode layer, a piezoelectric film formed by sputtering and an upper electrode layer are laminated in this order on a substrate. Since the defect rate of the piezoelectric element is 1% or less and the spontaneous polarization of the piezoelectric film is directed from the upper electrode layer toward the lower electrode layer, it is effective for practical use such as a piezoelectric actuator.

以下、図面を参照して本発明の実施の形態について説明する。
本発明の実施形態にかかる圧電素子構造体の製造方法および圧電素子構造体を図1〜4を参照して説明する。図1は本発明の製造方法により得られる圧電素子構造体1の概略平面図、図2は本発明の製造方法により得られる圧電素子構造体1の要部断面図、図3は圧電体膜成膜直後の圧電素子構造体の要部断面図、図4は分極処理の際の印加電圧パルス波形を示す図である。なお、視認しやすくするため、構成要素の縮尺は実際のものとは適宜異ならせてある。
Embodiments of the present invention will be described below with reference to the drawings.
A method for manufacturing a piezoelectric element structure and a piezoelectric element structure according to an embodiment of the present invention will be described with reference to FIGS. 1 is a schematic plan view of a piezoelectric element structure 1 obtained by the manufacturing method of the present invention, FIG. 2 is a cross-sectional view of the main part of the piezoelectric element structure 1 obtained by the manufacturing method of the present invention, and FIG. FIG. 4 is a cross-sectional view of the main part of the piezoelectric element structure immediately after the film, and FIG. In addition, in order to make it easy to visually recognize, the scale of the component is appropriately changed from the actual one.

「圧電素子構造体」
まず、本実施形態の製造方法により得られる圧電素子構造体の構成について説明する。図1および図2に示すように、圧電素子構造体1は、基板11上に複数の圧電素子2を備えてなる。本実施形態においては、基板11は複数のダイアフラム構造が形成されてなる構造体であり、各ダイアフラム12上にそれぞれ圧電素子2が設けられている。圧電素子2は、下部電極層22、スパッタ法により成膜された圧電体膜23、上部電極層24が基板11上に順次積層された素子であり、上部電極と下部電極とにより厚み方向に電界が印加されるようになっている。
"Piezoelectric element structure"
First, the structure of the piezoelectric element structure obtained by the manufacturing method of this embodiment will be described. As shown in FIGS. 1 and 2, the piezoelectric element structure 1 includes a plurality of piezoelectric elements 2 on a substrate 11. In the present embodiment, the substrate 11 is a structure in which a plurality of diaphragm structures are formed, and the piezoelectric element 2 is provided on each diaphragm 12. The piezoelectric element 2 is an element in which a lower electrode layer 22, a piezoelectric film 23 formed by a sputtering method, and an upper electrode layer 24 are sequentially stacked on the substrate 11, and an electric field is formed in the thickness direction by the upper electrode and the lower electrode. Is applied.

下部電極層22は基板の略全面に形成されており複数の圧電素子2の共通電極となっており、圧電体膜、上部電極層が各ダイアフラム12に応じた分離パターン状に構成されている。なお、圧電体膜は連続膜でもよいが、互いに分離する構成とすることで、個々の素子における伸縮がスムーズに起こるので、より大きな変位量が得られ好ましい。   The lower electrode layer 22 is formed on substantially the entire surface of the substrate and serves as a common electrode for the plurality of piezoelectric elements 2, and the piezoelectric film and the upper electrode layer are configured in a separation pattern corresponding to each diaphragm 12. Although the piezoelectric film may be a continuous film, it is preferable that the piezoelectric element film be separated from each other because the expansion and contraction of each element occurs smoothly.

また、圧電体膜が個々の素子毎に分離されている場合、圧電体膜上に設けられる上部電極層は、圧電体膜の表面において中央部に圧電体膜より小さめに形成することが好ましい。圧電体膜が非常に薄くなってくると、上部電極、下部電極の間隔が小さく圧電体膜両端からリークが生じる恐れがあるためである。ただし、構造体の製造上は圧電体膜と上部電極層の大きさは略一致したものとする方が工程を簡素化できる。   In addition, when the piezoelectric film is separated for each element, it is preferable that the upper electrode layer provided on the piezoelectric film is formed to be smaller than the piezoelectric film at the center of the surface of the piezoelectric film. This is because when the piezoelectric film becomes very thin, the distance between the upper electrode and the lower electrode is small, and there is a risk of leakage from both ends of the piezoelectric film. However, in manufacturing the structure, the process can be simplified if the sizes of the piezoelectric film and the upper electrode layer are substantially the same.

この圧電素子構造体1における圧電素子の圧電体膜23の自発分極dpの向きは、上部電極層24から下部電極層22に向かう向きであり、素子欠陥率は好ましくは1%以下である。   The direction of the spontaneous polarization dp of the piezoelectric film 23 of the piezoelectric element in the piezoelectric element structure 1 is the direction from the upper electrode layer 24 to the lower electrode layer 22, and the element defect rate is preferably 1% or less.

基板11としては、熱伝導率、加工性が良いことからシリコン基板が好ましく、特には、シリコン基板上にSiO膜とSi活性層とが順次積層されたSOI基板等の積層基板が好適に用いられる。また、振動板12と下部電極層22との間に、格子整合性を良好にするためのバッファ層や、電極と基板との密着性を良好にするための密着層等を設けても構わない。 As the substrate 11, a silicon substrate is preferable because of its good thermal conductivity and workability. In particular, a stacked substrate such as an SOI substrate in which a SiO 2 film and a Si active layer are sequentially stacked on a silicon substrate is preferably used. It is done. Further, a buffer layer for improving the lattice matching, an adhesion layer for improving the adhesion between the electrode and the substrate, or the like may be provided between the diaphragm 12 and the lower electrode layer 22. .

振動板は基板11の一部を加工したものに限るものではなく、基板とは別体とし、基板と貼り合わせてもよい。基板と振動板とを別体で構成する場合には、基板としては、シリコンのみならず,ガラス,ステンレス(SUS),イットリウム安定化ジルコニア(YSZ),アルミナ,サファイヤ,及びシリコンカーバイド等を用いることができる。   The diaphragm is not limited to a part of the substrate 11 processed, and may be separated from the substrate and bonded to the substrate. When the substrate and the diaphragm are configured separately, not only silicon but also glass, stainless steel (SUS), yttrium stabilized zirconia (YSZ), alumina, sapphire, silicon carbide, etc. should be used as the substrate. Can do.

下部電極層22の主成分としては、特に制限なく、Ir、Au,Pt,IrO,RuO,LaNiO,及びSrRuO等の金属又は金属酸化物、及びこれらの組合せが挙げられる。下部電極層22と上部電極層24の厚みは特に制限なく、50〜500nmであることが好ましい。 The main component of the lower electrode layer 22 is not particularly limited and includes metals or metal oxides such as Ir, Au, Pt, IrO 2 , RuO 2 , LaNiO 3 , and SrRuO 3 , and combinations thereof. The thicknesses of the lower electrode layer 22 and the upper electrode layer 24 are not particularly limited and are preferably 50 to 500 nm.

上部電極層24の主成分としては、特に制限なく、下部電極層22で例示した材料、Al,Ta,Cr,及びCu等の一般的に半導体プロセスで用いられている電極材料、及びこれらの組合せが挙げられる。   The main component of the upper electrode layer 24 is not particularly limited, and the materials exemplified in the lower electrode layer 22, electrode materials generally used in semiconductor processes such as Al, Ta, Cr, and Cu, and combinations thereof Is mentioned.

圧電体膜23の膜厚は特に制限なく、通常1μm以上であり、例えば1〜10μmである。   The film thickness of the piezoelectric film 23 is not particularly limited, and is usually 1 μm or more, for example, 1 to 10 μm.

「圧電素子構造体の製造方法」
次に、上記圧電素子構造体1を製造する本実施形態の圧電素子構造体の製造方法を説明する。
複数のダイアフラム構造が形成されてなる基板11を用意し、該基板11上に下部電極層22を形成する。必要に応じて、下部電極層22を成膜する前に、バッファ層や密着層を成膜してもよい。その後、下部電極層22上に圧電体膜23をスパッタ法により成膜し、圧電体膜23上に上部電極層24を成膜する。上部電極層24と圧電体膜23とをエッチングしてダイアフラム構造に対応させて分離させ、複数の圧電素子を備えた圧電素子構造体とする。
"Method for manufacturing piezoelectric element structure"
Next, a method for manufacturing the piezoelectric element structure according to this embodiment for manufacturing the piezoelectric element structure 1 will be described.
A substrate 11 formed with a plurality of diaphragm structures is prepared, and a lower electrode layer 22 is formed on the substrate 11. If necessary, a buffer layer or an adhesion layer may be formed before the lower electrode layer 22 is formed. Thereafter, the piezoelectric film 23 is formed on the lower electrode layer 22 by sputtering, and the upper electrode layer 24 is formed on the piezoelectric film 23. The upper electrode layer 24 and the piezoelectric film 23 are etched and separated so as to correspond to the diaphragm structure, thereby obtaining a piezoelectric element structure including a plurality of piezoelectric elements.

図3に示すように、分極処理を施していない成膜後の圧電体膜23は、その分極dpの向きが、下部電極から上部電極に向かう向きとなっている。この圧電体膜23に対してパルス電界を印加することにより分極dpの向きを反転させる反転分極処理を行う。   As shown in FIG. 3, the direction of the polarization dp of the piezoelectric film 23 that has not been subjected to the polarization treatment is directed from the lower electrode to the upper electrode. An inversion polarization process for inverting the direction of the polarization dp by applying a pulse electric field to the piezoelectric film 23 is performed.

圧電体膜23の下部電極を接地させ、各上部電極を正電位として、上下電極間に上部電極から下部電極に向かう向きの電界をパルス印加する。電圧の大きさは圧電体膜23の抗電界以上の電界が圧電体膜23に印加される大きさとする。電圧保持時間は1分〜30分程度とし、パルス周波数(パルスの周期)に特に制限はないが、例えば、0.1kHz〜1MHz程度とする。分極反転時の圧電体膜23の温度は室温〜100℃程度とし、室温より高い温度で分極させる場合は、予め膜の温度を昇温させた後に電界を印加することが望ましい。膜の温度を昇温させると膜の抗電界が小さくなるため、室温時よりも小さい電圧で分極の反転が可能となる。ただし、膜の温度がキュリー点に近づくと、急激な抵抗の減少に伴う暗電流の増加が生じるため、膜の温度は室温〜100℃程度の範囲でキュリー点より十分に低い温度とすることが望ましい。   The lower electrode of the piezoelectric film 23 is grounded, each upper electrode is set to a positive potential, and an electric field in a direction from the upper electrode to the lower electrode is applied between the upper and lower electrodes. The magnitude of the voltage is such that an electric field equal to or greater than the coercive electric field of the piezoelectric film 23 is applied to the piezoelectric film 23. The voltage holding time is about 1 to 30 minutes, and the pulse frequency (pulse period) is not particularly limited, but is about 0.1 kHz to 1 MHz, for example. The temperature of the piezoelectric film 23 at the time of polarization reversal is about room temperature to 100 ° C. When polarization is performed at a temperature higher than room temperature, it is desirable to apply the electric field after the temperature of the film has been raised in advance. When the temperature of the film is raised, the coercive electric field of the film is reduced, so that the polarization can be reversed with a voltage smaller than that at room temperature. However, as the film temperature approaches the Curie point, dark current increases with a rapid decrease in resistance, so the film temperature should be sufficiently lower than the Curie point in the range of room temperature to about 100 ° C. desirable.

印加電圧パルス波形は、サイン波のような徐々に昇降する波形よりも図4に示すような矩形波の方が好ましい。矩形波の方が電圧を印加しない時間をより多くとることができ、冷却時間(非電圧印加時間)をより多く確保することができるためである。さらに、冷却効率を高めるためには、パルス印加における電圧印加時間Aと、非電圧印加時間Bとの比B/Aを1以上、すなわち、図4の波形においてA≦Bとすることが好ましい。なお、B/Aを10以上とすることがさらに好ましい。   The applied voltage pulse waveform is preferably a rectangular wave as shown in FIG. 4 rather than a waveform that gradually rises and falls like a sine wave. This is because the rectangular wave can take more time during which no voltage is applied, and can secure more cooling time (non-voltage application time). Further, in order to increase the cooling efficiency, it is preferable that the ratio B / A between the voltage application time A in the pulse application and the non-voltage application time B is 1 or more, that is, A ≦ B in the waveform of FIG. It is more preferable that B / A is 10 or more.

図5は、PZT薄膜の温度対電流値の測定結果(昇温、降温曲線)を示すものであり、PZT薄膜に30kV/mmの電圧を印加しつつ昇温もしくは降温時の暗電流値の変化を測定したものである。   FIG. 5 shows the measurement results (temperature rise and temperature drop curves) of the temperature versus current value of the PZT thin film. Changes in dark current value during temperature rise or temperature drop while applying a voltage of 30 kV / mm to the PZT thin film. Is measured.

この図5から、キュリー点(約300℃)に近づくほど急激に抵抗が下がり、電流値が上昇することがわかる。昇温時において、室温側から150℃付近までは暗電流値はほぼ0であるが、150℃を超えると暗電流値が徐々に大きくなり始め、200℃を超えると増大する。従来技術の項で述べたとおり、分極処理における電界印加時に、電界集中箇所にて発熱が進むと急激に抵抗が下がり、これにより更なる電荷集中が生じ、膜破壊に至ると考えられることから、膜の温度を、急激に抵抗が大きくなる温度より低い温度に抑える必要がある。例えば、図5に示すPZT圧電体膜であれば、その温度を200℃以上に上昇させなければ膜破壊に至らないと考えられる。本発明における、パルス電界を印加する分極処理によれば、電圧印加により圧電体膜中の組成欠陥や構造欠陥等の電荷が溜まりやすい部分に電荷集中が起こったとしても、周期的に冷却時間(電界のかからない時間)があり、この冷却時間があることにより電荷集中箇所の発熱を抑制することができ、膜破壊を抑制することができる。   From FIG. 5, it can be seen that the resistance rapidly decreases and the current value increases as the temperature approaches the Curie point (about 300 ° C.). At the time of temperature rise, the dark current value is almost 0 from the room temperature side to around 150 ° C., but when it exceeds 150 ° C., the dark current value starts to gradually increase, and when it exceeds 200 ° C., it increases. As described in the section of the prior art, when an electric field is applied in the polarization process, if heat generation proceeds at an electric field concentration point, the resistance rapidly decreases, which causes further charge concentration, which leads to film destruction. It is necessary to suppress the temperature of the film to a temperature lower than the temperature at which the resistance rapidly increases. For example, in the case of the PZT piezoelectric film shown in FIG. 5, it is considered that the film does not break unless the temperature is raised to 200 ° C. or higher. According to the polarization treatment in which the pulse electric field is applied in the present invention, even if charge concentration occurs in a portion where charges such as composition defects and structural defects in the piezoelectric film tend to accumulate due to voltage application, the cooling time ( There is a time during which no electric field is applied, and the presence of this cooling time makes it possible to suppress heat generation at the charge concentration portion and to suppress film breakdown.

特にPZT圧電体膜のように、Pbを含むペロブスカイト型酸化物からなる膜は、スパッタによる成膜時にPbの組成欠陥が生じやすく、この組成欠陥部分は電荷集中が起こりやすいものであることから、パルス電界を印加する分極処理を適用する効果が高い。   In particular, a film made of a perovskite oxide containing Pb, such as a PZT piezoelectric film, is prone to Pb composition defects when formed by sputtering, and this composition defect part tends to cause charge concentration. The effect of applying a polarization treatment that applies a pulse electric field is high.

また、膜厚が薄ければ薄いほど電荷集中による破壊確率は大きくなるため、パルス電界の印加による分極処理は、膜厚の薄い、例えば20μm以下、さらには10μmの以下の圧電体膜に対して効果が高い。   In addition, the thinner the film thickness, the greater the probability of breakdown due to charge concentration. Therefore, the polarization treatment by applying a pulsed electric field is applied to a piezoelectric film having a small film thickness, for example, 20 μm or less, or 10 μm or less. High effect.

上記実施形態の製造方法のように、基板上にスパッタ成膜により圧電体膜を成膜し、その後、パルス電界による分極処理を行うことにより、図2に示すような自発分極dpが上部電極24から下部電極22へ向かう向き(下向き)の、素子欠陥率が抑制された圧電素子構造体1を得ることができる。特に、パルス電界印加における電圧印加時間Aと非電圧印加時間Bとの比B/Aを1以上とすることにより素子欠陥率を1%以下に、比B/Aを10以上とすることにより素子欠陥率をゼロとすることができる(実施例参照)。   As in the manufacturing method of the above-described embodiment, a piezoelectric film is formed on the substrate by sputtering, and then a polarization process using a pulsed electric field is performed, so that the spontaneous polarization dp as shown in FIG. Thus, the piezoelectric element structure 1 in which the element defect rate in the direction (downward) toward the lower electrode 22 is suppressed can be obtained. In particular, when the ratio B / A between the voltage application time A and the non-voltage application time B in the pulse electric field application is 1 or more, the element defect rate is 1% or less, and the ratio B / A is 10 or more. The defect rate can be made zero (see the examples).

本圧電素子構造体1では、上部電極層24をアドレス電極とする正電圧駆動により、電界印加強度の増減に伴う伸縮が効果的に起こり、電界誘起歪による圧電効果が効果的に得られる。すなわち、本圧電素子構造体1を用いたアクチュエータを構成する場合、下部電極層22を印加電圧が固定されるグラウンド(GND)電極とし、上部電極層24を印加電圧が変動されるアドレス電極として、正電圧駆動ドライバDを利用することができるので、負電圧駆動ドライバを利用する場合と比較して、コストを抑制することができると共に、装置全体の大きさを小さく構成することができる。 In the piezoelectric element structure 1, due to the positive voltage drive using the upper electrode layer 24 as an address electrode, the expansion and contraction accompanying the increase and decrease of the electric field applied intensity occurs effectively, and the piezoelectric effect due to the electric field induced strain is effectively obtained. That is, when an actuator using the piezoelectric element structure 1 is configured, the lower electrode layer 22 is a ground (GND) electrode to which an applied voltage is fixed, and the upper electrode layer 24 is an address electrode whose applied voltage is varied. Since the positive voltage drive driver D + can be used, the cost can be suppressed and the size of the entire apparatus can be reduced as compared with the case of using the negative voltage drive driver.

本圧電素子構造体1は、成電圧駆動ドライバD+を備え、例えば、振動板12の下部をインクを貯留する加圧液室としてインクジェット式記録ヘッドに適用することができ、多チャンネルインク吐出部分の圧電変位が均一化されるため、インク吐出量が一定となり、面内均一性アップによる高画質化に繋がる。また、本発明の製造方法を用いれば素子破壊率を1%以下に抑制することができるため、歩留まりを上昇させコストダウンが可能となる。   The piezoelectric element structure 1 includes a voltage drive driver D +, and can be applied to an ink jet recording head, for example, as a pressurized liquid chamber for storing ink at the lower part of the diaphragm 12. Since the piezoelectric displacement is made uniform, the ink discharge amount becomes constant, which leads to an increase in image quality by increasing the in-plane uniformity. Further, if the manufacturing method of the present invention is used, the element breakdown rate can be suppressed to 1% or less, so that the yield can be increased and the cost can be reduced.

本実施形態において、成膜される圧電体膜としては、スパッタ法で成膜されることにより、基板から膜表面に向かう自発分極を生じる圧電体膜であればいかなるものであってもよい。   In the present embodiment, the piezoelectric film to be formed may be any piezoelectric film that generates spontaneous polarization from the substrate toward the film surface by sputtering.

特に、以下の成膜条件下で成膜することにより、非常に圧電特性の良好な圧電体膜を得ることができ好ましい。   In particular, it is preferable to form a film under the following film forming conditions because a piezoelectric film having very good piezoelectric characteristics can be obtained.

圧電体膜の成膜は、所定のスパッタ装置内において行う。スパッタ法において、成膜される膜の特性を左右するファクターとしては、成膜温度、基板の種類、基板に先に成膜された膜があれば下地の組成、基板の表面エネルギー、成膜圧力、雰囲気ガス中の酸素量、投入電力、基板−ターゲット間距離、プラズマ中の電子温度及び電子密度、プラズマ中の活性種密度及び活性種の寿命等が考えられる。   The piezoelectric film is formed in a predetermined sputtering apparatus. In the sputtering method, factors that affect the characteristics of the film to be formed include the film formation temperature, the type of substrate, the composition of the substrate, the surface energy of the substrate, and the film formation pressure if there is a film previously formed on the substrate. The oxygen amount in the atmosphere gas, the input power, the substrate-target distance, the electron temperature and electron density in the plasma, the active species density in the plasma and the lifetime of the active species, etc. can be considered.

本出願人は多々ある成膜ファクターの中で、成膜される膜の特性への影響の大きなファクターを検討し、良質な膜を成膜可能となる成膜条件を見出した(本出願人が先に出願している特願2006-263978号,特願2006−263979号,特願2006-263980号(本件出願時において未公開)を参照。)
具体的には、成膜温度Tsと、Vs−Vf(Vsは成膜時のプラズマ中のプラズマ電位、Vfはフローティング電位)、Vs、及び基板−ターゲット間距離Dのいずれかとを好適化することにより、良質な膜を成膜できることを見出している。すなわち、成膜温度Tsを横軸にし、Vs−Vf,Vs,及び基板−ターゲット間距離Dのいずれか縦軸にして、膜の特性をプロットすると、ある範囲内(以下に示す条件)において良質な膜を成膜できることを見出した。なお、成膜温度Tsは、成膜する圧電体膜のキュリー点よりも高い温度である。
The applicant has studied the factors that have a great influence on the properties of the film to be formed, and found the film forming conditions that enable the formation of a good quality film. (Refer to Japanese Patent Application Nos. 2006-263978, 2006-263379, and 2006-263980, which have been filed earlier.)
Specifically, the film formation temperature Ts, Vs−Vf (Vs is the plasma potential in the plasma during film formation, Vf is the floating potential), Vs, and the substrate-target distance D are optimized. Thus, it has been found that a high-quality film can be formed. In other words, when the film characteristics are plotted with the film formation temperature Ts as the horizontal axis and any of the vertical axes of Vs−Vf, Vs and the substrate-target distance D, the film quality is good within a certain range (the conditions shown below). It was found that a simple film can be formed. The film formation temperature Ts is higher than the Curie point of the piezoelectric film to be formed.

(第1の成膜条件)
成膜温度Tsと、Vs−Vfとを好適化した成膜条件であり、成膜温度Ts(℃)と、成膜時のプラズマ中のプラズマ電位Vs(V)とフローティング電位Vf(V)との差であるVs−Vf(V)とが、下記式(1)及び(2)を充足する成膜条件で成膜を行う。なお、下記式(1)〜(3)を充足する成膜条件で成膜を行うことが特に好ましい◎
Ts(℃)≧400・・・(1)、
−0.2Ts+100<Vs−Vf(V)<−0.2Ts+130・・・(2)、
10≦Vs−Vf(V)≦35・・・(3)
(第2の成膜条件)
成膜温度Tsと基板BとターゲットTとの離間距離(基板―ターゲット間距離)D(mm)とを好適化した成膜条件であり、成膜温度Ts(℃)と基板―ターゲット間距離D(mm)とが下記式(4)及び(5)を充足する条件、又は(6)及び(7)を充足する成膜条件で成膜する。
400≦Ts(℃)≦500・・・(4)、
30≦D(mm)≦80・・・(5)、
500≦Ts(℃)≦600・・・(6)、
30≦D(mm)≦100・・・(7)
(First film formation conditions)
This is a film formation condition in which the film formation temperature Ts and Vs−Vf are optimized. The film formation temperature Ts (° C.), the plasma potential Vs (V) in the plasma during film formation, and the floating potential Vf (V) The film is formed under the film forming conditions satisfying the following formulas (1) and (2) with Vs−Vf (V) which is the difference between the two. Note that it is particularly preferable to perform film formation under film formation conditions that satisfy the following formulas (1) to (3).
Ts (° C.) ≧ 400 (1),
−0.2Ts + 100 <Vs−Vf (V) <− 0.2Ts + 130 (2),
10 ≦ Vs−Vf (V) ≦ 35 (3)
(Second film formation condition)
This is a film forming condition that optimizes the film forming temperature Ts and the distance (substrate-target distance) D (mm) between the substrate B and the target T. The film forming temperature Ts (° C.) and the substrate-target distance D The film is formed under the condition that (mm) satisfies the following formulas (4) and (5), or the film forming condition that satisfies (6) and (7).
400 ≦ Ts (° C.) ≦ 500 (4),
30 ≦ D (mm) ≦ 80 (5),
500 ≦ Ts (° C.) ≦ 600 (6),
30 ≦ D (mm) ≦ 100 (7)

(第3の成膜条件)
成膜温度Tsと成膜時のプラズマ中のプラズマ電位Vs(V)とを好適化した成膜条件であり、成膜温度Ts(℃)と、成膜時のプラズマ中のプラズマ電位Vs(V)とが、下記式(8)及び(9)を充足する成膜条件又は、(10)及び(11)を充足する成膜条件で成膜する。
400≦Ts(℃)≦475・・・・(8)、
20≦Vs(V)≦50・・・・・・(9)、
475≦Ts(℃)≦600・・・(10)、
Vs(V)≦40・・・・・・・・(11)
(Third film forming conditions)
This is a film forming condition in which the film forming temperature Ts and the plasma potential Vs (V) in the plasma during film formation are optimized. The film forming temperature Ts (° C.) and the plasma potential Vs (V in the plasma during film formation). ) Are formed under film forming conditions that satisfy the following formulas (8) and (9) or film forming conditions that satisfy (10) and (11).
400 ≦ Ts (° C.) ≦ 475 (8),
20 ≦ Vs (V) ≦ 50 (9),
475 ≦ Ts (° C.) ≦ 600 (10),
Vs (V) ≦ 40 (11)

なお、上述の第1から第3の成膜条件のいずれかを満たす条件で、例えば、下記一般式(P−1)、(P−2)で表されるペロブスカイト型酸化物からなる圧電体膜を成膜することにより、配向性の高い圧電体膜を得ることができる。   Note that a piezoelectric film made of a perovskite oxide represented by the following general formulas (P-1) and (P-2), for example, under a condition that satisfies any of the first to third film forming conditions described above. By forming the film, a highly oriented piezoelectric film can be obtained.

Pb(Zrb1Tib2b3)O・・・(P−1)
(式(P−1)中、XはNb,W,Ni,Biからなる群より選ばれた少なくとも1種の金属元素である。a>0、b1>0、b2>0、b3≧0。a=1.0であり、かつb1+b2+b3=1.0である場合が標準であるが、これらの数値はペロブスカイト構造を取り得る範囲内で1.0からずれてもよい。)
(Pba1)(Zrb1Tib2)O・・・(P−2)
(式(P−2)中、XはLa、Bi、Wからなる群より選ばれた少なくとも1種の金属元素である。a>0、a1≧0、b1>0、b2>0、a+a1=1.0であり、かつb1+b2=1.0である場合が標準であるが、これらの数値はペロブスカイト構造を取り得る範囲内で1.0からずれてもよい。)
なお、Vs−Vfは、基板とターゲットとの間にアースを設置するなどして、変えることができる。なお、本発明者が先に出願している特願2006-263981号(本件出願時において未公開)に記載の成膜装置を用いることにより、簡易な方法でプラズマ空間電位を調整することができる。この成膜装置は、ターゲットを保持するターゲットホルダの成膜基板側の外周を取囲むシールドを備え、シールドの存在によって、プラズマ空間の電位状態を調整することができるよう構成されている。
Pb a (Zr b1 Ti b2 X b3 ) O 3 (P-1)
(In Formula (P-1), X is at least one metal element selected from the group consisting of Nb, W, Ni, and Bi. A> 0, b1> 0, b2> 0, b3 ≧ 0. (It is standard that a = 1.0 and b1 + b2 + b3 = 1.0, but these values may deviate from 1.0 within a range where a perovskite structure can be taken.)
(Pb a X a1 ) (Zr b1 Ti b2 ) O 3 (P-2)
(In Formula (P-2), X is at least one metal element selected from the group consisting of La, Bi, and W. a> 0, a1 ≧ 0, b1> 0, b2> 0, a + a1 = (The standard is 1.0 and b1 + b2 = 1.0, but these values may deviate from 1.0 within a range where a perovskite structure can be taken.)
Vs−Vf can be changed by installing a ground between the substrate and the target. Note that the plasma space potential can be adjusted by a simple method by using the film forming apparatus described in Japanese Patent Application No. 2006-263881 filed earlier by the present inventor (not disclosed at the time of this application). . This film forming apparatus includes a shield that surrounds the outer periphery of the target holder that holds the target on the film forming substrate side, and is configured so that the potential state of the plasma space can be adjusted by the presence of the shield.

このようにして得られた圧電体膜は、結晶配向度が高くかつ自発分極の向きが圧電体膜表面から基板(下部電極から上部電極)に向かうものとなっている。   The piezoelectric film thus obtained has a high degree of crystal orientation and the direction of spontaneous polarization is directed from the surface of the piezoelectric film to the substrate (from the lower electrode to the upper electrode).

なお、上記では特にPZT系の圧電体膜について例を挙げたが、PZT系以外のBaTiOやLiNbOなどの圧電材料においてもスパッタ法で成膜することにより、PZT系と同様の自発分極が生じることから、これらの圧電体膜を備えるものとしてもよい。 In the above, an example has been given particularly for a PZT-based piezoelectric film. However, by using a sputtering method to form a piezoelectric material such as BaTiO 3 or LiNbO 3 other than the PZT-based film, the same spontaneous polarization as in the PZT system can be obtained. Therefore, these piezoelectric films may be provided.

以下に示す構造体に対し、実施例および比較例の条件による分極処理を施し、評価を行った。図6および図7は分極処理を行った構造体および分極処理時の構成を示す概念図であり、図6は要部の概略断面図、図7は要部の概略平面図である。   The structure shown below was subjected to polarization treatment under the conditions of Examples and Comparative Examples and evaluated. 6 and 7 are conceptual diagrams showing a structure subjected to polarization processing and a configuration at the time of polarization processing, FIG. 6 is a schematic cross-sectional view of the main part, and FIG. 7 is a schematic plan view of the main part.

実施例および比較例の分極処理に供される構造体4は、Si基板31上に下部電極層32としてTi層32aおよびIr層32bを形成し、下部電極層32上に、スパッタ法により膜厚5μmのPZT圧電体膜33を成膜し、さらにTi層34a、Ir層34bからなる上部電極34をPZT圧電体膜33上にパターン形成したものである。ここではPZT圧電体膜33上に200チャンネル(200素子相当)分の電極を形成した。さらに、各上部電極34から引き出し配線36を形成し、その末端には電極パッド35を形成した。なお、引き出し配線36および電極パット35形成領域においては、圧電体膜33上にポリイミド樹脂層37を設け、該樹脂層37上に配線36、パッド35を形成している。   In the structure 4 subjected to the polarization treatment of the example and the comparative example, the Ti layer 32a and the Ir layer 32b are formed as the lower electrode layer 32 on the Si substrate 31, and the film thickness is formed on the lower electrode layer 32 by sputtering. A PZT piezoelectric film 33 having a thickness of 5 μm is formed, and an upper electrode 34 including a Ti layer 34 a and an Ir layer 34 b is formed on the PZT piezoelectric film 33 by patterning. Here, electrodes for 200 channels (corresponding to 200 elements) were formed on the PZT piezoelectric film 33. Furthermore, a lead wiring 36 was formed from each upper electrode 34, and an electrode pad 35 was formed at the end thereof. In the region where the lead wiring 36 and the electrode pad 35 are formed, a polyimide resin layer 37 is provided on the piezoelectric film 33, and the wiring 36 and the pad 35 are formed on the resin layer 37.

電極パッド35にプローブもしくはワイヤーボンディングもしくはFPC(Flexible Printed Circuit)配線により分極反転駆動電源40に接続し、下部電極32は接地させた。   The electrode pad 35 was connected to the polarization inversion drive power supply 40 by a probe, wire bonding, or FPC (Flexible Printed Circuit) wiring, and the lower electrode 32 was grounded.

(実施例1)
印加電圧:10kV/mm
電圧保持時間:10分
パルス周波数0.1kHz〜1MHz
電圧印加時間と非印加時間の比B/A=1
圧電体膜の温度:室温〜100℃
(室温より高温にする場合には、電圧印加を行う前に昇温する。)
上記電界印加条件の範囲で、上記構成の構造体4の各電極層間(200チャンネル)に対し同時にパルス電界印加による分極反転処理を行い、200チャンネル中の破壊されたチャンネル数から破壊率を調べた。
Example 1
Applied voltage: 10 kV / mm
Voltage holding time: 10 minutes Pulse frequency 0.1 kHz to 1 MHz
Ratio of voltage application time and non-application time B / A = 1
Temperature of piezoelectric film: room temperature to 100 ° C
(If the temperature is higher than room temperature, the temperature is raised before applying the voltage.)
Within the range of the electric field application conditions, each electrode layer (200 channels) of the structure 4 having the above configuration was simultaneously subjected to a polarization inversion process by applying a pulse electric field, and the destruction rate was examined from the number of broken channels in the 200 channels. .

その結果、上記のパルス周波数範囲においては、顕著な周波数依存は確認されず、いずれも破壊率は0−1%であった。   As a result, in the above pulse frequency range, no significant frequency dependence was confirmed, and the destruction rate was 0-1% in all cases.

(比較例1)
上記実施例1の条件においてパルス電界ではなく連続電界を印加を行うものとし、圧電体膜の温度が室温(25℃)の場合、および100℃の場合について、連続電界印加による分極反転処理を行い、破壊率を調べた。
(Comparative Example 1)
A continuous electric field is applied instead of a pulsed electric field under the conditions of Example 1 above, and polarization inversion processing is performed by applying a continuous electric field when the temperature of the piezoelectric film is room temperature (25 ° C.) and when the temperature is 100 ° C. The destruction rate was examined.

その結果、連続電界による分極処理を行った構造体のうち、室温で処理を行ったものにおける破壊率は15%であり、100℃で処理を行ったものにおける破壊率は30%であった。   As a result, among the structures subjected to the polarization treatment by the continuous electric field, the destruction rate in the case where the treatment was performed at room temperature was 15%, and the destruction rate in the case where the treatment was performed at 100 ° C. was 30%.

実施例1および比較例の結果から、パルス電界印加による分極処理を用いれば、連続電界印加による分極処理の場合と比較して顕著な破壊率低減効果が得られることを確認した。   From the results of Example 1 and the comparative example, it was confirmed that if the polarization treatment by applying a pulsed electric field is used, a remarkable destruction rate reducing effect can be obtained as compared with the case of the polarization treatment by applying a continuous electric field.

(実施例2)
印加電圧:10kV/mm、
電圧保持時間:10分
パルス周波数:100kHz
電圧印加時間と非印加時間の比B/A=0.01〜100
圧電体膜の温度:室温(25℃)、100℃(100℃の場合、電圧印加を行う前に昇温する。)
複数の構造体に対し、それぞれ上記条件範囲でパルス電界を印加して分極反転を行い、破壊率を調べた。それぞれの膜温度毎に電圧印加時間と非印加時間の比B/Aを変化させた結果を図8に示す。
(Example 2)
Applied voltage: 10 kV / mm,
Voltage holding time: 10 minutes Pulse frequency: 100 kHz
Ratio of voltage application time and non-application time B / A = 0.01-100
Temperature of piezoelectric film: room temperature (25 ° C.), 100 ° C. (in the case of 100 ° C., the temperature is increased before voltage application)
With respect to the plurality of structures, a pulse electric field was applied within the above condition range to perform polarization inversion, and the breakdown rate was examined. FIG. 8 shows the result of changing the ratio B / A between the voltage application time and the non-application time for each film temperature.

図8に示すように、分極時の圧電体膜の温度が室温であるとき、100℃であるときのいずれの場合にも、パルス電界印加時の比B/Aが大きいほど比破壊率が減少した。特に電圧印加時間と非印加時間が1:1のB/Aが1以上で破壊率が1%以下となる顕著な破壊率低減が確認され、さらに比B/Aが10以上では安定して破壊率ゼロとなることが確認できた。   As shown in FIG. 8, when the temperature of the piezoelectric film at the time of polarization is room temperature or 100 ° C., the specific breakdown rate decreases as the ratio B / A at the time of applying the pulse electric field increases. did. In particular, it was confirmed that the B / A with a voltage application time and a non-application time of 1: 1 was 1 or more and the destruction rate was 1% or less, and a significant reduction in the destruction rate was confirmed. Further, when the ratio B / A was 10 or more, the destruction was stable. It was confirmed that the rate was zero.

なお、ここで、分極処理における破壊率とは、分極処理後の構造体における素子欠陥率と同義である。   Here, the breakdown rate in the polarization treatment is synonymous with the element defect rate in the structure after the polarization treatment.

本発明の圧電素子構造体は、インクジェット式記録ヘッド,磁気記録再生ヘッド,MEMS(Micro Electro-Mechanical Systems)デバイス,マイクロポンプ,超音波探触子等に搭載される圧電アクチュエータ等に好ましく利用できる。   The piezoelectric element structure of the present invention can be preferably used for a piezoelectric actuator mounted on an ink jet recording head, a magnetic recording / reproducing head, a MEMS (Micro Electro-Mechanical Systems) device, a micro pump, an ultrasonic probe, and the like.

本発明に係る実施形態の製造方法により得られる圧電素子構造体の概略平面図Schematic plan view of a piezoelectric element structure obtained by a manufacturing method according to an embodiment of the present invention 本発明に係る実施形態の製造方法により得られる圧電素子構造体の要部断面図Sectional drawing of the principal part of the piezoelectric element structure obtained by the manufacturing method of embodiment which concerns on this invention 本発明に係る実施形態の製造方法における圧電体膜成膜直後の構造体の要部断面図Sectional drawing of the principal part of the structure body immediately after film-forming of the piezoelectric film in the manufacturing method of embodiment which concerns on this invention 分極処理の際の印加電圧パルス波形を示す図The figure which shows the applied voltage pulse waveform at the time of polarization processing PZT圧電体膜における暗電流の温度依存性を示す図The figure which shows the temperature dependence of the dark current in a PZT piezoelectric material film. 実施例の構造体の構成および分極処理時の構成を示す要部の概略断面図Schematic cross-sectional view of the main part showing the structure of the structure of the example and the structure during polarization treatment 実施例の構造体の構成および分極処理時の構成を示す要部の概略平面図Schematic plan view of the main part showing the structure of the structure of the example and the structure during polarization processing 分極処理時における破壊率の電圧印加時間と非印加時間の比B/A依存性を示す図The figure which shows the ratio B / A dependence of the voltage application time of a breakdown rate at the time of a polarization process, and non-application time

符号の説明Explanation of symbols

1 圧電素子構造体
2 圧電素子
4 圧電素子構造体(分極処理前)
11、31 基板
12 振動板
22、32 下部電極層
23、33 圧電体膜
24、34 上部電極層
DESCRIPTION OF SYMBOLS 1 Piezoelectric element structure 2 Piezoelectric element 4 Piezoelectric element structure (before polarization process)
11, 31 Substrate 12 Diaphragm 22, 32 Lower electrode layer 23, 33 Piezoelectric film 24, 34 Upper electrode layer

Claims (6)

基板上に、下部電極層、圧電体膜および上部電極層がこの順に積層されてなる多数の圧電素子を備えた圧電素子構造体を製造する圧電素子構造体の製造方法において、
前記基板上に前記下部電極層を共通電極として形成し、
該下部電極層上に前記圧電体膜をスパッタ法により成膜し、
前記圧電体膜上に、前記上部電極層を個別電極として形成し、
該成膜により自発分極が前記下部電極層から前記上部電極層に向かう向きとなっている圧電体膜に対し、該圧電体膜の抗電界以上の大きさの、前記上部電極層から前記下部電極層に向かう電界をパルス印加することを特徴とする圧電素子構造体の製造方法。
In the manufacturing method of a piezoelectric element structure for manufacturing a piezoelectric element structure including a large number of piezoelectric elements in which a lower electrode layer, a piezoelectric film, and an upper electrode layer are laminated in this order on a substrate,
Forming the lower electrode layer on the substrate as a common electrode;
Forming the piezoelectric film on the lower electrode layer by sputtering;
On the piezoelectric film, the upper electrode layer is formed as an individual electrode,
With respect to the piezoelectric film in which spontaneous polarization is directed from the lower electrode layer toward the upper electrode layer by the film formation, the upper electrode layer has a magnitude greater than the coercive electric field of the piezoelectric film and the lower electrode. A method of manufacturing a piezoelectric element structure, wherein an electric field directed to a layer is applied with a pulse.
前記圧電体膜が、少なくともPbを含むペロブスカイト型酸化物であることを特徴とする請求項1記載の圧電素子構造体の製造方法。   2. The method of manufacturing a piezoelectric element structure according to claim 1, wherein the piezoelectric film is a perovskite oxide containing at least Pb. 前記電界のパルス印加における電圧印加時間Aと、非電圧印加時間Bとの比B/Aが1以上であることを特徴とする請求項1または2項記載の圧電素子構造体の製造方法。   3. The method for manufacturing a piezoelectric element structure according to claim 1, wherein a ratio B / A between a voltage application time A and a non-voltage application time B in pulse application of the electric field is 1 or more. 前記電界のパルス印加における電圧印加時間Aと、非電圧印加時間Bとの比B/Aが10以上であることを特徴とする請求項3項記載の圧電素子構造体の製造方法。   4. The method of manufacturing a piezoelectric element structure according to claim 3, wherein a ratio B / A between the voltage application time A and the non-voltage application time B in the pulse application of the electric field is 10 or more. 基板上に、下部電極層、スパッタ法により成膜された圧電体膜及び上部電極層がこの順に積層されてなる多数の圧電素子を備えた圧電素子構造体であって、
前記下部電極層が共通電極であり、前記上部電極層が個別電極である、請求項1から4いずれか1項記載の方法で作製された圧電素子構造体であり、
該圧電素子構造体における圧電素子の前記圧電体膜の分極反転処理に伴う膜破壊による欠陥率が1%以下であり、
前記圧電体膜の自発分極が前記上部電極層から前記下部電極層に向かう向きであることを特徴とする圧電素子構造体。
A piezoelectric element structure comprising a plurality of piezoelectric elements in which a lower electrode layer, a piezoelectric film formed by sputtering and an upper electrode layer are laminated in this order on a substrate,
The piezoelectric element structure produced by the method according to any one of claims 1 to 4, wherein the lower electrode layer is a common electrode and the upper electrode layer is an individual electrode.
The defect rate due to film breakage due to the polarization inversion process of the piezoelectric film of the piezoelectric element in the piezoelectric element structure is 1% or less,
The piezoelectric element structure according to claim 1, wherein the spontaneous polarization of the piezoelectric film is directed from the upper electrode layer toward the lower electrode layer.
前記圧電体膜が、少なくともPbを含むペロブスカイト型酸化物であることを特徴とする請求項5記載の圧電素子構造体。   6. The piezoelectric element structure according to claim 5, wherein the piezoelectric film is a perovskite oxide containing at least Pb.
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