JP5381591B2 - Delay analysis apparatus, delay analysis method, and delay analysis program - Google Patents

Description

  The present invention relates to a delay analysis apparatus, a delay analysis method, and a delay analysis program.

  A technique using timing analysis is known when performing analysis on delay of an integrated circuit.

  Timing analysis is an analysis method for evaluating the operating frequency of a chip using a CAD tool at the design stage and confirming whether the target operating frequency is achieved. For example, in the case of designing with an operation frequency of 2.5 GHz as a target, it is analyzed whether a signal arrives at a time of 400 ps or less, which is the reciprocal of 2.5 GHz, between all the memory elements.

  Timing analysis is generally classified into static timing analysis and dynamic timing analysis. In addition, static timing analysis has been proposed for static timing analysis that has been used in the past (hereinafter, static timing analysis that has been conventionally used is referred to as STA (Static Timing Analysis)). Statistical analysis (hereinafter, SSTA (Statistical Static Timing Analysis)) which is an analysis method.

  Deterministic static timing analysis, path-based STA, and block-based STA are known for STA, and path-based SSTA and block-based SSTA are known for SSTA.

  Here, STA, SSTA, and block-based SSTA will be described with reference to FIG.

  In the STA, when calculating the delay of the path, the delay value of each element of the gate element and the wiring constituting the path is cumulatively calculated toward the subsequent stage. The delay value at this time is one fixed numerical value. In the cumulative calculation, a method of processing with priority on the circuit depth is a path-based STA, and a method of processing with priority on the circuit width is a block-based STA. In the example of FIG. 8, in the case of the path-based STA, processing is performed in the order of the path from the latch A to the latch C, the path from the latch B to the latch C, and the path from the latch B to the latch D. In the case of the block-based STA, delay values are accumulated simultaneously from the latch A and the latch B to the output side one gate at a time. Since the gate p has two inputs, the accumulation processing of the delay of the gate p is performed when the accumulation of the two paths from the latch A to the gate p and from the latch B to the gate p is completed. In the process of obtaining the maximum delay, the delay of the gate p is accumulated in the larger delay of the accumulated delays of the two paths of the gate p, and the process proceeds. In this way, when there are a plurality of inputs for one gate, an operation for selecting the largest delay is called a MAX operation.

  In contrast to the above STA, SSTA represents the delay value of each element of the gate and wiring constituting the path as a probability density function in which the horizontal axis is the delay value and the vertical axis is the probability density. . Further, regarding the accumulation of path delays, STA simply adds numerical values, but SSTA performs statistical addition of probability density functions. In addition, the MAX operation in the STA is a numerical operation that simply leaves a large numerical value, but in the SSTA, a statistical operation called statistical MAX of two probability density functions is performed. In this SSTA processing, the block-based SSTA is a method of processing with priority in width as described in the description of the block-based STA.

  In addition, the following techniques are known.

JP 2008-102837 A Japanese Patent Laid-Open No. 8-6988 JP 2000-222452 A JP 2001-67383 A

Jing-Jia Liou et al., `` False-Path-Aware Statistical Timing Analysis and Efficient Path Selection for Delay Testing and Timing Validation '', International Conference on Computer Aided Design, 2002, pp 566-569 Shuji Tsukiyama et al., "Techniques to Remove False Paths in Statistical Static Timing Analysis", ASICON, 2001, pp 39-44 Rajesh Garg et al., "On the Improvement of Statistical Timing Analysis", ICCD, 2006 Vikram Iyengar et al., "Variation-Aware Performance Verification Using At-Speed Structural Test And Statistical Timing", International Conference on Computer Aided Design, 2007, pp 405-412

  When analyzing an integrated circuit using SSTA, the path chosen must actually open logically. This is because when the path is not logically opened, that is, when there is no possibility of logically passing through the path, the path does not affect the timing yield. A problem that is difficult to solve in SSTA is the elimination of false paths that do not open logically. Since the false path does not affect the timing yield distribution of the actual integrated circuit at all, if it is not excluded, the analysis result is estimated to be smaller than the original numerical value.

  The present invention has been made to solve the above-described problems, and it is an object of the present invention to provide a delay analysis apparatus, a delay analysis method, and a delay analysis program capable of eliminating a false path in a block-based SSTA. .

  The delay analyzer sets an assumed fault for each pin between the start point latch and the end point latch, an acquisition unit that acquires data related to the start point latch and end point latch of the path that can be a path in which signal propagation is delayed on the integrated circuit. The determination unit that determines whether or not the signal change generated in the start point latch can propagate to the end point latch is expressed for each setting and the delay of each element constituting the path is expressed as a probability density function, and expressed as a probability density function. Statistical timing analysis to calculate the delay distribution of the path by cumulatively calculating the distribution from the start point latch to the end point latch. An analysis unit that performs the cumulative calculation.

  It is possible to perform analysis by deleting false paths that are not logically opened, and to obtain an analysis result correlated with reality.

It is a figure which shows an example of the functional block of the delay analyzer based on this Embodiment. It is a flowchart which shows an example of operation | movement of the delay analyzer based on this Embodiment. It is a figure which shows the application range of the conventional SSTA, and the application range of SSTA which concerns on this Embodiment. It is an example of the schematic diagram of the circuit used for description about "opening a path" based on this Embodiment. It is a schematic diagram which shows the condition when performing SSTA again based on this Embodiment. It is a figure which shows an example of the hardware constitutions of the computer system applicable to the delay analysis apparatus which concerns on this Embodiment. It is a figure which shows an example of the hardware constitutions of the main-body part in the computer system applicable to the delay analysis apparatus which concerns on this Embodiment. It is an example of the schematic diagram of the circuit used for description of STA and SSTA.

  This embodiment will be described below. The false path can be classified into three types. The first is a functional false path, which is a logically open path, but in an actual computer, it is a path that is not actually opened in any instruction execution order. The second is a boolean untrue path, a path that does not open for any combination of input values. The third is a delay dependent false path, which is a boolean true path but does not open depending on the timing delay. In the present embodiment, a technique suitable for eliminating a false path classified as a boolean untrue path will be described. In the following description, the integrated circuit to be analyzed is described as a processor, but this embodiment can be applied to any integrated circuit.

  FIG. 1 shows a delay analysis apparatus according to the present embodiment. The delay analysis apparatus 100 includes a cell library input unit 1 that acquires a cell library 51 that has been used conventionally, and a design data input unit 2 that acquires processor design data 52 that has been used. The cell library 51 and the processor design data 52 are stored in the memory 61.

  The delay analysis apparatus 100 also has a memory data input unit 4 that acquires a cell library 51 and processor design data 52 stored in the memory 61. The delay analysis apparatus 100 performs STA using the cell library 51 and the processor design data 52, and signal propagation is delayed in the processor, so that the processor cannot operate at the design operating frequency. It has a static timing analysis unit 5 that identifies a critical path within a range that can be performed by the STA. The delay analysis apparatus 100 includes a critical path output unit 6 that outputs critical path information 53 that is information related to the critical path specified by the static timing analysis unit 5.

  In addition, the delay analysis apparatus 100 uses the critical path information 53, the cell library 51 stored in the memory 61, and the processor design data 52 to start a path start point latch that can be a path in which signal propagation is delayed in the processor. And a critical path selection unit 7 for selecting a necessary number of pairs of the end point latch and the end point latch. The pair selected in this way is hereinafter referred to as the worst N path. Although the number of worst N paths will be described later, it is assumed that the number of the analysis results is sufficient.

  In addition, the delay analysis apparatus 100 includes a storage unit 8 that stores a pair of the start point latch and the end point latch selected by the critical path selection unit 7 in the memory 61.

  The delay analysis apparatus 100 includes a cell library 51 stored in the memory 61, processor design data 52, and a memory data input unit 9 for acquiring the worst N path. In addition, the delay analysis apparatus 100 uses the data acquired by the data input unit 9 to apply block-based SSTA to the entire logic circuit between the start point latch and the end point latch of each path, so that the start point / end point latch pair A statistical timing analysis unit 10 for generating the delay distribution. The delay analysis apparatus 100 also includes a delay distribution graph output unit 11 that outputs the delay distribution of the start and end latch pairs generated by the statistical timing analysis unit 10 as a delay distribution graph 54, respectively.

  The delay analysis apparatus 100 has a delay distribution graph input unit 12 that acquires the delay distribution of the start and end latch pairs from the delay distribution graph 54, and α × σ (where α is a constant and σ is a standard deviation) of each delay distribution. And a test target path selection unit 13 that sorts the pairs of the start point latch and the end point latch in descending order of the value. The delay analysis apparatus 100 includes a test target path output unit 14 that outputs the sorted start point and end point latch pairs as test target path information 55 in the sort order.

  The delay analysis apparatus 100 includes a test target path input unit 15 that acquires the start and end latch pairs in descending order of the delay value in the test target path information 55, and a storage unit 16 that stores the acquired start and end latch pairs in the memory 61. Have The delay analysis apparatus 100 performs transition faults, which are one of the delay fault models and are assumed faults, in accordance with the conventional method, for the pins of the logic circuit between the start point latch and end point latch to be processed in the memory 61. It has a hypothetical failure setting unit 17 for setting.

  The delay analysis apparatus 100 includes a delay test generation unit 18 that attempts to create a pattern in which a signal change occurs between a start point latch and an end point latch to be processed for each set hypothesis failure. The delay analysis apparatus 100 outputs, in the form of false path information 56, an in-circuit identification name of a pin that has not been opened by the delay test generation unit 18 for each start point and end point latch pair currently being processed. A path information output unit 19 is included.

  The statistical timing analysis unit 10 further re-executes the SSTA that is executed first. However, in this SSTA re-execution, in the process of propagating the delay distribution while forward tracing the circuit forward from the subsequent stage to the front stage in order to obtain the statistical delay distribution for the logic circuits in the start and end latch pairs, When a pin list of a false path is acquired from the path information 56 and the delay distribution is propagated, processing is performed so that the delay distribution is not propagated to the subsequent stage with the pins in the pin list.

  The delay analysis apparatus 100 includes a timing yield calculation unit 20 that calculates a processor timing yield distribution 57 by processing using the delay distribution obtained for the start point and end point latch pairs by the above-described processing, using a conventional method.

  The function units from the cell library input unit 1 to the storage unit 8 and the memory 61 are referred to as a pair selection unit 101. The test target path input unit 15, the storage unit 16, and the memory 61 are referred to as an acquisition unit 102. The hypothetical failure setting unit 17, the delay test generation unit 18, the false path information output unit 19, and the false path information 56 are set as the determination unit 103.

  The statistical timing analysis unit 10, the delay distribution graph output unit 11, and the delay distribution graph 54 of each path are referred to as an analysis unit 104. The delay distribution graph input unit 12, the test target path selection unit 13, the test target path output unit 14, and the test target path information 55 are referred to as a sort unit 105.

  Next, the operation of the delay analysis apparatus 100 will be described with reference to FIG. In the following description of the operation, description of units responsible for input / output of data such as the storage unit 3 and the memory data input unit 4 is omitted.

  The static timing analysis unit 5 performs a conventional STA process on the cell library 51 and the processor design data 52, and outputs critical path information (S1). Next, the critical path selection unit 7 selects the worst N path from the critical path information 53 (S2).

  A method of obtaining the number (N) selected as the worst N path will be described. First, the critical path selection unit 7 obtains the frequency yield distribution of the entire chip from the delay distributions of the N start point latches and the end point latches, and further calculates the entire chip from the delay distributions of the (N + 1) start point latches and the end point latches. The frequency yield distribution is obtained. When the difference between the obtained two frequency yield distributions is equal to or less than a predetermined value, the data for the (N + 1) th path is unnecessary, and N at that time is the number of worst N paths.

  Note that the frequency yield of the entire chip is a distribution graph created by actually measuring the maximum operating frequency of each manufactured chip and producing the maximum operating frequency on the horizontal axis and the ratio of the number of chips on the vertical axis. Further, where to determine the difference in frequency yield distribution, in this embodiment, in the ratio of the vertical axis, the difference between the maximum operating frequency values of the two horizontal axes of the two distributions at a target ratio value, It is defined that there is no difference when this value difference is equal to or less than a predetermined value. How small the predetermined value is depends on the accuracy to be obtained.

  Thereafter, the statistical timing analysis unit 10 performs the SSTA process for each pair of the start point latch and end point latch selected by the critical path selection unit 7 and creates a delay distribution graph 54 for each pair (S3). Note that the statistical timing analysis unit 10 performs block-based statistical timing analysis.

  Here, with reference to FIG. 3, the application range of the SSTA of the prior art and the application range of the SSTA in the present embodiment will be described. In the prior art, SSTA (block-based SSTA) is applied to the entire integrated circuit (see FIG. 3A), but in this embodiment, the start point latch and the end point that have become critical paths as a result of STA A block-based SSTA is applied to a circuit between a pair of latches (see FIG. 3B). In FIG. 3, the start point latch and the end point latch are indicated as FF (Flip Flop).

  In the SSTA processing in the statistical timing analysis unit 10, statistical delay calculation is performed on all the logic circuits within the range shown in FIG. 3B, that is, between the start latch and the end latch. That is, here, a delay distribution is obtained in consideration of all paths between the start point latch and the end point latch.

  Returning to the description of FIG. The test target path selection unit 13 calculates α × σ values of each delay distribution, sorts the pairs of start point latches and end point latches in descending order, and the test target path input unit 15 sets the start point and end point in the sort order. One latch pair is acquired (S4). In this embodiment, for example, the value of α is α = −3, but any constant such as α = 3 may be used. The hypothetical fault setting unit 17 sets a transition fault, which is a hypothetical fault, for each pin of the logic circuit between the start point latch and the end point latch to be processed according to the conventional method (S5).

  The delay test generation unit 18 attempts to create a pattern such that a signal change occurs between the start point latch and the end point latch of the path to be processed for each hypothetical failure (S6).

  The delay test generation unit 18 determines whether or not a path is opened in a delay manner (S7), and if no path is opened in a delayed manner (S7, no), this hypothetical failure point is a false path point. And try the next hypothetical failure. If at least one path is opened in a delayed manner and the pattern generation is successful (S7, yes), this hypothetical failure point is marked as not a false path point, and the process returns to step S6, where the pattern for the next hypothetical failure is obtained. Attempt to generate.

  Here, “the path is opened in a delayed manner” will be described with reference to FIG. In FIG. 4, for example, a path from the latch C to the latch D via the gate y and the gate z is a delay test target. In this embodiment, when the signal change generated by the latch C on the path can be propagated to the latch D, the path from the latch C to the latch D is opened in a delay manner. In the example of FIG. 4, the path from the latch C to the latch D is not opened. In order for the path from the latch C to the latch D to open, the input that is not on the path among the two inputs of the gate y needs to be 1 because the gate y is an AND circuit. On the other hand, of the two inputs of the gate z, an input not on the path needs to be set to 0 because the gate z is an or circuit. This means that the output of gate x needs to be 1 and 0, which is logically impossible, so the path from latch C to latch D will not open. That is, the path from the latch C to the latch D is a false path. Since the circuit shown in FIG. 4 contains redundant logic circuits, a false path occurs. Redundant logic circuits are not intended by designers and may result in unintended cases.

  Returning to the description of FIG. The delay test generation unit 18 causes the false path information output unit 19 to output the in-circuit identification name of the pin marked as the false path point in the start point and end point latch pair currently being processed as the false path information 56 (S8). ), It is determined whether the delay test generation for all hypothetical faults has been completed (S9). As a result of this processing, the in-circuit identification names of the pins are output to the start point and end point latch pairs for all pins marked as false path points.

  If the pattern generation has not been completed (S9, no), the delay test generation unit 18 returns to step S6 and tries to generate a pattern at the next hypothetical failure point. On the other hand, when the pattern generation is completed (S9, yes), the statistical timing analysis unit 10 performs SSTA again. Here, a pin list that does not open a path is input from within the false path information 56, and the delay distribution is calculated. For the pins in the pin list during the propagation process, the delay distribution graph 54 is generated in which the delay distribution is not cumulatively calculated in the subsequent stage and the pin list in which the path is not opened in a delayed manner is excluded (S10).

  The process of step S10 will be described with reference to FIG. FIG. 5 is a schematic diagram illustrating a situation when the SSTA process is executed by the statistical timing analysis unit 10 on the logic circuit between the start point latch A and the end point latch B. FIG. For example, when the pin A2 of the gate g2 is registered in the latch pair of the start point latch A and the end point latch B in the false path information 56, the statistical timing analysis unit 10 cannot originally generate the delay value of the pin A2 of the gate g2. By setting a value, for example, 0, etc., processing that does not propagate the delay distribution is performed.

  The timing yield calculation unit 20 obtains the timing yield distribution of the processor by processing the delay distribution graph for each start point / end point latch pair obtained in step S10 by the conventional method.

  When the delay analysis apparatus 100 according to the present embodiment generates a delay test pattern for each path, if the path is not opened with respect to the start-point latch / end-point latch pair, this path is logically a false path. Can be determined as a result. Further, in order to consider the false paths of some paths in the start / end latch pair, the delay analysis apparatus 100 is based on the transition fault model for one start / end latch pair logic circuit. Using this method, pattern generation is attempted for each of the faults assumed in the logic circuit. Even when the path is opened for any one of the hypothetical faults, the delay analysis apparatus 100 tries to generate a pattern for another hypothetical fault. The delay analysis apparatus 100 lists hypothetical faults in which the path is not opened for each start-point / end-point latch pair.

  When the delay analysis device 100 obtains a delay distribution for a logic circuit in a start / end latch pair, the delay analysis apparatus 100 obtains a pin list in which a path is not opened by the start / end latch pair, and delay distribution is performed for pins in the pin list by SSTA processing. Adopt a method that does not propagate. In this way, an accurate false path can be taken into account for each start point and end point latch pair.

  According to the present embodiment, in block-based statistical timing analysis that is currently widely used as statistical timing analysis, the delay distribution of each path is obtained, and the timing yield of the entire integrated circuit is obtained by statistical MAX processing of these distributions. When calculating the distribution, it is possible to easily perform an analysis by removing false paths that do not logically open and do not affect the timing yield, and obtain a result that is correlated with the reality as an analysis result of the timing yield Can do.

  The present invention can be applied to the following computer system. FIG. 6 is a diagram illustrating an example of a computer system to which the present invention is applied. A computer system 920 shown in FIG. 6 includes a CPU (Central Processing Unit), a main body 901 including a memory, a disk drive, and the like, a display 902 that displays an image according to an instruction from the main body 901, and various information on the computer system 920. A keyboard 903 for input, a mouse 904 for designating an arbitrary position on the display screen 902a of the display 902, and a communication device 905 for accessing an external database or the like and downloading a program or the like stored in another computer system. The communication device 905 may be a network communication card, a modem, or the like.

  A program for executing the above-described steps in the computer system constituting the delay analysis apparatus as described above can be provided as a delay analysis program. By storing this program in a recording medium readable by the computer system, the program can be executed by the computer system constituting the delay analysis apparatus. A program for executing the above steps is stored in a portable recording medium such as a disk 910 or downloaded from a recording medium 906 of another computer system by the communication device 905. Also, a delay analysis program (delay analysis software) that causes the computer system 920 to have at least a delay analysis function is input to the computer system 920 and compiled. This program causes the computer system 920 to operate as a delay analysis device having a delay analysis function. Further, this program may be stored in a computer-readable recording medium such as a disk 910, for example. Here, as a recording medium readable by the computer system 920, an internal storage device such as a ROM (Read Only Memory) or a RAM (Random Access Memory), which is internally mounted in the computer, a disk 910, a flexible disk, a DVD (Digital Versatile). Disk), a magneto-optical disk, a portable storage medium such as an IC (Integrated Circuit) card, a database holding a computer program, another computer system and its database, or communication means such as a communication device 905. Various recording media accessible by a computer system connected to each other.

  FIG. 7 is a diagram illustrating an example of a hardware configuration of the main body unit 901 in the computer system 920. The main unit 901 includes a CPU 951, a memory 952 (corresponding to the above-described memory 61), a disk drive 953 that reads and writes data from a portable recording medium such as the disk 910, and an HDD (Hard disk drive) 954 that is a nonvolatile storage unit. And an I / O device 955 for controlling communication with the outside. Each functional unit described above is realized by a program held in advance in a nonvolatile storage unit such as the HDD 954 and the disk 910 cooperating with hardware resources such as the CPU 951 and the memory 952. In addition, each of the above data is stored in the HDD 954 or the memory 952.

As mentioned above, according to this Embodiment, the technical idea shown with the following additional remarks is disclosed.
(Additional remark 1) The acquisition part which acquires the data regarding the starting point latch of the path | route which can become a path | route which signal propagation delays on an integrated circuit, and an end point latch,
A determination unit configured to set a hypothetical failure for each pin between the start point latch and the end point latch and determine whether a signal change generated in the start point latch can be propagated to the end point latch; ,
Statistical timing for calculating the delay distribution of the path by expressing the delay of each element constituting the path as a probability density function and cumulatively calculating the distribution expressed by the probability density function from the start point latch to the end point latch. An analysis unit that performs an analysis so that the distribution is not cumulatively calculated in the subsequent stage in the pin when it is determined that the signal change cannot be propagated by the determination unit;
A delay analysis apparatus.
(Additional remark 2) Based on the design data of the integrated circuit hold | maintained at the memory | storage device, the pair selection part which selects two or more pairs of the data regarding the start point latch of the path | route which can become a path | pass which signal propagation delays in the said integrated circuit ,
Statistical timing analysis is performed on a circuit between a start point latch and an end point latch of a pair selected by the pair selection unit, and a statistical timing analysis unit for calculating a delay distribution for each pair, and
A sorting unit that sorts a plurality of pairs selected by the pair selection unit based on a deviation of each delay distribution calculated by the statistical timing analysis unit;
The acquisition unit acquires data on a start point latch and an end point latch in the order of the pairs sorted by the sorting unit,
The determination unit according to claim 1, wherein the determination unit determines whether or not a signal change generated in the start point latch of the path can be propagated to the end point latch in the order of the pairs acquired by the acquisition unit. Delay analyzer.
(Additional remark 3) The said pair selection part represents each delay of each element which comprises a path | pass with one value, respectively, and delays a path | pass by performing each cumulative value calculation from the said start point latch toward the said end point latch. Supplementary note 2 characterized by selecting a path that can be a path in which signal propagation is delayed in the integrated circuit by using a static timing analysis for calculating a value, and selecting a pair of start and end latches of the path. The delay analysis device described.
(Additional remark 4) The said sort part calculates the standard deviation of each delay distribution calculated by the said statistical timing analysis part, and sorts from the one with the larger value obtained by integrating | accumulating a predetermined constant to this standard deviation. The delay analysis apparatus according to appendix 2, characterized by:
(Appendix 5) The computer
Get data about the start and end latches of the path that can be a path that delays signal propagation on the integrated circuit,
A hypothetical failure is set for each pin between the start point latch and the end point latch, and whether or not a signal change generated in the start point latch can be propagated to the end point latch is determined for each setting.
Statistical timing for calculating the delay distribution of the path by expressing the delay of each element constituting the path as a probability density function and cumulatively calculating the distribution expressed by the probability density function from the start point latch to the end point latch. A delay analysis method that executes a process of performing analysis so that the distribution is not cumulatively calculated in the subsequent stage at the pin when it is determined that the signal change cannot be propagated.
(Appendix 6) Furthermore,
Based on the design data of the integrated circuit held in the storage device, a plurality of pairs of data relating to the start point latch and end point latch of the path that can be a path in which signal propagation is delayed in the integrated circuit,
Statistical timing analysis is performed on the circuit between the start point latch and end point latch of the selected pair, and the delay distribution for each pair is calculated,
Based on the deviation of each calculated delay distribution, the computer executes a process of sorting the selected pairs,
The step of obtaining data relating to the start point latch and the end point latch obtains data relating to the start point latch and the end point latch in the order of the sorted pairs,
6. The delay analysis method according to claim 5, wherein the determining step determines whether or not a signal change generated in the start point latch of the path can propagate to the end point latch in the order of the acquired pair. .
(Supplementary note 7) The step of selecting a plurality of pairs of data related to the start point latch and end point latch represents the delay of each element constituting the path by one value, and each of the values is transferred from the start point latch to the end point latch. By using static timing analysis that calculates the delay value of the path by performing cumulative calculation toward the path, a path that can be a signal propagation delay in the integrated circuit is selected, and the start point latch and end point latch of the path are selected. The delay analysis method according to appendix 6, wherein a pair is selected.
(Additional remark 8) The said sorting step calculates the standard deviation of each calculated delay distribution, and sorts from the one with the larger value obtained by integrating | accumulating a predetermined constant to this standard deviation. The delay analysis method described.

(Supplementary Note 9) Acquire data on a start point latch and an end point latch of a path that can be a path in which signal propagation is delayed on an integrated circuit
A hypothetical failure is set for each pin between the start point latch and the end point latch, and whether or not a signal change generated in the start point latch can be propagated to the end point latch is determined for each setting.
Statistical timing for calculating the delay distribution of the path by expressing the delay of each element constituting the path as a probability density function and cumulatively calculating the distribution expressed by the probability density function from the start point latch to the end point latch. A delay analysis program that causes a computer to execute a process of performing an analysis so that the distribution is not cumulatively calculated at a later stage when it is determined that a signal change cannot be propagated.
(Appendix 10) Furthermore,
Based on the design data of the integrated circuit held in the storage device, a plurality of pairs of data relating to the start point latch and end point latch of the path that can be a path in which signal propagation is delayed in the integrated circuit,
Statistical timing analysis is performed on the circuit between the start point latch and end point latch of the selected pair, and the delay distribution for each pair is calculated,
Based on the deviation of each calculated delay distribution, let the computer execute the process of sorting the selected multiple pairs,
The step of obtaining data relating to the start point latch and the end point latch obtains data relating to the start point latch and the end point latch in the order of the sorted pairs,
The delay analysis program according to claim 9, wherein the determining step determines whether or not the signal change generated in the start point latch of the path can propagate to the end point latch in the order of the acquired pair. .
(Supplementary Note 11) The step of selecting a plurality of pairs of data relating to the start point latch and end point latch represents the delay of each element constituting the path by one value, and each of the values is transferred from the start point latch to the end point latch. By using static timing analysis that calculates the delay value of the path by performing cumulative calculation toward the path, a path that can be a signal propagation delay in the integrated circuit is selected, and the start point latch and end point latch of the path are selected. The delay analysis program according to appendix 10, wherein a pair is selected.
(Additional remark 12) The said sorting step calculates the standard deviation of each calculated delay distribution, and sorts from the one with the larger value obtained by adding a predetermined constant to this standard deviation. The delay analysis program described.

  1 cell library input unit, 2 design data input unit, 3, 8, 16 storage unit, 4, 9 memory data input unit, 5 static timing analysis unit, 6 critical path output unit, 7 critical path selection unit, 10 statistical Timing analysis unit, 11 delay distribution graph output unit, 12 delay distribution graph input unit, 13 test target path selection unit, 14 test target path output unit, 15 test target path input unit, 17 hypothetical failure setting unit, 18 delay test generation unit , 19 False path information output unit, 20 Timing yield calculation unit, 51 Cell library, 52 Processor design data, 53 Critical path information, 54 Delay distribution graph of each path, 55 Test target path information, 56 False path information, 57 Integrated circuit Timing yield distribution, 61 memory, 1 0 Delay analyzer 101 pair selection unit, 102 obtaining unit, 103 determination unit, 104 analyzer, 105 sorter.

Claims (7)

An acquisition unit for acquiring data related to a start point latch and an end point latch of a path that can be a path in which signal propagation is delayed on the integrated circuit;
A determination unit configured to set a hypothetical failure for each pin between the start point latch and the end point latch and determine whether a signal change generated in the start point latch can be propagated to the end point latch; ,
Statistical timing for calculating the delay distribution of the path by expressing the delay of each element constituting the path as a probability density function and cumulatively calculating the distribution expressed by the probability density function from the start point latch to the end point latch. An analysis unit that performs an analysis so that the distribution is not cumulatively calculated in the subsequent stage in the pin when it is determined that the signal change cannot be propagated by the determination unit;
A pair selection unit that selects a plurality of pairs of data related to the start point latch and end point latch of a path that can be a path in which signal propagation is delayed in the integrated circuit based on design data of the integrated circuit held in the storage device;
Statistical timing analysis is performed on a circuit between a start point latch and an end point latch of a pair selected by the pair selection unit, and a statistical timing analysis unit for calculating a delay distribution for each pair, and
A sorting unit that sorts a plurality of pairs selected by the pair selection unit based on a deviation of each delay distribution calculated by the statistical timing analysis unit;
The acquisition unit acquires data on a start point latch and an end point latch in the order of the pairs sorted by the sorting unit,
The delay analysis apparatus according to claim 1, wherein the determination unit determines whether or not a signal change generated in a start point latch of the path can propagate to an end point latch in the order of the pairs acquired by the acquisition unit. The pair selection unit represents a delay value of each element constituting a path by a single value, and calculates a delay value of the path by performing cumulative calculation from the start point latch to the end point latch. using static timing analysis, the integrated circuit in the signal propagation select the path that can be a path delay, according to claim 1, wherein selecting a start latch, the end point latch pair of the path delay Analysis device. The sorting unit calculates a standard deviation of each delay distribution calculated by the statistical timing analysis unit, and sorts from a larger value obtained by adding a predetermined constant to the standard deviation. The delay analysis apparatus according to claim 1 or 2 . Computer
Get data about the start and end latches of the path that can be a path that delays signal propagation on the integrated circuit,
A hypothetical failure is set for each pin between the start point latch and the end point latch, and whether or not a signal change generated in the start point latch can be propagated to the end point latch is determined for each setting.
Statistical timing for calculating the delay distribution of the path by expressing the delay of each element constituting the path as a probability density function and cumulatively calculating the distribution expressed by the probability density function from the start point latch to the end point latch. analyzing, by a pin when the signal change is determined to not be propagated have lines so as not to calculate the cumulative distribution downstream,
Based on the design data of the integrated circuit held in the storage device, a plurality of pairs of data relating to the start point latch and end point latch of the path that can be a path in which signal propagation is delayed in the integrated circuit,
Statistical timing analysis is performed on the circuit between the start point latch and end point latch of the selected pair, and the delay distribution for each pair is calculated,
Based on the deviation of each calculated delay distribution , execute the process of sorting the selected multiple pairs ,
The step of obtaining data relating to the start point latch and the end point latch obtains data relating to the start point latch and the end point latch in the order of the sorted pairs,
The delay analysis method according to any one of claims 1 to 4, wherein the determining step determines whether or not a signal change generated in the start point latch of the path can propagate to the end point latch in the order of the acquired pair . The step of selecting a plurality of pairs of data relating to the start point latch and end point latch represents the delay of each element constituting the path by one value, and cumulatively calculates each of the values from the start point latch to the end point latch. By using static timing analysis that calculates the delay value of the path by performing the above, a path that can be a signal propagation delay in the integrated circuit is selected, and a pair of start and end latches of the path is selected. The delay analysis method according to claim 4, wherein: Get data about the start and end latches of the path that can be a path that delays signal propagation on the integrated circuit,
A hypothetical failure is set for each pin between the start point latch and the end point latch, and whether or not a signal change generated in the start point latch can be propagated to the end point latch is determined for each setting.
Statistical timing for calculating the delay distribution of the path by expressing the delay of each element constituting the path as a probability density function and cumulatively calculating the distribution expressed by the probability density function from the start point latch to the end point latch. analyzing, by a pin when the signal change is determined to not be propagated have lines so as not to calculate the cumulative distribution downstream,
Based on the design data of the integrated circuit held in the storage device, a plurality of pairs of data relating to the start point latch and end point latch of the path that can be a path in which signal propagation is delayed in the integrated circuit,
Statistical timing analysis is performed on the circuit between the start point latch and end point latch of the selected pair, and the delay distribution for each pair is calculated,
Based on the deviation of each calculated delay distribution, let the computer execute the process of sorting the selected multiple pairs ,
The step of obtaining data relating to the start point latch and the end point latch obtains data relating to the start point latch and the end point latch in the order of the sorted pairs,
The delay analysis program characterized in that the determination step determines whether or not the signal change generated in the start point latch of the path can propagate to the end point latch in the order of the acquired pair . The step of selecting a plurality of pairs of data relating to the start point latch and end point latch represents the delay of each element constituting the path by one value, and cumulatively calculates each of the values from the start point latch to the end point latch. By using static timing analysis that calculates the delay value of the path by performing the above, a path that can be a signal propagation delay in the integrated circuit is selected, and a pair of start and end latches of the path is selected. The delay analysis program according to claim 6 .

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