JP5377195B2 - Electroless copper plating solution, electroless copper plating method, and method for forming embedded wiring - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electroless copper-plating solution which can form an electroless copper-plated layer that is uniform even into the bottom of the hole regardless of the size of the inner diameter of the hole, an electroless copper-plating method, and a method for forming an embedded wiring, which can form reliable embedded wiring in the inner part of the hole by forming the electroless-copper-plated layer. <P>SOLUTION: The electroless copper-plating solution contains a polyethylene glycol compound having a thiol group or a disulfide bond, and copper ions. Further, the electroless copper-plating method is characterized in that a substrate 1 with a hole 2 formed is dipped into the electroless copper-plating solution to form an electroless-copper-plated layer 6 at the inside of the hole. Further, the method for forming of embedded wiring is characterized in the substrate 1 with the hole 2 formed is dipped into the electroless copper-plating solution to form embedded wiring made of the electroless-copper-plated layer 6 at the inside of the hole. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to an electroless copper plating solution, an electroless copper plating method, and a method for forming an embedded wiring.

Semiconductor chips mounted on electronic devices are required to have higher density in order to cope with problems such as space saving of mounting area and improvement of processing speed.
A three-dimensional semiconductor chip is known as an example of a high-density semiconductor chip (for example, Patent Document 1).
That is, the three-dimensional semiconductor chip is a technique in which a plurality of semiconductor chips are stacked and the stacked semiconductor chips are interconnected to increase the density of the integrated circuit. Since each semiconductor chip used for such a three-dimensional semiconductor chip needs to be conductive on both sides of the chip substrate, conventionally, for example, a hole is provided in the semiconductor chip, and a conductive member is provided in the through hole. An embedded wiring formed by embedding is used.

  As a specific method for forming such embedded wiring, for example, a barrier film such as tantalum nitride is formed on the entire substrate in which holes are formed, and then a plating catalyst made of palladium is deposited on the barrier film, Then, the method of forming an electroless copper plating layer in the inside of the said hole by immersing in an electroless copper plating bath is disclosed (patent document 2).

  However, according to the prior art as described above, in order to form a uniform electroless copper plating layer to the depth of the hole, the inner diameter of the hole needs to be at least 10 μm, and the inner diameter becomes 10 μm. When electroless copper plating is performed on a hole that does not satisfy, there is a problem that it is difficult to form the electroless copper plating layer uniformly to the back of the hole.

In addition, a method of embedding tungsten in the hole by a CVD method has been studied (see Non-Patent Document 1).
However, since the electrical resistivity of tungsten is as high as about 20 μΩcm, and a high temperature process of about 400 ° C. is required when filling tungsten by CVD, a manufacturing process and a manufacturing apparatus for mass production are required. There was a problem of becoming a big deal.

JP 2003-203914 A WO2005 / 038088

Through Silicon Via Technologies for Extreme miniatulized 3D Integrated Wireless Sensor SYSTEMS (e-CUBES), Peter Ramm, and Arminn Klumpp, IEEE IITC 2008, pp.7-9.

In view of the above-described problems of the prior art, the present invention provides an electroless copper plating solution and an electroless copper capable of forming a uniform electroless copper plating layer to the depth of the hole regardless of the inner diameter of the hole. An object is to provide a plating method.
Further, the present invention provides a buried wiring capable of forming a uniform electroless copper plating layer to the depth of the hole regardless of the inner diameter of the hole and forming a highly reliable buried wiring inside the hole. Another object of the present invention is to provide a forming method.

  In order to solve the above problems, the present invention provides an electroless copper plating solution containing a polyethylene glycol compound having a thiol group or a disulfide bond, and copper ions.

  According to the electroless copper plating solution according to the present invention, by using an electroless copper plating solution containing a polyethylene glycol compound having a thiol group or a disulfide bond, the electroless copper plating solution is relatively uniformly electroless from the hole entrance to the back. There is an effect that a copper plating layer is formed.

  Further, the present invention is an electroless copper plating method characterized by immersing a substrate having holes formed in the above electroless copper plating solution and forming an electroless copper plating layer inside the holes, And a method of forming an embedded wiring, comprising: dipping a substrate having holes formed in the electroless copper plating solution as described above to form an embedded wiring made of an electroless copper plating layer inside the holes. provide.

  According to the electroless copper plating method and the embedded wiring forming method according to the present invention, by using an electroless copper plating solution containing a polyethylene glycol compound having a thiol group or a disulfide bond, the inner diameter of the hole formed in the substrate Regardless of the size, there is an effect that the electroless copper plating layer is formed with a relatively uniform thickness from the entrance to the back of the hole, and the formed electroless copper plating layer is particularly suitable for embedded wiring can do.

As described above, according to the electroless copper plating solution and the electroless copper plating method according to the present invention, it is possible to form a uniform electroless copper plating layer up to the depth of the hole regardless of the inner diameter of the hole. It becomes.
Further, according to the method for forming a buried wiring according to the present invention, a uniform electroless copper plating layer is formed to the depth of the hole regardless of the inner diameter of the hole. High embedded wiring can be formed.

  Furthermore, according to the present invention, a copper plating layer having excellent conductivity and a buried wiring are formed by an electroless process at a relatively low temperature of at most 100 ° C. without requiring a high temperature process such as a CVD method. It becomes possible.

The manufacturing process figure which showed one Embodiment of the electroless copper plating method which concerns on this invention. The manufacturing process figure which showed other embodiment of the electroless copper plating method which concerns on this invention. 2 is a cross-sectional image of an electroless copper plating layer obtained in Example 1. FIG. 2 is a cross-sectional image of an electroless copper plating layer obtained in Example 2. FIG. 4 is a cross-sectional image of an electroless copper plating layer obtained in Example 3. FIG. 4 is a cross-sectional image of an electroless copper plating layer obtained in Example 4. FIG. The cross-sectional image of the electroless copper plating layer obtained in Comparative Example 1. The cross-sectional image of the electroless copper plating layer obtained in Comparative Example 2.

  Specifically, the polyethylene glycol compound used in the present invention includes a polyethylene glycol compound containing a thiol group represented by the following general formula (1), or a disulfide bond represented by the following general formula (2). It has a polyethylene glycol compound.

_{^{HS-R 1 - (OC 2}} H 4) n -OR 2 ··· (1)

(Wherein R ¹ is alkyl having 1 to 20 carbon atoms, R ² is either hydrogen or an alkyl group having 1 to 5 carbon atoms and having a substituent, and n is an integer of 2 or more. And examples of the substituent include a hydroxyl group, a carboxyl group, a halogen atom, an alkoxy group, a nitro group, a cyano group, and a carbonyl group.

R ² O— (C ₂ H ₄ O) _n —R ¹ —S—S—R ¹ — (OC ₂ H ₄ ) _n —OR ² (2)

(Here, R ¹ , R ² , and n are as defined in the above formula (1).)

Specific examples of these polyethylene glycol compounds include
(1-mercapto-11-undecyl) tri (ethylene glycol) [HSC ₁₁ H ₂₂ (OC ₂ H ₄ ) ₆ OH], (1-mercapto-11-undecyl) tetra (ethylene glycol) [HSC ₁₁ H ₂₂ (OC ₂ H ₄ ) ₄ OH], (1-mercapto-11-undecyl) hexa (ethylene glycol) [HSC ₁₁ H ₂₂ (OC ₂ H ₄ ) ₃ OH], methoxy-tri (ethylene glycol) undecanethiol [HSC ₁₁ H ₂₂ (OC ₂ H ₄ ) ₃ OCH ₂ COOH], methoxy-tetra (ethylene glycol) undecanethiol [HSC ₁₁ H ₂₂ (OC ₂ H ₄ ) ₆ OCH ₃ ], methoxy-hexa (ethylene glycol) undecanethiol [HSC ₁₁ H ₂₂ (OC ₂ H ₄ ) ₄ OCH ₃ ], carboxy-tetra (ethylene glycol) undecanethiol [HSC ₁₁ H ₂₂ (OC ₂ H ₄ ) ₃ OCH ₃ ], tetra (ethylene glycol) undecyl disulfide [(-SC ₁₁ H ₂₂ (OC ₂ H ₄ ) ₄ OH) ₂ ] The

  The molecular weight of the polyethylene glycol compound is not particularly limited, but is preferably less than 1000, more preferably 350 to 800.

  The concentration of the polyethylene glycol compound is not particularly limited, but is preferably 0.05 mass ppm or more and 5.0 mass ppm or less, preferably 0.1 mass ppm or more and 2.0 mass ppm. More preferably, it is ppm or less. When the concentration of the polyethylene glycol compound exceeds 5.0 ppm by mass, the plating suppression effect becomes too strong and the copper thickness may be reduced.

  Moreover, about components other than the said polyethylene glycol compound in this electroless copper plating liquid, the well-known thing conventionally used for the electroless plating of copper can be used. That is, the electroless copper plating solution generally contains a soluble copper salt as a copper ion source, a copper ion complexing (chelating) agent, and a reducing agent, and further contains necessary additives, and has a pH value. Is an aqueous solution adjusted to about 12-13.

  As a copper salt which is a copper ion source, any copper salt may be used as long as it can generate copper ions when dissolved in water. For example, copper sulfate, copper nitrate, copper chloride, copper bromide, copper oxide, copper hydroxide, Examples include copper pyrophosphate.

  Any complexing agent for copper ions may be used as long as it can form a complex with copper ions. Examples thereof include oxycarboxylic acids such as lactic acid, malic acid, tartaric acid, citric acid, and gluconic acid, or salts thereof, nitrilotriacetic acid. , Ethylenediaminetetraacetic acid (EDTA), hydroxyethylethylenediaminetriacetic acid, diethylenetriaminepentaacetic acid, triethylenetetraminehexaacetic acid, 1,3-propanediaminetetraacetic acid, hydroxyethyliminodiacetic acid, dihydroxyethylglycine, glycol etherdiaminetetraacetic acid, asparagine Examples thereof include aminocarboxylic acids such as acid diacetic acid, methylglycine diacetic acid, glutamic acid diacetic acid and ethylenediamine disuccinic acid or salts thereof, triethanolamine, and glycerin.

  Examples of the reducing agent include those capable of reducing copper ions, such as formaldehyde, paraformaldehyde, dimethylamine borane, borohydride, glyoxylic acid, reducing sugar, and divalent cobalt ions.

  Additives are used for purposes such as improving the properties of the electroless copper plating layer, improving the stability of the solution accompanying continuous use of the electroless copper plating solution, improving the plating deposition rate, or suppressing fluctuations in the plating deposition rate. Accordingly, a surfactant, a stabilizer, a pH adjuster and the like are appropriately added.

  Specific examples of the surfactant include polyethylene glycol (PEG), polypropylene glycol, polyethylene glycol monomethyl ether, polyethylene glycol dimethyl ether, and polyacrylic acid.

  Examples of the stabilizer include bipyridyl (pyridyl derivative), a cyanide compound, an organic nitrile phenanthroline, and picinoline.

  Examples of the pH adjuster include sodium hydroxide, tetramethylammonium hydroxide (TMAH), potassium hydroxide, ammonia and the like.

  In addition, when performing electroless copper plating, conditions such as pH and temperature can be appropriately selected according to the physical properties of the object to be plated. As a specific example of preferable conditions, pH 12 to 12.8, A temperature of 60 to 80 ° C. and an immersion time of 30 to 90 minutes can be mentioned.

  The electroless copper plating method according to the present invention can be carried out by immersing a substrate having holes formed therein in an electroless copper plating solution having the above-described configuration and conditions.

FIG. 1 is a manufacturing process diagram showing a first embodiment when an embedded wiring is formed in a silicon substrate by applying one embodiment of the electroless copper plating method according to the present invention.
As shown in FIG. 1, the embedded wiring forming method of the present embodiment is mainly a first step of forming a hole 2 such as a through via in the silicon substrate 1 by reactive ion etching or the like (FIG. 1A). ), A second step (FIG. 1 (c)) for forming the base treatment layer 5 on the silicon substrate 1 in which the hole 2 is formed, and the silicon substrate 1 in which the base treatment layer 5 is configured as an electroless copper plating solution A third step (FIG. 1 (d)) for forming the electroless copper plating layer 6 by immersing in the substrate, a fourth step (FIG. 1 (e)) for polishing and thinning the back surface of the silicon substrate 1, and a back surface A fifth step (FIG. 1 (f)) for forming the bump 7 on the hole 2 penetrating to the side, a sixth step (FIG. 1 (g)) for sputtering a metal film on the front side, and a first step for patterning the surface. 7 steps (FIG. 1 (h)) and an eighth step (FIG. 1 (i)) for forming bumps 7 on the front side of the through holes. To have.

As a 1st process (FIG. 1 (a)) which forms the hole 2 (via), it can employ | adopt suitably from a conventionally well-known method. Specifically, for example, as a dry etching technique, a general-purpose technique using a fluorine-based or chlorine-based gas or the like can be applied. In particular, a hole having a large aspect ratio (hole depth / hole diameter) is formed. Can adopt the method which adopted the technique of ICP-RIE (Inductively Coupled Plasma Reactive Ion Etching: Inductively Coupled Plasma-Reactive Ion Etching) capable of high-speed deep etching, more particularly, sulfur hexafluoride ( A method called a Bosch process in which an etching step using SF ₆ ) and a protection step using a fluorocarbon gas such as C ₄ F ₈ are repeated can be suitably employed.

  According to the present invention, even a hole having a small diameter and a high aspect ratio can form a uniform copper plating layer all the way to the back. For example, the diameter is 1 to 10 μm and the aspect ratio is 5 to 10 A hole is preferable, and in particular, a hole having a diameter of 2 to 6 μm and an aspect ratio of 10 to 30 is more preferable.

As a pretreatment for forming the base treatment layer 5, it is preferable that a coupling agent 4 such as a silane coupling agent is adsorbed on the surface of the SiO ₂ layer 3 (FIG. 1B). Formation of the layer 5 is facilitated.

As the second step (FIG. 1C) for forming the base treatment layer 5, a process for depositing a metal film capable of displacement plating or a catalyst adsorption process can be employed.
As a process for depositing a metal film capable of displacement plating, Ni, Co, WNi, WCo are formed by a method of forming a base treatment layer made of W, WN, Ta, TaN or the like by a CVD method, or by an electroless plating method. , Or an alloy containing another metal such as P (phosphorus) or B (boron) (for example, Ni—WP alloy, Ni—WB alloy, Co—WP alloy, And a method of forming a base treatment layer made of a Co—W—B alloy or the like.

  On the other hand, as the catalyst adsorption treatment, for example, a treatment in which a sample is immersed in an aqueous palladium chloride solution to adsorb Pd ions serving as a catalyst to the surface can be employed. Specifically, it is immersed in a tin chloride solution to adsorb tin ions on the surface, then immersed in an aqueous palladium chloride solution to replace tin ions with Pd ions to adsorb Pd ions, and further immersed in sodium hydroxide Then, the catalyst adsorption treatment is performed by a series of steps of removing excess tin ions.

  The third step (FIG. 1 (d)) for forming the electroless copper plating layer 6 is performed by immersing in the electroless copper plating solution having the above-described configuration under the pH and temperature conditions as described above. Through the process, the electroless copper plating layer 6 is formed in the substantially entire inner area of the hole 2.

  The fourth step (FIG. 1 (e)) for polishing and thinning the back surface of the silicon substrate 1 is a process of thinning until the hole 2 is exposed on the back surface side and penetrates, In addition to the polishing method, various etching methods can be employed.

  In the fifth step (FIG. 1 (f)), bumps 7 are formed on the holes 2 penetrating the back surface. The bumps 7 are formed in a protruding state on the back surface of the silicon substrate 1, and the surface thereof is formed in a substantially spherical shape. The bumps are formed by a printing method or the like.

  On the other hand, on the front side, after the metal film 8 is sputtered by the sixth step (FIG. 1 (g)), the surface is etched by leaving the predetermined pattern by the seventh step (FIG. 1 (h)). A pattern is formed.

  Further, the bump 7 is formed on the upper front side of the through hole 2 through the eighth step (FIG. 1I).

  Such a method of forming a buried wiring according to the first embodiment is suitable when the diameter of the hole 2 is approximately 2 μm or less. When the diameter of the hole 2 exceeds about 5 μm, the embedded wiring forming method of the second embodiment as described below is suitable.

  FIG. 2 is a manufacturing process diagram illustrating a method for forming embedded wiring according to the second embodiment. As shown in FIG. 2, in the second embodiment, a first step (FIG. 2A) of forming a hole 2 such as a through via in the silicon substrate 1 by reactive ion etching or the like, and a hole 2 2nd process (FIG.2 (c)) which forms the base processing layer 5 in the silicon substrate 1 in which this was formed, and the silicon substrate 1 in which the base processing layer 5 was comprised were immersed in electroless copper plating solution, and electroless 3rd process (FIG.2 (d)) which forms the copper plating layer 6, 4th process (FIG.2 (e)) which embeds Cu in the hole 2 by electrolytic copper plating, and the back surface of the silicon substrate 1 is grind | polished. The fifth step (FIG. 2 (f)) for thinning the film, the sixth step (FIG. 1 (g)) for forming the bump 7 on the hole 2 penetrating the back surface, and the seventh step for patterning the surface. The process (FIG. 2 (h)) and the 8th process (FIG. 2 (i)) which forms the bump 7 in the front side of a through-hole are provided.

  Here, in 2nd embodiment, the 1st process (FIG.2 (a)) which forms the hole part 2, the 2nd process (FIG.2 (c)) which forms the base treatment layer 5, the electroless copper plating layer 6 A third step (FIG. 2 (d)) for forming, a fifth step (FIG. 2 (f)) for polishing the back surface of the silicon substrate 1 to form a thin film, and bumps 7 on the holes 2 penetrating the back surface side. A sixth step (FIG. 1 (g)) to be formed, a seventh step (FIG. 2 (h)) for patterning the surface, and an eighth step (FIG. 2 (i)) for forming bumps 7 on the front side of the through holes. Since is the same as in the first embodiment, the description thereof is omitted.

  The fourth step (FIG. 2 (e)) is a step of embedding Cu in the hole 2 by electrolytic copper plating, but the electroless copper plating layer 6 is formed by the third step (FIG. 2 (d)) before that. Since it is formed, the electroless copper plating layer 6 becomes a seed layer, and the electrolytic copper plating layer 9 is formed. Therefore, when the electroless copper plating is performed using the electroless copper plating solution having the above-described configuration, the electroless copper plating layer 6 is uniformly formed to the depth of the hole 2. It is formed so as to be buried almost completely up to the back of the hole 2.

  As described above, in both cases of the first embodiment and the second embodiment, the embedded wiring is surely formed in the through via having a high aspect ratio.

  In the above embodiment, the case where the through via hole having the embedded wiring is formed in the silicon substrate has been described. However, the present invention is not limited to this, and for example, the hole is formed in an insulating layer made of another insulating material. It can also be applied to the formation of buried wiring on the inside of a film or trench, etc., or to the formation of a conductive film with a uniform film thickness on the surface of various materials having severe irregularities on the micrometer scale. it can.

  In addition, an unillustrated transistor, a memory element, an integrated circuit including other electronic elements, and the like can be formed on a semiconductor substrate made of silicon by a known method.

  According to the method for forming a buried wiring according to the present invention, a copper buried wiring excellent in conductivity can be formed with a uniform thickness up to the inside of a through via hole having a diameter of several μm and a high aspect ratio. Therefore, the present invention can be particularly preferably employed in the field of manufacturing a three-dimensional semiconductor integrated circuit device in which, for example, semiconductor integrated circuits are stacked, which can contribute to further increase in the density of the semiconductor integrated circuit and can be mounted. A highly reliable semiconductor integrated circuit device can be manufactured.

Example 1
A hole having a diameter of about 4 μm and a depth of about 40 μm (that is, an aspect ratio of about 20) is formed in a silicon substrate by an Bosch process using an etching apparatus manufactured by Samco International, and then a tungsten base treatment film is formed by CVD. Then, it was immersed in an electroless copper plating solution having the following configuration and conditions to form an electroless copper plating layer.

-Composition of electroless copper plating solution Copper sulfate: 6.4 g / L
Glyoxylic acid: 18 g / L
EDTA: 70 g / L
PEG (molecular weight 4000): 500 mass ppm
Polyethylene glycol compound A (tetra (ethylene glycol) undecyl disulfide molecular weight 759): 0.5 mass ppm
・ Immersion conditions Temperature: 70 ℃
Immersion time: 90 minutes pH: 12.5 (adjusted with TMAH)

(Example 2)
Electroless copper plating was performed in the same manner as in Example 1 except that a hole having a diameter of about 8 μm and a depth of about 40 μm (that is, an aspect ratio: about 5) was formed on the silicon substrate.

(Example 3)
The electroless copper plating solution was subjected to electroless copper plating in the same manner as in Example 1 except that one having the following composition was used.
-Composition of electroless copper plating solution Copper sulfate: 6.4 g / L
Glyoxylic acid: 18 g / L
EDTA: 70 g / L
PEG (molecular weight 4000): 500 mass ppm
Polyethylene glycol compound B (carboxy-tetra (ethylene glycol) undecanethiol molecular weight 394): 0.5 mass ppm

Example 4
Electroless copper plating was performed in the same manner as in Example 3 except that a hole having a diameter of about 8 μm and a depth of about 40 μm (that is, aspect ratio: about 5) was formed on the silicon substrate.

(Comparative Example 1)
The electroless copper plating solution was subjected to electroless copper plating in the same manner as in Example 1 except that one having the following composition was used.
-Composition of electroless copper plating solution Copper sulfate: 6.4 g / L
Glyoxylic acid: 18 g / L
EDTA: 70 g / L
PEG (molecular weight 4000): 500 mass ppm
Polyethylene glycol compound: None

(Comparative Example 2)
Electroless copper plating was performed in the same manner as in Comparative Example 1 except that a hole having a diameter of about 8 μm and a depth of about 40 μm (that is, an aspect ratio: about 5) was formed on the silicon substrate.

About an Example and a comparative example, the electroless copper plating solution composition and the diameter of a hole are shown in the following Table 1.

3 to 8 show images obtained by photographing the cross section of the vicinity of the holes of the electroless copper plating layer obtained in Examples and Comparative Examples with a FIB (Focused Ion Beam) apparatus.
As shown in FIGS. 3 to 8, in Examples 1 to 4, the entrance of the hole was not blocked, and copper was deposited with a substantially uniform film thickness from the entrance to the back of the hole.

  On the other hand, in the case of Comparative Examples 1 and 2 shown in FIG. 7 and FIG. 8, the copper deposition thickness differs greatly between the hole entrance and the back, and a copper plating layer having a uniform thickness is not formed. Admitted.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Hole 3 Oxide film 4 Coupling agent layer 5 Barrier layer 6 Electroless copper plating layer 7 Bump 8 Metal sputter film 9 Electrolytic copper plating layer

Claims (4)

  An electroless copper plating solution comprising a polyethylene glycol compound having a thiol group or a disulfide bond, and copper ions.   2. The electroless copper plating solution according to claim 1, wherein the polyethylene glycol compound has a molecular weight of 350 to 800.   3. An electroless copper plating method comprising immersing a substrate having holes formed in the electroless copper plating solution according to claim 1 or 2 to form an electroless copper plating layer inside the holes.   A buried wiring comprising immersing a substrate in which holes are formed in the electroless copper plating solution according to claim 1 or 2 and forming an embedded wiring made of an electroless copper plating layer inside the holes. Forming method.

Images