JP5360153B2 - Surge detection circuit for sensors - Google Patents

Description

The present invention relates to a sensor surge detection circuit for detecting a surge output from a sensor.
In recent years, sensors have been used in various fields, and the sensor output has become minute with the miniaturization of the sensor, so that it is used in combination with a detection circuit that detects the sensor output. Some sensors generate a surge due to stress or a sudden temperature change, and therefore it is necessary to prevent the next stage damage due to the surge.

  FIG. 6 shows a conventional example of a sensor output detection circuit provided with a surge protection circuit. The output signal of the sensor 1 is output to the next stage circuit through the input stage amplifiers 2a and 2b mounted in the chip, respectively.

  Surge protection circuits are connected to the input terminals of the input stage amplifiers 2a and 2b, respectively. The surge protection circuit includes a diode D1 connected to the high potential side power supply VDD with the input terminal side as an anode, and a diode D2 connected to the low potential side power supply GND with the input terminal side as a cathode.

  The high potential side surge applied from the sensor 1 to the input terminal is absorbed by the high potential side power supply VDD via the diode D1, and the low potential side surge applied from the sensor 1 to the input terminal via the diode D2. Is absorbed by the low potential side power supply GND. Such an operation protects the input stage amplifiers 2a and 2b.

Patent Document 1 discloses a configuration for preventing malfunction and destruction of a single pulse input such as a surge in a horizontal deflection circuit of a television receiver.
Patent Document 2 discloses a configuration in which pulses are detected by a pulse detection circuit and supplied to a level holding circuit together with an input signal through a pulse stretching circuit in order to prevent malfunction due to noise such as static electricity or surge. Yes.

JP-A-6-303445 (FIG. 2) JP 2004-23576 A

  The surge protection circuit as described above usually has only a slight surge absorption capability in order to prevent the output voltage of the sensor 1 from being very small and the increase in parasitic capacitance at the input terminals of the input stage amplifiers 2a and 2b. Is connected.

  On the other hand, the sensor 1 may output a surge of several tens V to hundreds of V in a minute time due to stress or a rapid temperature change, and such a surge protection circuit absorbs such a sharp surge. I can't. Therefore, the input stage amplifiers 2a and 2b and the circuit of the next stage may be deteriorated in characteristics or permanently destroyed.

Patent Documents 1 and 2 do not disclose a configuration for preventing a decrease in reliability due to deterioration of internal IC characteristics due to a surge.
SUMMARY OF THE INVENTION An object of the present invention is to provide a sensor surge detection circuit that determines deterioration in characteristics inside a chip due to a surge input from a sensor outside the chip and outputs a warning signal.

The above object is achieved by a surge detecting circuit connected to the input terminal sensor, the input circuit connected to an input terminal, connected to said input terminal, an input for comparison with the same circuit configuration as the input circuit a circuit detects the level difference between the output signal of the comparator input circuit and an output signal of said input circuit, and a level difference detection circuit for outputting a detection signal, when the level difference is a predetermined value or more, the and a control unit for outputting a warning signal on the basis of the detection signal, and a memory circuit for storing a correction value for correcting the operating characteristics of said input circuit, said control unit, said control unit, said detection signal wherein the memory circuit reads out the correction value is accomplished by read on the basis of the correction value to correct the operation characteristics of the entering force circuit Rousset capacitors for surge detection circuit based.

  ADVANTAGE OF THE INVENTION According to this invention, the surge detection circuit for sensors which outputs the warning signal by determining the characteristic deterioration inside a chip | tip by the surge input from the sensor outside a chip | tip can be provided.

It is a circuit diagram showing a first embodiment. It is a circuit diagram which shows 2nd embodiment. It is a circuit diagram which shows 3rd embodiment. It is a circuit diagram which shows 4th Embodiment. It is a circuit diagram which shows 5th embodiment. It is a circuit diagram which shows a prior art example.

(First embodiment)
FIG. 1 shows a first embodiment of a sensor output detection circuit embodying the present invention. The input terminal T of the chip is connected to the input circuit 11, and the sensor output signal Vs input to the input terminal T is output to the next stage via the input circuit 11.

  A surge protection circuit 12 is connected to the input terminal T. The surge protection circuit 12 includes a diode D1 connected to the high potential power supply VDD with the input terminal T side as an anode, and a diode D2 connected to the low potential power supply GND with the input terminal T side as a cathode. The operation is the same as in the conventional example.

A surge detector is connected to the input terminal T. The surge detection device includes a surge detection unit 13, a counter 14, a memory circuit 15, and a control unit 16.
When the surge detector 13 detects a surge exceeding a predetermined value at the input terminal T, the surge detector 13 outputs a pulse signal to the counter 14. The counter 14 accumulates input pulse signals and outputs the accumulated value to the memory circuit 15.

The memory circuit 15 includes a non-volatile memory and stores the accumulated value output from the counter 14.
A controller 16 is connected to the memory circuit 15. Then, the control unit 16 reads the accumulated value stored in the nonvolatile memory, and outputs a warning signal A when the accumulated value reaches a preset warning setting value. The warning signal A is output from, for example, an external pin to a microcomputer chip.

  In the surge detection device configured as described above, the surge input to the input terminal T is detected by the surge detection unit 13, and the number of detections is accumulated by the counter 14 and stored in the memory circuit 15. When the accumulated value stored in the memory circuit 15 reaches the warning set value, the warning signal A is output from the control unit 16.

In the sensor output detection circuit including the surge detection device as described above, the following operational effects can be obtained.
(1) When a surge is input to the input circuit 11, the number of surge inputs is accumulated in the surge detector 13 and the memory circuit 15, and when the accumulated value reaches the warning set value, a warning signal A is output. Can do. Therefore, it can be recognized from the warning signal A that the input circuit 11 or the circuit at the next stage may be deteriorated.
(2) Since the memory circuit 15 is equipped with a non-volatile memory, the stored accumulated value can be held even if the power supply of the sensor output detection circuit is shut off. Therefore, it is possible to accurately detect the accumulated value from the start of use of the sensor output detection circuit regardless of whether the sensor output detection circuit is powered off or not.
(3) When a non-volatile memory for other uses is mounted on a chip on which the sensor output detection circuit is mounted, the non-volatile memory can be used as the memory circuit 15.
(Second embodiment)
FIG. 2 shows a second embodiment. In this embodiment, a timer circuit 17 is connected to the surge detector 13, and other configurations are the same as those in the first embodiment. The same components as those in the first embodiment will be described with the same reference numerals.

  The timer circuit 17 operates the surge detector 13 within a predetermined time range set in advance. Then, the memory circuit 15 stores the cumulative value of the number of surge detections within a predetermined time set by the timer circuit 17. When the accumulated value reaches the warning set value, a warning signal A is output from the control unit 16.

Therefore, when the number of surge detections reaches the warning set value within the time set by the timer circuit 17, the warning signal A can be output.
(Third embodiment)
FIG. 3 shows a third embodiment. In this embodiment, a plurality of input circuits are connected in parallel, and when the number of surge detections reaches a predetermined number, the input circuits are switched and used. The same components as those in the first embodiment will be described with the same reference numerals.

  The input circuits 18 a and 18 b are connected in parallel between the input terminal T and the next stage circuit 19, and switches 20 a to 20 d are disposed between the input terminal T and the next stage circuit 19, respectively. The switches 20a to 20d are controlled to be opened and closed by the control unit 21.

  That is, when the sensor output detection circuit is activated, the switches 20a and 20b are closed and the switches 20c and 20d are opened. In this state, the surge is counted by the counter 14, and when the cumulative value reaches the first set value, the control unit 21 opens the switches 20a and 20b and closes the switches 20c and 20d. The first set value is a value that may cause characteristic degradation in the input circuit 18a due to repeated input of surges.

  After the switches 20c and 20d are closed, the surge is further counted by the counter 14, and when the accumulated value reaches the second set value, the control unit 21 opens the switches 20c and 20d. Then, a warning signal A is output from the control unit 21.

With such a configuration, in addition to the operational effects obtained in the first embodiment, since the input circuits 18a and 18b are switched and used, it is possible to obtain an operational effect that can extend the life of the input circuit. it can.
(Fourth embodiment)
FIG. 4 shows a fourth embodiment. This embodiment is provided with a comparison input circuit for detecting characteristic deterioration of the input circuit due to a surge. The same components as those in the first embodiment will be described with the same reference numerals.

  The input circuit 11 and the comparison input circuit 22 are connected to the input terminal T. Output signals of the input circuit 11 and the comparison input circuit 22 are input to the level difference detection circuit 23. The level difference detection circuit 23 detects the level difference between the output signals of both the input circuits 11 and 22 and outputs the detected value to the control unit 24.

The control unit 24 detects that the characteristic deterioration has occurred in the input circuit 11 and outputs a warning signal A when the input detection value becomes a predetermined value or more.
The comparison input circuit 22 attenuates the surge by increasing the distance from the input terminal T, for example, so that the characteristic deterioration due to the surge does not occur.

With such a configuration, it is possible to detect the characteristic deterioration of the input circuit 11 and output the warning signal A. Further, since the comparison input circuit 22 and the level difference detection circuit 23 having the same configuration as the input circuit 11 can detect characteristic deterioration of the input circuit 11 as compared with the first embodiment, the memory circuit 15 Even a chip that does not have the function can detect the characteristic deterioration and output the warning signal A.
(Fifth embodiment)
FIG. 5 shows a fifth embodiment. This embodiment has a function of correcting the characteristics of the input circuit 11 based on the output signal of the level difference detection circuit 23 of the fourth embodiment. The same components as those in the fourth embodiment will be described with the same reference numerals.

  The output signal of the level difference detection circuit 23 is output to the control unit 25. A memory circuit 26 is connected to the control unit 25. The memory circuit 26 is composed of a nonvolatile memory, and stores a correction table for correcting the gain or offset value of the input circuit 11 according to the level difference between the output signals of the input circuit 11 and the comparison input circuit 22. .

  The control unit 25 reads the correction value from the memory circuit 26 based on the output signal of the level difference detection circuit 23, adjusts the gain or offset value of the input circuit 11 according to the correction value, and the input circuit 11 and the comparison input The circuit 22 operates so as to reduce the level difference between the output signals of the circuit 22.

  If the level difference between the output signals of the input circuit 11 and the comparison input circuit 22 exceeds a predetermined value even after the gain or offset value adjustment processing of the input circuit 11 is performed, the control unit 25 outputs the warning signal A. Is output.

  With such a configuration, in addition to the operational effects obtained in the fourth embodiment, the control unit 25 adjusts the gain or offset value of the input circuit 11 so as to correct the characteristic deterioration of the input circuit 11. Therefore, the life of the input circuit 11 can be extended.

You may implement the said embodiment in the following aspects.
The timer circuit 17 of the second embodiment may be provided in the third embodiment.
In the third embodiment, a larger number of input circuits may be connected in parallel to be switchable.

DESCRIPTION OF SYMBOLS 11 Input circuit 22 Comparison input circuit 23 Level difference detection circuit 24, 25 Control part 26 Memory circuit T Input terminal A Warning signal

Claims (2)

A surge detection circuit for a sensor connected to an input terminal,
An input circuit connected to the input terminal;
A comparison input circuit connected to the input terminal and having the same circuit configuration as the input circuit;
By detecting the level difference between the output signal of the output signal and the comparison input circuit of the input circuit, and a level difference detection circuit for outputting a detection signal,
A control unit that outputs a warning signal based on the detection signal when the level difference is greater than or equal to a predetermined value ;
And a memory circuit for storing a correction value for correcting the operating characteristics of said input circuit,
Wherein the control unit, sensor, wherein said on the basis of the detection signal reading said correction value from said memory circuit, Turkey to correct the operating characteristics of the entering force circuit based on the correction value read out Surge detection circuit. The sensor surge detection circuit according to claim 1 , wherein the memory circuit includes a nonvolatile memory.

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