JP5356371B2 - Semiconductor device manufacturing method characterized by gate stressor and semiconductor device - Google Patents

Description

  This disclosure relates generally to semiconductor devices, and more particularly to a method of forming a semiconductor device featuring a gate stressor and a semiconductor device.

  Current NMOS process-induced stressors such as tensile etch stop layer (ESL) or embedded silicon carbon (eSiC) are (i) relatively weak and unable to scale to small pitches, or (ii) either Cannot be easily manufactured. In addition, current NMOS process induction stressors induce significant stress in longer channel devices such as non-volatile memory (NVM), power or analog devices.

  Accordingly, there is a need for improved methods and apparatus to overcome the problems in the prior art as described above.

1 is a partial cross-sectional view of a portion of a semiconductor device at a stage during manufacture, the device featuring a metal gate stressor according to an embodiment of the invention. FIG. 2 is a plan view of a part of the semiconductor device of FIG. 1. FIG. 2 is a partial cross-sectional view of a portion of the semiconductor device of FIG. 1 at another stage during manufacture. FIG. 4 is a partial cross-sectional view of a portion of the semiconductor device of FIG. 3 at yet another stage during manufacture. FIG. 5 is a plan view of a part of the semiconductor device of FIG. 4. FIG. 6 is a partial cross-sectional view of a portion of the semiconductor device of FIGS. 4 and 5 at an implant stage during manufacture. FIG. 7 is a partial cross-sectional view of a portion of the semiconductor device of FIG. 6 at an annealing stage during manufacture. FIG. 8 is a partial cross-sectional view of a portion of the semiconductor device of FIG. 7 at yet another stage during manufacture, the semiconductor device featuring a metal gate stressor according to an embodiment of the present invention. FIG. 2 is a partial cross-sectional view of a portion of the semiconductor device of FIG. 1 in manufacturing according to another embodiment of the invention.

  A semiconductor device featuring a gate stressor as described herein advantageously provides a strong, manufacturable stressor for NMOS metal gate devices. For both short and long channel devices, the gate stressor is conveniently scalable, for example, to small pitches on the order of submicron pitch. In addition, the stress can be scaled up or down to even higher levels by thinning the corresponding metal gate. In addition, the gate stressor according to the presently disclosed embodiments can additionally be used advantageously in conjunction with current tension etch stop layers (ESLs) and buried stressors. According to certain embodiments, the structure and method provide enhanced NMOS functionality using oxidation of the region above the metal gate. For example, oxidation on a metal gate can be used to induce a large mobility-enhancing stress on the NFET channel of the device. Furthermore, during oxygen implants, masking the gate contact pad with the implant block effectively reduces any undesirable or adverse impact on the gate contact pad.

  Examples of sources of increased NMOS mobility provided by gate stressors according to embodiments of the present disclosure include one or more (1) vertical compression in the channel, (ii) lateral tension in the channel, and ( iii) Includes channel width tension. In addition to increasing NMOS mobility, these stresses tend to reduce the threshold voltage (Vt), which is typically advantageous for metal gate device performance.

  FIG. 1 is a partial cross-sectional view of a portion of a semiconductor device 10 at a stage during manufacture, which features a metal gate stressor according to certain embodiments of the present disclosure. Included in a partial cross-sectional view of a portion of the semiconductor device 10 is a semiconductor layer 12. In certain embodiments, the semiconductor layer 12 is made of any semiconductor material or material such as, for example, gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, single crystal silicon, or combinations thereof. It may be made. The semiconductor device 10 also includes one or more insulating regions 14 (only one region is shown in FIG. 1). For example, the insulating region 14 has a shallow trench isolation that defines the desired activated semiconductor device region 28 (FIG. 2). Insulating region 14 is formed using any suitable technique.

The semiconductor device 10 further includes gate stacks 16 and 18. In one embodiment, gate stacks 16 and 18 comprise a metal gate stack that includes a gate dielectric 20, a gate metal 22 and a polycrystalline semiconductor 24. The specific composition, thickness, and characteristics of the gate dielectric layer 20, the gate metal 22, and the polycrystalline semiconductor 24 are each selected according to the given gate stack requirements of the desired semiconductor device application, and are used herein. No further discussion. In one embodiment, the gate dielectric 20 comprises hafnium zirconium oxide (HfZrOx) having a density on the order of 8 g / cm ³ , and the gate metal 22 is tantalum carbon (TaC) having a density on the order of 14 g / cm ^3. The polycrystalline semiconductor 24 may be made of polysilicon. Further, FIG. 1 shows the spacing or dimensions between the gate and the insulator, exemplified by reference numeral 26. The spacing between the gate and the insulator represents the distance from the edge of the gate stack to the edge of the adjacent insulating region, as further discussed herein.

  FIG. 2 is a plan view of a portion of the semiconductor device 10 of FIG. The boundary of the activated device region, indicated by reference numeral 28, is illustrated in FIG. In addition, gate contact pads 30 and 32 corresponding to gate stacks 16 and 18 are illustrated. Note that the gate contact pads 30 and 32 are located outside the boundaries of the active area 28. Subsequent device contacts (not shown) contact portions of the gate stack 16 or 18 corresponding to the regions of the gate contact pads 30 and 32, respectively. A cross-sectional view of a portion of the semiconductor device 10 of FIG. 1 is taken along line 1-1 of FIG.

  FIG. 3 is a partial cross-sectional view of a portion of the semiconductor device 10 of FIG. 1 at another stage during manufacture. FIG. 3 illustrates sidewall zero spacers 34 formed along the sidewalls of gate stacks 16 and 18. In some embodiments, the sidewall zero spacer 34 comprises a nitride spacer that provides protection to the gate metal and gate dielectric of the gate stacks 16 and 18 during the next processing step. Although FIG. 3 illustrates a spacer for protecting the gate metal and the sidewall of the gate dielectric, the spacer may be formed only along the sidewall of the metal gate having a corresponding portion of the gate dielectric under the spacer. . The sidewall spacer can also be made of any suitable material in addition to nitride or other than nitride. In addition, the protective liner 36 is formed overlying the structure, and the protective liner provides a level of protection with respect to the underlying layer (or layers thereof) during the next processing step or subsequent steps. I will provide a. In certain embodiments, the protective liner 36 comprises an oxide liner. In addition, FIG. 3 illustrates an implant block 38, which may be a single layer or layers from the next implant step for implanting a stressor species (as discussed further herein below). Provides protection of the lying layer. In one embodiment, the implant block 38 consists of at least one selected from the group consisting of SiN and TiN. As shown, the implant block 38 is formed as a large spacer using, for example, suitable techniques known in the art for the formation of sidewall spacers. In one embodiment, the implant block 38 is formed such that the coverage of the implant block is (i) equal to or greater than the gate pitch and (ii) equal to or greater than the gate-to-insulator spacing 26. Is done. Gate pitch is defined as the centerline spacing between adjacent gate stacks.

  4 is a partial cross-sectional view of a portion of the semiconductor device 10 of FIG. 3 at a further stage during manufacture. In particular, in some embodiments, the structure of FIG. 3 is processed using a suitable etch to expose the top surface 40 of the polycrystalline semiconductor 24 for each gate stack 16 and 18. For example, the etching can also include a suitable dry or wet etch. Furthermore, the etching exposes a portion of the insulating region 14, indicated by reference numeral 42. In another embodiment, the structure of FIG. 3 is not processed using etching, but the processing progress therefor will be discussed below with respect to FIG.

  Following exposure of the top surface 40 of the polycrystalline semiconductor 24, the gate contact pad regions 30 and 32 are masked using a suitable masking technique. FIG. 5 is a plan view of a portion of the semiconductor device of FIG. 4, illustrating masking of the gate contact pad regions 30 and 32, which includes forming an implant blocking mask 44. For example, the gate contact pad regions 30 and 32 can be masked (masked out) using a modified good mask. Masking of the gate contact pad regions 30 and 32 is a subsequent implant for implanting a stressor species into the unmasked portions of the gate stacks 16 and 18 (as discussed further herein below). Appropriate implant blocks are conveniently provided in the gate contact pad regions 30 and 32 during the steps. As illustrated in FIG. 5, the exposed surface 40 of a portion of the gate stacks 16 and 18 overlying the region of the activated device region 28 is prepared for the next step of implanting the stressor species. . In addition, a portion of the activation device region 28 is protected via the implant block 38.

  FIG. 6 is a partial cross-sectional view of a portion of the semiconductor device 10 of FIGS. 4 and 5 during the implant stage of manufacture. In some embodiments, a portion of the semiconductor device 10 of FIG. 6 is treated with a high dose oxygen implant 46, as described further below. The high dose oxygen implant stops at the gate metal 22 of the gate stacks 16 and 18 and piles up in the corresponding region indicated by reference numeral 48 due to the higher stopping force of the gate metal 22. As a result, each region 48 provides conditions for subsequent oxide formation at the desired location in the corresponding gate stack. Furthermore, the implant block 38 advantageously protects the region underlying the semiconductor layer 12 and the implant block 38 is characterized by an implant stop force sufficient to prevent the implant species from reaching the semiconductor layer 12. In particular, the implant block 38 prevents the implant species from reaching the underlying activated semiconductor region 28 (FIG. 5), while within the gate stacks 16 and 18 as required, Allows placement. Furthermore, source / drain regions already formed or not yet formed are protected by the implant block 38. Further, the implant block mask 44 advantageously protects the corresponding gate contact pad regions 30 and 32 from being implanted by the implant type. In addition, the implant block mask 44 can also provide protection to other portions of the semiconductor layer 12 of the activated device region 28 that are not protected by the implant block 38.

According to embodiments of the present disclosure, implant conditions including implant energy and density are:
High dose oxygen implants are selected such that no significant amount of oxygen is tailed into the channel region underlying the device being formed. In other words, the implant energy is sufficient to effectively remove oxygen tailing for a given thickness of metal gate, while at the interface between the polysilicon and the metal gate of the gate stack. It still provides sufficient density of oxygen. For example, in a polysilicon / TaC gate stack containing a 10 nanometer thick TaC gate metal, the implant conditions can include a 1 × 10 ¹⁸ / cm ³ oxygen implant at 25-35 keV, while Provide a sufficient density of oxygen at the polysilicon / TaC interface, for example on the order of greater than about 1 × 10 ²³ cm ⁻³ .

Other implant conditions are possible. Range of width / depth condition of the implant profile, strong channel stress, and, for example, including a condition that the address of oxygen tailing, can be used to provide the corresponding enhancements such as Id _sat reinforced. Thus, as discussed herein, structures and methods for gate stacks are also used in conjunction with implant optimization or alone to further reduce oxygen tailing. In some embodiments, a shorter gate stack allows for the use of lower energy implants that further improve the control of oxygen tailing. In another embodiment, a thicker metal gate (eg, TaC) increases the oxygen that is stopped in the gate stack. In another embodiment, a high stopping force material can be placed in the active region above the metal gate prior to polycrystalline semiconductor deposition. In yet another aspect, a xenon (Xe) pre-amorphization implant (PAI) in the activation region prior to polycrystalline semiconductor deposition that amorphizes the top portion of the gate can increase the stopping force.

  FIG. 7 is a partial cross-sectional view of a portion of the semiconductor device 10 of FIG. 6 at an annealing stage during manufacture. In some embodiments, a portion of the semiconductor device 10 is treated with a high temperature anneal, which forms a stressor 50 in the implant region 48 (FIG. 6) of the gate stacks 16 and 18. In some embodiments, the polysilicon semiconductor 24 comprises a material selected from polysilicon, silicon germanium, and silicon carbon, and the stressor 50 comprises an oxygenate formed from the oxide implant region 48 using a high temperature anneal. . Further, the high temperature anneal includes a suitable laser / spike anneal. In a subsequent annealing step, the implant block 38 is removed using suitable techniques. For example, the implant block 38 can be removed by a suitable etch such as, for example, a hot phosphorus etch (for SiN) or a piranha etch (for TiN). Furthermore, the plant block 38 can be removed until a subsequent implant stage and before the annealing stage.

  FIG. 8 is a partial cross-sectional view of a portion of the semiconductor device 10 of FIG. 7 during a further manufacturing process, the semiconductor device characterizing a stressor 50 according to certain embodiments of the present disclosure. Further processing includes the formation of source / drain regions 52, sidewall spacers 54, and silicide regions 56 using appropriate techniques for similar formation. Since implants are prohibited in the gate contact pad regions 30 and 32 via the implant block mask 44, they overlie the corresponding gate stacks 16 and 18 on the gate contact pad regions 30 and 32. Note that the electrical contact to the silicide is not adversely affected by the presence of metal gate stressors in other parts of the gate stack.

  FIG. 9 is a partial cross-sectional view of a portion of the semiconductor device of FIG. 1 in manufacture according to another embodiment. In particular, FIG. 9 illustrates sidewall zero-spacers 34 formed along the sidewalls of gate stacks 16 and 18. In one embodiment, sidewall zero-spacer 34 comprises a nitride spacer that provides protection to the gate metal and gate dielectric of gate stacks 16 and 18 during the next processing step. In addition, a protective liner 36 is formed overlying the structure, and the protective liner is a layer (or layers) that underlies a level of protection during the next processing step or steps from the next. ) To provide. In certain embodiments, the protective liner 36 comprises an oxide liner. In addition, FIG. 9 illustrates an implant block 380, which is a single underlying layer from the next implant step for implanting a stressor species (as discussed further herein below). Provides protection of the layer or layers. In some embodiments, the implant block 380 comprises at least one selected from the group consisting of SiN and TiN. As shown, the implant block 380 is formed by etch back and blanket deposition using, for example, suitable deposition and planarization techniques known in the art. In certain embodiments, the implant block 380 provides an implant block range that includes (i) a range greater than or equal to the gate pitch, and (ii) a range greater than or equal to 26 between the gate and the insulator. As described above, the gate pitch is defined as the centerline spacing between adjacent gate stacks. Planarization of the implant block 380 also includes forming the surface 400. As shown, surface 400 includes an exposed portion of liner 36. In another embodiment, the surface 400 includes the top surface of the polycrystalline semiconductor 24 of the gate stacks 16 and 18. With respect to FIGS. 5-8, as discussed above herein, the following process continues further and the implant block 380 is replaced with the implant block 38.

  According to embodiments of the present disclosure, a method is provided to prevent oxygen from undesirably entering a source / drain region of a semiconductor device, the semiconductor device having a large gate to insulator region spacing dimension. Characterized as: The stressor implants discussed herein depend on part of the device layout. For example, during the process of compensating for the large gate-to-insulator region spacing and minimizing the resulting dummy gate-to-insulator region spacing, a dummy gate is used, thereby providing a corresponding spacer.・ Make masking common. Thus, in the absence of this type of dummy gate, isolation region spacing devices from wide gates alone are not suitable for preventing oxygen from entering the corresponding source / drain regions. The method according to the embodiments of the present disclosure is very applicable because the highest performance logic CMOS devices use in the vicinity of the minimum acceptable gate to insulator area space.

  In another embodiment, the method is suitable for applications that use large gate to insulator region space, and the method includes nitride deposition following a chemical mechanical planarization prior to the oxygen implant step. Including. This embodiment covers large gate-to-insulator region space where nitride deposition is insufficient to cover large gate-to-insulator region space in semiconductor device implementations where only nitride spacers are used. This is different from the embodiment using nitride spacers in that it is sufficient.

In certain embodiments, the semiconductor device provides the correct stress to enhance NMOS device performance in all directions, the stress including providing lateral and width tension as well as vertical compression. With respect to the (100) <110> orientation, NMOS semiconductor devices are characterized as having short channel Id _Sat responses to lateral and width tensions on the order of 1.9 and 0.2, respectively. Furthermore, the short channel Id _Sat response of NMOS semiconductor devices to vertical compression is on the order of 2.1. Furthermore, the unit is the change in the percentage Id _Sat per 100 MPa for a short channel device.

  In certain embodiments, the structures and methods use oxide on the metal gate to induce large mobility increasing stresses in the NFET channel. This embodiment provides a strong, scalable, manufacturable stressor for NMOS. In addition, the stressors are scalable (eg, thinner metal gates) and work for longer channel devices (eg, for NVM, power or analog devices). Furthermore, this embodiment can additionally be used with conventional ESL stressors and with eSiC.

  In one aspect of the present invention, a method of forming a semiconductor device in and on a semiconductor layer includes a first conductive layer and a semiconductor that includes a second layer over the first conductive layer. Forming a gate stack on the layer, wherein the first layer is more conductive and provides a greater stopping force to the implant than the second layer; Implanting seeds in the second layer; forming source / drain regions in a semiconductor layer on the opposite side of the gate stack; and semiconductor in a region where the gate stack is below the gate stack. Heating the gate stack after the implanting step so as to exert a stress on the layer. The step of forming the gate stack is further characterized by the first conductive layer being made of metal. The step of forming the gate stack is further characterized by the second layer comprising polysilicon. The implanting step is further characterized by the species having oxygen. The heating step is performed before the step of forming the source / drain regions. The step of heating is after the step of forming the source / drain regions.

  In one embodiment, the step of forming the gate stack includes the step of forming a gate dielectric between the semiconductor layer and the first conductive layer over the channel between the source and drain regions. It is further characterized by its body. The step of forming the gate stack is further characterized in that the gate stack extends over the activation region of the semiconductor layer and comprises an extension to a gate contact pad outside the activation region. The method further comprises masking the gate contact pad while exposing the gate stack over the active region during the implanting step. The heating step is further characterized in that the stress comprises a tensile lateral stress and a compressive normal stress.

  In another embodiment, forming a first sidewall spacer around the gate stack prior to the implanting step and forming the source / drain regions after the implanting step. And removing the first side wall spacer before. Depositing a filter layer on and around the gate stack, and performing a chemical mechanical polishing on the filter layer prior to the implanting step. The implanting step further comprises energy that causes a maximum concentration of the species to be within 10 nanometers of the first layer.

  In yet another embodiment, a method of forming a semiconductor device in and on a semiconductor layer comprises the step of forming a gate stack over a channel region of the semiconductor layer, comprising: A stack comprising a gate dielectric over the semiconductor layer, a metal layer over the gate dielectric, and a polysilicon layer over the metal layer; Implanting oxygen into the substrate, wherein the maximum concentration of oxygen from the implant is in the second layer and within 10 nanometers of the metal layer; and Forming source / drain regions in the semiconductor layer on the opposite side of the stack, and so that the oxygen can react with the polysilicon layer; After the step of implant, characterized by having a, a step of heating said gate stack. The method further includes forming sidewall spacers around the gate stack before the implanting step and removing the sidewall spacers prior to forming the source / drain regions. Features. The step of forming the gate stack is further characterized by the metal layer having tantalum and carbon. Forming the gate stack is further characterized by the gate stack extending over an activation region of a substrate layer and having an extension in a gate contact pad outside the activation region; Masking the gate contact pad while exposing the gate stack over the active region during the implanting step.

In yet another embodiment, the semiconductor device is
A semiconductor layer;
A first conductive layer on the semiconductor layer;
A second layer on the first layer;
A stressor disposed in a second layer within 10 nanometers of the first conductive layer;
A gate stack over the substrate, wherein the first layer is more conductive and provides a greater stopping force against the implant than the second layer. The gate stack,
A source / drain region in the semiconductor layer opposite the gate stack;
It is characterized by having.

  The stressor is adjacent to the first conductive layer. The first conductive layer is made of metal, the second layer is made of polysilicon, and the stressor is made of oxide. The stressor generates lateral tensile stress in the channel region of the semiconductor layer between the source / drain regions under the gate stack.

Although the present invention has been described with respect to a particular conductivity type or polarity, it will be apparent to those skilled in the art that the conductivity type and polarity can be changed.
Further, the terms “front”, “rear”, “top”, “bottom”, “top”, “bottom” and the like in the claims are used for descriptive purposes and are The purpose is not to describe the relative position. In this application, the conditions used are such that the embodiments of the invention described can be operated, for example, in different orientations than those illustrated or described herein. It can be exchanged under appropriate circumstances.

  Thus, the architecture represented herein is merely exemplary. And it will be appreciated that many other architectures that achieve the same functionality can be implemented. An arrangement of components that are abstract but can be determined and that can achieve the same function is effectively “related” so that the desired function is achieved. Thus, here two components that are combined to achieve a particular function appear to be “related” to each other, and the desired function is achieved regardless of the architecture or intermediate components. Similarly, two related components may also appear to be “operably connected” or “operably coupled” to each other to achieve a desired function.

  Furthermore, those skilled in the art will recognize that the boundaries between the functional operations described above are merely exemplary. The functional multiple operations can be combined into a single operation and / or the functional single operation can be distributed to additional operations. In addition, other embodiments include multiple examples of specific operations, and the order of operations can be changed in various other embodiments.

  Although the invention has been described herein with reference to specific embodiments, various changes and modifications can be made without departing from the scope of the invention as defined in the following claims. For example, the gate dielectric may be a stack of dielectric materials, the metal gate may be a stack of metals, oxide spacers may be used in place of nitride spacers, etc. . Accordingly, the specification and drawings are merely illustrative and not limiting and all such variations are included within the scope of the invention.

The term “coupled” as used herein is not limited to direct coupling or mechanical coupling.
Terms such as “first” and “second” are used to arbitrarily distinguish between elements such as those described. Thus, these terms are not intended to indicate temporal or other priorities of these elements.

Claims (3)

A method of forming a semiconductor device comprising:
Forming an insulator in the semiconductor layer to define an active region;
Forming a first gate stack on the semiconductor layer, including a first conductive layer and a second layer on the first conductive layer, the method comprising:
Wherein the first layer is more conductive than the second layer and provides a greater stopping force for the implant,
The first gate stack overlies a non-total portion of the activation region;
And forming the thus uncovered in the first gate stack, the implant blocks on a portion of the active region adjacent to the first gate stack,
Implanting an implant species in the second layer, wherein the implant is performed after forming a first gate stack and forming the implant block;
Removing the implant block;
Forming source / drain regions in semiconductor layers on opposite sides of the first gate stack;
Heating the first gate stack after the implanting step so that the first gate stack exerts stress on a semiconductor layer in a region under the first gate stack;
A method characterized by comprising: A method of forming a semiconductor device in and on a semiconductor layer, comprising:
Forming a gate stack over the channel region of the semiconductor layer, the gate stack comprising a gate dielectric over the semiconductor layer, a metal layer over the gate dielectric, and the metal Comprising a polysilicon layer on the layer; and
The method comprising: implanting oxygen into the gate stack, the maximum concentration of the implanted oxygen is in the polysilicon layer, characterized in that is within 10 nanometers of the metal layer, the steps,
Forming source / drain regions in semiconductor layers on opposite sides of the gate stack;
Heating the gate stack after the implanting step so that the oxygen can react with the polysilicon layer;
A method characterized by comprising: A method of forming a semiconductor device in and on a semiconductor layer, comprising:
A first conductive layer, the gate stack includes a second layer on said first conductive layer, and forming on the semiconductor layer, wherein the first layer of the second A step characterized in that it is more conductive than the layer and provides a greater stopping force for the implant;
Implanting an implant species in the second layer, wherein the implant is performed at an energy such that a maximum concentration of implant species is within 10 nanometers of the first conductive layer. And steps to
Forming source / drain regions in semiconductor layers on opposite sides of the gate stack;
Heating the gate stack after the implanting step such that the gate stack exerts stress on a semiconductor layer in a region under the gate stack;
A method characterized by comprising:

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