JP5349270B2 - Wiring circuit board and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring circuit board and a method of manufacturing the same, improving adhesiveness between wiring patterns and an insulation layer. <P>SOLUTION: The wiring circuit board 70 includes the insulation layer 1. A plurality of wiring patterns 7 are formed on the insulation layer 1. Each of the wiring patterns 7 includes an interface layer 2, a first seed layer 3, a second seed layer 4 and a wiring layer 6. The interface layer 2, the first seed layer 3, the second seed layer 4 and the wiring layer 6 are laminated on the insulation layer 1 in this order. The interface layer 2 is formed so that the electrode voltage is not less than -0.3 V and not more than 0.01 V, the electrode voltage being against a saturated calomel electrode in a mixed aqueous solution including sulfuric acid at a concentration of 18% (volume concentration) and hydrochloric acid at a concentration of 10%. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a printed circuit board and a method for manufacturing the same.

  Conventionally, a base material having a structure in which a metal layer is formed on an insulating layer is used in the manufacture of a printed circuit board. When manufacturing such a substrate, in order to improve the adhesion between the insulating layer and the metal layer, plasma treatment is performed on the insulating layer by performing glow discharge under reduced pressure, and then, for example, vacuum deposition is performed on the insulating layer. A metal layer is formed on (see, for example, Patent Document 1).

Japanese Patent Laid-Open No. 1999-92916

  When a printed circuit board is manufactured using the above base material, for example, a conductor layer having a predetermined pattern is formed on the metal layer by electrolytic plating, and the exposed metal layer portion is removed by etching using an etching solution. Thereby, a wiring pattern composed of a metal layer and a conductor layer is formed. However, at the time of etching the metal layer, a part of the metal layer and the conductor layer that should not be removed may be eluted into the etching solution, and the lower part of the side surface of the wiring pattern may be depressed. Thereby, the adhesion between the wiring pattern and the insulating layer decreases.

  An object of the present invention is to provide a printed circuit board capable of improving the adhesion between a wiring pattern and an insulating layer, and a manufacturing method thereof.

[1] The present invention
(1) A method for manufacturing a printed circuit board according to the present invention includes a step of forming an interface layer on an insulating layer, a step of forming a conductor layer on the interface layer, and etching the interface layer and the conductor layer with an etchant. Forming a wiring pattern by etching, and in the step of forming the interface layer, an electrode potential with respect to a saturated calomel electrode in a mixed aqueous solution containing sulfuric acid at a concentration of 18% and hydrochloric acid at a concentration of 10% is formed. In the mixed aqueous solution containing sulfuric acid at a concentration of 18% and hydrochloric acid at a concentration of 10% by performing plasma treatment on the insulating layer using a material of −0.3 V or more and 0.01 V or less as an electrode. The interface layer is formed so that the electrode potential with respect to the saturated calomel electrode is −0.3 V or more and 0.01 V or less, and the electrode used for the plasma treatment is nickel-chromium alloy. Includes at least one of nickel, and forming the conductor layer includes forming a first seed layer made of a nickel-chromium alloy on the interface layer, and forming a first seed layer made of copper on the first seed layer. And a step of forming a wiring layer made of copper having a predetermined pattern by electrolytic plating on the second seed layer.
In the manufacturing method, an interface layer is formed on the insulating layer. In this case, the interface layer is formed so that the electrode potential with respect to the saturated calomel electrode is -0.3 V or more and 0.01 V or less in a mixed aqueous solution containing sulfuric acid at a volume concentration of 18% and hydrochloric acid at a volume concentration of 10%. Is done. Subsequently, a conductor layer is formed on the interface layer, and the interface layer and the conductor layer are etched with an etchant to form a wiring pattern.
In this case, it is possible to prevent the side portion of the wiring pattern from being excessively eluted into the etching solution during etching of the conductor layer. As a result, the adhesion between the insulating layer and the wiring pattern can be improved.
The step of forming the interface layer is a material in which the electrode potential with respect to the saturated calomel electrode in a mixed aqueous solution containing sulfuric acid at a concentration of 18% and hydrochloric acid at a concentration of 10% is −0.3 V or more and 0.01 V or less. Is used as an electrode, and plasma treatment is performed on the insulating layer.
In this case, a part of the material used for the electrode is sputtered and deposited on the insulating layer, whereby the interface layer is formed. This facilitates the interface layer so that the electrode potential with respect to the saturated calomel electrode in a mixed aqueous solution containing sulfuric acid at a volume concentration of 18% and hydrochloric acid at a volume concentration of 10% is −0.3 V or more and 0.01 V or less. Can be formed.
In the step of performing plasma treatment, at least one of nickel-chromium alloy or nickel is used for the electrode.
The nickel-chromium alloy and nickel have an electrode potential of −0.3 V or more and 0.01 V or less with respect to a saturated calomel electrode in a mixed aqueous solution containing sulfuric acid at a volume concentration of 18% and hydrochloric acid at a volume concentration of 10%. Therefore, by using at least one of a nickel-chromium alloy and nickel as an electrode during plasma treatment, saturated calomel in a mixed aqueous solution containing sulfuric acid at a volume concentration of 18% and hydrochloric acid at a volume concentration of 10% is used. The interface layer can be easily formed so that the electrode potential with respect to the electrode is −0.3 V or more and 0.01 V or less.
The step of forming the conductor layer includes a step of forming a first seed layer made of a nickel-chromium alloy on the interface layer and a step of forming a second seed layer made of copper on the first seed layer. And forming a wiring layer made of copper having a predetermined pattern by electrolytic plating on the second seed layer.
In this case, unnecessary portions of the second seed layer, the first seed layer, and the interface layer are removed by etching using an etchant. In this case, the etching of the side surface portion of the wiring pattern is prevented from proceeding preferentially over the etching of the second seed layer, the first seed layer, and the interface layer portion to be removed. This prevents the side surface portion of the wiring pattern from being excessively eluted into the etching solution. As a result, the adhesion between the insulating layer and the wiring pattern can be improved.
(2) The step of forming the wiring pattern may include a step of etching the interface layer and the first and second seed layers except under the wiring layer.
[2] Reference form (1) A printed circuit board according to a reference form includes an insulating layer and a wiring pattern formed on the insulating layer, and the wiring pattern includes an interface layer formed on the insulating layer, and an interface And the electrode potential of the interface layer with respect to the saturated calomel electrode in a mixed aqueous solution containing sulfuric acid at a concentration of 18% and hydrochloric acid at a concentration of 10%. .01V or less.

  In the printed circuit board, a wiring pattern including an interface layer and a conductor layer is formed on the insulating layer. In this case, an interface layer is formed in which the electrode potential with respect to the saturated calomel electrode is −0.3 V or more and 0.01 V or less in a mixed aqueous solution containing sulfuric acid at a concentration of 18% and hydrochloric acid at a concentration of 10%. .

  Accordingly, when the wiring pattern is formed by etching using an etching solution during the manufacture of the printed circuit board, it is possible to prevent the side portions of the wiring pattern from being excessively eluted into the etching solution. As a result, the adhesion between the insulating layer and the wiring pattern can be improved.

  (2) The conductor layer includes a first seed layer made of a nickel-chromium alloy formed on the interface layer, a second seed layer made of copper formed on the first seed layer, and a second seed layer And a wiring layer made of copper formed on the seed layer.

  In this case, the second seed to be removed when unnecessary parts of the second seed layer, the first seed layer, and the interface layer are removed by etching using an etchant during the manufacture of the printed circuit board. It is possible to prevent the etching of the side portion of the wiring pattern from proceeding preferentially over the etching of the layer, the first seed layer, and the interface layer. Thereby, it is possible to prevent the side portion of the wiring pattern from being excessively eluted into the etching solution. As a result, the adhesion between the insulating layer and the wiring pattern can be improved.

(3) A method for manufacturing a printed circuit board according to a reference embodiment includes a step of forming an interface layer on an insulating layer, a step of forming a conductor layer on the interface layer, and etching the interface layer and the conductor layer with an etchant. Forming a wiring pattern by etching, and in the step of forming the interface layer, an electrode potential with respect to a saturated calomel electrode in a mixed aqueous solution containing sulfuric acid at a concentration of 18% and hydrochloric acid at a concentration of 10% is formed. The interface layer is formed so as to be −0.3 V or more and 0.01 V or less.

  In the manufacturing method, an interface layer is formed on the insulating layer. In this case, the interface layer is formed so that the electrode potential with respect to the saturated calomel electrode is -0.3 V or more and 0.01 V or less in a mixed aqueous solution containing sulfuric acid at a volume concentration of 18% and hydrochloric acid at a volume concentration of 10%. Is done. Subsequently, a conductor layer is formed on the interface layer, and the interface layer and the conductor layer are etched with an etchant to form a wiring pattern.

  In this case, it is possible to prevent the side portion of the wiring pattern from being excessively eluted into the etching solution during etching of the conductor layer. As a result, the adhesion between the insulating layer and the wiring pattern can be improved.

  (4) In the step of forming the interface layer, the electrode potential with respect to the saturated calomel electrode in the mixed aqueous solution containing sulfuric acid at a concentration of 18% and hydrochloric acid at a concentration of 10% is −0.3 V or more and 0.01 V or less. A step of performing plasma treatment on the insulating layer using a material for the electrode may be included.

  In this case, a part of the material used for the electrode is sputtered and deposited on the insulating layer, whereby the interface layer is formed. This facilitates the interface layer so that the electrode potential with respect to the saturated calomel electrode in a mixed aqueous solution containing sulfuric acid at a volume concentration of 18% and hydrochloric acid at a volume concentration of 10% is −0.3 V or more and 0.01 V or less. Can be formed.

  (5) In the step of performing the plasma treatment, at least one of stainless steel, copper, nickel-chromium alloy, or nickel may be used for the electrode.

  In this case, stainless steel, copper, nickel-chromium alloy and nickel have an electrode potential of −0.3 V or more with respect to a saturated calomel electrode in a mixed aqueous solution containing sulfuric acid at a volume concentration of 18% and hydrochloric acid at a volume concentration of 10%. 0.01 V or less. Therefore, by using at least one of stainless steel, copper, nickel-chromium alloy and nickel as an electrode during plasma treatment, a mixed aqueous solution containing sulfuric acid at a volume concentration of 18% and hydrochloric acid at a volume concentration of 10%. The interface layer can be easily formed so that the electrode potential with respect to the saturated calomel electrode in the inside is −0.3 V or more and 0.01 V or less.

  (6) The step of forming the conductor layer includes a step of forming a first seed layer made of nickel-chromium alloy on the interface layer and a second seed layer made of copper on the first seed layer. And a step of forming a wiring layer made of copper having a predetermined pattern by electrolytic plating on the second seed layer.

  In this case, unnecessary portions of the second seed layer, the first seed layer, and the interface layer are removed by etching using an etchant. In this case, the etching of the side surface portion of the wiring pattern is prevented from proceeding preferentially over the etching of the second seed layer, the first seed layer, and the interface layer portion to be removed. This prevents the side surface portion of the wiring pattern from being excessively eluted into the etching solution. As a result, the adhesion between the insulating layer and the wiring pattern can be improved.

  (7) The step of forming the wiring pattern may include a step of etching the interface layer and the first and second seed layers except under the wiring layer.

  In this case, the etching of the side surface portion of the wiring pattern is prevented from proceeding preferentially over the etching of the second seed layer, the first seed layer and the interface layer portion to be removed. This prevents the side surface portion of the wiring pattern from being excessively eluted into the etching solution. As a result, the adhesion between the insulating layer and the wiring pattern can be improved.

  According to the present invention, the side portion of the wiring pattern is prevented from being excessively eluted into the etching solution. As a result, the adhesion between the insulating layer and the wiring pattern can be improved.

1 is a schematic cross-sectional view of a printed circuit board according to an embodiment of the present invention. It is typical process sectional drawing which shows the manufacturing method of the printed circuit board which concerns on one embodiment of this invention. It is typical process sectional drawing which shows the manufacturing method of the printed circuit board which concerns on one embodiment of this invention. It is a figure which shows the structure of a film formation apparatus. It is a schematic diagram which shows the example of the wiring pattern which the part which should not be removed eluted excessively.

  Hereinafter, a printed circuit board and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings.

(1) Structure of printed circuit board FIG. 1 is a schematic cross-sectional view of a printed circuit board according to the present embodiment. As shown in FIG. 1, the printed circuit board 70 includes an insulating layer 1. As a material of the insulating layer 1, for example, a polymer film such as polyimide, polyamideimide, polyester, liquid crystal polymer, polyethersulfone or norbornene is used. The thickness of the insulating layer 1 is, for example, 1 μm or more and 100 μm or less, and preferably 5 μm or more and 50 μm or less.

  A plurality of wiring patterns 7 are formed on the insulating layer 1. Each wiring pattern 7 includes an interface layer 2, a first seed layer 3, a second seed layer 4, and a wiring layer 6. The interface layer 2, the first seed layer 3, the second seed layer 4 and the wiring layer 6 are laminated on the insulating layer 1 in this order. The first seed layer 3 is made of, for example, a nickel-chromium alloy, and the second seed layer 4 and the wiring layer 6 are made of, for example, copper.

  In addition, as a material of the first seed layer 3, for example, a metal such as nickel, chromium, molybdenum, or zinc, or an alloy containing these metals may be used instead of the nickel-chromium alloy. As a material of the second seed layer 4, for example, a metal such as aluminum or silver, or an alloy containing these metals may be used instead of copper. As a material for the wiring layer 6, for example, a metal such as silver or tin, or an alloy containing these metals may be used instead of copper.

  The thickness of the interface layer 2 is, for example, greater than 0 nm and 50 nm or less, and preferably greater than 0 nm and 10 nm or less. The thickness of the first seed layer 3 is, for example, 5 nm to 100 nm, and preferably 5 nm to 50 nm. The thickness of the second seed layer 4 is, for example, not less than 5 nm and not more than 300 nm, and preferably not less than 5 nm and not more than 100 nm. The thickness of the wiring layer 6 is, for example, 1 μm or more and 100 μm or less, and preferably 5 μm or more and 50 μm or less. A metal layer made of, for example, stainless steel may be provided on the lower surface of the insulating layer 1.

  Here, the present inventor has found that excessive etching of the side surface portion of the wiring pattern is prevented when the interface layer 2 has an electrode potential within a specific range from experiments and examinations described later. Therefore, in the present embodiment, the interface layer 2 is formed so as to have an electrode potential within a specific range. Specifically, the interface layer 2 has an electrode potential with respect to a saturated calomel electrode in a mixed aqueous solution containing sulfuric acid at a concentration (volume concentration) of 18% and hydrochloric acid at a concentration of 10%. It is formed to be as follows. The interface layer 2 having such an electrode potential can be formed using a material such as stainless steel, copper, nickel-chromium alloy, or nickel.

(2) Method for Manufacturing Printed Circuit Board A method for manufacturing the printed circuit board 70 according to the present embodiment will be described below. 2 and 3 are schematic process cross-sectional views showing a method for manufacturing the printed circuit board 70 according to the present embodiment. In the manufacturing method shown in FIGS. 2 and 3, a plurality of printed circuit boards 70 are integrally formed, and finally they are separated.

  As shown in FIG. 2A, a long insulating layer 1 made of polyimide, for example, is prepared. In this case, a base material in which a metal layer made of, for example, stainless steel is formed on one surface (the lower surface in FIG. 2A) of the insulating layer 1 may be used.

  Next, as illustrated in FIG. 2B, the interface layer 2, the first seed layer 3, and the second seed layer 4 are formed in this order on the insulating layer 1. Details of the step of forming the interface layer 2, the first seed layer 3, and the second seed layer 4 will be described later.

  Next, as shown in FIG. 2 (c), a dry film or the like is laminated on the second seed layer 4, exposed and developed to have a pattern opposite to the wiring pattern formed in the subsequent process. A resist 5 is formed.

  Next, as shown in FIG. 2D, a wiring layer 6 made of, for example, copper is formed on the exposed portion of the second seed layer 4 by electrolytic plating. Next, as shown in FIG. 3E, the plating resist 5 is removed by peeling or the like.

  Subsequently, as shown in FIG. 3F, the second seed layer 4, the first seed layer 3 and the interface layer 2 are sequentially removed using an etching solution except for the region under the wiring layer 6. As the etchant, sulfuric acid / hydrogen peroxide, nitric acid / hydrogen peroxide, sodium peroxide, potassium ferricyanide, or the like is used. Thereby, a wiring pattern 7 including the interface layer 2, the first seed layer 3, the second seed layer 4, and the wiring layer 6 is formed.

  In this way, a plurality of printed circuit boards 70 are integrally formed. Thereafter, the insulating layer 1 is cut into a predetermined shape, whereby the plurality of printed circuit boards 70 are separated from each other.

(3) Step of forming interface layer, first seed layer, and second seed layer Hereinafter, step of forming interface layer 2, first seed layer 3, and second seed layer 4 (step of FIG. 2B) ) Will be described in detail. The interface layer 2, the first seed layer 3, and the second seed layer 4 are formed in a film forming apparatus described below. FIG. 4 is a diagram illustrating an example of the configuration of the film forming apparatus.

  As shown in FIG. 4, the film forming apparatus 100 includes a vacuum chamber 90. The vacuum chamber 90 is evacuated by a vacuum pump (not shown). In the vacuum chamber 90, an electrode roller 86, a plasma electrode 87, sputter deposition electrodes 88 and 89, roll shafts 80 and 85, and guide rollers 81 to 84 are provided.

  One end and the other end of the long insulating layer 1 are wound around the roll shafts 80 and 85, respectively. An electrode roller 86 is disposed between the roll shaft 80 and the roll shaft 85. Guide rollers 81 and 82 are disposed between the roll shaft 80 and the electrode roller 86, and guide rollers 83 and 84 are disposed between the roll shaft 85 and the electrode roller 86.

  The insulating layer 1 is disposed along the outer peripheral surface of the electrode roller 86. The insulating layer 1 is held and conveyed by the guide rollers 81 and 82 between the electrode roller 86 and the roll shaft 80, and is held and conveyed by the guide rollers 83 and 84 between the electrode roller 86 and the roll shaft 85.

  A plasma electrode 87 and sputter deposition electrodes 88 and 89 are arranged so as to face the outer peripheral surface of the electrode roller 86, respectively. A high frequency power source 92 is connected to the plasma electrode 87 via a matching circuit 91. An ingot 87 a is attached to the discharge surface of the plasma electrode 87.

  In the present embodiment, as the material of the ingot 87a, the electrode potential with respect to the saturated calomel electrode in a mixed aqueous solution containing sulfuric acid at a concentration of 18% and hydrochloric acid at a concentration of 10% is -0.3V or more and 0.01V or less. It is preferable to use a material that is Examples of such a material include stainless steel, copper, nickel-chromium alloy, or nickel.

  DC power supplies 93 and 94 are connected to the sputter deposition electrodes 88 and 89, respectively. For example, an ingot 88a made of copper is attached to the sputtering vapor deposition electrode 88 as a sputtering target.

  An ingot 89a made of, for example, a nickel-chromium alloy is attached to the sputter deposition electrode 89 as a sputtering target.

  As the sputtering deposition electrodes 88 and 89, for example, planar magnetron type cathode electrodes are used. In that case, magnetron type DC sputtering can be performed at a higher deposition rate than when performing normal DC sputtering or high frequency sputtering.

  Next, the operation of the film forming apparatus 100 will be described. First, the vacuum chamber 90 is evacuated by a vacuum pump (not shown). Subsequently, for example, a mixed gas of nitrogen and oxygen is introduced into the vacuum chamber 90 as a discharge gas for plasma processing described later.

  In this state, the insulating layer 1 fed from the roll shaft 80 is guided to the electrode roller 86 by the guide rollers 81 and 82. Plasma treatment is performed on the insulating layer 1 by the plasma electrode 87 on the outer peripheral surface of the electrode roller 86. In this case, a part of the ingot 87 a is sputtered and deposited on the insulating layer 1. Thereby, as shown in FIG. 2B, the interface layer 2 made of the material of the ingot 87 a is formed on the insulating layer 1.

  Here, the plasma treatment condition is that the electrode potential of the interface layer 2 with respect to the saturated calomel electrode in a mixed aqueous solution containing sulfuric acid at a concentration of 18% and hydrochloric acid at a concentration of 10% is −0.3 V or more and 0.01 V or less. Adjust so that The insulating layer 1 subjected to the plasma treatment is guided to the roll shaft 85 by the guide rollers 83 and 84 and is taken up by the roll shaft 85.

  When the plasma treatment is performed on the entire insulating layer 1, the atmosphere in the vacuum chamber 90 is replaced with, for example, argon gas from a mixed gas of nitrogen and oxygen. Note that helium, neon, xenon, krypton, or the like may be used instead of argon gas. In that state, the insulating layer 1 after the plasma treatment is sent out from the roll shaft 85. The insulating layer 1 is guided to the electrode roller 86 by the guide rollers 84 and 83. Subsequently, a first seed layer 3 made of a nickel-chromium alloy (material of the ingot 89a) is formed on the interface layer 2 by sputtering between the electrode roller 86 and the sputter deposition electrode 89.

  Next, the second seed layer 4 made of copper (material of the ingot 88a) is formed on the first seed layer 3 by sputtering between the electrode roller 86 and the sputter deposition electrode 88. In this manner, the interface layer 2, the first seed layer 3, and the second seed layer 4 are sequentially formed on the insulating layer 1.

(3) Etching of wiring pattern Depending on the plasma processing conditions in the film forming apparatus 100 described above, the portion of the wiring pattern 7 that should not be removed in the subsequent etching step (step of FIG. 3 (f)) is excessively etched. May elute.

  FIG. 5 is a schematic cross-sectional view showing an example of the wiring pattern 7 in which a portion that should not be removed is excessively eluted. As shown in FIG. 5, the lower portion of the side surface of the wiring pattern 7 is excessively eluted in the etching solution, and the width of the lower end portion of the wiring pattern 7 becomes smaller than the width of the upper end portion. In this case, since the adhesion between the insulating layer 1 and the wiring pattern 7 is lowered, the wiring pattern 7 may be peeled off from the insulating layer 1.

  The reason why such a phenomenon occurs is that the potential of the interface layer 2 is increased depending on the conditions of the plasma treatment. In that case, the etching is less likely to proceed closer to the interface layer 2. Therefore, when the second seed layer 4 is etched, etching of the side surface portion of the wiring layer 6 of the wiring pattern 7 proceeds preferentially, and when the first seed layer 3 is etched, the first pattern of the wiring pattern 7 is etched. The etching of the side surface portion of the second seed layer 4 proceeds preferentially, and when the interface layer 2 is etched, the etching of the side surface portion of the first seed layer 3 of the wiring pattern 7 proceeds preferentially. In this way, the side surface portion of the wiring pattern 7 is excessively etched.

(4) Effects In the printed circuit board 70 according to the present embodiment, the electrode potential with respect to the saturated calomel electrode in a mixed aqueous solution containing sulfuric acid at a concentration of 18% and hydrochloric acid at a concentration of 10% is −0.3 V or more. Interfacial layer 2 is formed to be 0.01 V or less.

  In this case, the etching of the side surface portion of the wiring pattern 7 is prevented from proceeding preferentially over the etching of the portion of the interface layer 2 and the first and second seed layers 3 and 4 to be removed. This prevents the side surface portion of the wiring pattern 7 from being excessively eluted into the etching solution. As a result, sufficient adhesion between the insulating layer 1 and the wiring pattern 7 can be ensured.

(5) Examples 1-4 and Comparative Examples 1-2
(5-1) Example 1
As Example 1, a printed circuit board 70 was manufactured under the following conditions.

  First, a two-layer base material in which a metal layer made of stainless steel is formed on one surface of an insulating layer 1 made of polyimide is prepared. In the film forming apparatus 100, the interface layer 2, the first and first layers are formed on the insulating layer 1. 2 seed layers 3 and 4 were formed.

  In this case, a nickel-chromium alloy (NiCr) containing nickel and chromium in a ratio of 80:20 was used as the material of the ingots 87a and 89a, and copper was used as the material of the ingot 88a.

In a state where a mixed gas containing nitrogen (N ₂ ) and oxygen (O ₂ ) in a ratio of 97: 3 is introduced into the vacuum chamber 90 as a discharge gas, and the atmospheric pressure in the vacuum chamber 90 is maintained at 10 ⁻¹ Pa, The insulating layer 1 was subjected to plasma treatment. Thereby, an interface layer 2 made of a nickel-chromium alloy was formed on the insulating layer 1.

In addition, the integrated power density at the time of plasma processing was 20 W · s / cm ² using a high frequency power supply 92 of 13.56 MHz. Here, the integrated power density is a value obtained by dividing the product of the power supplied to the plasma electrode 87 and the plasma processing time by the area of the discharge surface of the plasma electrode 87.

Next, argon gas is introduced into the vacuum chamber 90, the atmospheric pressure in the vacuum chamber 90 is reduced to 7.8 × 10 ⁻² Pa, and a first seed made of a nickel-chromium alloy is formed on the interface layer 2 by sputtering. A layer 3 and a second seed layer 4 made of copper were sequentially formed. The thickness of the first seed layer 3 was 20 nm, and the thickness of the second seed layer 4 was 75 nm.

  Thereafter, as shown in FIG. 2C to FIG. 3F, the wiring layer 6 is formed on the second seed layer 4 by electrolytic plating, and the second layer except for the region under the wiring layer 6 is formed. By removing the seed layer 4, the first seed layer 3 and the interface layer 2 using an etching solution, a wiring pattern comprising the interface layer 2, the first seed layer 3, the second seed layer 4 and the wiring layer 6 is used. 7 was formed.

  Note that copper was used as the material of the wiring layer 6 and the thickness of the wiring layer 6 was 10 μm. Moreover, Okuno Pharmaceutical Co., Ltd. top lip and Nippon Kayaku Co., Ltd. flicker NLB were used as etching liquid.

  Then, the printed circuit board 70 of Example 1 was obtained by isolate | separating the several printed circuit board 70 from each other.

(5-2) Example 2
Except for using nickel (Ni) instead of nickel-chromium alloy as a material for the ingot 87a and using nitrogen gas (N ₂ ) instead of a mixed gas of nitrogen and oxygen as a discharge gas for plasma treatment, A printed circuit board 70 was produced in the same manner as in Example 1 above.

(5-3) Example 3
A printed circuit board 70 was produced in the same manner as in Example 1 except that nitrogen gas (N ₂ ) was used instead of the mixed gas of nitrogen and oxygen as the discharge gas for the plasma treatment.

(5-4) Example 4
Except for using stainless steel (SUS304) instead of nickel-chromium alloy as the material of the ingot 87a and using nitrogen gas (N ₂ ) instead of the mixed gas of nitrogen and oxygen as the discharge gas for the plasma treatment, A printed circuit board 70 was produced in the same manner as in Example 1 above.

(5-5) Comparative Example 1
Except for using zirconium (Zr) instead of nickel-chromium alloy as a material for the ingot 87a and using nitrogen gas (N ₂ ) instead of a mixed gas of nitrogen and oxygen as a discharge gas for plasma treatment, A printed circuit board 70 was produced in the same manner as in Example 1 above.

(5-6) Comparative Example 2
Except for using chromium (Cr) instead of nickel-chromium alloy as a material for the ingot 87a and using nitrogen gas (N ₂ ) instead of a mixed gas of nitrogen and oxygen as a discharge gas for plasma treatment, A printed circuit board 70 was produced in the same manner as in Example 1 above.

(5-7) Presence / absence of side etching of wiring pattern and saturation calomel electrode potential of interface layer Etching of side surface portion of wiring pattern 7 in wiring circuit boards 70 of Examples 1 to 4 and Comparative Examples 1 and 2 (hereinafter, The presence or absence of side etching) was examined using a SEM (scanning electron microscope).

  Moreover, the electrode potential of the interface layer 2 of the printed circuit board 70 of Examples 1 to 4 and Comparative Examples 1 and 2 was examined. In this case, a saturated calomel electrode was used as the reference electrode. Specifically, the wiring pattern 7 of each wiring circuit board 70 was masked so that only the surface of the wiring layer 6 was exposed. In this state, each printed circuit board 70 was inserted together with a saturated calomel electrode into a mixed aqueous solution containing sulfuric acid at a concentration of 18% and hydrochloric acid at a concentration of 10%.

  Then, the potential of the wiring pattern 7 with respect to the saturated calomel electrode was measured for a predetermined time by a data logger. In this case, the wiring layer 6, the second seed layer 4, the first seed layer 3, and the interface layer 2 are eluted and disappeared in the mixed aqueous solution in this order. The potentials of the seed layer 3, the interface layer 2, and the insulating layer 1 are obtained in this order.

  In this example, the extreme value of the measured value from when the potential of the first seed layer 3 (nickel-chromium alloy) is measured until the potential of the insulating layer 1 (polyimide) is measured is defined as the potential of the interface layer 2. did.

(5-8) Evaluation Table 1 shows the conditions of plasma processing in the wired circuit boards 70 of Examples 1 to 4 and Comparative Examples 1 and 2, the electrode potential of the interface layer 2 with respect to the saturated calomel electrode, and the side etching of the wiring pattern 7 It is the table | surface which showed the presence or absence of.

  As shown in Table 1, in the wired circuit boards 70 of Examples 1 to 4, the electrode potential of the interface layer 2 with respect to the saturated calomel electrode was −0.28 to 0.01V. Moreover, the side part of the wiring pattern 7 was not etched.

  On the other hand, in the printed circuit board 70 of the comparative example 1, the electrode potential of the interface layer 2 with respect to the saturated calomel electrode was 0.11V. Further, the side surfaces of the second seed layer 4 and the wiring layer 6 of the wiring pattern 7 were excessively etched.

  In the printed circuit board 70 of Comparative Example 2, the potential of the interface layer 2 with respect to the saturated calomel electrode was −0.4V. Further, the side surface portion of the first seed layer 3 of the wiring pattern 7 was excessively etched.

  From the above, the interface layer 2 in which the electrode potential with respect to the saturated calomel electrode in a mixed aqueous solution containing sulfuric acid at a concentration of 18% and hydrochloric acid at a concentration of 10% is −0.3 V or more and 0.01 V or less. As a result, it was found that the side portions of the wiring pattern 7 were prevented from being excessively etched, and the adhesion between the wiring pattern 7 and the insulating layer 1 was improved.

(6) Correspondence relationship between each constituent element of claim and each element of the embodiment Hereinafter, an example of correspondence between each constituent element of the claim and each element of the embodiment will be described. It is not limited to examples.

  In the above embodiment, the insulating layer 1 is an example of an insulating layer, the wiring pattern 7 is an example of a wiring pattern, the interface layer 2 is an example of an interface layer, the first seed layer 3, the second layer The seed layer 4 and the wiring layer 6 are examples of conductor layers, the first seed layer 3 is an example of a first seed layer, the second seed layer 4 is an example of a second seed layer, Layer 6 is an example of a wiring layer.

  As each constituent element in the claims, various other elements having configurations or functions described in the claims can be used.

  The present invention can be effectively used for various printed circuit boards.

DESCRIPTION OF SYMBOLS 1 Insulating layer 2 Interface layer 3 1st seed layer 4 2nd seed layer 5 Plating resist 6 Wiring layer 7 Wiring pattern 70 Wiring circuit board 80, 85 Roll axis 81, 82, 83, 84 Guide roll 86 Electrode roller 87 Plasma Electrode 88, 89 Magnetron sputtering electrode 90 Vacuum chamber 91 Matching circuit 92 High frequency power source 93, 94 DC power source 100 Film forming apparatus

Claims (2)

Forming an interface layer on the insulating layer;
Forming a conductor layer on the interface layer;
Forming a wiring pattern by etching the interface layer and the conductor layer using an etching solution,
In the step of forming the interface layer , a material having an electrode potential of −0.3 V or more and 0.01 V or less with respect to a saturated calomel electrode in a mixed aqueous solution containing sulfuric acid at a concentration of 18% and hydrochloric acid at a concentration of 10%. By using the electrode for plasma treatment on the insulating layer, the electrode potential with respect to the saturated calomel electrode in a mixed aqueous solution containing sulfuric acid at a concentration of 18% and hydrochloric acid at a concentration of 10% is −0.3 V or more. Forming the interface layer to be 0.01 V or less ,
The electrode used for the plasma treatment includes at least one of a nickel-chromium alloy or nickel,
The step of forming the conductor layer includes:
Forming a first seed layer made of a nickel-chromium alloy on the interface layer;
Forming a second seed layer of copper on the first seed layer;
Forming a wiring layer made of copper having a predetermined pattern by electrolytic plating on the second seed layer . The step of forming the wiring pattern includes:
The method of manufacturing the printed circuit board according to claim 1, characterized in that it comprises a step of etching portions of the interface layer and the first and second seed layer except under said wiring layer.

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