JP5348035B2 - projector - Google Patents

Description

  The present invention relates to a projector that displays an image on a projection surface.

  When displaying a rectangular image (hereinafter also referred to as an original image) on a projection surface such as a screen using a projector, the image displayed on the projection surface (hereinafter referred to as a projection image) depending on the relative positional relationship between the projector and the projection surface. (Also referred to as an image) may be distorted into a trapezoid, a parallelogram, or other quadrangle. Including the projection distortion other than the trapezoidal distortion, it is referred to as “trapezoidal distortion” in this specification. In this way, when trapezoidal distortion occurs in the projected image, a technique for correcting trapezoidal distortion that corrects the projected image to be displayed in a rectangular shape by using a projective transformation technique is used.

JP 2007-150531 A

  In a projector that generates image light representing an image using a liquid crystal panel, an image distorted in the opposite direction to the projected image on the projection surface (hereinafter also referred to as a corrected image) when correcting keystone distortion, Produced on a liquid crystal panel. The pixel value of the corrected video is obtained by performing pixel interpolation based on the pixel value of the original video. When obtaining the pixel value of one pixel of the corrected image, for example, the coordinates of the original image corresponding to the pixel of the corrected image are calculated, and pixel interpolation is performed using a plurality of surrounding pixels (for example, surrounding 16 pixels). I do. That is, in the trapezoidal distortion correction processing, since a large amount of processing is performed, it is desired to increase the processing speed.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

Application Example 1 A projector that projects and displays an image on a projection surface,
An image light output unit for generating and outputting image light representing the image;
A frame video storage unit for storing input video data input to the projector as a frame video composed of a plurality of lines;
A storage unit having a smaller capacity and a higher speed than the frame image storage unit, and N × M (N in the line direction and the pixel direction intersecting with the input image data of the frame image stored in the frame image storage unit, respectively. , M ≧ 2) a block video storage unit for storing a part of the input video data of the frame video in units of block video data composed of pixels;
A correction processing unit that performs a correction process for correcting distortion of an image projected on the projection surface, and is based on the block video data stored in the block video storage unit. A correction processing unit that generates corrected video data and outputs the video data representing the image projected on the projection surface to the video light output unit;
With
The correction processing unit corrects the correction prior to storing all of the initialization block video data, which is block video data stored in the block video storage unit at the start of the correction processing on a frame video for one frame. Projector to start processing.

  According to this configuration, since the correction process is performed without waiting for the initialization of the cache block storage unit to be completed, compared with the case where the correction process is started after the initialization of the cache block storage unit is completed. Thus, the processing time from the start of initialization of the cache block storage unit to the completion of correction processing for one frame can be shortened.

[Application Example 2] In the projector described in Application Example 1,
The initialization block video data is determined based on a correction parameter used for the correction process.

  In this way, the block video data required in the correction process can be used as the initialization block video data.

[Application Example 3] In the projector described in Application Example 2,
The correction parameter is a projector for converting the coordinates of the corrected video data into the coordinates of the video data before correction.

  According to this configuration, for example, even when the projector is used while being suspended, appropriate block video data can be used as the initialization block video data.

[Application Example 4] In the projector described in Application Example 2,
When the video after the correction processing is a video that clips and displays the video before the correction processing,
The projector, wherein the correction parameter is a minimum coordinate in the pixel direction of an area to be displayed in an image before the correction process.

  According to this configuration, even when clipping and projecting, appropriate block video data can be used as initialized block video data.

  Note that the present invention can be realized in various modes. For example, it can be realized in a form such as a projective transformation processing device, an image processing device, and an image processing method using a block video storage device.

It is explanatory drawing which shows a trapezoid distortion correction | amendment notionally. It is explanatory drawing which shows notionally the production method of the image data after correction | amendment. It is a figure which shows notionally the method of pixel interpolation. 1 is a block diagram schematically showing a configuration of a projector as an embodiment of the present invention. 3 is a functional block diagram illustrating a configuration of a trapezoidal distortion correction unit 120. FIG. 3 is a diagram schematically showing a relationship between a frame buffer 150 and a cache block storage unit 122. FIG. 4 is a diagram illustrating an example of a cache block stored in a cache block storage unit 122. FIG. It is a figure which shows notionally the relationship between the cache block memory | storage part 122 and the tag information storage part 123 for cache blocks. It is explanatory drawing which shows the example of the hit determination using tag information. It is process drawing which shows typically the flow of the image data generation process after correction | amendment. It is a schematic diagram which shows typically an example of the image | video IG1 after correction | amendment. It is a schematic diagram which shows typically the other example of the image | video IG1 after correction | amendment. FIG. 3 is a diagram showing an inclination angle of the projector 100. It is process drawing which shows typically the flow of the image data generation process after correction | amendment of a comparative example.

Next, embodiments of the present invention will be described in the following order based on examples.
A. First embodiment:
A-1. Overview of keystone correction:
A-2. Projector configuration:
A-3. Keystone distortion correction section:
A-4. Cache block storage configuration:
A-5. Configuration of tag information storage unit for cache block:
A-6. Hit judgment:
A-7. Keystone distortion correction process:
A-8. Effects of the embodiment:
B. Variations:

A. Example:
A-1. Overview of keystone correction:
The projector 100 as one embodiment of the present invention projects image light representing an image and displays the image on a projection surface such as a screen SC. The projector 100 is a projector capable of correcting a trapezoidal distortion of a video displayed on the screen SC and displaying a rectangular video when a rectangular video is input. Prior to the description of the configuration of the projector 100, an outline of trapezoidal distortion correction in the projector 100 of the present embodiment will be briefly described.

  FIG. 1 is an explanatory diagram conceptually showing trapezoidal distortion correction. As shown in the figure, when the projector 100 is arranged with an inclination in the horizontal direction (left-right direction) and the vertical direction (up-down direction) with respect to the screen SC, it is displayed on the liquid crystal panel unit 192. The video (pre-correction video IG0) is rectangular, whereas the video PIG0 projected on the screen SC has a trapezoidal distortion in each of the horizontal and vertical directions. In FIG. 1, for convenience of explanation, the liquid crystal panel unit 192 included in the projector 100 is displayed outside the projector 100.

  Therefore, when a projected image (corrected image IG1) distorted in the opposite direction to the image projected on the screen SC is formed on the liquid crystal panel unit 192 using a projective transformation technique, a rectangular image is displayed on the screen SC. PIG1 is displayed (FIG. 1). In this way, correction for making a video having a trapezoidal distortion appear rectangular (the shape of the video that should be originally displayed) is called a trapezoidal distortion correction.

  FIG. 2 is an explanatory diagram conceptually showing a method of creating corrected video data. FIG. 2A shows a pre-correction video IG0, and FIG. 2B shows a post-correction video IG1. A broken line in FIG. 2B indicates the outer shape of the image IG0 before correction. Since the pre-correction video IG0 has been subjected to video processing so as to be displayed on the full frame of the liquid crystal panel unit 192, the broken line in FIG. 2B indicates the frame of the liquid crystal panel unit 192.

  In the present embodiment, the coordinates of the pre-correction video IG0 and the post-correction video IG1 are pixel coordinates when the pre-correction video IG0 and the post-correction video IG1 are displayed on the liquid crystal panel unit 192. Hereinafter, the pixel coordinates of the liquid crystal panel unit 192 when the corrected image IG1 is displayed are referred to as corrected coordinates. Of the pixel coordinates of the liquid crystal panel unit 192, the pixel coordinates of the area where the corrected image IG1 is not displayed are also referred to using the corrected coordinates. The coordinates obtained by converting the corrected coordinates to the coordinate positions (pixel coordinates of the liquid crystal panel) in the pre-correction video IG0 by reverse projection conversion are referred to as pre-correction coordinates.

  An outline of a method of creating corrected video data representing the corrected video IG1 will be described with reference to FIG. In order to create the corrected video data, the pixel values (R, G, B values) of all the pixel coordinates constituting the corrected video IG1 are obtained based on the pixel values of the uncorrected video IG0. For example, a method of obtaining the pixel value of the coordinate P1 (X, Y) surrounded by the middle square of the corrected image IG1 shown in FIG.

  First, the corrected coordinates P1 (X, Y) for which the pixel value is to be obtained are converted to the uncorrected coordinates P0 (x, y). Since the pre-correction video IG0 and the post-correction video IG1 do not have an integer multiple correspondence, the calculated pre-correction coordinates P0 (x, y) include decimals. Therefore, in order to obtain the pixel value of the post-correction coordinates P1 (X, Y), the pixel values of 16 coordinates near the pre-correction coordinates P0 (x, y) are used to calculate the coordinates of the pre-correction coordinates P0 (x, y). Estimate the pixel value. This is called pixel interpolation. Accordingly, based on the converted pre-correction coordinates P0 (x, y), neighboring pixel blocks are read out, and pixel interpolation is performed using the filter coefficients. Thereby, the pixel value of the coordinate P1 (X, Y) of the corrected image IG1 is obtained. That is, post-correction video data representing the post-correction video IG1 is created by performing pixel interpolation on the pixel values of all pixels (coordinates) constituting the post-correction video IG1 for each pixel.

  FIG. 3 is a diagram conceptually illustrating a pixel interpolation method. FIG. 3 illustrates a method of obtaining the pixel value of the uncorrected coordinate P0 (x, y) obtained by converting the corrected coordinate P1 (X, Y) by pixel interpolation. In the figure, the pre-correction coordinates P0 (x, y) are indicated by hatched circles, and the surrounding 16 coordinates are indicated by white circles. Since the pixel value of the pre-correction coordinate P0 (x, y) is obtained by pixel interpolation, the pixel value of the pre-correction coordinate P0 (x, y) is “interpolated pixel”, and the pixel values of the surrounding 16 coordinates are the pre-correction video data. Since it is known, it is also called “known pixel”.

  In FIG. 3, pixel values of 16 pixels that are known pixels are represented by DATA [m] [n] (m = 0, 1, 2, 3 (x direction); n = 0, 1, 2, 3 (y direction). ). The interpolation pixel is obtained by a convolution operation of the pixel value of 16 pixels and the filter coefficient. The filter coefficient takes into account the influence of the distance between the interpolation pixel and the known pixel (for example, the distance between the known pixel of DATA [1] [1] and the interpolation pixel is dx in the x direction and dy in the y direction). It is a coefficient and is determined for each known pixel. In FIG. 3, the filter coefficients are indicated as COEF [m] [n] (m = 0, 1, 2, 3 (x direction); n = 0, 1, 2, 3 (y direction)). In this embodiment, a two-dimensional filter coefficient is used, but the filter coefficient may be decomposed into one dimension.

A-2. Projector configuration:
FIG. 4 is a block diagram schematically showing a configuration of a projector as an embodiment of the present invention. As illustrated, the projector 100 includes a video input unit 110, an IP conversion unit 112, a resolution conversion unit 114, a video synthesis unit 116, a trapezoidal distortion correction unit 120, a liquid crystal panel drive unit 140, and a frame buffer 150. A high-speed bus control unit 160, a low-speed bus control unit 162, a processor unit 170, an imaging unit 180, a sensor unit 182, an illumination optical system 190, a liquid crystal panel unit 192, and a projection optical system 194. It is structured in the center. Among the components described above, the components other than the illumination optical system 190, the liquid crystal panel unit 192, and the projection optical system 194 are connected to each other via the high-speed bus 102 or the low-speed bus 104.

  The video input unit 110 performs A / D conversion on an input video signal input from a DVD player or personal computer (not shown) via a cable, if necessary, and supplies the digital video signal to the IP conversion unit 112.

  The IP conversion unit 112 executes processing for converting the format of the video data supplied from the video input unit 110 from the interlace method to the progressive method, and supplies the obtained video data to the resolution conversion unit 114.

  The resolution conversion unit 114 performs a size enlargement process or a reduction process (that is, resolution conversion process) on the video data supplied from the IP conversion unit 112, and supplies the obtained video data to the video synthesis unit 116. To do.

  The video composition unit 116 synthesizes the video data supplied from the resolution conversion unit 114 and an OSD (On Screen Display) such as a menu screen, and writes the resultant data in the frame buffer 150 as pre-correction video data.

  The frame buffer 150 can store data of one frame or a plurality of frames. In this embodiment, an inexpensive and large-capacity DRAM (Dynamic Random Access Memory) is used as the frame buffer 150. The frame buffer 150 in this embodiment corresponds to a frame video storage unit in the claims.

  The trapezoidal distortion correction unit 120 corrects trapezoidal distortion that occurs when projection is performed with the projection axis of the projector 100 tilted with respect to the screen SC. Specifically, in order to display the pre-correction video represented by the pre-correction video data stored in the frame buffer 150 on the liquid crystal panel unit 192 in a shape that compensates for trapezoidal distortion, the correction processing is performed on the pre-correction video data. The corrected video data is supplied to the liquid crystal panel driving unit 140. The trapezoidal distortion correction unit 120 will be described in detail later.

  The liquid crystal panel drive unit 140 drives the liquid crystal panel unit 192 based on the digital video signal input through the trapezoidal distortion correction unit 120. The liquid crystal panel unit 192 includes a transmissive liquid crystal panel in which a plurality of pixels are arranged in a matrix. The liquid crystal panel unit 192 is driven by the liquid crystal panel driving unit 140, and changes the light transmittance in each pixel arranged in a matrix, thereby changing the illumination light emitted from the illumination optical system 190 to an effective image. An image for modulation into a new image light is formed. In this embodiment, the mode of the liquid crystal panel unit 192 is WUXGA, and the resolution is 1920 × 1200 dots. In this embodiment, the liquid crystal panel pixel coordinates are defined as x = 0 to 1919 and y = 0 to 1199. The liquid crystal panel unit 192 may have a resolution different from that of this embodiment.

  The illumination optical system 190 includes, for example, lamps such as a high pressure mercury lamp and an ultrahigh pressure mercury lamp, and other light emitters. The projection optical system 194 is attached to the front surface of the housing of the projector 100, expands the light modulated into the image light by the liquid crystal panel unit 192, and projects it onto the screen SC. The projection optical system 194 includes a zoom lens (not shown), and can change the degree of enlargement (zoom state) when projecting light transmitted through the liquid crystal panel unit 192. The liquid crystal panel driving unit 140, the liquid crystal panel unit 192, the illumination optical system 190, and the projection optical system 194 in this embodiment correspond to the image light output unit in the claims.

  The processor unit 170 controls the operation of each unit in the projector 100 by reading and executing a control program stored in a storage unit (not shown). Further, corrected coordinates (X0 to X3, Y0 to Y3) described later based on the captured image captured by the imaging unit 180, the tilt of the projector 100 detected by the sensor unit 182 and the instruction from the user (FIG. 2), a coordinate conversion coefficient (described in detail later) of the coordinate conversion matrix is calculated and output to the trapezoidal distortion correction unit 120. In this embodiment, the processor unit 170 is configured to receive an instruction from the user through an operation panel (not shown) provided in the main body of the projector 100. For example, the instruction from the user through a remote control is controlled by the remote controller. The processor unit 170 may receive the instruction from the user via the low-speed bus 104.

  The imaging unit 180 has a CCD camera and generates a captured video. The captured video generated by the imaging unit 180 is stored in a captured video memory (not shown). Note that the imaging unit 180 may have another imaging device instead of the CCD camera.

  The sensor unit 182 can detect the tilt angle formed by the CCD optical axis of the imaging unit 180 and the horizontal plane by detecting the tilt of the projector 100 from the vertical direction.

A-3. Keystone distortion correction section:
As described above, the trapezoidal distortion correction unit 120 generates post-correction video data in which the pre-correction video represented by the pre-correction video data stored in the frame buffer 150 is corrected to a shape that compensates for trapezoidal distortion. FIG. 5 is a functional block diagram illustrating a configuration of the trapezoidal distortion correction unit 120. The trapezoidal distortion correction unit 120 includes a cache block control unit 121, a cache block storage unit 122, a cache block tag information storage unit 123, an interpolation block reading unit 124, a pixel interpolation unit 125, a FIFO unit 126, and a register. The unit 127, the control unit 128, the coordinate conversion unit 129, the filter coefficient calculation unit 130, and the hit determination unit 131 are mainly configured.

  The cache block control unit 121 acquires the pre-correction video data stored in the frame buffer 150 for each pixel block composed of 8 × 8 pixels and stores it in the cache block storage unit 122. In the following description, a block of pixels composed of 8 × 8 pixels is referred to as a “cache block”. Further, the cache block control unit 121 updates the tag information stored in the cache block tag information storage unit 123. As will be described later, the cache block acquired by the cache block control unit 121 is predetermined when the cache block storage unit 122 is initialized, and is designated by the hit determination unit 131 after the initialization is completed. Is done. In this embodiment, when the trapezoidal distortion correction process for one frame is started, a cache block to be stored first (hereinafter also referred to as “initialization block”) is read from the frame buffer 150 and stored in the cache block storage unit 122. Writing is referred to as “initialization of the cache block storage unit 122”.

  The cache block storage unit 122 can store a part of the pre-correction video data for one frame stored in the frame buffer 150 in units of cache blocks including 8 × 8 pixels. The cache block storage unit 122 includes a plurality of block areas in which one cache block (video data composed of 8 × 8 pixels) can be stored. In this embodiment, as will be described in detail later, the cache block storage unit 122 includes a block area of 240 columns × 4 rows. In this embodiment, the cache block storage unit 122 is configured by a small capacity and high speed SRAM (Static Random Access Memory). The cache block storage unit 122 in this embodiment corresponds to the block video storage unit in the claims.

  The cache block tag information storage unit 123 stores tag information that is management information when the cache block storage unit 122 is managed in units of block areas.

  The interpolation block reading unit 124 reads out an interpolation block composed of 4 × 4 pixels necessary for pixel interpolation in the pixel interpolation unit 125 from the cache block storage unit 122 and supplies it to the pixel interpolation unit 125. As will be described in detail later, when the pre-correction coordinates are outside the pre-correction video data, that is, outside the range of the pre-correction video IG0 shown in FIG. The background color data is supplied to the pixel interpolation unit 125 as an interpolation block.

  The pixel interpolation unit 125 executes pixel interpolation processing based on the interpolation block supplied from the interpolation block reading unit 124 and the filter coefficient supplied from the filter coefficient calculation unit 130, and performs interpolation pixel (corrected video pixel). Is obtained and output to the liquid crystal panel driving unit 140 (FIG. 4) via the FIFO unit 126.

  The register unit 127 stores parameters supplied from the processor unit 170. Specifically, the register unit 127 includes parameters such as the frame width and frame height of the pre-correction video, the coordinate conversion coefficients A to H of the coordinate conversion matrix, and background colors (for example, black, gray, blue). Etc.) is stored as background color data. The coordinate conversion coefficients A to H are calculated by the processor unit 170 using the following determinant (formula 1) of projective transformation. Specifically, the processor unit 170 converts the uncorrected coordinates (x0 to x3, y0 to y3) (see FIG. 2) into the corrected coordinates (X0 to X3, Y0 to Y3) (see FIG. 2) by projective transformation. As converted, the four coordinates (X0 to X3, Y0 to Y3) of the corrected image IG1 are input to the determinant (Formula 1) to derive the coordinate conversion coefficients A to H. The coordinate conversion coefficients A to H in the present embodiment correspond to correction parameters in claims.

  In this embodiment, before the correction image data generation process is started, the image PIG0 displayed on the screen SC before the trapezoidal distortion correction is imaged by the imaging unit 180. The processor unit 170 (FIG. 4) obtains the coordinates (X0 to X3, Y0 to Y3) (FIG. 2B) of the four vertices in the corrected image IG1 after the trapezoidal distortion correction based on the captured image. Yes.

  Note that the sensor unit 182 may detect the inclination of the projector 100 from the vertical direction, and obtain corrected coordinates (X0 to X3, Y0 to Y3) based on the detected angle. Also, the keystone distortion correction may be performed manually by the user operating the remote controller. In such a case, the processor unit 170 obtains corrected coordinates (X0 to X3, Y0 to Y3) based on an instruction from the user received via the remote control unit.

  The control unit 128 controls the trapezoidal distortion correction unit 120 in general. For example, a frame start signal indicating the start of a frame is output to all blocks in accordance with the synchronization signal input to the control unit 128. For example, when 60 frames are displayed per second, the synchronization signal is input every 1/60 seconds. In FIG. 5, the arrow indicating the output of the frame start signal for the blocks other than the cache block control unit 121 and the coordinate conversion unit 129 is omitted for the sake of easy viewing.

  The coordinate conversion unit 129 uses the coordinate conversion coefficients A to H supplied from the register unit 127 and the following (Expression 2) and (Expression 3) to correct the coordinates of the corrected image IG1 after performing the trapezoidal distortion correction. The value (coordinate after correction) is converted into the coordinate value (coordinate before correction) of the pre-correction video IG0 (rectangular video). Since the pre-correction video IG0 and the post-correction video IG1 do not have an integer multiple correspondence, the pre-correction coordinates calculated by the coordinate conversion unit 129 include decimals. The coordinate conversion unit 129 divides the uncorrected coordinates into an integer part and a decimal part, supplies the integer part to the hit determination unit 131, and supplies the decimal part to the filter coefficient calculation unit 130.

  Here, the above-described calculation method of the pre-correction coordinates will be described. Since the corrected image IG1 is considered to be an image obtained by projective transformation of the uncorrected image IG0, the uncorrected coordinates are based on the following (Expression 2) and (Expression 3) with respect to the corrected coordinates. Then, it is calculated by reverse projective transformation. It is assumed that the uncorrected coordinates (x, y) are converted to corrected coordinates (X, Y) by projective transformation.

上記（式２）、（式３）中の係数Ａ〜Ｈは、レジスター部１２７に記憶されている。

The coefficients A to H in the above (Expression 2) and (Expression 3) are stored in the register unit 127.

  Based on the decimal part supplied from the coordinate conversion unit 129, the filter coefficient calculation unit 130 selects a filter coefficient used when executing the pixel interpolation process from the filter coefficient table, and selects the selected filter coefficient as a pixel. This is supplied to the interpolation unit 125. The filter coefficient table is a table showing the relationship between the distance between the interpolation pixel and the known pixel shown in FIG. 3 and the filter coefficient, and a result calculated in advance is stored in a memory included in the filter coefficient calculation unit 130.

  The hit determination unit 131 first determines whether or not the pre-correction coordinates are the background, based on the integer part of the pre-correction coordinates supplied from the coordinate conversion unit 129. If it is determined that it is not the background, the hit determination unit 131 determines that the pixel value of the coordinates used for pixel interpolation in the pixel interpolation unit 125 is based on the integer part of the coordinates before correction supplied from the coordinate conversion unit 129. It is determined whether it is stored in the storage unit 122. Hereinafter, this determination is referred to as “hit determination”. As a result of the hit determination, when a pixel value necessary for pixel interpolation is not stored in the cache block storage unit 122, a request for acquiring a necessary cache block is issued to the cache block control unit 121. As a result of the hit determination, when a pixel value necessary for pixel interpolation is stored in the cache block storage unit 122, the read position in the cache block storage unit 122 is supplied to the interpolation block reading unit 124. The flow of the hit determination process will be described later.

A-4. Cache block storage configuration:
FIG. 6 is a diagram schematically illustrating the relationship between the frame buffer 150 and the cache block storage unit 122. FIG. 6 shows a state where the pre-correction video data for one frame stored in the frame buffer 150 is divided into cache block units each consisting of 8 × 8 pixels. In this embodiment, the pre-correction video data stored in the frame buffer 150 is composed of 1920 × 1200 pixels, and such pre-correction video data is divided into 240 × 150 cache blocks. The character string (x, y) described in each cache block indicates the position (column number, line number) in the x direction and y direction of the cache block. In this embodiment, the direction in which the columns are arranged is the x direction, and the direction in which the row direction rows are arranged is the y direction. The x direction in this embodiment corresponds to the line direction in the claims, and the y direction corresponds to the pixel direction in the claims.

  The cache block storage unit 122 includes 240 × 4 rows of block areas that can store one cache block. In FIG. 6, in order to identify each block area, numbers (column (0-239), row (0-3)) are given. The cache block storage unit 122 can store a portion of 240 × 4 pieces of pre-correction video data for one frame stored in the frame buffer 150.

  In this embodiment, when a frame start signal is input to the cache block control unit 121, the cache blocks (0, 0) to (239, 3) are read from the frame buffer 150 and stored in the cache block storage unit 122. (Initialization of the cache block storage unit 122). The cache block is stored in the block area having the same column number as the column number of each cache block in the cache block storage unit 122. Therefore, when the trapezoidal distortion correction process is started, each block area of the cache block storage unit 122 stores a cache block having the same column number and row number as the column number and row number of the block area. (FIG. 6). That is, the width of the cache block storage unit 122 is the same as the width of the frame buffer 150, the height of the cache block storage unit 122 is 4 cache blocks, and the cache block storage unit 122 includes 32 lines of 1 frame. Pixel data for (4 cache blocks × 8 px) is stored.

  FIG. 7 is a diagram illustrating an example of a cache block stored in the cache block storage unit 122. The cache block stored in the cache block storage unit 122 is updated as the trapezoidal distortion correction process proceeds. When a cache block read request (cache block request) is input from the hit determination unit 131, the cache block control unit 121 receives a specified coordinate position (column, row) from the frame buffer 150 based on the cache block request. The cache block is read out, and the read cache block is stored in the designated block area (column, row) of the cache block storage unit 122. Therefore, during the trapezoidal distortion correction process, as shown in FIG. 7, the cache block stored in the cache block storage unit 122 is a cache block at a position as illustrated in the frame buffer 150.

  The interpolation block is shown by hatching in FIG. In this embodiment, since the cache block is composed of 8 × 8 pixels and the interpolation block is composed of 4 × 4 pixels, the interpolation block becomes a part of the cache block. As will be described later, an interpolation block necessary for pixel interpolation is read based on position information supplied from the hit determination unit 131.

  The interpolation block is included in (1) one cache block, (2) straddling two cache blocks adjacent in the y direction, (3) straddling two cache blocks adjacent in the x direction, (4 ) There are cases where it extends over four cache blocks of 2 rows × 2 columns. In FIG. 7, (4) the case of straddling four cache blocks of 2 rows × 2 columns is illustrated.

A-5. Configuration of tag information storage unit for cache block:
The cache block tag information storage unit 123 stores tag information that is management information when the cache block storage unit 122 is managed in units of block areas. FIG. 8 is a diagram conceptually showing the relationship between the cache block storage unit 122 and the cache block tag information storage unit 123. As shown in the figure, the cache block tag information storage unit 123 stores 240 × 4 tag information corresponding to the 240 × 4 block areas of the cache block storage unit 122.

  Specifically, as tag information, (1) information indicating whether or not to wait for writing from the frame buffer 150 to the cache block storage unit 122 (WRITING = 1 in the case of waiting for writing), and (2) data in the block area is valid. (Valid = 1 when valid, valid = 0 when invalid), and (3) a coordinate Y_ADR indicating where in the frame buffer 150 the cache block stored in the block area is located Stored. The coordinate Y_ADR in (3) holds information in which the y coordinate in the frame buffer 150 of the upper left pixel of the cache block is 1/8. In this embodiment, the line number shown in FIG. 6 is set as the coordinate Y_ADR. In (2), “valid” indicates that the cache block at the coordinate Y_ADR is stored in the cache block storage unit 122, and “invalid” indicates that the cache block at the coordinate Y_ADR is not stored in the cache block storage unit 122. As described above, when the cache block specified by the hit determination unit 131 or the initialization block is stored in the cache block storage unit 122, the cache block control unit 121 corresponds to the cache block tag information storage unit 123. The tag information to be updated is updated to VALID = 1 and WRITEING = 0.

A-6. Hit judgment:
FIG. 9 is an explanatory diagram illustrating an example of hit determination using tag information. In FIG. 9, the cache block storage unit 122 is being initialized, and the cache blocks (0, 0) to (239, 1) in the cache block storage unit 122 are transferred to the cache blocks (0, 0) to (239, 1). ) Is illustrated as an example. That is, tag information related to the block area (2, 0) in the cache block storage unit 122 is stored in 2 columns and 0 rows of the cache block tag information storage unit 123. The 16 pixels used for pixel interpolation are (x [0], y [0]), (x [1], y [1]), (x [2], y [2]), ..., (x [15], y [15]), hit determination is performed pixel by pixel in order from (x [0], y [0]). For example, hit determination when (x [0], y [0]) = (16, 16) will be described with reference to FIG.

  When determining whether or not a cache block including (x [0], y [0]) = (16, 16) is stored in the cache block storage unit 122, first, the hit determination unit 131 uses the cache block The tag of the corresponding column is extracted from the tag information storage unit 123. Since one cache block is composed of 8 × 8 pixels, the corresponding column can be obtained by dividing the x coordinate of the pixel used for pixel interpolation by 8. Since (x [0], y [0]) = (16, 16) corresponds to the second column, the tag in the second column is extracted.

  In FIG. 9, the extracted tag information is written on the right side of the page. Hit determination is performed in ascending order of tag line numbers. Hereinafter, tag information is represented by TAG [line number]. TAG [0] is WRITEING = 0, VALID = 1, and Y_ADR = 0. WRITEING = 0 indicates that writing is not waiting, and VALID = 1 indicates that data is valid. When Y_ADR = 0 is converted into the y coordinate of the pre-correction video, 0 × 8 = 0. That is, according to TAG [0], it can be seen that there is a block in the cache block storage unit 122 in which the y coordinate of the pixel at the upper left corner of the cache block is y coordinate = 0 in the pre-correction video.

  TAG [1] is WRITEING = 0, VALID = 1, and Y_ADR = 1. WRITEING = 0 indicates that writing is not waiting, and VALID = 1 indicates that data is valid. When Y_ADR = 1 is converted into the y coordinate of the pre-correction video, 1 × 8 = 8. That is, according to TAG [1], it can be seen that there is a block in the cache block storage unit 122 in which the y coordinate of the upper left pixel of the cache block is y coordinate = 8 in the pre-correction video.

  TAG [2] is WRITEING = 1, VALID = 0, and Y_ADR = 2. WRITEING = 1 indicates that the writing is waiting, and VALID = 0 indicates that the data is invalid. When Y_ADR = 2 is converted to the y coordinate of the pre-correction video, 2 × 8 = 16. That is, according to TAG [2], it can be seen that a block in which the y coordinate of the pixel at the upper left corner of the cache block has y coordinate = 16 in the pre-correction video is waiting for writing, and can be read after a while.

  TAG [3] is WRITEING = 1, VALID = 0, and Y_ADR = 3. WRITEING = 1 indicates that the writing is waiting, and VALID = 0 indicates that the data is invalid. When Y_ADR = 3 is converted into the y coordinate of the pre-correction video, 3 × 8 = 24. That is, according to TAG [3], it can be seen that the block whose y coordinate of the upper left pixel of the cache block is y coordinate = 24 in the pre-correction video is waiting for writing.

  That is, as a result of determining whether or not a cache block including (x [0], y [0]) = (16, 16) is stored in the cache block storage unit 122, (x [0], y [0 ]) = (16, 16) is included in the cache block, and after a while, it is determined that it can be read out.

A-7. Keystone distortion correction process:
In this embodiment, the trapezoidal distortion correction processing is all processing executed in the trapezoidal distortion correction unit 120, that is, cache block storage processing from the frame buffer 150 to the cache block storage unit 122, and corrected video data generation processing. including. In the trapezoidal distortion correction unit 120 in this embodiment, when a frame start signal is output from the control unit 128 (FIG. 5) and input to the cache block control unit 121 (FIG. 5) and the coordinate conversion unit 129 (FIG. 5), The cache block control unit 121 reads the initialization block and writes it to the cache block storage unit 122 (starts initialization of the cache block storage unit 122). At the same time, the coordinate conversion unit 129 coordinates the corrected video (corrected coordinate). Is converted to the coordinates before correction. That is, in this embodiment, the corrected video data generation process is started simultaneously with the start of initialization of the cache block storage unit 122. In other words, the corrected video data generation process is started prior to completion of initialization of the cache block storage unit 122. In this embodiment, the initialization block is a cache block of (0, 0) to (239, 3) as described above. The corrected video data generation processing in this embodiment corresponds to the correction processing in the claims, and the initialization block corresponds to the initialization block video data in the claims.

  The flow of initialization of the cache block storage unit 122 will be described below. First, when a frame start signal is input, the cache block control unit 121 (FIG. 5) updates all tag information stored in the cache block tag information storage unit 123. Specifically, the cache block coordinates Y_ADR stored in each block area of the cache block storage unit 122 upon initialization of the cache block storage unit 122 are written, WRITEING = 1 (waiting to be written), VALID = 0 (block area Data is invalid).

  At the same time as updating the tag information, the cache block control unit 121 reads the initialization block from the frame buffer 150 and starts writing to the cache block storage unit 122. When one cache block is stored in the initialization process, the corresponding tag information in the cache block tag information storage unit 123 is updated by the cache block control unit 121, and WRINTING = 0 and VALID = 1.

  FIG. 10 is a process diagram schematically showing the flow of the corrected video data generation process. The coordinate conversion unit 129 (FIG. 5) determines whether or not a frame start signal has been input (step S102). The coordinate conversion unit 129 waits until the frame start signal is input (NO in step S102). When the frame start signal is input (YES in step S102), as described above, the coordinates of the corrected video are obtained. The coordinates before correction are obtained by converting the coordinates after correction (step S104).

  When the integer part of the pre-correction coordinates calculated by the coordinate conversion unit 129 is input to the hit determination unit 131 (FIG. 5), the hit determination unit 131 first determines whether or not the surrounding pixel of the pre-correction coordinates is the background (step S106). . This peripheral pixel is a pixel constituting an interpolation block for obtaining the pixel value of the corrected coordinate corresponding to the calculated pre-correction coordinate by interpolation. Specifically, this process is a process for determining whether or not all the peripheral pixels, that is, all the 16 pixels constituting the interpolation block are the background. The coordinates of each peripheral pixel can be easily specified from the calculated pre-correction coordinates. If this point is described using the pixel arrangement shown in FIG. 3, when the pre-correction coordinates are calculated as P0 (x, y), the coordinates (Int (x), Int ( Since y)) corresponds to the coordinates of the known pixels of DATA [1] [1] shown in FIG. 3, the coordinates of the known pixels of DATA [0] [0] are (Int (x) −1, Int (y ) -1). Similarly, the coordinates of the known pixel of DATA [3] [0] are (Int (x) +2, Int (y) -1), and the coordinates of the known pixel of DATA [3] [3] are (Int (x) +2, Int (y) +2), the coordinates of the known pixels of DATA [0] [3] are (Int (x) -1, Int (y) +2). Therefore, in this embodiment, any one of the integer part Int (x) +2 <x0, Int (x) +2 <x3, Int (x) -1> x1, Int (x) -1> x2 of the x coordinate before correction. Or the integer part Int (y) +2 <y0, Int (y) +2 <y1, Int (y) -1> y2, Int (y) -1> y3 of the y-coordinate before correction If the condition is satisfied, all the surrounding pixels are determined to be the background. x0 to x3, y0 to y3 are shown in FIG. Specifically, in this embodiment, (x0, y0) = (0, 0), (x1, y1) = (1919, 0), (x2, y2) = (1919, 1199), (x3, y3) ) = (0, 1199), Int (x) +2 <0 (ie, negative), Int (x) -1> 1919, Int (y) +2 <0 (ie, negative), Int (y) When any one of −1> 1199 is satisfied, all the surrounding pixels are determined to be the background. Note that the same determination can be made by using the pre-correction x coordinate including the decimal part and the pre-correction y coordinate instead of Int (x) and Int (y).

  If all of the surrounding pixels are determined to be the background in the hit determination unit 131 (YES in step S106), it is not necessary to perform interpolation, so there is no need to refer to the cache block tag information storage unit 123. . Therefore, the interpolation block reading unit 124 reads the background color data from the register unit 127 and supplies it to the pixel interpolation unit 125 (FIG. 5) (step S112).

  On the other hand, when the hit determination unit 131 determines that at least one of the peripheral pixels is not the background (NO in step S106), the peripheral pixel that is not the background among all the peripheral pixels is specified, and the peripheral that is not the specified background Hit determination is performed for the pixel (step S108). For the peripheral pixels that are not backgrounds, the value X that is the x coordinate of the peripheral pixels satisfies all of X ≧ x0, X ≧ x3, X ≦ x1, and X ≦ x2 for each of the peripheral pixels, and y This can be done by determining whether or not the value Y as coordinates satisfies all of Y ≧ y0, Y ≧ y1, Y ≦ y2, and Y ≦ y3. A peripheral pixel that satisfies these conditional expressions is specified as a peripheral pixel that is not a background. As a result of the hit determination, if WRITEING = 1 (waiting for writing) is found (NO in step S108), the hit determination unit 131 issues a cache block request to the cache block control unit 121, and a predetermined time has elapsed. After that, step S108 is performed again. That is, steps S108 and S110 are repeated until the target cache block is stored in the cache block storage unit 122.

  In this embodiment, when the initialization of the cache block storage unit 122 is not completed, the process of initialization of the cache block storage unit 122 is awaited by repeating steps S108 and S110. When the initialization process proceeds and the target cache block is stored, the tag information in the cache block tag information storage unit 123 is updated, and WRINTING = 0 and VALID = 1. Hit determination is performed again (step S108). If it is determined that the tag corresponding to the block area in which the target cache block is stored is WRINTING = 0 and VALID = 1 (YES in step S108), the hit The determination unit 131 supplies the interpolation block reading position to the interpolation block reading unit 124.

  When the interpolation block readout position is supplied to the interpolation block readout unit 124, the interpolation block readout unit 124 (FIG. 5) reads out the interpolation block from the cache block storage unit 122 based on the supplied readout position (step S112). . On the other hand, the filter coefficient calculation unit 130 (FIG. 5) selects a filter coefficient from the filter coefficient table based on the decimal part of the coordinates before correction obtained in step S104. The interpolation block reading process in the interpolation block reading unit 124 and the filter coefficient calculation process in the filter coefficient calculation unit 130 are performed in parallel. When both processes are completed, the process proceeds to step S116.

  When the interpolation block is supplied from the interpolation block reading unit 124 and the filter coefficient is supplied from the filter coefficient calculation unit 130, the pixel interpolation unit 125 (FIG. 5) performs convolution using the supplied interpolation block and filter coefficient. A pixel value of the corrected coordinates is calculated by calculation (step S116). When background color data is supplied to the pixel interpolation unit 125, the pixel value of the corrected coordinates calculated by the pixel interpolation unit 125 becomes background color data.

  By repeating the above steps S102 to S116 until the corrected coordinates (X, Y) = (0, 0) to (frame width −1, frame height −1), corrected video data is generated. The In this embodiment, since the frame width is 1920 and the frame height is 1200, steps S102 to S116 are repeated until the corrected coordinates (X, Y) = (0, 0) to (1919, 1199). When the frame width and the frame height are different from those of the present embodiment, the steps S102 to S116 are performed after the corrected coordinates (X, Y) = (0, 0) to (frame width−1, frame height− By repeating the process up to 1), corrected video data is generated.

A-8. Effects of the embodiment:
As described above, according to the projector 100 in this embodiment, when the frame start signal is input to the cache block control unit 121 and the coordinate conversion unit 129, the initialization of the cache block storage unit 122 is started. The corrected video data generation process is started. That is, the post-correction video data generation processing is performed before completion of initialization of the cache block storage unit 122 without waiting for the initialization of the cache block storage unit 122 to be completed. Therefore, compared with the case where the corrected video data generation process is started after the initialization of the cache block storage unit 122 is completed (comparative example described later), the correction for one frame from the start of the initialization of the cache block storage unit 122 It is possible to reduce the processing time required for the trapezoidal distortion correction processing, which is the processing time until the generation of the subsequent video data is completed.

  In a computer, generally, frequently used data is temporarily stored in a cache memory that is faster than the main memory, and information is transferred between the cache memory and the CPU instead of the main memory having a low operation speed. By exchanging, the processing speed is increased. In a computer, when data necessary for processing is normally read from the main memory and stored in the cache memory, the data used last time is stored as it is in the next processing, and is necessary for the next processing. If the data exists in the cache memory, the data is used. If not, the necessary data is read from the main memory and stored in the cache memory. In contrast, in this embodiment, the frame buffer 150 functions as a main memory, and the cache block storage unit 122 functions as a cache memory. In this embodiment, in the trapezoidal distortion correction process, since the data to be stored first in the cache block storage unit 122 is known in advance, the concept of “initialization of the cache block storage unit 122” is introduced. In general, data processing is not started until the initialization of the storage device is completed, but in this embodiment, the corrected video data generation processing is started prior to the completion of initialization of the storage device (cache block storage unit 122). Therefore, it is possible to shorten the processing time when a large amount of processing is performed as in the trapezoidal distortion correction processing.

  Hereinafter, the effect of the present embodiment will be described in detail by exemplifying the corrected image IG1 (FIGS. 11 and 12). FIG. 11 is a schematic diagram schematically illustrating an example of the corrected image IG1, and FIG. 12 is a schematic diagram schematically illustrating another example of the corrected image IG1. In FIGS. 11 and 12, the area displayed in the background color is displayed with hatching. FIG. 11 exemplifies a corrected image IG1 when the projector 100 is disposed at an angle of 45 degrees (θy = 45) and 20 degrees (θx = 20). FIG. 13 is a diagram illustrating the tilt angle of the projector 100. As shown in FIG. 13A, when the state in which the projector 100 is arranged facing the screen SC is viewed from the side, the arrangement of the projector 100 when the projection axis of the projector 100 is perpendicular to the screen is shown. The vertical angle is 0 degree (θy = 0), and the elevation angle is θy (vertical angle). As shown in FIG. 13B, when the projector 100 is disposed facing the screen SC as viewed from above, the arrangement of the projector 100 when the projection axis of the projector 100 is perpendicular to the screen. The horizontal angle is 0 degree (θx = 0), and the clockwise angle is θx (lateral angle).

  In the example shown in FIG. 11, the area AR1 up to the line indicated by the broken line at the top of the liquid crystal panel unit 192 is the background color. As shown in FIG. 2, the trapezoidal distortion correction processing is performed on the liquid crystal panel unit 192 line by line from the top to the bottom of the liquid crystal panel unit 192 (from the smallest coordinate in the pixel direction to the larger one). The drawing is processed from the left to the right (from the smallest coordinate to the largest coordinate in the line direction). In the post-correction video data generation process, since the background color is all processed while the area AR1 is processed, the process can proceed even if no cache block is stored in the cache block storage unit 122. Therefore, the processing time required for the trapezoidal distortion correction process can be shortened by starting the corrected video data generation process without waiting for the initialization of the cache block storage unit 122 to be completed. If the initialization of the cache block storage unit 122 is completed while the corrected video data generation process for the area AR1 is being performed, the cache block storage unit 122 when calculating the pixel value of the corrected video IG1 is sent to the cache block storage unit 122. Cache block write latency can be reduced.

  FIG. 12 exemplifies a corrected image IG1 when the projector 100 is disposed at an angle of 20 degrees (θy = 20) and 30 degrees (θx = 30). In the example shown in FIG. 12, the first few pixels on the first line of the liquid crystal panel unit 192 (shown as AR2 in FIG. 12) are the background color, but the corrected video IG1 is displayed from the first line. After the start of the corrected video data generation process, the uncorrected video data is required earlier than the example shown in FIG. Even in such a case, the cache block storage unit 122 can be initialized while the corrected video data generation process for the first few pixels on the first line of the liquid crystal panel unit 192 is being advanced. Compared to the case where the corrected video data generation process is started after the initialization of the cache block storage unit 122 is completed, the processing time of the trapezoidal distortion correction process can be shortened.

  Hereinafter, as a comparative example, a process flow when the corrected video data generation process is started after completion of initialization of the cache block storage unit 122 will be described. FIG. 14 is a process diagram schematically showing the flow of the corrected video data generation process of the comparative example. In the comparative example, as in the present embodiment, when a frame start signal is input (step T102), the coordinates before correction are calculated for the corrected coordinates (0, 0) (step T104). Subsequently, the hit determination unit 131 determines whether or not the initialization of the cache block storage unit 122 has been completed (step T106). Until the initialization of the cache block storage unit 122 is completed, step T106 is repeated and the process does not proceed to the next step. When the initialization of the cache block storage unit 122 is completed, for the first time, after performing interpolation block reading (step T112) and filter coefficient calculation (step T114) for the corrected coordinates (0, 0), pixel interpolation is performed. Calculation processing is performed (step T116). That is, the processing time required for the trapezoidal distortion correction processing is the time required for initialization of the cache memory + the time required for the corrected video data generation processing per frame.

  In addition to the above effects, in the present embodiment, in the cache block tag information storage unit 123, the tag information corresponds to all the block areas included in the cache block storage unit 122 and is arranged in the same arrangement as the block areas. Stored. The cache block is stored in the block area having the same column number as the cache block. Therefore, when the hit determination is performed, the tag information column is first extracted for the coordinates to be hit-determined, and the hit determination is sequentially performed for the column. Judgment can be speeded up.

  In this embodiment, since a large-capacity and low-speed frame buffer (DRAM) is used as the primary buffer and a small-capacity and high-speed cache memory (SRAM) is used as the secondary buffer, the cost can be reduced. it can.

B. Modifications The present invention is not limited to the above-described embodiments, and can be implemented in various modes without departing from the scope of the invention.

  (1) In the above-described embodiment, an example in which the cache blocks (0, 0) to (239, 3) are the initialization blocks has been described. However, the initialization block is not limited to the above-described embodiment, and trapezoidal distortion correction is performed. A cache block that is likely to be required for processing may be used as an initialization block. For example, when tiling projection is performed (projecting and displaying an image using two or more projectors), if a part of the upper part of the uncorrected image is unnecessary, the uppermost portion of the necessary uncorrected image data A cache block of 4 rows × 240 columns including a cache block including these lines may be used as an initialization block. Similarly, when clipping and projecting, a cache block of 4 rows × 240 columns including a cache block including the uppermost line of necessary video data may be used as an initialization block. That is, when clipping and projecting, the initial block may be determined based on the minimum coordinate (minimum line) in the pixel direction of the area to be displayed in the pre-correction video. In addition, when the projector 100 is used while being suspended, for example, when the trapezoidal distortion correction process is started from the bottom line, the cache blocks (0, 146) to (239, 149 including the bottom line are included. ) May be the initial block. Specifically, if the coordinate transformation coefficients E and H are negative, it is determined that the suspension is reversed, and the block is determined as an initialization block. In other words, the initial block may be determined based on the coordinate conversion coefficients E and H. The initialization block may not be 4 rows × 240 columns.

  (2) In the above-described embodiment, the prefetching in which the cache block required for the subsequent pixel interpolation process is predicted and the cache block is stored in the cache block storage unit 122 while the trapezoidal distortion correction process is in progress. You may make it the structure which processes. In this way, the processing time of the trapezoidal distortion correction process can be further shortened.

  (3) The number of pixels in one frame, the number of pixels in the cache block, and the number of pixels in the interpolation block (number of pixels used for pixel interpolation) are not limited to the above-described embodiments.

  (4) You may comprise as a projective transformation processing apparatus provided with the frame buffer 150 and the trapezoid distortion correction part 120 in an above-described Example. For example, a video display device configured to display a video on a video display unit such as a liquid crystal panel or an organic EL (Electro-Luminescence) panel based on the video data converted by the projective conversion processing device can do. Further, a digital camera including a projection conversion processing device and a video display unit such as a liquid crystal panel may be configured. In this case, the projective transformation processing device corrects distortion (perspective distortion) that occurs when the camera sensor is not parallel to the subject and outputs it to the video display unit, so that the camera sensor applies to the subject. The images captured so as to be parallel to each other are displayed on the image display unit. Further, for example, the video data subjected to the conversion processing by the projective conversion processing device may be output to various output devices such as output to a printer or writing to a hard disk. In such a case, similarly to the above-described embodiment, the post-correction video data processing is performed prior to the completion of the initialization of the cache block storage unit 122, so that the processing time of the projective transformation processing can be shortened. .

  (5) In the embodiment described above, the projector 100 modulates the light from the illumination optical system 190 using the transmissive liquid crystal panel unit 192, but is not limited to the transmissive liquid crystal panel unit 192. For example, using a digital micromirror device (DMD (registered trademark): Digital Micro-Mirror Device), a reflective liquid crystal panel (LCOS (registered trademark): Liquid Crystal on Silicon), etc., from the illumination optical system 190 The light may be modulated. Further, it may be a CRT projector that projects an image on a small CRT (cathode ray tube) onto a projection surface, or may be configured to generate image light using an organic EL.

  (6) In the above embodiment, a part of the function realized by software may be realized by hardware, or a part of the function realized by hardware may be realized by software.

  (7) In the above embodiment, the cache block storage unit 122 has the same width as the frame width of one frame, and the cache block is stored in the block area having the same column number as the column number of the cache block. However, the width of the cache block storage unit 122 may not be the same as the frame width of one frame. The cache block may not be stored in the block area having the same column number as the cache block. Even if it does in this way, hit determination can be performed using tag information because tag information is provided with the information of both x coordinate and y coordinate.

DESCRIPTION OF SYMBOLS 100 ... Projector 102 ... High speed bus 104 ... Low speed bus 110 ... Video input part 112 ... IP conversion part 114 ... Resolution conversion part 116 ... Video composition part 120 ... Trapezoid distortion correction part 121 ... Cache block control part 122 ... Cache block memory | storage part 123 ... tag information storage unit for cache block 124 ... interpolation block reading unit 125 ... pixel interpolation unit 126 ... FIFO unit 127 ... register unit 128 ... control unit 129 ... coordinate conversion unit 130 ... filter coefficient calculation unit 131 ... hit determination unit 140 ... liquid crystal Panel drive unit 150 ... Frame buffer 160 ... High-speed bus control unit 162 ... Low-speed bus control unit 170 ... Processor unit 180 ... Imaging unit 182 ... Sensor unit 190 ... Illumination optical system 192 ... Liquid crystal panel unit 194 ... Projection optical system SC ... Screen IG ... corrected image IG1 ... corrected image

Claims (4)

A projector that projects and displays an image on a projection surface,
An image light output unit for generating and outputting image light representing the image;
A frame video storage unit for storing input video data input to the projector as a frame video composed of a plurality of lines;
A storage unit having a smaller capacity and a higher speed than the frame image storage unit, and N × M (N in the line direction and the pixel direction intersecting with the input image data of the frame image stored in the frame image storage unit, respectively. , M ≧ 2) a block video storage unit for storing a part of the input video data of the frame video in units of block video data composed of pixels;
A correction processing unit that performs a correction process for correcting distortion of an image projected on the projection surface, and is based on the block video data stored in the block video storage unit. A correction processing unit that generates corrected video data and outputs the video data representing the image projected on the projection surface to the video light output unit;
With
The correction processing unit corrects the correction prior to storing all of the initialization block video data, which is block video data stored in the block video storage unit at the start of the correction processing on a frame video for one frame. Projector to start processing. The projector according to claim 1.
The initialization block video data is determined based on a correction parameter used for the correction process. The projector according to claim 2,
The correction parameter is a projector for converting the coordinates of the corrected video data into the coordinates of the video data before correction. The projector according to claim 2,
When the video after the correction processing is a video that clips and displays the video before the correction processing,
The projector, wherein the correction parameter is a minimum coordinate in the pixel direction of an area to be displayed in an image before the correction process.

Images