JP5340236B2 - Demodulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correct a delay time difference between signals and to suppress deterioration of a reception characteristic even if input timing of the signal differs due to a difference in a radiowave transmissions path length and a cable length between reception antenna branches. <P>SOLUTION: A delay correction portion 15-1 detects a reception antenna branch (reference branch) whose symbol start timing is delayed the most, stores data in a buffer to delay it and adjusts symbol timing. A delay correction portion 15-2 detects a reception antenna branch (reference branch) whose frame start timing is delayed the most, stores data in the buffer to delay it and adjusts frame timing. A delay correction portion 15-3 stores respective data in the buffer and reads them after they are delayed by a prescribed delay amount. When a symbol number is determined to be duplicate, a read pointer is changed by considering that data of a new reception antenna branch is delayed the most. <P>COPYRIGHT: (C)2012,JPO&amp;INPIT

Description

  The present invention performs macro diversity reception for digital signal processing and synthesis of received signals by using a plurality of receiving antennas distributed at distant locations, and performs diversity reception, adaptive array antenna reception, MIMO (Multi -Input Multi-Output) relates to a demodulator that realizes transmission and the like.

  Conventionally, a mobile relay system for carrying out road race relay such as marathon in an urban area is known. In this mobile relay system, a high-definition video signal captured by a camera is transmitted along a course through an OFDM (Orthogonal Frequency Division Multiplexing) type radio transmission device (FPU: Field Pick-up Unit) mounted on a mobile relay vehicle. It is transmitted to a receiving point (receiving antenna) installed on the rooftop of the building. Signals received at each receiving point are converted from electrical signals to optical signals, collected via optical fibers to a receiving master station called a switching center, and demodulated by independent demodulation devices provided for each receiving antenna branch. Is done. The TS (Transport Stream) signal of each receiving antenna branch output from the demodulator is appropriately switched by an automatic switcher according to the quality. Thereby, the broadcast relay without interruption is realizable.

  However, since this mobile relay stem needs to have a demodulator that outputs a TS signal for each reception antenna branch, the scale of the system increases. In addition, since the reception system of this mobile relay system is a selective diversity reception system that selects any one TS signal from among a plurality of reception antenna branch TS signals, signals are received simultaneously at a plurality of reception points. Even if the signal is received, signals other than the selected reception point are discarded. Therefore, in order to achieve both simplification of the mobile relay system and line reliability, the reception system of the mobile relay system may be a combined diversity reception system or an adaptive array reception system that appropriately combines the signals at each reception point. desirable.

  On the other hand, studies on applying a MIMO transmission technology capable of dramatically improving transmission capacity to an FPU are underway (see Non-Patent Document 1). In the MIMO transmission technique, it is assumed that a plurality of array antenna elements are used for both the transmission device and the reception device. For this reason, when the MIMO transmission technique is applied to road race relay, signals at a plurality of reception points need to be simultaneously input to the demodulation device.

  Regardless of the combination diversity reception method, adaptive array reception method, or MIMO transmission method used as the mobile relay system reception method, the demodulator receives signals from a plurality of reception antenna branches input from each reception point. Are combined by digital signal processing, there is a signal delay time difference between the receiving antenna branches due to the difference in the radio wave propagation path length and the optical fiber path length. If this delay time difference becomes large, the demodulator synthesizes signals with different symbol timings, so that it is assumed that not only the reception characteristics deteriorate, but also that the video is completely destroyed. Therefore, it is essential for the demodulating apparatus to correct the delay time difference between the receiving antenna branches accurately before combining the signals of the receiving antenna branches.

  As a first method for correcting the signal delay time difference between the receiving antenna branches, the path length of the optical fiber provided between each receiving point and the demodulator is measured, and a delay corresponding to the path length difference is measured. It is assumed that a fixed buffer for performing the above is provided and the signal is stored in the buffer and delayed. Thereby, the symbol timing of the signal between the receiving antenna branches can be made uniform.

  Further, as a second method, it is assumed that a signal called a guard interval (hereinafter referred to as GI (Guard Interval)) is added to a symbol and a delay time difference of the signal is absorbed within this GI period. This GI is a signal for suppressing the influence of inter-symbol interference due to multipath in an OFDM signal often used in the mobile communication field. The reception characteristics when this technique is used have been reported (see Non-Patent Document 2).

Mitsuyama, Kanbara, Serizawa, Nakagawa, Ikeda, "LDPC coding MIMO-OFDM transmission experiment in the road race course", Technical Report of the Institute of Image Information and Television Engineers, vol. 34, no. 5, pp.13-16, BCT2010-27, 2010 S. Okamura, M. Okada, and S. Komaki, “Ubiquitous antenna system for joint detection of COFDM signals,” IEICE Trans. Fundamentals, vol. E85-A, no. 7, pp.1685-1692, Jul. 2002

  However, in the first method described above (a method in which a fixed buffer that delays for a time corresponding to the difference in optical fiber path length is used to align the symbol timing of signals between receiving antenna branches), the relay course is different. In some cases, the path length of the optical fiber to be used is also different, so there is a problem that the processing becomes complicated and cannot be flexibly handled. In addition, there is also a problem that it is impossible to cope with a case where the difference in radio wave propagation path varies from moment to moment as the mobile relay vehicle moves.

  In addition, the above-described second method (method of absorbing a delay time difference between signals in the reception antenna branches within the GI period) has a problem that it cannot cope with a case where the delay time difference exceeds the GI period. A method of shifting the FFT (Fast Fourier Transform) window position forward in time by the delay time difference is also assumed, but since the GI period effective for multipath is shortened, the multipath resistance is improved. The problem of deterioration arises.

  FIG. 29 is a diagram for explaining a delay time difference correction method for shifting the FFT window forward in the prior art. (1) shows a case where there is no delay time difference between the reception antenna branches, and (2) shows the reception antenna branch. Shows the case where there is a delay time difference between the two. Referring to FIG. 29 (1), when there is no delay time difference between signals between reception antenna branch # 1 and reception antenna branch # 2, the FFT window position that does not cause intersymbol interference is within the range of the GI period. Since it is set, it can be seen that the effective GI period is unchanged. On the other hand, referring to FIG. 29 (2), when there is a delay time difference in the signals between reception antenna branch # 1 and reception antenna branch # 2, the FFT window position that does not cause intersymbol interference is only the delay time difference. It can be seen that the effective GI period is shortened because it is set to be shifted forward in time. In this case, the multipath resistance is deteriorated.

  As described above, in the mobile relay system, when combining diversity reception, adaptive array reception, or MIMO transmission by macro diversity is realized, the radio wave propagation path length and the optical fiber path length may be different between the reception antenna branches. Since the timing is not aligned, there is a problem in that appropriate combining processing cannot be performed and reception characteristics are greatly deteriorated or reception itself cannot be performed.

  In order to solve this problem, as a method of correcting the delay time difference between the receiving antenna branches, the signal of the most delayed receiving antenna branch is used as a time axis reference, and the signals of other receiving antenna branches are stored in the buffer. Thus, it is desirable to delay the signal so that the symbol timing of each signal is matched. Even if the signals of each receiving antenna branch are randomly input to the demodulator in time, the delay due to correction processing is minimized as much as possible, the buffer capacity is kept to the minimum necessary, and the continuity of the time axis is maintained. It is desirable to be able to do it.

  Therefore, the present invention has been made to solve the above-described problems, and the object of the present invention is to perform a reception between the receiving antenna branches when performing macro diversity reception from a plurality of receiving antennas arranged in a distributed manner via a cable such as an optical fiber. It is an object of the present invention to provide a demodulator capable of correcting a delay time difference between signals and suppressing deterioration of reception characteristics even when signal input timing differs due to differences in radio wave propagation path length and cable length.

In order to achieve the above object, a demodulator according to the present invention performs macro diversity reception via a plurality of reception antennas and cables arranged in a distributed manner, and inputs and demodulates a reception signal of each reception antenna branch. In the demodulator for synthesizing the received signals, a digital orthogonal demodulator that digitally orthogonally demodulates the received signal for each reception antenna branch, a symbol start timing is detected from the digital orthogonal demodulated signal, and the signal of the symbol start timing is A symbol synchronization unit that generates each reception antenna branch, an FFT (Fast Fourier Transform) that performs an effective symbol included in the digital quadrature demodulated signal, and an FFT unit that generates a frequency domain signal for each reception antenna branch; Receiving and receiving the FFTed signal and the signal of the symbol start timing Input for each tener branch, based on the signal of the symbol start timing, writes the FFT signal to the first buffer, reads out the signal having the same symbol timing in each receiving antenna branch from the first buffer, and outputs it A signal having the same symbol timing is input to each reception antenna branch, the input signal is written to a second buffer, and the signal having the same frame timing is received in each reception antenna branch. A second delay correction unit that reads out and outputs from the second buffer, and inputs the signal having the same frame timing for each reception antenna branch, writes the input signal into the third buffer, and outputs the third buffer. The signal of each receiving antenna branch delayed within the Comprising a third delay correcting section that reads output from the file, and the second delay correcting section inputs the coincidence signal of said symbol timing for each receiving antenna branch, based on the signal of the receiving antenna branch A frame start timing detection unit that detects a frame start timing and generates a signal of the frame start timing for each receiving antenna branch; and a signal of a symbol start timing in a signal having the same symbol timing as a signal of a reference branch symbol start timing Second write timing for outputting a write control signal for each receiving antenna branch for writing a symbol of the signal having the same symbol timing to the second buffer for each signal of the reference branch symbol start timing Control part and front A reference branch symbol start timing signal is input, a read control signal for reading a symbol from the second buffer is output for each reception antenna branch for each reference branch symbol start timing signal, and the reference branch symbol start is started. A timing signal is output, and further, the frame start timing signal is input to each reception antenna branch, the most preceding frame start timing is detected in all the reception antenna branches, and the frame start timing is set as the start 1 A frame start timing pulse observation window having a frame length is set, and the reception antenna branch with the most delayed frame start timing is detected as a reference branch within the frame start timing pulse observation window. At the frame start timing of the reference branch, A second read timing control unit for outputting the read control signal for reading the symbol written in the second buffer from the beginning of the frame for each reception antenna branch, the signal having the same symbol timing and the write A control signal is input for each reception antenna branch, and based on the write control signal, a symbol of the signal having the same symbol timing is written to the second buffer, and the read control signal is input for each reception antenna branch, And a second memory that reads the symbols written in the second buffer for each reception antenna branch based on the read control signal, and the third delay correction unit has a reference branch symbol start timing The signal is input and the reference branch symbol starts timing A third write timing control unit that outputs, for each receiving antenna branch, a write control signal for writing the symbol of the signal having the same frame timing to the third buffer for each of the signals, and the reference branch symbol start timing And a read control signal for reading out a symbol at a position delayed by a predetermined amount from the position of the symbol written in the third buffer for each signal at the reference branch symbol start timing. In addition, a new reference branch is detected by the second delay correction unit, the frame start timing of the reference branch is delayed from the frame start timing of the previous reference branch, and If a symbol is duplicated, the duplicate A third read timing control unit that outputs the read control signal for preventing the duplicated symbols from being read from the third buffer according to the number of bits; A write control signal is input for each reception antenna branch, and based on the write control signal, a symbol of the signal having the same frame timing is written to the third buffer, and the read control signal is input for each reception antenna branch. And a third memory for reading the symbols written in the third buffer for each reception antenna branch based on the read control signal .

In the demodulator according to the present invention, the second delay correction unit includes a new second read timing control unit instead of the second read timing control unit, and the new second read timing control. In addition to the second read timing control unit, the unit further holds the detected reference branch and the frame start timing of the reference branch, and inputs a signal of the frame start timing for each reception antenna branch, A frame start timing pulse observation window having a length of 1 frame starting from the frame start timing is set and detected in the frame start timing pulse observation window. At the frame start timing of the reference branch, the second buffer Outputs the read control signal for reading was incorporated comes symbols from the first frame in each receiving antenna branch, characterized in that.

Also, in the demodulator according to the present invention, the first delay correction unit inputs the signal of the symbol start timing for each reception antenna branch, and outputs the symbol of the FFT signal for each signal of the symbol start timing. A first write timing control unit that outputs a write control signal for writing the sample to the first buffer for each reception antenna branch, and inputs a signal of the symbol start timing for each reception antenna branch. For each symbol start timing signal, a read control signal for reading a sample from the second buffer is output for each reception antenna branch, and further, a symbol start timing pulse observation of one symbol length is observed at an arbitrary time position. Set the window and observe the symbol start timing pulse And detecting the received antenna branch with the most delayed symbol start timing as a reference branch, and reading the sample written in the first buffer from the beginning of the symbol at the symbol start timing of the reference branch. A first read timing control unit that outputs a read control signal for each reception antenna branch and outputs a signal of a symbol start timing of the reference branch as a signal of a reference branch symbol start timing; the FFT signal and the write control A signal is input for each reception antenna branch, and based on the write control signal, the FFT-processed signal sample is written to the first buffer, and the read control signal is input for each receive antenna branch, and the read control is performed. Based on the signal A first memory for reading samples written in the first buffer for each receive antenna branch, characterized by comprising a.

In the demodulator according to the present invention, the first delay correction unit includes a new first read timing control unit instead of the first read timing control unit, and the new first read timing control. Unit outputs, for each receiving antenna branch, the read control signal for reading the sample written in the first buffer from the beginning of the symbol at the timing of the reference pulse generated for each OFDM symbol period length, The reference branch symbol start timing signal is output as a reference branch symbol start timing signal .

  The demodulator according to the present invention includes a digital quadrature demodulator, a symbol synchronizer, the first delay corrector provided after the symbol synchronizer, the FFT unit, and the FFT unit. The second delay correction unit and the third delay correction unit provided in a subsequent stage, wherein the first delay correction unit receives a time-domain signal and a symbol start timing signal for each reception antenna branch. The signal in the time domain is written into the first buffer based on the signal at the symbol start timing, and the signal having the same symbol timing is read out from the first buffer at each reception antenna branch and output. It is characterized by that.

  According to the present invention, even when the signal input timing differs due to the difference in the radio wave propagation path length and the cable length between the receiving antenna branches, the delay time difference between the signals can be corrected. Therefore, since the timing of the signals can be matched between the receiving antenna branches, the signals can be appropriately combined, and the deterioration of the receiving characteristics can be suppressed.

It is a figure explaining the outline | summary at the time of using the macro diversity reception system containing the demodulation apparatus by embodiment of this invention for road race relay. 1 is a block diagram illustrating a configuration of a demodulation device according to Embodiment 1. FIG. It is a block diagram which shows the structure of a 1st delay correction | amendment part. It is a timing chart which shows processing of the 1st delay amendment part. It is a flowchart which shows the process of a 1st delay correction | amendment part. It is a flowchart which shows the process of the write-timing control part in a 1st delay correction | amendment part. It is a flowchart which shows the process of the read-out timing control part in a 1st delay correction | amendment part. It is a figure explaining the pointer management by the read timing control part in a 1st delay correction | amendment part. It is a flowchart which shows the process of the memory part in a 1st delay correction | amendment part. It is a timing chart which shows the process of the modification in a 1st delay correction | amendment part. It is a flowchart which shows the process of the modification in a 1st delay correction | amendment part. It is a flowchart which shows the process of the read-out timing control part of the modification in a 1st delay correction | amendment part. It is a block diagram which shows the structure of a 2nd delay correction | amendment part. It is a timing chart which shows the processing of the 2nd delay amendment part. It is a flowchart which shows the process of a 2nd delay correction | amendment part. It is a flowchart which shows the process of the read-out timing control part in a 2nd delay correction | amendment part. It is a figure explaining the pointer management by the read timing control part in a 2nd delay correction | amendment part. It is a figure explaining the RD pointer in a 2nd delay correction | amendment part, (1) shows the case where the signal of a reference branch is not interrupted, (2) shows the case where the signal of a reference branch is interrupted. It is a timing chart which shows the process of the modification in a 2nd delay correction | amendment part. It is a flowchart which shows the process of the modification in a 2nd delay correction | amendment part. It is a flowchart which shows the process of the read-out timing control part of the modification in a 2nd delay correction | amendment part. 12 is a timing chart illustrating a state in which the most delayed receiving antenna branch is changed and symbols are output in duplicate in a modification of the second delay correction unit. In the modification of a 2nd delay correction | amendment part, it is a figure explaining the RD pointer of the state in which a symbol overlaps and is output when the most late receiving antenna branch is changed. It is a block diagram which shows the structure of a 3rd delay correction | amendment part. It is a flowchart which shows the process of a 3rd delay correction | amendment part. It is a flowchart which shows the process of the read-out timing control part in a 3rd delay correction | amendment part. FIG. 6 is a diagram for explaining pointer management by a read timing control unit in a third delay correction unit, where (1) shows a case where the reference branch does not change, and (2) is updated to a new reference branch delayed by one symbol period. Indicates the case. It is a block diagram which shows the structure of the demodulation apparatus in Example 2. In the prior art, it is a figure explaining the delay time difference correction method which shifts an FFT window ahead, (1) shows the case where there is no delay time difference between receiving antenna branches, (2) shows the delay time difference between receiving antenna branches. Indicates a case.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.
[Macro diversity reception system]
First, an overview of a macro diversity reception system including a demodulation device according to an embodiment of the present invention will be described. FIG. 1 is a diagram for explaining the outline when the macro diversity reception system is used for road race relay.

  The mobile relay vehicle 1 is loaded with a modulation device (not shown), and the modulation device OFDM modulates the photographed road race high-definition video signal and transmits the modulation signal from the transmission point (antenna) 2. In each building in the vicinity of the mobile relay vehicle 1, a reception point (antenna) 3 is installed on the roof. The plurality of reception points 3 receive the modulated signal transmitted from the transmission point 2 of the mobile relay vehicle 1. The modulated signal received by the receiving point 3 is converted from an electrical signal to an optical signal by an E / O (electric / optical) converter (Electrical to Optical Converter) 7, and is converted into an O / E (optical signal) via the optical fiber 4. It is transmitted to an optical / electrical converter 8. In the O / E converter 8, the optical signal is converted into an electric signal. A demodulating device 6 is installed in the switching center 5, and the demodulating device 6 inputs modulation signals from a plurality of reception points 3 via the E / O converter 7, the optical fiber 4 and the O / E converter 8. Then, demodulation processing and synthesis processing are performed on the plurality of modulation signals.

  The reception point 3 that can receive the modulated signal transmitted from the transmission point 2 of the mobile relay vehicle 1 becomes different as the mobile relay vehicle 1 moves. As the mobile relay vehicle 1 moves, there is a reception point 3 that terminates reception of the modulation signal (the modulation signal is interrupted), and there is also a reception point 3 that newly starts reception of the modulation signal. When each receiving point 3 is installed at a location distant from each other, the radio wave propagation path length from the transmitting antenna at the transmitting point 2 to the receiving antenna at the receiving point 3 in the mobile relay vehicle 1 depends on the position of the mobile relay vehicle 1. to differ greatly. In addition, when an existing dark fiber or the like is used as an optical line by the optical fiber 4, generally, the path length of the optical fiber 4 from each reception point 3 to the switching center 5 is different. For example, there is a difference of, for example, about 30 km between the optical line with the shortest path length of the optical fiber 4 and the longest optical line.

  The demodulator 6 according to the embodiment of the present invention converts a modulated signal transmitted from the transmission point 2 into a reception point 3 and an E / O converter due to the difference in the radio wave propagation path length between the reception antenna branches and the path length of the optical fiber 4. 7. Even when the input timing through the optical fiber 4 and the O / E converter 8 differs between the receiving antenna branches, the modulation signal is interrupted and cannot be input, or the modulation signal input is newly started. Even when there is a receiving antenna branch to be processed, the delay time difference of the signal between the receiving antenna branches is appropriately corrected, and the timing (symbol start timing and frame start timing) of each signal is matched. .

  In the following embodiment, the description will be made based on an OFDM signal or the like that conforms to the ARIB STD-B33 standard “portable OFDM digital wireless transmission system for transmitting television broadcast program material” handled by the wireless device for transmitting broadcast material. If it is an OFDM signal, it is not limited to the said standard. Moreover, as long as the signal format is such that a part of the signal is cyclically repeated as in the GI, the present invention is not limited to the OFDM signal and can be applied to other signal formats.

  Hereinafter, the demodulator 6 shown in FIG. 1 will be described in detail. The demodulating device 6 according to the first embodiment described below includes three delay correction units, and corrects a delay time difference of signals between reception antenna branches in the frequency domain after the FFT calculation. Further, the demodulator 6 of the second embodiment described below includes three delay correction units as in the first embodiment, and the first delay correction unit performs processing in the time domain before the FFT calculation, and the second The third delay correction unit performs processing in the frequency domain after the FFT operation, and corrects the delay time difference of the signals between the reception antenna branches.

  The first delay correction unit detects a reception antenna branch (reference branch) with the most delayed symbol start timing among the signals of the plurality of reception antenna branches within a predetermined symbol start timing pulse observation window, and receives other signals. Is stored in the first buffer and delayed to match the signal of the reference branch. Thereby, the symbol timing of the signal between the receiving antenna branches can be matched.

  A modification of the first delay correction unit stores the signals of all the receiving antenna branches in the first buffer and delays them, and the symbol coincides with the symbol timing of each receiving antenna branch, and the symbols of the specific branches whose phases are independent. The signals of all receiving antenna branches are read out at a timing independent of the timing. Thereby, the symbol timing of the signal between the receiving antenna branches can be matched.

  The second delay correction unit performs a process of matching the frame timing on the signal of each reception antenna branch whose symbol timing is matched by the first delay correction unit. That is, the second delay correction unit detects the receiving antenna branch (reference branch) with the most delayed frame start timing within the frame start timing pulse observation window having a length of one frame from the head of the most preceding signal frame, Other signals are stored in the second buffer and delayed to match the signal of the reference branch. Thereby, when there is a delay time difference of one symbol period or more in the signal between the receiving antenna branches, the frame timing of each signal can be matched.

  The third delay correction unit stores the signal of each reception antenna branch whose frame timing is matched by the second delay correction unit in the third buffer, and reads it after being delayed by a predetermined delay amount. When a signal delayed from the signal of the reference branch is input, the read pointer is changed and the signal is read from the third buffer. In this case, duplicate signals of the same symbol are stored in the third buffer. However, since the read pointer is changed, the same symbol is not read out continuously and the continuity of the time axis is ensured. be able to.

[Demodulator / Example 1]
First, the demodulator 6 according to the first embodiment will be described in detail. FIG. 2 is a block diagram illustrating a configuration of the demodulation device 6 according to the first embodiment. The demodulator 6-1 includes an A / D conversion unit (Analogue to Digital Converter) 10, a digital orthogonal demodulation unit 11, a symbol synchronization / AFC (Automatic Frequency Control) unit 12, a GI removal unit 13, an FFT (Fast Fourier Transform: (Fast Fourier Transform) unit 14, delay correction units 15-1 to 15-3, and complex weight calculation / multiplication / addition unit 16. OFDM demodulation processing is performed by the A / D conversion unit 10, the digital orthogonal demodulation unit 11, the symbol synchronization / AFC unit 12, the GI removal unit 13, and the FFT unit 14, and delay correction processing is performed by the delay correction units 15-1 to 15-3. Is done.

  The demodulating device 6-1 passes from each reception point 3 through the E / O converter 7, the optical fiber 4, and the O / E converter 8 to a radio frequency band (RF) or an intermediate frequency band lower than the radio frequency. When an (IF: Intermediate Frequency) signal is input, a converter (not shown) converts the input signal into a signal in a frequency band that allows digital signal processing. The A / D converter 10 receives a signal from a converter (not shown), quantizes the input analog signal, and converts it into a digital signal. The digital quadrature demodulator 11 receives a digital signal from the A / D converter 10 and performs digital quadrature demodulation.

  The symbol synchronization / AFC unit 12 receives the signal subjected to digital orthogonal demodulation from the digital orthogonal demodulation unit 11, performs symbol synchronization processing and AFC (Automatic Frequency Control) on the input signal, and performs symbol synchronization by GI correlation. Detect start timing. The signal of the symbol start timing of each reception antenna branch detected by the symbol synchronization / AFC unit 12 is output to the delay correction unit 15-1 via the GI removal unit 13 and the FFT unit 14. Here, the symbol start timing is detected only for the reception antenna branch that can properly receive the modulation signal at the reception point 3, and a signal of the symbol start timing in the reception antenna branch is output. Therefore, when the modulation signal is interrupted, the symbol start timing signal of the receiving antenna branch is not output, and when the modulation signal of the new receiving antenna branch is received, the signal of the symbol start timing of the receiving antenna branch is output. Will come to be.

  The GI removing unit 13 receives the AFC signal and the symbol start timing signal from the symbol synchronization / AFC unit 12, sets an FFT window, removes the GI, extracts an effective symbol, and outputs an effective symbol length signal. Generate. The FFT unit 14 receives an effective symbol length signal and a symbol start timing signal from the GI removal unit 13, performs FFT on the time domain signal, and converts the signal into a frequency domain signal. The update of the FFT window position is performed at the same timing in units of the predetermined plurality of symbols when the complex weight calculation / multiplication / addition unit 16 performs synthesis processing for each of the predetermined plurality of symbols. Thereby, the update timing of the FFT window position and the update timing of the complex weight calculation / multiplication / addition unit 16 can be matched, and the update of the FFT window position and the synthesis process are performed for each same target symbol.

  In the A / D conversion unit 10, the digital orthogonal demodulation unit 11, the symbol synchronization / AFC unit 12, the GI removal unit 13, and the FFT unit 14, the sampling frequency and the operation clock are common between the receiving antenna branches. Further, it is assumed that the local oscillator, symbol synchronization timing, and frequency correction processing in the frequency conversion are not common between the reception antenna branches but are independent for each reception antenna branch.

  By the OFDM demodulation processing of the A / D conversion unit 10, the digital orthogonal demodulation unit 11, the symbol synchronization / AFC unit 12, the GI removal unit 13, and the FFT unit 14, the frequency domain signal and the symbol start timing signal in each reception antenna branch are obtained. Is generated and output to the delay correction unit 15-1.

  The delay correction unit 15-1 receives the frequency domain signal (data) and the symbol start timing signal in each receiving antenna branch from the FFT unit 14, and the symbol start timing is the most within a predetermined symbol start timing pulse observation window. The delayed receiving antenna branch (reference branch) is detected, the data of the other receiving antenna branches are stored in the first buffer and delayed, and the symbol timing is adjusted to the data of the reference branch. The data of each receiving antenna branch with the matching symbol timing and the signal of the symbol start timing (reference branch symbol start timing) of the reference branch are output to the delay correction unit 15-2.

  The delay correction unit 15-2 receives the data of each reception antenna branch and the signal of the reference branch symbol start timing that match the symbol timing from the delay correction unit 15-1, and uses the frame start timing detected at an arbitrary timing as a reference. In addition, a period corresponding to a predetermined number of symbols before and after that (for example, ± 10 symbol period) is set as a frame start timing pulse observation window, and within the observation window, the receiving antenna branch with the latest frame start timing (reference) Branch) is detected, the other receive antenna branches are stored in the second buffer and delayed, and the frame timing is adjusted to the data of the reference branch. The data of each receiving antenna branch with the matching frame timing and the signal (including the symbol number) of the reference branch symbol start timing are output to the delay correction unit 15-3.

  The delay correction unit 15-3 receives, from the delay correction unit 15-2, the data of each receiving antenna branch and the reference branch symbol start timing signal (including the symbol number) that match the frame timing, Data is stored in the third buffer, read out and output after being delayed by a predetermined delay amount. When the symbol number included in the input signal of the reference branch symbol start timing is duplicated, it is determined that the signal is delayed from the signal of the reference branch, the read pointer is changed according to the number of duplicates, Data is read from buffer No. 3. As a result, the same symbol data is not read out of the third buffer, and symbols with consecutive symbol numbers are read out on the time axis. The delay correction unit 15-3 inputs the symbol movement amount instead of the symbol number from the delay correction unit 15-2, advances the read pointer by the number indicated by the symbol movement amount, and reads the data from the third buffer. It may be. In this case, the delay correction unit 15-2 monitors how many symbols the frame start timing of the reference branch has moved, and outputs the symbol movement amount to the delay correction unit 15-3.

  The complex weight calculation / multiplication / addition unit 16 ensures that the data in which the delay time difference is corrected between the receiving antenna branches, that is, the symbol and the frame timing match from the delay correction unit 15-3, and the continuity of the symbols on the time axis is ensured. The data of each receiving antenna branch is input, the complex weight calculation and multiplication processing are performed on each data to synthesize the data, and the combined data is output. For example, in the case of MIMO transmission, a signal transmitted from the modulation device is detected and output by a signal separation and detection algorithm such as ZF (Zero Forcing) method, MMSE (Minimum Mean Square Error).

  As described above, according to the demodulating device 6-1, the delay time difference of the signal between the receiving antenna branches is corrected, and a plurality of data in which the symbol and the frame timing match and the continuity of the symbols on the time axis is ensured. Since they are combined, it is possible to suppress degradation of reception characteristics.

[First delay correction]
Next, the first delay correction processing by the delay correction unit 15-1 shown in FIG. 2 will be described in detail. 3 is a block diagram showing a configuration of the delay correction unit 15-1, FIG. 4 is a timing chart showing processing of the delay correction unit 15-1, and FIG. 5 shows processing of the delay correction unit 15-1. It is a flowchart which shows. As described above, the delay correction unit 15-1 has a function of correcting the delay time difference within one OFDM symbol period and matching the symbol timing. Hereinafter, description will be made assuming that the number of reception antenna branches is three. The delay correction unit 15-1 includes write timing control units 21-1 to 21-3, memory units 22-1 to 22-3, and a read timing control unit 23.

  A non-signal branch detection / invalidation unit (not shown) of the delay correction unit 15-1 receives from the FFT unit 14 a frequency domain signal (data 1, 2,...) Of each reception antenna branch and a symbol start timing signal ( SYC1, 2,...) Are input, the branch to be invalidated is detected for each symbol, and the output to the delay correction unit 15-1 is invalidated. Specifically, the no-signal branch detection / invalidation unit applies a predetermined data carrier or an unmodulated carrier corresponding to a pilot signal and a guard band to the input data 1, 2,. The ratio is calculated, and when it is determined that the calculated value is equal to or less than a predetermined threshold, the signal is invalidated so as not to be output to the subsequent stage. Signals of branches other than those determined to be invalid are output to the delay correction unit 15-1. In addition, the no-signal branch detection / invalidation unit determines that it is a valid symbol start timing when the input SYC 1, 2,... Has periodicity and exceeds a preset threshold. Assuming that the signal has been correctly received in the system, the receiving antenna branch to be received may be determined, and the branch that does not satisfy the above condition may be determined to be invalid. Hereinafter, it is assumed that the systems 1 to 3 and SYC 1 to 3 are identified as reception antenna branches to be received, and the number thereof is 3.

  In addition, a null signal insertion unit (not shown) of the delay correction unit 15-1 performs null for a period corresponding to the GI period for each symbol with respect to the data of the receiving antenna branch specified by the non-signal branch detection / invalidation unit (not shown). Insert a signal. This null signal is a signal for maintaining the processing timing.

  The delay correction unit 15-1 receives the data 1 to 3 and the symbol start timing signal SYC1 converted into the frequency domain from the FFT unit 14 through a non-signal branch detection / invalidation unit and a null signal insertion unit (not shown). -3 are input (step S501). The write timing control unit 21-1 receives SYC1, generates a control signal WR1 (including the WR pointer 1 indicating the write position) for writing data 1 into the buffer of the memory unit 22-1 for each sample, The data is output to the unit 22-1 (step S502). The write timing control units 21-2 and 21-3 also perform the same processing as the write timing control unit 21-1, and input SYC2 and 3 to generate control signals WR2 and 3 (including WR pointers 2 and 3). Output to the memory units 22-2 and 22-3. Here, the write timing control units 21-1 to 21-3 increment the WR pointers 1 to 3 every time one sample of data is input (not shown). In the initial state, the WR pointer 1 and an RD pointer 1 described later indicate the same position, and the WR pointers 2 and 3 and an RD pointer 2 and 3 described later also indicate the same position. The same applies to delay correction units 15-1 ', 15-2, 15-2', and 15-3 described later.

  The memory unit 22-1 receives data 1 (data 1 with a null signal inserted) and also receives a control signal WR1 (including the WR pointer 1) from the write timing control unit 21-1, and the control signal WR1 At the input timing, data 1 is written in the position indicated by the WR pointer 1 in the buffer (step S503). The memory units 22-2 and 22-3 perform the same processing as the memory unit 22-1, and receive the input data 2 and 3 at the input timing of the control signals WR2 and 3 (including the WR pointers 2 and 3). Write to the position indicated by the WR pointers 2 and 3 in the buffer.

  The readout timing control unit 23 inputs SYC1 to SYC3, sets a symbol start timing pulse observation window (1 OFDM symbol length) at an arbitrary time position, and the most delayed signal among SYC1 to SYC3 within the observation window. The receiving antenna branch (reference branch) is detected (step S504). In this case, the read timing control unit 23 receives the number of valid reception antenna branches from a non-signal branch detection / invalidation unit (not shown), and compares the number of reception antenna branches with the number of input SYC 1 to 3. When the same number is determined, it is determined that the most delayed signal among SYC1 to SYC3 is input, and the reference branch is detected at that timing. Then, the read timing control unit 23 uses the symbol start timing of the reference branch as the reference branch symbol start timing, and at this timing, the data 1 to 3 from the buffers of the memory units 22-1 to 22-3 have the same timing for each sample. Control signals RD1 to RD1-3 (including RD pointers 1 to 3 indicating the read position) to be read at the same timing, and the control signals RD1 to RD3 to the memory units 22-1 to 22- are generated at the same timing. 3 (step S505).

  The memory unit 22-1 receives the control signal RD1 (including the RD pointer 1) from the read timing control unit 23, and reads data 1 from the position indicated by the RD pointer 1 in the buffer at the input timing of the control signal RD1. (Step S506). The memory units 22-2 and 22-3 perform the same processing as the memory unit 22-1, and at the input timing of the control signals RD2 and 3 (including the RD pointers 2 and 3), the RD pointers 2 and 2 in the buffer. Data 2 and 3 are sequentially read from the position indicated by 3 for each sample.

  The delay correction unit 15-1 uses the data 1 to 3 read from the memory units 22-1 to 22-3 and the SYC that is the reference branch symbol start timing signal generated by the read timing control unit 23 as a delay correction unit. It outputs to 15-2 (step S507).

  In FIG. 4, each Si (i = 0 to 407) represents a symbol and is composed of complex signal values of 1024 points equal to the FFT size arranged in time series in the order of carrier numbers. Further, xx is a signal in a period corresponding to the GI period, and is a signal in a section removed in the process of FFT calculation, and indicates a null signal inserted by a null signal insertion unit (not shown).

  The control signals WR1 to WR3 generated by the write timing control units 21-1 to 21-3 are turned on (high) at the timing of SYC1 to SYC3 and turned off (low) after the clock of the FFT size (1024 points). Signal. Moreover, since SYC2 is the most delayed among SYC1 to SYC2, SYC2 becomes SYC. Further, the control signals RD1 to RD3 generated by the read timing control unit 23 are signals that are turned on at the SYC timing and turned off after the clock of the FFT size (1024 points).

  As shown in FIG. 4, when there is a delay time difference due to the radio wave propagation path length and the path length of the optical fiber 4 between the reception antenna branches, the phases of SYC1 to SYC3 are different from each other at the reception antenna branch. Therefore, the delay correction unit 15-1 sets a symbol start timing pulse observation window (observation window corresponding to one OFDM symbol period) that can be set at an arbitrary position, and the phase of the symbol start timing is the most within the observation window. Data obtained by detecting delayed reception antenna branch # 2 (reference branch), delaying data 1 and 3 of other reception antenna branches # 1 and 3 and aligning symbol start timing with reception antenna branch # 2 which is the reference branch 1 to 3 (S0 of data 1, S407 of data 2 and S0 of data 3) are output. As a result, the delay difference within one OFDM symbol period is absorbed, and data 1 to 3 with matching symbol timing are output.

(Write timing controller)
Next, the write timing control units 21-1 to 21-3 shown in FIG. 3 will be described in detail. FIG. 6 is a flowchart showing the processing of the write timing control unit 21-1. In the write timing control unit 21-1, the signals output from the FFT unit 14 and the non-signal branch detection / invalidation unit (not shown) are input sample by sample to the buffers of the memory units 22-1 to 22-3 in the order of carrier numbers. In this case, the WR pointer 1 is incremented by one (step S601). That is, every time one sample of data 1 is input, it is incremented by one. The WR pointer 1 is a pointer indicating a position at which a sample of data 1 is written in the buffer of the memory unit 22-1.

  After step S601, the write timing control unit 21-1 generates a control signal WR1 (including WR pointer 1) indicating the timing for writing data 1 at the position of the WR pointer 1, and outputs the control signal WR1 to the memory unit 22-1. Step S602). The write timing control units 21-2 and 21-3 perform the same process as the write timing control unit 21-1.

  As described above, the write timing control units 21-1 to 21-3 have the signals output from the FFT unit 14 and the non-signal branch detection / invalidation unit (not shown) in the memory units 22-1 to 22-3 in the order of carrier numbers. When one sample is input to the buffer, every time one sample of data 1 is input, the WR pointers 1 to 3 are incremented, and control signals WR1 to WR3 are generated and output to the memory units 22-1 to 22-3. . Thereby, in the memory units 22-1 to 22-3, data 1 to 3 are sequentially written at the positions of the WR pointers 1 to 3 included in the control signals WR1 to WR3.

(Reading timing controller)
Next, the read timing control unit 23 shown in FIG. 3 will be described in detail. FIG. 7 is a flowchart showing processing of the read timing control unit 23, and FIG. 8 is a diagram for explaining pointer management by the read timing control unit 23. The read timing control unit 23 sets the symbol start timing pulse observation window having a length of 1 OFDM symbol period to an arbitrary time position (step S701), and determines whether any of the signals SYC1 to SYC3 is input (step S701). S702).

  When the read timing control unit 23 determines in step S702 that any one of the signals SYC1 to SYC3 is input (step S702: Y), the input signal is the most delayed symbol start timing among SYC1 to SYC3. It is determined whether the signal is a signal (step S703). On the other hand, if it is determined in step S702 that any of the signals SYC1 to SYC3 is not input (step S702: N), the process waits until it is input.

  If the read timing control unit 23 determines in step S703 that the input signal is the most delayed symbol start timing signal among SYC1 to SYC1-3 (step S703: Y), the process proceeds to step S704. On the other hand, if it is determined in step S703 that the input signal is not the most delayed symbol start timing signal among SYC1 to SYC3 (step S703: N), the process proceeds to step S702. Specifically, in step S703, the read timing control unit 23 inputs the number of reception antenna branches (3 in this example) from a non-signal branch detection / invalidation unit (not shown), and displays the symbol start timing pulse observation window. The number of SYC1 to SYC3 input from the start time is counted, and when the count number is smaller than 3, it is determined that the input signal is not the most delayed symbol start timing signal among SYC1 to SYC3. Is 3, it is determined that the input signal is the most delayed symbol start timing signal among SYC1 to SYC3. As a result, the most delayed signal among SYC1 to SYC3 can be determined in the middle of the symbol start timing pulse observation window, and the processing from step S704 to step S707 shown below can be performed at that timing. .

  The read timing control unit 23 proceeds from step S703 to detect the reception antenna branch at the most delayed symbol start timing within the symbol start timing pulse observation window as the reference branch (step S704). When the read timing control unit 23 outputs samples one by one from the buffers of the memory units 22-1 to 22-3 in the order of carrier numbers, the read timing control unit 23 reads the samples in order at the symbol start timing of the reference branch. The RD pointers 1 to 3 are sequentially set by incrementing 1 to 3 (step S705). Then, the read timing control unit 23 generates control signals RD1 to RD3 (including RD pointers 1 to 3) for reading samples of data 1 to 3 from the positions of the RD pointers 1 to 3, and the memory unit 22-1 To 22-3 (step S706). As shown in FIG. 8, the difference between the WR pointers 1 to 3 and the RD pointers 1 to 3 reflects the difference in the input timings of SYC1 to SYC3 shown in FIG. That is, since SYC2 is the most delayed signal, and data 1 to 3 are read at the timing of SYC2, in the memory unit 22-1, the difference between the WR pointer 1 and the RD pointer 1 is the difference between SYC1 and SYC2. In the memory unit 22-3, the difference between the WR pointer 3 and the RD pointer 3 corresponds to the timing difference between SYC3 and SYC2. Also, the read timing control unit 23 proceeds from step S704, and outputs the symbol start timing signal of the reference branch to the delay correction unit 15-2 as SYC (step S707).

  As described above, the read timing control unit 23 uses the reception antenna branch of the most delayed signal among SYC1 to SYC3 as the reference branch, and at the symbol start timing of the most delayed signal among SYC1 to SYC3, RD pointers 1 to 3 for reading samples from the memory are sequentially set, control signals RD1 to RD3 for reading data 1 to 3 from the buffer are generated at the same timing, and output to the memory units 22-1 to 22-3. . Thereby, within the symbol start timing pulse observation window, the data 1 to 3 are read from the buffers of the memory units 22-1 to 22-3 at the same timing, and the symbol start timing of the most delayed signal among SYC1 to SYC3. Every time, data 1 to 3 are sequentially read from the buffers of the memory units 22-1 to 22-3.

(Memory part)
Next, the memory units 22-1 to 22-3 illustrated in FIG. 3 will be described in detail. FIG. 9 is a flowchart showing the processing of the memory unit 22-1. The memory unit 22-1 determines whether or not the control signal WR1 (including the WR pointer 1) is input from the write timing control unit 21-1 (step S901), and determines that the control signal WR1 is input (step S901). Step S901: Y), the inputted data 1 is written in the position of the WR pointer 1 in the buffer (step S902). On the other hand, if it is determined that the control signal WR1 is not input (step S901: N), the process proceeds to step S903.

  The memory unit 22-1 moves from step S901 or step S902 to determine whether or not the control signal RD1 (including the RD pointer 1) is input from the read timing control unit 23 (step S903), and the control signal RD1. Is determined to be input (step S903: Y), data 1 is read from the position of the RD pointer 1 in the buffer (step S904). On the other hand, if it is determined that the control signal RD1 has not been input (step S903: N), the process ends, and the process proceeds to step S901. The memory units 22-2 and 22-3 perform the same processing as the memory unit 22-1.

  In this manner, each time the control signals WR1 to 3 are input, the memory units 22-1 to 22-3 write the data 1 to 3 at the positions of the WR pointers 1 to 3 in the buffer, and the control signals RD1 to RD3 are written. Each time data is input, data 1 to 3 are read from the positions of the RD pointers 1 to 3 in the buffer at the same timing.

  Since the first delay correction unit 15-1 only corrects the shift within one OFDM symbol period between the reception antenna branches, the reception unit branches # 1 to ## in the memory units 22-1 to 22-3. The size of the buffer required in 3 only needs to have a capacity corresponding to one OFDM symbol period. In FIG. 4, when processing is performed with a complex signal value of IQ of 12 bits for each subcarrier, a buffer for delaying a signal for a maximum of 1024 subcarriers of one OFDM symbol is required, so 2 × 12 × 1 kbit = 24 kbit ( A buffer capacity of 1 kbit = 1024 bits) is required for each reception antenna branch.

  As described above, according to the memory units 22-1 to 22-3, the data can be delayed by the delay buffer corresponding to one OFDM symbol period at the maximum, and the symbol timing of all the data can be matched. That is, the delay time within one OFDM symbol period is corrected with the minimum necessary buffer capacity, and the symbol timing can be matched.

  As described above, according to the delay correction unit 15-1 shown in FIGS. 2 and 3, the data 1 to 3 are buffered every time data is output from the FFT unit 14 and the no-signal branch detection / invalidation unit. In the symbol start timing pulse observation window, the most delayed signal receiving antenna branch among SYC1 to SYC3 is detected as a reference branch, and data 1 to 3 are read simultaneously at the symbol start timing of the reference branch. I made it. As a result, the data of the receiving antenna branches other than the reference branch can be stored and delayed. If there is a delay time difference between the data 1 to 3 between the receiving antenna branches, the symbol timing of each data 1 to 3 is set to the reference timing. It can be adjusted to the symbol timing of the branch.

  This is because the delay correction unit 15-1 inputs data and symbol start timings of a plurality of reception antenna branches, and then the signal is interrupted, or a signal of a new reception antenna branch is input. Even if there is a change in the number or system of data, data is written to the buffer at the symbol start timing and read from the buffer at the most delayed symbol start timing within the symbol start timing pulse observation window. It is possible to match all input data with a change in the number or system of antenna branches to the symbol timing of the reference branch in the symbol start timing pulse observation window. Since the delay correction unit 15-1 cannot actually detect the most delayed reception antenna branch, the delay correction unit 15-1 uses the most delayed signal within the symbol start timing pulse observation window determined at random timing. Performs only the matching process. However, if the symbol timing between the receiving antenna branches is matched in advance by the delay correcting unit 15-1, if the signal of the reference branch is interrupted as will be described later, a new reception delayed from the signal of the reference branch will be performed. There is an advantage that when the reference symbol timing is changed, such as when an antenna branch signal is input, the deviation can be easily adjusted in symbol units by delay correction units 15-2 and 15-3 described later. Further, since the signals of all branches can be processed at the same symbol timing, there is an advantage that it is easy to mount a circuit for maintaining signal continuity.

(Problem of delay correction unit 15-1)
However, in the delay correction unit 15-1, when a signal of a new branch other than the valid branch is input and the symbol timing of the signal is behind the timing of the reference branch, the newly input branch is used as the reference. As a result, the delay amount of the already input branch increases. When the branch signal is repeatedly input or not input, the buffer for one symbol is almost full in a short time.

  Therefore, the modification of the delay correction unit 15-1 performs the following process instead of the first delay correction process described above.

[Modification of First Delay Correction]
Next, a modification of the first delay correction process by the delay correction unit 15-1 shown in FIGS. 2 and 3 will be described in detail. In this modified example, as described above, the signals of all the receiving antenna branches are stored in the first buffer and delayed, the period matches the symbol timing of each receiving antenna branch, and the phase becomes the symbol timing of an independent specific branch. The signals of all receiving antenna branches are read at a timing that does not depend. Thereby, the symbol timing of the signal between the receiving antenna branches can be matched.

  The delay correction unit 15-1 'includes the same components as the delay correction unit 15-1 shown in FIG. Comparing the delay correction unit 15-1 and the delay correction unit 15-1 ′ described above, both are the same in that they have a function of correcting the delay time difference in the OFDM symbol period and matching the symbol timing. The delay correction unit 15-1 reads out from the buffer at the timing of the most delayed signal among SYC1 to SYC3, whereas the delay correction unit 15-1 ′ has a predetermined relationship that is not related to SYC1 to SYC3. It is different in that reading from the buffer is performed at the timing. In FIG. 3, the delay correction unit 15-1 'includes a read timing control unit 23 (hereinafter referred to as a read timing control unit 23') that performs processing different from that of the delay correction unit 15-1. The write timing control units 21-1 to 21-3, the memory units 22-1 to 22-3, the non-signal branch detection / invalidation unit, and the null signal insertion unit (not shown) perform the same processing as described above. Hereinafter, description will be made assuming that the number of reception antenna branches is three.

  In the flowchart of FIG. 11, the processes of step S1101 to step S1103, step S1105, and step S1106 are the same as steps S501 to S503, step S506, and step S507 of the flowchart showing the process of the delay correction unit 15-1 illustrated in FIG. This is the same as each process. The read timing control unit 23 ′ of the delay correction unit 15-1 ′ proceeds from step S1103 to generate SYC at a predetermined timing, and from the buffers of the memory units 22-1 to 22-3 based on SYC. Control signals RD1 to RD3 (including RD pointers 1 to 3) serving as a common read timing for reading the symbols of data 1 to 3 at the same timing are generated, and the control signals RD1 to RD3 are stored in the memory unit 22 at the same timing. Output to -1 to 22-3, respectively (step S1104). Details of the predetermined timing for generating SYC will be described later.

  In FIG. 10, each Si (i = 0 to 407) indicates a symbol as in FIG. 4, and xx is a signal in a period corresponding to the GI period, and is a signal in a section that is removed in the FFT calculation process. There is a null signal inserted by a null signal insertion unit (not shown).

  The control signals WR1 to WR3 generated by the write timing control units 21-1 to 21-3 are turned on (high) at the timing of SYC1 to SYC3 and turned off (low) after the clock of the FFT size (1024 points). Signal. Further, the control signals RD1 to RD3 generated by the read timing control unit 23 ′ are turned on (high) at the timing of SYC generated at a predetermined timing, and turned off (low) after the clock of the FFT size (1024 points). ).

  As shown in FIG. 10, when there is a delay time difference due to the radio wave propagation path length and the optical fiber 4 path length between the reception antenna branches, the phases of the symbol start timing pulses SYC1 to SYC1 to 3 are different for each reception antenna branch. It will be a thing. Therefore, the delay correction unit 15-1 ′ generates SYC at a predetermined timing, delays all the data 1 to 3, and sets the data 1 to 3 (S0 of data 1 and the data 2 of data 2) with the same symbol start timing. S407 and S0 of data 3) are output. As a result, the delay time difference within one OFDM symbol period is absorbed, and data 1 to 3 having the same symbol timing are output.

(Reading timing controller)
Next, the read timing control unit 23 ′ of the delay correction unit 15-1 ′ will be described in detail. FIG. 12 is a flowchart showing the processing of the read timing control unit 23 ′. The read timing control unit 23 ′ generates a reference pulse for each OFDM symbol period length based on the clock recovered by a clock recovery unit (not shown in FIG. 2) included in the demodulator 6-1 (step S1201). FIG. 10). The read timing control unit 23 ′ generates SYC at this timing, performs the same processing as the read timing control unit 23 shown in FIG. 7, and reads data from the buffers of the memory units 22-1 to 22-3. . This reference pulse is a reference pulse that is generated inside the demodulator 6-1 and has a period that matches the symbol timing of each branch and is independent of the phase.

  When the read timing control unit 23 ′ outputs the samples one by one from the buffers of the memory units 22-1 to 22-3 in the order of the carrier numbers, the RD pointers 1 to 3 for reading the samples in order at the timing of the reference pulse. RD pointers 1 to 3 are sequentially set by incrementing (step S1202). The read timing control unit 23 ′ generates control signals RD1 to RD3 (including RD pointers 1 to 3) for reading samples of data 1 to 3 from the positions of the RD pointers 1 to 3, and the memory unit 22−. 1 to 22-3 (step S1203). Further, the read timing control unit 23 'proceeds from step S1201, generates SYC from the reference pulse, and outputs it to the delay correction unit 15-2 (step S1204).

  As described above, according to the delay correction unit 15-1 ', signals from the FFT unit 14 and the non-signal branch detection / invalidation unit (not shown) are sequentially written to the buffer and read at a predetermined timing. As a result, the data 1 to 3 of all the receiving antenna branches can be stored in the buffer and delayed, and if there is a delay time difference between the data 1 to 3 between the receiving antenna branches, the symbol timing of each data 1 to 3 Can be combined.

(Problems of delay correction units 15-1 and 15-1 ′)
However, in the delay correction units 15-1 and 15-1 ′ described above, the frame start timing may not match. As in the examples of FIGS. 4 and 10, the data 1 to 3 output by the delay correction units 15-1 and 15-1 ′ are S 0, S 407, and S 0, respectively. The symbol numbers are shifted, and the frame start timings do not match. As described above, when the data 2 is delayed by more than one OFDM symbol period with respect to the data 1 and 3 of the other receiving antenna branches, only the first delay correction processing by the delay correction units 15-1 and 15-1 ′ is performed. , The deviation of the OFDM symbol unit remains.

  Therefore, the delay correction unit 15-2 at the subsequent stage performs delay correction in units of OFDM symbols, that is, second delay correction for matching the frame timing.

[Second delay correction]
Next, the second delay correction processing by the delay correction unit 15-2 illustrated in FIG. 2 will be described in detail. 13 is a block diagram showing the configuration of the delay correction unit 15-2, FIG. 14 is a timing chart showing the processing of the delay correction unit 15-2, and FIG. 15 shows the processing of the delay correction unit 15-2. It is a flowchart which shows. As described above, when there is a delay time difference between the reception antenna branches exceeding one OFDM symbol period as a result of the first delay correction processing by the delay correction unit 15-1, the delay correction unit 15-2 performs the OFDM symbol unit. It has a function of correcting the shift and matching the frame timing. Hereinafter, description will be made assuming that the number of reception antenna branches is three. The delay correction unit 15-2 includes frame start timing detection units 24-1 to 24-3, write timing control units 25-1 to 25-3, memory units 26-1 to 26-3, and a read timing control unit 27. I have.

  The delay correction unit 15-2 inputs data 1 to 3 and SYC which is a signal of the reference branch symbol start timing from the delay correction unit 15-1 (step S1501). The frame start timing detector 24-1 receives data 1, acquires a symbol number based on a TMCC (Transmission and Multiplexing Configuration Control) control signal included in the data 1, and obtains a symbol number 0 (S 0). SYC is detected as the frame start timing FRMSYC1, and FRMSYC1 is output to the read timing control unit 27 (step S1502). The frame start timing detection units 24-2 and 24-3 also perform the same processing as the frame start timing detection unit 24-1, input data 2 and 3, and generate symbols from the TMCC control signals included in the data 2 and 3 The number is acquired, and the frame start timings FRMSYC 2 and 3 are detected and output to the read timing control unit 27.

  The write timing control unit 25-1 receives SYC, generates a control signal WR1 (including the WR pointer 1) for writing the symbol of data 1 into the buffer of the memory unit 26-1, and sends the control signal WR1 to the memory unit 26-1. Output (step S1503). The write timing control units 25-2 and 25-3 also perform the same processing as the write timing control unit 25-1 and input SYC to generate control signals WR2 and 3 (including WR pointers 2 and 3). The data is output to the memory units 26-2 and 26-3. Here, the write timing control units 25-1 to 25-3 increment the WR pointers 1 to 3 every time SYC is input.

  The memory unit 26-1 receives data 1 and also receives a control signal WR 1 (including the WR pointer 1) from the write timing control unit 25-1, and receives a symbol of data 1 at the input timing of the control signal WR 1. Write to the position indicated by the WR pointer 1 in the buffer (step S1504). The memory units 26-2 and 26-3 also perform the same processing as the memory unit 26-1, and at the input timing of the control signals WR2 and 3 (including the WR pointers 2 and 3), The symbol is written in the position indicated by the WR pointers 2 and 3 in the buffer.

  The read timing control unit 27 inputs SYC and inputs FRMSYC1 to FRMSC1 to 3 from the frame start timing detection units 24-1 to 24-3. One frame period is set in the frame start timing pulse observation window (from the top) (step S1505). Specifically, the read timing control unit 27 sets a period (for example, ± 10 symbol periods) corresponding to a predetermined number of symbols before and after the frame start timing detected at an arbitrary timing. One frame period is set in the frame start timing pulse observation window from the most preceding signal when all the FRMSYC1 to 3 are input within the period. Then, the read timing control unit 27 detects the reception antenna branch (reference branch) of the most delayed signal among the FRMSYC 1 to 3 within the frame start timing pulse observation window (step S1506). Specifically, the read timing control unit 27 inputs the number of reception antenna branches from a non-signal branch detection / invalidation unit (not shown) of the delay correction unit 15-1, the number of reception antenna branches, and the input FRSYC1. When the same number is determined, it is determined that the most delayed signal among the FRMSYC1 to FRMSC1 to 3 is input, and the reference branch is detected at that timing.

  The read timing control unit 27 is a control signal serving as a common read timing for reading the symbols of data 1 to 3 from the buffers of the memory units 26-1 to 26-3 at the same timing at the frame start timing of the reference branch. RD1 to RD3 (including RD pointers 1 to 3) are generated, and control signals RD1 to RD3 are output to the memory units 26-1 to 26-3, respectively, at the same timing (step S1507). Thereby, at the frame start timing of the reference branch, the start symbol (symbol of symbol number 0 (S0)) of the frames 1 to 3 is read, and the subsequent symbols are also read sequentially.

  The memory unit 26-1 receives the control signal RD1 (including the RD pointer 1) from the read timing control unit 27, and reads the symbol of data 1 from the buffer at the input timing of the control signal RD1 (step S1508). The memory units 26-2 and 26-3 perform the same processing as the memory unit 26-1, and at the input timing of the control signals RD2 and 3 (including the RD pointers 2 and 3), the data 2 and 3 are transferred from the buffer. Read a symbol. That is, each time the memory units 26-1 to 26-3 input the control signals RD1 to RD3 (including the RD pointers 1 to 3), the data 1 to 3 written in the buffer are the same between the reception antenna branches. At the timing, the symbol number 0 (S0) is sequentially read out.

  The delay correction unit 15-2 outputs the data 1 to 3 and SYC (including the symbol number) read from the memory units 26-1 to 26-3 to the delay correction unit 15-3 (step S1509). Note that the symbol number 0 is assigned to the SYC at the frame start timing of the reference branch in the read timing control unit 27, and is incremented each time SYC is input thereafter. When the delay correction unit 15-3 inputs the symbol movement amount instead of the symbol number from the delay correction unit 15-2, the delay correction unit 15-2 determines how many symbols the frame start timing of the reference branch has moved. Monitor the symbol movement amount. Then, the delay correction unit 15-2 outputs SYC (including the symbol movement amount) to the delay correction unit 15-3.

  In FIG. 14, data 3 is the most delayed among the data 1 to 3 input from the delay correction unit 15-1, and with reference to data 3, a delay time difference of 3 OFDM symbols remains with respect to data 1. Thus, a delay time difference of 2 OFDM symbols remains for data 2. In the standard specified in ARIB STD-B33, for example, a 408 OFDM symbol is set as one OFDM frame, and the frame start timing is detected every 408 symbols. The frame number is assigned with a number from 0 to 7 in a super frame composed of, for example, 8 frames.

  As shown in FIG. 14, the time positions of FRMSYC1 to FRMSC3 indicating the frame start timing are different in the receiving antenna branches # 1 to # 3. Therefore, when the frame correction timing FRMSYC1 detected at an arbitrary timing is used as a reference, the delay correction unit 15-2 sets a period corresponding to a predetermined number of symbols before and after that, and all the FRMSYC1 within that period. The most advanced FRSYC1 when .about.3 is input is detected, and one frame period from the head of the frame is set as a frame start timing pulse observation window. Then, the delay correction unit 15-2 uses the reception antenna branch # 3 with the most delayed pulse phase in the observation window as a reference branch, stores the data of the other reception antenna branches # 1 and # 2 in a buffer, and delays them. The frame positions on the time axis are matched between the receiving antenna branches.

(Write timing controller)
The write timing control units 25-1 to 25-3 illustrated in FIG. 13 perform the same processing as in FIG. That is, each time the SYC is input, the write timing control units 25-1 to 25-3 increment the WR pointers 1 to 3, generate control signals WR1 to WR3, and store them in the memory units 26-1 to 26-3. Output. Thereby, in the memory units 26-1 to 26-3, the symbols of the data 1 to 3 are sequentially written at the positions of the WR pointers 1 to 3 included in the control signals WR 1 to 3 at every SYC timing.

(Reading timing controller)
Next, the read timing control unit 27 shown in FIG. 13 will be described in detail. FIG. 16 is a flowchart showing the processing of the read timing control unit 27, and FIG. 17 is a diagram for explaining pointer management by the read timing control unit 27. The read timing control unit 27 determines whether or not SYC has been input (step S1601). If it is determined that SYC has been input (step S1601: Y), whether or not one of FRMSYC1 to 3 has been input. Determination is made (step S1602). If it is determined in step S1601 that SYC has not been input (step S1601: N), the read timing control unit 27 ends the process, proceeds to step S1601, and waits for input of SYC.

  When the read timing control unit 27 determines in step S1602 that one of FRMSYC1 to FRMSC3 is input (step S1602: Y), the read timing control unit 27 corresponds to the predetermined number of symbols before and after the input frame start timing. Set the time period. Then, the read timing control unit 27 determines whether or not the signal is the most preceding frame start timing when all the FRMSYC1 to 3 are input within the period (step S1603), and the most preceding frame start timing is determined. If it is determined that the signal is the signal (step S1603: Y), a frame start timing pulse observation window having a length of one frame period is set from the frame start timing (step S1604), and the process proceeds to step S1607.

  On the other hand, when it is determined in step S1603 that the input FRMSYC1 to FRMSC1-3 are not the signal with the earliest frame start timing (step S1603: N), the read timing control unit 27 determines whether the signal is the latest frame start timing signal. Is determined (step S1605). Specifically, the read timing control unit 27 inputs the number of reception antenna branches (3 in this example) from a non-signal branch detection / invalidation unit (not shown) of the delay correction unit 15-1 and receives a frame start timing pulse. The number of FRMSYC1 to 3 input from the start time of the observation window is counted, and when the count number is smaller than 3, it is determined that the input signal is not the most delayed frame start timing signal among FRMSYC1 to 3 When the count number is 3, it is determined that the input signal is the most delayed frame start timing signal among FRMSYC 1 to 3. Thereby, the most delayed signal among FRMSYC1 to FRMSC3 can be determined in the middle of the frame start timing pulse observation window.

  When the read timing control unit 27 determines that the input FRMSYC1 to 3 are the signals of the latest frame start timing in step S1605 (step S1605: Y), the frame start delayed most in the frame start timing pulse observation window. The reception antenna branch at the timing is detected as a reference branch (step S1606).

  The read timing control unit 27 determines in step S1602 that any one of FRMSYC1 to FRMSC1 to 3 is not input (step S1602: N), or shifts from step S1604, or inputs FRMSYC1 to 1 in step S1605. If it is determined that 3 is not the signal of the latest frame start timing (step S1605: N), or the process proceeds from step S1606, the RD pointers 1 to 3 are incremented (step S1607), and the process proceeds to step S1608 and step S1609. . Note that the read timing control unit 27 sets the RD pointers 1 to 3 for sequentially reading from the symbol of symbol number 0 when the process proceeds from step S1606.

  The read timing control unit 27 proceeds from step S1607 to generate control signals RD1 to RD3 (including RD pointers 1 to 3) for reading the symbols of data 1 to 3 from the positions of the RD pointers 1 to 3, The data is output to the memory units 26-1 to 26-3 (step S1608). In addition, the read timing control unit 27 shifts from step S1607 to assign symbol number 0 (S0) at the frame start timing of the reference branch, and thereafter increments the symbol number every time SYC is input, and inputs SYC ( (Including the symbol number) is output to the delay correction unit 15-3 (step S1609). When the delay correction unit 15-3 inputs the symbol movement amount instead of the symbol number from the delay correction unit 15-2, the delay correction unit 15-2 performs SYC (including the symbol movement amount) as described above. The data is output to the delay correction unit 15-3.

  As described above, the read timing control unit 27 uses the receiving antenna branch of the most delayed signal among the FRMSYC1 to FRMSC3 as the reference branch, and sequentially stores the symbols of the data 1 to 3 from the buffer from the symbol number 0 at this timing. Control signals RD1 to RD3 for reading at the same timing are generated and output to the memory units 26-1 to 26-3. That is, for the data 1 to 3 written in the buffers of the memory units 26-1 to 26-3, the symbol with the symbol number 0 (S0) is read out at the most delayed frame start timing among the FRMSYC 1 to 3. , Every time SYC is input, the subsequent symbols are sequentially read out.

(Memory part)
The memory units 26-1 to 26-3 illustrated in FIG. 13 perform the same processing as in FIG. That is, each time the memory units 26-1 to 26-3 input the control signals WR1 to WR3 (including the WR pointers 1 to 3) from the write timing control units 25-1 to 25-3, Each time the symbol is written at the position of the WR pointers 1 to 3 in the buffer and the control signals RD1 to RD3 (including the RD pointers 1 to 3) are input from the read timing control unit 27, the RD pointers 1 to 3 in the buffer The symbols of data 1 to 3 are read from the position at the same timing.

  Note that the size of the delay buffer of the memory units 26-1 to 26-3 required for each of the receiving antenna branches # 1 to # 3 is the actual amount of delay and hardware such as an FPGA (Field Programmable Gate Array). Is set in units of OFDM symbols in consideration of the memory capacity installed in the. For example, when it is necessary to correct up to a delay time difference of 10 OFDM symbols at the maximum, a buffer capacity of 2 × 12 × 1024 × 10 = 240 kbit is required for each reception antenna branch. When the OFDM symbol length is 56 μsec, the delay of 10 OFDM symbols corresponds to a path length difference of about 160 km.

  Thus, according to the memory units 26-1 to 26-3, the data is delayed by the buffer having a capacity corresponding to the maximum OFDM symbol length assumed to be delayed, and the frame start timings of all the data 1 to 3 are set. Can be matched. That is, the delay time within one frame period is corrected with the minimum necessary buffer capacity, and the frame timing can be matched.

  As described above, according to the delay correction unit 15-2 shown in FIG. 2 and FIG. 13, each time SYC1 to SYC3 is input, the symbols of data 1 to 3 are written to the buffer, and the frame start timing pulse observation window , The receiving antenna branch of the most delayed signal among FRMSYC 1 to 3 is detected as a reference branch, and the symbols of data 1 to 3 are sequentially read out simultaneously at the frame start timing of the reference branch. That is, at the frame start timing of the reference branch, the symbol number 0 (S0) of data 1 to 3 is read, and the subsequent symbols are also read sequentially. As a result, the data of the receiving antenna branches other than the reference branch can be stored and delayed. When there is a delay time difference exceeding 1 OFDM symbol period in the data 1 to 3 between the receiving antenna branches, Frame timing can be adjusted.

(Problem of delay correction unit 15-2)
By the way, in the macro diversity reception system shown in FIG. 1, the system and number of signals input to the demodulator 6-1 through the plurality of reception points 3 change as the mobile relay vehicle 1 moves. That is, the time position of the most delayed frame start timing may vary, the signal may be interrupted in the middle, or the signal may be input via the new receiving antenna 3 from the middle. However, the delay correction unit 15-2 illustrated in FIG. 13 does not assume such a case. When the signal of the reference branch is interrupted after the delay correction process is established in the initial state (a), or when a signal of a new receiving antenna branch delayed from the signal of the reference branch is input (b) The following inconvenience occurs.

  In the case of (a), for example, if the reference branch is changed to the second delayed reception antenna branch, the processing of the delay correction unit 15-2 causes the past reference branch and the second delayed reception antenna branch to be The symbol period corresponding to the difference between them is lost, resulting in a problem that the video is temporarily interrupted.

  FIG. 18 is a diagram illustrating the RD pointer of the buffer in the memory unit 26-1, and corresponds to the timing chart of FIG. (1) shows a case where the signal of the reference branch (reception antenna branch # 3) is not interrupted, and (2) shows that the signal of the reference branch (reception antenna branch # 3) is interrupted and a new reception antenna branch # 2 Is detected as a reference branch. As shown in FIG. 14 and FIG. 18 (1), in the state where the receiving antenna branch # 3 is detected as the reference branch, at the timing of FRMSYC2, the symbol number 406 (data 1) from the buffer of the memory unit 26-1. The symbol of S406) is read (see the location at time t2 in FIG. 18A).

  When the signal of the most delayed receiving antenna branch # 3 is interrupted, the read timing control unit 27 inputs the number 2 of receiving antenna branches from a non-signal branch detection / invalidating unit (not shown) of the delay correcting unit 15-1. Then, after FRMSYC1 is input, FRMSYC2 is input, and this is determined as the most delayed frame start timing. Then, the read timing control unit 27 sets the RD pointers 1 and 2 for reading the symbol of symbol number 0, and generates control signals RD1 and RD2. In this case, as shown in FIG. 18 (2), since the timing of FRMSYC2 becomes the frame start timing of the reference branch, the symbol number 0 (S0) of data 1 is read from the buffer of the memory unit 26-1 at the timing of FRMSYC2. ) Is read (see the location at time t2 in FIG. 18B). That is, after the symbol number 405 (S405) of the data 1 is read (see the location at time t1), the symbols of the symbol number 406 (S406) and the symbol number 407 (S407) are not read and are lost. .

  FIG. 18 (2) shows a case where the signal of the reference branch in (a) is interrupted. In this case, since the frame start timing of the reference branch moves to a time position earlier than before, symbol number 406 The symbol with the symbol number 407 (S407) and the symbol number 407 (S407) is missing without being read out.

  Therefore, in the modified example of the delay correction unit 15-2, the following process is performed instead of the second delay correction process by the delay correction unit 15-2 described above. Note that the problem and the corresponding processing that occur in the case of (b) will be described later.

[Modification of Second Delay Correction]
Next, a modified example of the second delay correction process by the delay correction unit 15-2 illustrated in FIG. 13 will be described in detail. In this modification, in order to prevent symbols from being lost even when the reception signal of the reference branch is interrupted, the detected reference branch is always held as the reference branch, and the read timing from the buffer is not changed. Thus, the continuity of symbols on the time axis is maintained. FIG. 19 is a timing chart showing processing of a modified example of the delay correction unit 15-2 (hereinafter referred to as delay correction unit 15-2 ′), and FIG. 20 shows the processing of the delay correction unit 15-2 ′. It is a flowchart.

  The delay correction unit 15-2 'includes the same components as the delay correction unit 15-2 illustrated in FIG. Comparing the delay correction unit 15-2 and the delay correction unit 15-2 'described above, they are the same in that both have a function of correcting the delay time difference exceeding one OFDM symbol period and matching the frame timing. However, the delay correction unit 15-2 described above uses the receiving antenna branch of the most delayed signal among the FRMSYC1 to FRMSC1-3 as a reference branch, and reads the symbol of symbol number 0 (S0) at that timing. The delay correction unit 15-2 ′ is different in that the detected reference branch and its frame start timing are held, and the symbol number 0 (S0) of data 1 to 3 is always read at that timing. . In FIG. 13, the delay correction unit 15-2 'includes a read timing control unit 27 (hereinafter referred to as a read timing control unit 27') that performs processing different from that of the delay correction unit 15-2. The frame start timing detection units 24-1 to 24-3, the write timing control units 25-1 to 25-3, and the memory units 26-1 to 26-3 perform the same processing as described above. In the following description, the number of reception antenna branches is assumed to be 3.

  In the flowchart shown in FIG. 20, the processes in steps S2001 to S2005, S2007, and S2009 to S2011 are the same as the processes in steps S1501 to S1509 in the flowchart showing the processes of the delay correction unit 15-2 shown in FIG. It is the same as the processing. The read timing control unit 27 ′ of the delay correction unit 15-2 ′ proceeds from step S 2005 and determines whether or not the reference branch and its frame start timing have been held (step S 2006). If the read timing control unit 27 ′ determines in step S2006 that the read timing control unit 27 ′ has not held the received signal (step S2006: N), the reception antenna branch (FRMSYC1 to 3) of the most delayed signal in the frame start timing pulse observation window ( (Reference branch) is detected (step S2007), the reference branch and its frame start timing are held (step S2008), and the process proceeds to step S2009.

  On the other hand, if the read timing control unit 27 'determines in step S2006 that the reference branch and its frame start timing have been held (step S2006: Y), the read timing control unit 27' proceeds to step S2009. As a result, even if the signal of the reference branch is interrupted, the new reference branch is not detected (the second delayed receiving antenna branch is not detected as the reference branch), and held in step S2008. A reference branch can be used. At the frame start timing, control signals RD1 to RD3 can be generated and data 1 to 3 can be read from the buffer (steps S2009 to S2011 described later).

  If the signal of the receiving antenna branch # 3 is interrupted, the data 3 is not input and the FRMSYC3 is not generated. Therefore, the control signals RD1 and RD1 and 2 are generated in step S2009, and the data 1 and 2 are generated in steps S2010 and S2011. Are read from the buffer and output.

  In FIG. 19, since FRMSYC3 is most delayed among FRMSYC1 to FRMSYC1-3, the receiving antenna branch # 3 becomes the reference branch, and FRMSYC3 becomes the frame start timing of the reference branch and is held. The delay correction unit 15-2 ′ always uses the received reference branch and the frame start timing as a reference branch without detecting a new reference branch, and uses the held reference branch and its frame start timing. At the start timing, control signals RD1 to RD3 for sequentially reading from the symbol of symbol number 0 are generated. After this timing, the symbols of data 1 to 3 written in the buffer are sequentially read from symbol number 0 (S0). When the signal of the receiving antenna branch # 3 is interrupted, the FRMSC3 and the data 3 are not input. In this case, since the delay correction unit 15-2 'does not detect a new reference branch, the data 1 and 2 can always be read from the buffer at the same timing.

(Reading timing controller)
Next, the read timing control unit 27 ′ of the delay correction unit 15-2 ′ will be described in detail. FIG. 21 is a flowchart showing the processing of the read timing control unit 27 ′. The read timing control unit 27 ′ determines whether or not SYC has been input (step S2101). If it is determined that SYC has been input (step S2101: Y), has the current frame start timing passed? It is determined whether or not (step S2102). If it is determined in step S2101 that SYC has not been input (step S2101: N), the read timing control unit 27 ′ ends the process, proceeds to step S2101, and waits for input of SYC.

  On the other hand, in step S2102, the read timing control unit 27 ′ determines that the currently held frame start timing has not passed or if it determines that the frame start timing is not held (step S2102: N). ) And FRMSYC1 to 3 are determined (step S2103). When the processing of the read timing control unit 27 'is started, the reference branch and the frame start timing are not held, and the process proceeds to step S2103. On the other hand, if it is determined in step S2102 that the currently held frame start timing has passed (step S2102: Y), the process proceeds to step S2110.

  When it is determined in step S2103 that any one of FRMSYC1 to FRMSC1 to 3 has been input (step S2103: Y), the read timing control unit 27 ′ sets the predetermined number of symbols before and after the input frame start timing as a reference. Set the corresponding period. Then, the read timing control unit 27 ′ determines whether or not it is the signal of the most preceding frame start timing when all the FRMSYC1 to 3 are input within the period (step S2104), and the most preceding frame start is determined. When it is determined that the signal is a timing signal (step S2104: Y), a frame start timing pulse observation window having a length of one frame period is set from the frame start timing (step S2105), and the process proceeds to step S2110.

  On the other hand, when it is determined in step S2104 that the input FRMSYC1 to FRMSC1-3 are not the most preceding frame start timing signals (step S2104: N), the read timing control unit 27 ′ holds the reference branch and its frame start timing. It is determined whether or not (step S2106).

  If the read timing control unit 27 ′ determines in step S2106 that the reference branch and its frame start timing have not been held (step S2106: N), whether the input FRMSYC1 to 3 are the signals of the latest frame start timing. It is determined whether or not (step S2107). On the other hand, if it is determined in step S2106 that the reference branch and its frame start timing have been held (step S2106: Y), the process proceeds to step S2110.

  When the read timing control unit 27 ′ determines in step S2107 that the input FRMSYC1 to 3 are the signals of the latest frame start timing (step S2107: Y), the most delayed frame in the frame start timing pulse observation window The reception antenna branch at the start timing is detected as a reference branch (step S2108), the reference branch and its frame start timing are held (step S2109), and the process proceeds to step S2110. On the other hand, if it is determined in step S2107 that the input FRMSYC1 to 3 are not the latest frame start timing signals (step S2107: N), the process proceeds to step S2110.

  The read timing control unit 27 ′ proceeds from step S2102, step S2103, step S2105, step S2106, step S2107, or step S2109, increments the RD pointers 1 to 3 (step S2110), and proceeds to step S2111 and step S2112. To do. Note that the read timing control unit 27 ′ sets RD pointers 1 to 3 for sequentially reading from the symbol of symbol number 0 when moving from step S 2102 or step S 2109.

  The read timing control unit 27 ′ proceeds from step S2110 to generate control signals RD1 to RD3 (including RD pointers 1 to 3) for reading the symbols of data 1 to 3 from the positions of the RD pointers 1 to 3. And output to the memory units 26-1 to 26-3 (step S2111). Also, the read timing control unit 27 ′ shifts from step S2110 to set the symbol number to 0 (S0) at the frame start timing of the reference branch, and then increments the symbol number every time SYC is input. (Including the number) is output to the delay correction unit 15-3 (step S2112). When the delay correction unit 15-3 inputs the symbol movement amount instead of the symbol number from the delay correction unit 15-2, the delay correction unit 15-2 performs SYC (including the symbol movement amount) as described above. The data is output to the delay correction unit 15-3.

  In this way, the read timing control unit 27 ′ uses the receiving antenna branch of the most delayed signal among the FRMSYC1 to 3 as the reference branch, holds the reference branch and its frame start timing, and thereafter detects the reference branch. Without generating the control signals RD1 to RD3 for reading the symbols of data 1 to 3 sequentially from the buffer at the same timing from the symbol number 0 at the held frame start timing. 3 is output. That is, even when the signal of the reference branch is interrupted, the data 1 to 3 written in the buffer are sequentially read from the symbol of symbol number 0 (S0) at each held symbol start timing.

  As described above, according to the delay correction unit 15-2 ′, each time SYC1 to SYC3 is input, the symbols of data 1 to 3 are written to the buffer, and within the frame start timing pulse observation window, The receiving antenna branch of the most delayed signal is held as a reference branch, the frame start timing is also held, and the symbols of data 1 to 3 are simultaneously read at the held frame start timing without detecting the reference branch. I did it. In other words, the symbol number 0 (S0) of data 1 to 3 is read at the frame start timing of the reference branch, and the subsequent symbols are also read sequentially. As a result, the data of the receiving antenna branches other than the reference branch can be stored and delayed. When there is a delay time difference exceeding 1 OFDM symbol period in the data 1 to 3 between the receiving antenna branches, Frame timing can be adjusted. Further, even when the signal of the reference branch is interrupted, it is possible to read out continuous symbols with the frame timings of the data 1 to 3 matching each other from the buffer.

(Problem of delay correction unit 15-2 ')
As described above, in the macro diversity reception system shown in FIG. 1, the system and number of signals input to the demodulator 6-1 via the plurality of reception points 3 change as the mobile relay vehicle 1 moves. Therefore, a case where the signal of the reference branch is interrupted (a) and a case where a signal of a new receiving antenna branch delayed from the signal of the reference branch is input (b) are assumed. The delay correction unit 15-2 ′ described above can cope with the case (a). However, the delay correction unit 15-2 ′ cannot cope with the case (b).

  Therefore, in addition to the above processing, the delay correction unit 15-2 ′ receives a signal of the detected reference branch or a signal delayed from the held reference branch signal, that is, a signal of the frame start timing of the reference branch. When a signal with a frame start timing later than that is input, it is necessary to update the reference branch and its frame start timing.

  However, even if processing for updating the reference branch and its frame start timing is added, the symbols read from the buffer become discontinuous, the same symbols are output repeatedly, and the continuity of symbols on the time axis is lost. Problems arise.

  FIG. 22 is a timing chart showing a state in which the most delayed receiving antenna branch is changed in the delay correction unit 15-2 ′, and symbols are output redundantly, and FIG. 23 illustrates the RD pointer in that state. It is a figure to do. As shown in FIG. 22, first, the signals of the receiving antenna branches # 1 to # 3 are received, the most delayed receiving antenna branch # 3 is detected as the reference branch, and the data 1 and 2 are delayed by the buffer. The symbol start timings are matched.

  Next, it is assumed that a signal of a new reception antenna branch # 4 that is delayed by one OFDM symbol from the reference branch that is the reception antenna branch # 3 is input. In this case, the reference branch is updated from the reception antenna branch # 3 to the reception antenna branch # 4, and the frame start timing of the reference branch is also updated to FRMSC4 of the reception antenna branch # 4. That is, the frame start timing of the reference branch is delayed by one OFDM symbol from FRMSYC3 to FRMSYC4. Therefore, the symbol of symbol number 0 (S0) is read from the buffer at the timing of FRMSYC3 (see the location at time t4 in FIG. 23), and the same symbol number from the buffer at the timing of FRMSYC4 one OFDM symbol after FRMSYC3. Since the symbol of 0 (S0) is read (see the location at time t5 in FIG. 23), the symbol of symbol number 0 (S0) is output twice in succession. In this case, inconsistency occurs in the deinterleaving or error correction processing in addition to the frame synchronization timing deviation in the subsequent stage, which may cause an instantaneous video interruption or the like.

  22 and 23, when a signal of a new receiving antenna branch delayed from the signal of the reference branch in (b) is input, the frame start timing of the reference branch moves to a time position later than before, and the symbol This shows that the symbol of number 0 (S0) is output twice in succession.

  Therefore, the delay correction unit 15-3 performs third delay correction for ensuring the continuity of symbols on the time axis so that the same symbols are not output repeatedly.

[Third delay correction]
Next, the third delay correction process by the delay correction unit 15-3 illustrated in FIG. 2 will be described in detail. FIG. 24 is a block diagram illustrating a configuration of the delay correction unit 15-3, and FIG. 25 is a flowchart illustrating processing of the delay correction unit 15-3. As described above, when the reference branch and its frame start timing are updated, the delay correction unit 15-3 has a function of ensuring continuity in the time axis of symbols read out and output from the buffer. Specifically, the delay correction unit 15-3 stores the signals of all reception antenna branches in a buffer, delays the same amount of the designated symbol in advance, and updates the reference branch and its frame start timing. Then, the RD pointer is advanced by the same amount on the time axis for all the receiving antenna branches. Hereinafter, a case where the number of reception antenna branches is changed from 3 to 4 and the reference branch and its frame start timing are updated will be described. The delay correction unit 15-3 includes a write timing control unit 28, memory units 29-1 to 29-4, and a read timing control unit 30.

  The delay correction unit 15-3 inputs data 1 to n and SYC (including a symbol number) from the delay correction unit 15-2 (step S2501). Here, n indicates the number of reception antenna branches, which is 3 before the reference branch is updated, and 4 after the update, and from a non-signal branch detection / invalidation unit (not shown) of the delay correction unit 15-1. Entered. The write timing control unit 28 receives SYC and generates control signals WR1 to n (including WR pointers 1 to n) for writing the symbols of data 1 to n to the buffers of the memory units 29-1 to 29-n. Then, the data is output to the memory units 29-1 to 29-n (step S2502). Here, the write timing control unit 28 increments the WR pointers 1 to n every time SYC is input.

  The memory units 29-1 to 29-n receive the data 1 to n and the control signals WR1 to n (including the WR pointers 1 to n) from the write timing control unit 28, and the control signals WR1 to n At the input timing, the symbols of data 1 to n are written in the positions of WR pointers 1 to n in the buffer (step S2503).

  The read timing control unit 30 inputs SYC (including a symbol number), determines whether or not there is an overlap of symbol numbers for each SYC to be input, and sets a parameter α (step S2504). The parameter α is data for determining the RD pointers 1 to n when it is determined that the symbol numbers are duplicated. When the read timing control unit 30 determines that the symbol numbers do not overlap, the read timing control unit 30 determines that the reference branch is unchanged and does not set α. If it is determined that the symbol numbers are duplicated, α = (number of duplicated symbols) is set. A specific method for setting the parameter α will be described later. When the delay correction unit 15-2 outputs the symbol movement amount instead of the symbol number, the delay correction unit 15-3 inputs SYC (including the symbol movement amount) and sets the symbol movement amount as the parameter α. To do.

  The read timing control unit 30 sets the RD pointers 1 to n at the timing when SYC is input, and reads the symbols of data 1 to n from the buffers of the memory units 29-1 to 29-n at the same timing. Control signals RD1 to RDn that are common readout timings are generated (step S2505). Here, the RD pointers 1 to n are shifted in advance by a predetermined delay amount with respect to the WR pointers 1 to n, and when the symbol number is duplicated (when the symbol movement amount is other than 0), only the parameter α is used. It is advanced.

  For example, when the demodulator 6-1 receives signals from the reception antenna branches # 1 to # 3 and the reception antenna branch # 3 is operating as a reference branch, a new signal from the reception antenna branch # 4 is obtained. And receiving antenna branch # 4 delayed by one OFDM symbol period from receiving antenna branch # 3 is updated to the reference branch, α = 1 is set, and RD pointers 1 to n are advanced by 1. Details will be described later.

  The memory units 29-1 to 29-n receive the control signals RD1 to n (including RD pointers 1 to n) from the read timing control unit 30, and the RDs in the buffer are input at the input timing of the control signals RD1 to n. The symbols of data 1 to n are read from the positions of the pointers 1 to n (step S2506). The delay correction unit 15-3 outputs the data 1 to n read from the memory units 29-1 to 29-n (step S2507).

  As described above, according to the read timing control unit 30, the RD pointers 1 to n are shifted in advance by a predetermined delay amount with respect to the WR pointers 1 to n, and the symbol numbers are duplicated as the reference symbol is updated. When it is determined that the RD pointers 1 to n are shifted, the RD pointers 1 to n are shifted by the overlapping number. Alternatively, the RD pointers 1 to n are shifted by the number of input symbol movement amounts. Thereby, the same symbol is not output redundantly from the delay correction unit 15-3, and the continuity of the symbols on the time axis can be ensured.

(Write timing controller)
The write timing control unit 28 shown in FIG. 24 performs the same processing as in FIG. That is, every time SYC is input, the write timing control unit 28 increments the WR pointers 1 to 4, generates control signals WR1 to WR4, and outputs them to the memory units 29-1 to 29-4. As a result, in the memory units 29-1 to 29-4, the symbols of the data 1 to 4 are sequentially written at the positions of the WR pointers 1 to 4 included in the control signals WR 1 to 4 at each SYC timing.

(Reading timing controller)
Next, the read timing control unit 30 shown in FIG. 24 will be described in detail. FIG. 26 is a flowchart showing processing of the read timing control unit 30, and FIG. 27 is a diagram for explaining pointer management by the read timing control unit 30. The read timing control unit 30 sets a pointer obtained by adding a predetermined initial delay amount (for example, 10) to preset initial WR pointers 1 to n as the initial RD pointers 1 to n. Here, the initial delay amount is the number of pointers for delaying the data 1 to n in the buffer by a designated symbol in advance (shifting the RD pointers 1 to n with respect to the WR pointers 1 to n). Further, n indicates the number of reception antenna branches, which is 3 before the reference branch is updated and 4 after the update, and is input from an unillustrated no-signal branch detection / invalidation unit of the delay correction unit 15-1. Is done.

  The read timing control unit 30 determines whether or not SYC has been input (step S2601). If it is determined that SYC has been input (step S2601: Y), the read timing control unit 30 acquires the symbol number included in the SYC, and the symbol number is It is determined whether or not they overlap (step S2602). Specifically, every time SYC is input, the read timing control unit 30 determines that the symbol number is not duplicated when the symbol number is incremented, and assigns a symbol number other than the symbol number 407 (S407). When the symbol number of S0 is input after the input, it is determined that the symbol number is duplicated. For example, in the example of FIGS. 22 and 27 (2), since the symbol number 0 (S0) is continuously input after the symbol number 0 (S0) is input, it is determined that the symbol numbers overlap. To do. In this case, the symbol number overlap number is 1. For example, when symbol number 0 (S0) is input after inputting symbol numbers 0 (S0), 1 (S1), and 2 (S2), it is determined that symbols overlap. In this case, the overlapping number of symbol numbers is 3. If it is determined in step S2601 that SYC has not been input (step S2601: N), the read timing control unit 30 ends the process and waits until SYC is input.

  If the read timing control unit 30 determines in step S2602 that the symbol numbers are duplicated (step S2602: Y), α = duplicate is set (step S2603), and the process proceeds to step S2604. On the other hand, if it is determined in step S2602 that the symbol numbers do not overlap (step S2602: N), the process proceeds to step S2604. Note that when the symbol correction amount is input instead of the symbol number from the delay correction unit 15-2, the delay correction unit 15-3 sets the input symbol movement amount as the parameter α. In the example of FIGS. 22 and 27 (2), the delay correction unit 15-3 receives the symbol movement amount 1 and sets the parameter α = 1.

  The read timing control unit 30 determines whether or not the current position of the RD pointers 1 to n is a position where the 407th symbol is written (step S2604). If it is determined in step S2604 that the current position of the RD pointers 1 to n is the position where the 407th symbol is written (step S2604: Y), the current RD pointers 1 to n are incremented. New RD pointers 1 to n added with α are generated (step S2605). If there is an overlapping symbol number in step S2602 (when the symbol movement amount is other than 0), the RD pointers 1 to n are advanced by α after being incremented. On the other hand, when it is determined that the current position of the RD pointers 1 to n is not the position where the symbol having the maximum carrier number 407 is written (step S2604: N), the current RD pointers 1 to n are incremented (step S2604). S2606).

  The read timing control unit 30 generates control signals RD1 to n (including RD pointers 1 to n) for reading the symbols of data 1 to n from the positions of the RD pointers 1 to n, and the memory units 29-1 to 29-29. -N is output (step S2607).

  As described above, the read timing control unit 30 sets the initial RD pointers 1 to n to the initial WR pointers 1 to n + initial delay amount, and determines whether or not the symbol numbers are duplicated when SYC is input. If there is an overlap, α = multiple is set, and if the current position of the RD pointers 1 to n is the position of the maximum value of the symbol number, the RD pointers 1 to n are incremented and advanced by α. I made it. The read timing control unit 30 is premised on adjusting the timing for outputting the carrier number 0 symbol when the reference branch is updated. As a result, the symbols of the data 1 to n written in the buffers of the memory units 29-1 to 29 -n are read out by being shifted from the WR pointers 1 to n by the initial delay amount, and the symbol numbers are duplicated. In this case, the symbols are sequentially read from the symbol number 0 (S0) at the position shifted by the overlap α.

  FIG. 27A shows the WR pointer and the RD pointer when the reference branch does not change. If the initial RD pointer is set to the initial WR pointer + initial delay amount 10 by the read timing control unit 30 in the initial state, the delay amount (delay symbol between the WR pointer and the RD pointer when the reference branch does not change). Long) is 10. As shown in FIG. 27 (1), when SYC is input at time t1, the symbol of symbol number 7 (S7) is written at the position of WR pointer = (t1). Then, in the read timing control unit 30, it is determined that the symbol numbers are not duplicated, the RD pointer is incremented, and the symbol is determined from the position of the RD pointer = (t1) that is 10 delays away from the WR pointer = (t1). The number 406 (S406) is read out. Next, when SYC is input at time t2, symbol number 8 (S8) is written at the position of WR pointer = (t2). Then, in the read timing control unit 30, it is determined that the symbol numbers do not overlap, the RD pointer is incremented, and the symbol is determined from the position of the RD pointer = (t2) that is 10 delays away from the WR pointer = (t2). Number 407 (S407) is read. Next, when SYC is input at time t3, symbol number 9 (S9) is written at the position of WR pointer = (t3). Then, the read timing control unit 30 determines that the symbol numbers do not overlap, determines that the position of the RD pointer is the position where the symbol number 407 (S407) is written, increments the RD pointer, and α = 0 is added, and the symbol number 0 (S0) is read from the position of the RD pointer = (t3) which is 10 delays away from the WR pointer = (t3).

  Thus, when the reference branch does not change, symbols are stored in the buffer in the order of the symbol numbers. In addition, the RD pointer is incremented by 1 while the delay amount between the WR pointer and the RD pointer is maintained at 10. As a result, the same symbols are not output from the buffer repeatedly, and the symbols are output successively in numerical order.

  FIG. 27 (2) shows the WR pointer and the RD pointer when updated to a new reference branch delayed by one symbol period. In the initial state, the read timing control unit 30 sets the initial RD pointer to the initial WR pointer + initial delay amount 10, and the delay amount between the WR pointer and the RD pointer is 10 when the reference branch does not change. It is assumed that the operation is established with the receiving antenna branch # 3 as a reference branch. If the reference branch is updated to a new receiving antenna branch # 4 that is delayed by one symbol period from the receiving antenna branch # 3, the delay amount is 9. As shown in FIG. 27 (2), when SYC is input at time ta to te, symbol number 0 (S0) is determined at read time control unit 30 at time tc. α = 0 is initialized, and at time td, it is determined that symbol number 0 (S0) is duplicated, and α = 1 is set.

  Next, when SYC is input at time t1, symbol number 6 (S6) is written at the position of WR pointer = (t1). Then, in the read timing control unit 30, it is determined that the symbol numbers are not duplicated, the RD pointer is incremented, and the symbol is determined from the position of the RD pointer = (t1) that is 10 delays away from the WR pointer = (t1). The number 406 (S406) is read out. Next, when SYC is input at time t2, symbol number 7 (S7) is written at the position of WR pointer = (t2). Then, in the read timing control unit 30, it is determined that the symbol numbers do not overlap, the RD pointer is incremented, and the symbol is determined from the position of the RD pointer = (t2) that is 10 delays away from the WR pointer = (t2). Number 407 (S407) is read. Next, when SYC is input at time t3, symbol number 8 (S8) is written at the position of WR pointer = (t3). Then, the read timing control unit 30 determines that the symbol numbers do not overlap, determines that the position of the RD pointer is the position where the symbol number 407 (S407) is written, increments the RD pointer, and α = 1 is added, and symbol number 0 (S0) is read from the position of RD pointer = (t3), which is a delay amount 9 away from WR pointer = (t3). The reason why α = 1 is added to the RD pointer and the RD pointer is advanced by one symbol is because the symbol of symbol number 0 (S0) is written in the buffer redundantly to avoid redundant reading.

  In this way, when updated to a new reference branch delayed by one symbol period, the RD pointer is advanced by α = 1 when the symbol number 0 (S0) is read, and between the WR pointer and the RD pointer. Is changed from 10 to 9, the same symbol is not output from the buffer repeatedly, and the symbols are output successively in the order of numbers.

(Memory part)
The memory units 29-1 to 29-4 illustrated in FIG. 24 perform the same processing as in FIG. That is, each time the memory units 29-1 to 29-4 receive the control signals WR 1 to 4 (including the WR pointers 1 to 4) from the write timing control unit 28, the memory units 29-1 to 29-4 Each time the control signals RD1 to RD4 (including the RD pointers 1 to 4) are input from the read timing control unit 30, the data 1 to 4 from the positions of the RD pointers 1 to 4 in the buffer are written. Are read at the same timing.

  As described above, according to the delay correction unit 15-3 illustrated in FIG. 2 and FIG. 24, each time SYC is input, the symbols of the data 1 to 3 of the reception antenna branches # 1 to # 3 are written to the buffer. Read and output after delaying by a predetermined delay amount. When it is determined that the data 4 of the new receiving antenna branch # 4 is the most delayed signal, and the reference branch is updated and symbol number 0 (S0) is duplicated, the RD pointers 1 to 4 are set to duplicate symbols. The data is changed according to the number 0 (S0), and data 1 to 4 are read from the buffer. As a result, the same symbol is not read from the buffer repeatedly, and consecutive symbols are output. Therefore, even a reception signal that is random in time can be subjected to reception processing that maintains the continuity of the time axis, and video and the like do not break down. Even if a new receive antenna branch signal that is delayed from the reference branch signal is input, that is, the frame start timing of the reference branch moves to a later time position than before, the same symbol is duplicated from the buffer. The consecutive symbols are output without being read out.

  Further, the buffer in the memory units 29-1 to 29-4 only needs to be able to store a symbol having a length of 10 symbols.

  As described above, according to the demodulator 6-1 of the first embodiment, the delay correction unit 15-1 receives the reception antenna branch (reference branch) with the most delayed symbol start timing within a predetermined symbol start timing pulse observation window. ) Is detected, the data of the other receiving antenna branches are stored in the first buffer and delayed, and the symbol timing is output in accordance with the data of the reference branch. In addition, the delay correction unit 15-2 sets a frame start timing pulse observation window having a length of one frame from the head of the frame of the most preceding data among the data of each reception antenna branch having the same symbol timing, and the observation window , The reception antenna branch (reference branch) with the most delayed frame start timing is detected, the other reception antenna branches are stored in the second buffer and delayed, and the frame timing is output in accordance with the data of the reference branch. I did it. Further, the delay correction unit 15-3 stores the data of each reception antenna branch with the matching frame timing in the third buffer, reads the data after delaying it by a predetermined delay amount, and outputs it. When the symbol numbers are duplicated, the read pointer is changed according to the number of duplicates, and data is read from the third buffer.

  This is necessary even when the delay time difference of the received signal between the receiving antenna branches is significantly different over one OFDM symbol period or when the received signal is randomly input to the demodulator 6-1. It is possible to generate a signal that maintains the continuity of the time axis while maintaining a minimum processing delay, and the symbol and frame timing coincide with the subsequent complex weight calculation / multiplication / addition unit 16, and the continuity of the symbol numbers Can be input. That is, the delay time difference of the received signal can be accurately corrected even when the reception timing is different due to the difference in the radio wave propagation path length and the wired transmission path length between the reception antenna branches. Accordingly, since the reception timing can be matched between the reception antenna branches, it is possible to appropriately combine the reception signals, and it is possible to suppress the deterioration of the reception characteristics. Then, it is possible to realize combined diversity reception, adaptive array reception, or MIMO transmission by macro diversity.

[Demodulator / Embodiment 2]
Next, the demodulation device 6 according to the second embodiment will be described in detail. FIG. 28 is a block diagram illustrating a configuration of the demodulation device 6 according to the second embodiment. The demodulator 6-2 includes an A / D converter 10, a digital orthogonal demodulator 11, a symbol synchronization / AFC unit 12, a delay corrector 15-1, a GI remover 13, an FFT unit 14, and a delay corrector 15-2. , A delay correction unit 15-3 and a complex weight calculation / multiplication / addition unit 16 are provided. Comparing the demodulating device 6-1 of the first embodiment shown in FIG. 2 with the demodulating device 6-2 of the second embodiment, in the demodulating device 6-1, the delay correcting unit 15-1 is provided at the subsequent stage of the FFT unit 14. In contrast, the first delay correction is performed on the signal in the frequency domain, whereas in the demodulation device 6-2, the delay correction unit 15-1 is provided between the symbol synchronization / AFC unit 12 and the GI removal unit 13. The difference is that the first delay correction is performed on the signal in the time domain.

  The delay correction unit 15-1 of the demodulator 6-2 receives the signal (data) AFC and the signal of the symbol start timing from the symbol synchronization / AFC unit 12, and the most delayed symbol for all time domain data A receiving antenna branch (reference branch) having a start timing is detected, and the symbol timing is adjusted to the data of the reference branch for all data. The data of each receiving antenna branch and the SYC signal that match the symbol timing are output to the GI removing unit 13. The demodulator 6-1 includes a null signal insertion unit that inserts a null signal in a period corresponding to the GI period for each symbol, but does not include the demodulator 6-2.

  The GI removal unit 13 receives the data and SYC of each reception antenna branch from the delay correction unit 15-1, sets the FFT window position, removes the GI, extracts the effective symbols, and generates a signal with an effective symbol length. To do.

  The delay correction unit 15-2 receives the data and SYC of each receiving antenna branch having the same symbol timing from the FFT unit 14, and matches the frame timing to the data of the reference branch for all data. Since the details of the processing of each component have been described, description thereof is omitted here.

  As described above, according to the demodulator 6-2 of the second embodiment, the same effects as those of the first embodiment can be obtained. In addition, since the FFT unit 14 according to the second embodiment performs FFT on the data of each reception antenna branch having the same symbol timing, it can collectively process the data of all the reception antenna branches. On the other hand, since the FFT unit 14 of the first embodiment performs FFT on the data of each reception antenna branch that does not match the symbol timing, it is necessary to perform parallel processing in the FFT circuit prepared for each reception antenna branch. That is, in the FFT unit 14 according to the second embodiment, processing can be performed in series with a single FFT circuit for all receiving antenna branches by increasing the operation clock. Therefore, the scale of the FFT circuit can be reduced. For example, when the number of receiving antenna branches is 2, processing is performed at twice the speed, and when the number of receiving antenna branches is 3, processing is performed at three times the speed, thereby reducing the size of the FFT circuit to 1 branch. Can be the same as

  The present invention has been described with reference to the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the technical idea thereof. In the above embodiment, in the delay correction unit 15-3, the buffer capacity in the memory units 29-1 to 29-4 is an amount for storing a symbol of 10 symbols, but is assumed in the hardware to be configured or in the actual environment. It is desirable to set the capacity appropriately in consideration of the amount of delay to be performed. As a result, the processing delay can be suppressed to the minimum necessary depending on the hardware or the actual environment.

  In the above embodiment, as shown in FIG. 1, the cable between the receiving point 3 and the demodulator 6 is the optical fiber 4, but other cables such as copper wires may be used.

DESCRIPTION OF SYMBOLS 1 Mobile relay vehicle 2 Transmission point 3 Reception point 4 Optical fiber 5 Switching center 6 Demodulator 7 E / O converter 8 O / E converter 10 A / D converter 11 Digital orthogonal demodulator 12 Symbol synchronization / AFC part 13 GI removal Unit 14 FFT unit 15 delay correction unit 16 complex weight calculation / multiplication / addition unit 21, 25, 28 write timing control unit 22, 26, 29 memory unit 23, 27, 30 read timing control unit 24 frame start timing detection unit

Claims (5)

In a demodulating device that performs macro diversity reception via a plurality of receiving antennas and cables arranged in a distributed manner, receives and demodulates received signals of each receiving antenna branch, and combines the demodulated signals,
A digital quadrature demodulator for digitally quadrature demodulating the received signal for each receive antenna branch;
A symbol synchronization unit that detects a symbol start timing from the digitally demodulated signal and generates a signal of the symbol start timing for each reception antenna branch;
An FFT unit that performs FFT (Fast Fourier Transform) on an effective symbol included in the digital quadrature demodulated signal, and generates a frequency domain signal for each reception antenna branch;
The FFT signal and the symbol start timing signal are input to each reception antenna branch, and the FFT signal is written to the first buffer based on the symbol start timing signal. A first delay correction unit that reads out and outputs a signal having the same timing from the first buffer;
The signal having the same symbol timing is input for each reception antenna branch, the input signal is written to the second buffer, and the signal having the same frame timing is read from the second buffer and output in each reception antenna branch. A second delay correction unit;
The signal having the same frame timing is input for each reception antenna branch, the input signal is written to a third buffer, and the signal of each reception antenna branch delayed in the third buffer is input to the third buffer. and a third delay correcting section that reads outputs from,
The second delay correction unit includes:
Frame start timing detection that inputs a signal having the same symbol timing for each reception antenna branch, detects a frame start timing based on the signal of the reception antenna branch, and generates a signal of the frame start timing for each reception antenna branch And
The signal of the symbol start timing in the signal having the same symbol timing is input as a signal of the reference branch symbol start timing, and the symbol of the signal having the same symbol timing is inputted for each signal of the reference branch symbol start timing. A second write timing control unit that outputs a write control signal for writing to the buffer for each reception antenna branch;
The reference branch symbol start timing signal is input, and for each reference branch symbol start timing signal, a read control signal for reading a symbol from the second buffer is output for each reception antenna branch. A start timing signal is output, and further, the frame start timing signal is input to each receiving antenna branch, the most preceding frame start timing is detected in all the receiving antenna branches, and the frame start timing is set as the start end. A frame start timing pulse observation window having a length of one frame is set, a reception antenna branch having the latest frame start timing is detected as a reference branch within the frame start timing pulse observation window, and a frame start timing of the reference branch is detected. Te, a second read timing control unit which outputs the read control signal for reading the symbols written in the second buffer from the first frame in each receiving antenna branch,
The signal having the same symbol timing and the write control signal are input for each reception antenna branch, and based on the write control signal, the symbol of the signal having the same symbol timing is written to the second buffer, and the read control is performed. A second memory for inputting a signal for each reception antenna branch and reading a symbol written in the second buffer for each reception antenna branch based on the read control signal;
The third delay correction unit includes:
A signal of the reference branch symbol start timing is input, and a write control signal for writing a symbol of the signal having the same frame timing is written to the third buffer for each reception antenna branch for each signal of the reference branch symbol start timing. A third write timing control section for outputting to
Read control for inputting a signal of the reference branch symbol start timing and reading out a symbol at a position delayed by a predetermined amount from the position of the symbol written in the third buffer for each signal of the reference branch symbol start timing A signal is output for each receiving antenna branch, a new reference branch is detected by the second delay correction unit, and the frame start timing of the reference branch is delayed from the frame start timing of the previous reference branch, When the symbols of the signals having the same timing are duplicated, a third control signal for outputting the readout control signal for preventing the duplicated symbols from being read from the third buffer according to the number of the duplicated symbols. A read timing control unit;
The frame timing matched signal and the write control signal are input for each receiving antenna branch, and based on the write control signal, the symbol of the frame timing matched signal is written to the third buffer, and the read control is performed. And a third memory for inputting a signal for each reception antenna branch and reading a symbol written in the third buffer for each reception antenna branch based on the read control signal. apparatus. The demodulator according to claim 1, wherein
The second delay correction unit includes a new second read timing control unit instead of the second read timing control unit,
In addition to the second read timing control unit, the new second read timing control unit further holds the detected reference branch and the frame start timing of the reference branch, and receives the signal of the frame start timing. Input for each antenna branch, detect the most preceding frame start timing among all the receiving antenna branches, set a frame start timing pulse observation window of one frame length starting from the frame start timing, and set the frame start timing Outputting the read control signal for reading the symbol written in the second buffer from the beginning of the frame for each reception antenna branch at the frame start timing of the held reference branch within the pulse observation window; A demodulator characterized by the above. The demodulator according to claim 1 or 2 ,
The first delay correction unit includes:
The signal for inputting the symbol start timing for each reception antenna branch, and writing for writing the samples to the first buffer for the samples constituting the symbol of the FFT signal for each signal of the symbol start timing A first write timing control unit that outputs a control signal for each reception antenna branch;
The symbol start timing signal is input for each reception antenna branch, and for each symbol start timing signal, a read control signal for reading a sample from the second buffer is output for each reception antenna branch. A symbol start timing pulse observation window having a length of 1 symbol is set at the time position, and a reception antenna branch with the most delayed symbol start timing is detected as a reference branch within the symbol start timing pulse observation window. At the symbol start timing, the readout control signal for reading out the sample written in the first buffer from the beginning of the symbol is output for each reception antenna branch, and the symbol start timing signal of the reference branch is used as a reference branch symbol. Start Taimin A first read timing controller for outputting a signal,
The FFT signal and the write control signal are input to each reception antenna branch, and based on the write control signal, the FFT signal sample is written to the first buffer, and the read control signal is received by the reception antenna. A demodulator comprising: a first memory that is input for each branch and reads the sample written in the first buffer for each reception antenna branch based on the read control signal . The demodulation device according to claim 3 , wherein
The first delay correction unit includes a new first read timing control unit instead of the first read timing control unit,
The new first read timing control unit reads the sample written in the first buffer from the beginning of a symbol at the timing of a reference pulse generated every OFDM symbol period length. For each reception antenna branch, and outputs a signal of the symbol start timing of the reference branch as a signal of the reference branch symbol start timing . In the demodulator according to any one of claims 1 to 4 ,
The digital quadrature demodulation unit, the symbol synchronization unit, the first delay correction unit provided at a subsequent stage of the symbol synchronization unit, the FFT unit, and the second at a subsequent stage of the FFT unit. A delay correction unit; and the third delay correction unit,
The first delay correction unit inputs a time-domain signal and the symbol start timing signal for each reception antenna branch, and based on the symbol start timing signal, converts the time-domain signal to the first buffer. And a signal having the same symbol timing in each receiving antenna branch is read out from the first buffer and output .

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