JP5338404B2 - Reordering processing method in switch device - Google Patents

Description

  The present invention relates to a reordering processing method in a switching device.

  If there is a switch path from the input unit to the output unit and the switch path has a different delay due to the presence of a buffer in the switch path, the cell order output from the input unit may be reversed and reach the output unit. In order to restore this to the original cell order, a reordering process is performed.

  Although it is not a switching device, as a method of transmitting a series of data to multiple paths between a transmitting terminal and a receiving terminal and correcting the order when the receiving terminal is reversed in order (hereinafter referred to as Reordering processing) There was something like the following.

  For example, in Patent Document 1, as a communication method for branching data of one communication flow used in communication between a transmission terminal and a reception terminal into a plurality of flows and restoring the original flow, the first LAN to which the transmission terminal belongs (Local Area Network) and a second LAN to which the receiving terminal belongs, respectively, gateways are installed, and TCP (Transmission Control Protocol) connection data sent from the transmitting terminal is transmitted in packet units in the first LAN gateway. The second LAN gateway performs a reordering process for reversing the order of packets received from a plurality of communication paths in accordance with the TCP sequence number.

  In this method, packets with a series of sequence numbers are distributed over multiple flows (or switch paths in terms of switch devices), and reordering processing of packets received from multiple paths is performed based on the series of sequence numbers. For this reason, if a packet drop occurs before arriving at the receiving apparatus, there is a drawback that the packet dropped in the reordering process waits for arrival and processing delay increases or the process itself stops.

  In Patent Document 2, a series of data is transmitted to a plurality of paths between a transmitting terminal and a receiving terminal, and the order is corrected using a sequence number (Reordering processing), thereby efficiently connecting a plurality of communication lines. As a method of using and improving the line utilization rate, a function is added to the TCP of the terminal, and the communication that conventionally used one TCP connection is changed to use a plurality of TCP connections.

  In this method, communication performed in one communication flow in communication between the transmission terminal and the reception terminal is divided into a plurality of communication flows and sent in parallel. That is, when data is transmitted from the transmission terminal to the reception terminal, the communication protocol of the transmission terminal divides the data of one communication flow and distributes the data to a plurality of communication flows, A new header is added to the TCP / IP (Transmission Control Protocol / Internet Protocol) packet as restoration information to restore the communication flow (that is, using two system sequence numbers), and data is transmitted in multiple communication flows. To do. The communication protocol of the receiving terminal refers to the restoration information of data received from a plurality of communication flows, and restores one communication flow.

  As described above, if two sequence numbers are used, packet drop monitoring can be performed for each flow. However, the method described in Patent Document 2 is similar to the method described in Patent Document 1, and packet drop before arrival at the receiving apparatus. When this occurs, there is a disadvantage that the packet dropped due to the reordering process waits for arrival and the processing delay increases or the process itself stops.

JP 2002-261478 A JP 2003-110604 A JP 2008-017387 A

Isaac Keslassy, "The Load-Balanced Router," Ph.D. Dissertation, Stanford University, June 2004

  As a method of transmitting a series of data to a plurality of paths between the transmitting terminal and the receiving terminal and correcting the order (Reordering processing) when there is an order reversal at the receiving terminal, a series of sequences is sent to the data to be transmitted. A switching device used as a network core router, etc., for assigning a number and performing a reordering process to restore the cell order based on the sequence number at the data reception point (corresponding to the output unit in the case of a switching device) When a cell drop occurs due to a bit error or the like in a switch path, for example, there is a problem that the dropped cell waits and processing stops.

  An object of the present invention is to provide a reordering processing method that does not increase processing delay or stop processing even when a cell drop occurs in a switch device in which a plurality of switch paths exist in the device. It is in.

  The reordering processing method in the switching device according to the present invention includes L (L is an integer greater than or equal to 2) input units, N (N is an integer greater than or equal to 2) output units, and one input unit from the one input unit. A reordering processing method in a switching device having K (K is an integer of 2 or more) switch paths for an output unit and a switch unit having an intermediate buffer unit provided for each switch path, Cell transmission for adding the time (cell time) of sending each cell to the invalid cell inserted and sent when there is no valid cell and valid cell sent from each input unit to each switch path A time information adding step; storing the valid cell sent from each input unit and the latest invalid cell in the intermediate buffer unit, and sequentially specifying the stored valid cell for each destination Time Is read out from the valid cell to which is added, and when there is no valid cell at the destination, the intermediate buffer processing step of reading out and transmitting the latest stored invalid cell, and the received from each intermediate buffer unit A reordering processing step for restoring the order of the valid cells based on the cell time added to the valid cell and the cell time added to the latest invalid cell and outputting from the output unit. And

  The switch device according to the present invention includes L (L is an integer of 2 or more) input units, N (N is an integer of 2 or more) output units, and one input unit to one output unit. And a switch unit having an intermediate stage buffer unit provided for each of the switch paths, wherein each switch path is connected to each input unit. Cell sending time information adding means for adding the time (cell time) of sending each cell to the valid cell and invalid cell inserted and sent when there is no valid cell, The valid cell sent from each input unit and the latest invalid cell are stored in the intermediate buffer unit, and each cell is sequentially designated for each destination, read out from the valid cell with the old cell time added, and sent. Valid destination When there is no data, an intermediate stage buffer processing means for reading out and sending out the latest invalid cell is provided, and in each output unit, the cell time added to the received valid cell and the latest invalid cell are added. Reordering processing means is provided for returning the order of the effective cells based on the existing cell time.

  According to the present invention, even when a cell is dropped due to a bit error or the like on the path from the input unit to the output unit, it is possible to perform the reordering process in which cells are transmitted in the order of oldest transmission time without stopping the process.

It is a block diagram which shows an example of the switch apparatus with which this invention is applied. FIG. 2 is an explanatory diagram of a switch path in the switch device shown in FIG. 1. It is a block diagram which shows embodiment of the input part to which the Reordering processing method of this invention is applied. It is a block diagram which shows embodiment of each intermediate | middle stage Buffer to which the Reordering processing method of this invention is applied. It is a block diagram which shows embodiment of each output part to which the Reordering processing method of this invention is applied. It is a figure for demonstrating the cell storing operation | movement of the intermediate | middle stage Buffer part in the switch apparatus of this invention. It is a figure for demonstrating the cell transmission operation | movement of the intermediate | middle stage Buffer part in the switch apparatus of this invention. It is a figure for demonstrating the cell transmission operation | movement of the output part in the switch apparatus of this invention.

  FIG. 1 is a block diagram showing an example of a switch configuration to which the present invention is applied. FIG. 1 shows a configuration example of a load balance type switch including L input units, k intermediate stage buffers, and N output units. is there. The operation of the load balance type switch is described in, for example, Patent Document 3 or Non-Patent Document 1.

  In this example, the cross section (XBAR) switch is connected between the input section and the intermediate stage buffer, and between the intermediate stage buffer and the output section, but the front stage XBAR Switch (1-2) and the rear stage XBAR Switch It is also possible to replace (1-4) with a form in which mesh connection is physically made using an optical cable or the like.

  The input units (1-1-1) to (1-1-L) are each connected to the input port of the previous stage XBAR Switch (1-2), and the output port of the previous stage XBAR Switch (1-2) is It is connected to the intermediate buffer (1-3-1) to (1-3-k). That is, the cells output from the input units (1-1-1) to (1-1-L) are transferred to the intermediate buffer (1-3-1) to (1) via the previous XBAR Switch (1-2). -3-k).

  Intermediate stage Buffer (1-3-1) to (1-3-k) receives from input section (1-1-1) to (1-1-L) via previous stage XBAR Switch (1-2) A built-in VOQ (Virtual Output Queue) is stored in the output unit as a destination. The output of the intermediate buffer (1-3-1) to (1-3-k) is connected to the input port of the post-stage XBAR Switch (1-4), and the output port of the post-stage XBAR Switch (1-4) Are connected to the output sections (1-5-1) to (1-5-N).

  In other words, the cells output from the intermediate buffer (1-3-1) to (1-3-k) are output from the output units (1-5-1) to (1) via the post-stage XBAR Switch (1-4). -5-N). Output units (1-5-1) to (1-5-N) receive cells from the latter stage XBAR Switch (1-4), and input units (1-1-1) to (1-1-L) When the cell order is confirmed, and the cell order is reversed, the process of making the cell order correct is performed.

  In the load balance type switch shown in FIG. 1, when a cell is sent from a certain input unit to a certain output unit, it is routed through any one of the intermediate buffers (1-3-1) to (1-3-k). Become. For this reason, as shown in FIG. 2, when a cell is output from the input unit 1 to the output unit 1, for example, k switch paths exist.

  In this case, the cell order does not change within the same switch path, but since the buffer (intermediate buffer) exists in the switch path, the intermediate buffer (1-3-1) to (1-3- k) The arrival time from the input unit to the output unit may be different for each switch path due to the difference in the cell accumulation state between them. When cells are sent using different switch paths, the cell order is reversed in the output unit May arrive. For this reason, a reordering process for returning the cell order to the original in the output unit is required.

  FIG. 3 is a block diagram showing an embodiment of an input unit to which the Reordering processing method of the present invention is applied (when the input unit has a four-block configuration from (4-1-1) to (4-1-4)). It is. In the input unit of this embodiment, the transmitted time information is added to the cell transmitted to each switch path.

  The input units (4-1-1) to (4-1-4) incorporate time information adding units (4-2-1) to (4-2-4), respectively. The time information adding units (4-2-1) to (4-2-4) add the cell time information received from the time information generating unit (4-4) to the received cell to add the preceding XBAR Switch (4 Output to -3). There are two types of cells that are input to the time information addition units (4-2-1) to (4-2-4): valid cells with valid data and invalid cells that are inserted when there is no valid cell. .

  The time information generation unit (4-4) has a built-in counter that counts up every time it takes to transmit one cell, and the cell time (count value) is input to the input units (4-1-1) to (4 -1-4) to the time information adding section (4-2-1) to (4-2-4).

  FIG. 4 is a block diagram showing an embodiment of each intermediate-stage buffer to which the reordering processing method of the present invention is applied (when the output unit has a 4-block configuration). In the intermediate buffer of this embodiment, received cells are managed by VOQ (Virtual Output Queue), and when there is no valid output cell in the destination queue, the latest invalid cell held internally is transmitted.

  For this reason, the intermediate buffer (5-1) includes a valid / invalid determination unit (5-2), a register (5-3), a VOQ (5-4), and a selection unit (5-5). The valid / invalid determination unit (5-2) divides the received cells into valid cells and invalid cells, and sends valid cells to the VOQ (5-4) and invalid cells to the register (5-3). The register (5-3) is a block for holding the received invalid cell and is overwritten every time an invalid cell is received, and always holds only the latest one cell information.

  The VOQ (5-4) is a memory having a VOQ (Virtual Output Queue) configuration in which a Queue is provided for each destination, and stores received valid cells for each destination. The selection unit (5-5) sequentially reads out the valid cells stored in each queue of the VOQ (5-4) or the invalid cells stored in the register (5-3) for each destination, and proceeds to the subsequent stage XBAR Switch. Output.

  FIG. 5 is a block diagram showing an embodiment of each output unit to which the Reordering processing method of the present invention is applied (when the intermediate stage buffer has a 4-block configuration). In the output unit of the present embodiment, a reordering process for restoring the order of valid cells to be output based on the cell time added to the received valid cell and the cell time added to the latest invalid cell received. Is done.

  The output unit (6-1) includes a reordering processing unit (6-5). The reordering processing unit (6-5) is composed of a write control unit (6-2), a MEM unit (6-3), and a read control unit (6-4). The MEM unit (6-3) is input. This is a memory composed of multiple queues so that valid cells are stored for each intermediate buffer through which the cells pass.

  The input effective cell is written from the write control unit (6-2) to the MEM unit (6-3) for each intermediate stage Buffer that has passed through. When an invalid cell is input, information on the invalid cell (the time of the installed cell, the intermediate buffer through which it passes) is sent to the read control unit (6-4). The read control unit (6-4) includes information on invalid cells received from the write control unit (6-2) and cell time information on valid cells stored at the head of each queue in the MEM unit (6-3). In consideration of the above, the effective cell read control from the MEM section (6-3) is performed.

  Next, the operation of this embodiment will be described.

  Each input unit in FIG. 3 is changed from the input units (1-1-1) to (1-1-L) in FIG. 1 to the input units (4-1-1) to (4-1-4). An example in the case of a block configuration is shown. The time information generator (4-4) has a built-in counter that counts up every cell time (time required to transmit one cell), and the cell time (count value) is input to the input unit (4-1-1 ) To (4-1-4) to send to the time information adding unit (4-2-1) to (4-2-4).

  The time information adding units (4-2-1) to (4-2-4) provided in the input units (4-1-1) to (4-1-4) The cell time information received from -4) is added to the received cell and output to the preceding XBAR Switch (4-3). There are two types of cells that are input to the time information addition units (4-2-1) to (4-2-4): valid cells with valid data and invalid cells that are inserted when there is no valid cell. However, the time information adding units (4-2-1) to (4-2-4) add the cell time information to both the valid cell and the invalid cell to add the preceding XBAR Switch (4 Output to -3).

  The intermediate stage buffer (5-1) in FIG. 4 corresponds to the intermediate stage buffers (1-3-1) to (1-3-k) in FIG. 1, and has four output units in FIG. An example is shown. The valid / invalid determination unit (5-2) divides the received cells into valid cells and invalid cells, and sends valid cells to the VOQ (5-4) and invalid cells to the register (5-3). The register (5-3) is a block that holds the received invalid cell, and is overwritten every time an invalid cell is received, and always holds only the latest one cell information.

  The VOQ (5-4) is a memory having a VOQ (Virtual Output Queue) configuration in which a Queue is provided for each destination, and is stored for each destination of the received valid cell. The selection unit (5-5) reads out and sends out valid cells one by one from each queue of the VOQ, but when no valid cells are stored in the queue, it is stored in the register (5-3). Read out invalid cells and send them.

  FIG. 6 shows the operation from cell input to storage in the register (5-3) or VOQ (5-4) in the intermediate stage Buffer (5-1) in FIG. 4 in order of cell time. The cell storage operation in the intermediate buffer will be described below in the order of cell input time. In the following description, the time information adding units (4-2-1) to (4-2-4) in the input units (4-1-1) to (4-1-4) in FIG. The added time information is indicated by a number surrounded by “”.

■ Cell time T1
Cell “1” for output unit 1 is received, cell “1” is stored in the queue that stores the cell for output unit 1 of VOQ (5-4),
■ Cell time T2
Invalid cell “2” received, invalid cell “2” written to register (5-3),

■ Cell time T3
Receive cell “3” destined for output unit 2, store cell “3” in Queue that stores cells destined for output unit 2 of VOQ (5-4),
■ Cell time T4
Cell “4” for output unit 3 received, cell “4” stored in Queue storing cell for output unit 3 of VOQ (5-4),

■ Cell time T5
Receive cell “5” destined for output unit 4, store cell “5” in Queue storing cell destined for output unit 4 of VOQ (5-4),
■ Cell time T6
Receive cell “6” destined for output unit 1, store cell “6” in Queue storing cell destined for output unit 1 of VOQ (5-4),

■ Cell time T7
Receive invalid cell “7”, write invalid cell “7” to register (5-3) (overwrites the content written at cell time T2),
■ Cell time T8
The cell “8” for the output unit 4 is received, and the cell “8” is stored in the queue storing the cell for the output unit 4 of the VOQ (5-4).

  FIG. 7 shows the process of reading cells from the register (5-3) or VOQ (5-4) in the intermediate buffer (5-1) in FIG. 4 in the order of cell time. The cell sending operation in the intermediate buffer will be described below in the order of cell sending time.

  Note that the cell transmission times T1 to T8 shown in FIG. 7 and the cell input times T1 to T8 shown in FIG. 6 are irrelevant and do not indicate that they coincide in time. Originally, the invalid cell information stored in the register (5-3) is overwritten every time an invalid cell is received. In this example, however, for the sake of simplicity, the invalid cell information always contains cell time 7 information. The case where the cell “7” is stored is shown.

■ Cell time T1
Read and send cell “1” for output unit 1 from VOQ (5-4),
■ Cell time T2
Read and send cell “3” for output unit 2 from VOQ (5-4),

■ Cell time T3
Read and send cell “4” for output unit 3 from VOQ (5-4),
■ Cell time T4
Read and send cell “5” destined for output unit 4 from VOQ (5-4).

■ Cell time T5
Read cell “6” destined for output unit 1 from VOQ (5-4) and send it out.
■ Cell time T6
Since the cell for the output unit 2 is not stored in the VOQ (5-4), the invalid cell “7” is read from the register (5-3) and sent out.

■ Cell time T7
Since the cell for output unit 3 is not stored in VOQ (5-4), invalid cell “7” is read from register (5-3) and sent out.
■ Cell time T8
Read and send cell “8” for output unit 4 from VOQ (5-4).

  The output unit (6-1) in FIG. 5 corresponds to the output units (1-5-1) to (1-5-k) in FIG. 1, and includes four intermediate stage buffers in FIG. An example is shown. The input effective cell is written from the write control unit (6-2) to the MEM unit (6-3) for each intermediate stage Buffer that has passed through. When an invalid cell is input, the information of the invalid cell (the time of the installed cell and the intermediate buffer passed through) is sent to the read control unit (6-4). Based on the invalid cell information received from the write control unit (6-2), the read control unit (6-4) obtains the latest invalid cell time information (latest invalid cell information) for each intermediate stage buffer passed through. keeping.

  Also, the read control unit (6-4) refers to the cell time information of the valid cell stored at the head of each Queue of the MEM unit (6-3), and selects the cell to which the oldest time information is added. Read out. If there is a queue in which no valid cell is stored among the queues of the MEM section (6-3), it is compared with the latest invalid cell information via the intermediate buffer associated with the queue.

  FIG. 8 shows a process of reading cells from the MEM unit (6-3) in the output unit of FIG. 5 in order of cell time. Hereinafter, an operation of reading a cell from the MEM unit (6-3) will be described in the order of cell transmission time.

  Note that the latest invalid cell information in FIG. 8 is provided in the read control unit (6-4) in FIG. 5, and the cell time information (latest cell time of the latest invalid cell held for each intermediate-stage buffer that has passed through. It is overwritten by the latest invalid cell entered for each intermediate buffer. Further, in this example, since the latest invalid cell information is simple, the latest invalid cell time information from the intermediate stages Buffer1 to Buffer4 is shown as a case where all the cell time 13 remains unchanged during the read operation.

■ Cell time T1
Compare the cell time of the first cell of each Queue that constitutes the MEM part (6-3), and read the cell “1” via the intermediate buffer 1 that has the oldest time information (cell time 1).
■ Cell time T2
Compare the cell time of the first cell of each Queue that constitutes the MEM part (6-3), and read the cell “2” via the intermediate buffer 1 that has the oldest time information (cell time 2).

■ Cell time T3
Compare the cell time of the first cell of each Queue that constitutes the MEM part (6-3), and read the cell “4” via the intermediate buffer 1 having the oldest time information (cell time 4).
■ Cell time T4
Compare the cell time of the first cell of each Queue constituting the MEM part (6-3), and read the cell “5” via the intermediate buffer 2 having the oldest time information (cell time 5).

■ Cell time T5
Compare the cell time of the first cell of each Queue constituting the MEM part (6-3), and read the cell “6” via the intermediate buffer 2 having the oldest time information (cell time 6).
■ Cell time T6
The cell time of the first cell of each Queue constituting the MEM section (6-3) is compared, and the cell “7” via the intermediate buffer 1 having the oldest time information (cell time 7) is read.

■ Cell time T7
Comparing the cell time of the first cell of each Queue that composes the MEM part (6-3), the Queue storing the cell via the intermediate buffer 1 is empty at this time, so the latest invalidity of the cell via the intermediate buffer 1 Cell information (cell time 13) is used as a comparison cell. As a result of comparison, the cell “8” via the intermediate buffer 2 having the oldest time information (cell time 8) is read.

  If the latest invalid cell time information of the cell via the intermediate buffer 1 is older than the valid cell time information stored via other intermediate buffers (for example, the cells via the intermediate buffers 2 to 4 are stored. If any of the first cells of the queue is a valid cell with a cell time newer than the latest invalid cell information (cell time 13) of the cell via the intermediate buffer 1, reading from the output unit is not performed. This is because there is a possibility that a valid cell arrives later than the invalid cell time information via the intermediate buffer 1 but later than the valid cell time information stored via another intermediate buffer. If the comparative reading is performed except for the cell information via the intermediate buffer 1 in which the queue is empty, the reading order may be reversed.

  Therefore, when the queue becomes empty, the latest invalid cell information via the intermediate buffer corresponding to the queue is used as a comparison cell, and a valid cell time is added that is older than the invalid cell time. By reading the effective cell to which the oldest cell time is added, the reading order is prevented from being reversed.

■ Cell time T8
Comparing the cell time of the first cell of each Queue composing the MEM part (6-3), since the Queue storing the cell via the intermediate buffer 1 and 2 is empty at this time, it passes through the intermediate buffer 1 and 2 The latest invalid cell information (cell time 13) of the cell is used as a comparison cell. As a result of comparison, the cell “9” via the intermediate buffer 3 having the oldest time information (cell time 9) is read out.

■ Cell time T9
Comparing the cell time of the first cell of each Queue composing the MEM part (6-3), the Queue that stores the cells via the intermediate buffer 1 and 2 is empty at this time. The latest invalid cell information (cell time 13) is used. As a result of comparison, the cell “10” via the intermediate buffer 3 having the oldest time information (cell time 10) is read.

■ Cell time T10
Comparing the cell time of the first cell of each Queue that constitutes the MEM part (6-3), since the Queue storing the cells via the intermediate stage Buffers 1, 2, 3 is empty at this time, the intermediate stage Buffers 1, 2, 3 The latest invalid cell information (cell time 13) of the routed cell is used as a comparison cell. As a result of comparison, cell “12” via intermediate buffer 4 having the oldest time information (cell time 12) is read.

  As a result of the above operation, the cell order output from the MEM unit (6-3) of the output unit 1 is the oldest time information (1, 2, 4, 5, 6, 7, 8) added in the input unit. , 9,10,12) and output. In this case, a valid cell was not output at cell times “3” and “11” (an invalid cell was output), and the arrival of a cell with cell time “3” or “11” added Without waiting, the cells stored in the MEM section (6-3) are read and output in the order of their time information.

  In FIG. 5, at time “10”, the cell “10” destined for the output unit 1 is sent from the input unit 1 to the intermediate buffer 3 and the cell “10” destined for the output unit 1 is sent from the input unit 2 to the intermediate buffer 4. Is output, and two cells “10” with time “10” are input to the output unit 1, and the Queue storing the cells via the intermediate buffer 3 of the MEM (6-3) and the intermediate buffer 4 are stored. The case where each is stored in a Queue storing cells is shown.

  In this case, the cell order output from the MEM unit (6-3) of the output unit 1 is the oldest order of time information (1,2,4,5,6,7,8,9, 10, 10, 12), but any cell having the same time information (in this case, time information “10”) can be read first without any problem. In the example shown in FIG. 5, the cell via the young intermediate stage Buffer 3 is output first.

  As described above, in the present embodiment, the cell order output from the output unit 1 is determined when the valid cells are stored in all the queues of the MEM (memory) unit that stores cells for each intermediate stage buffer that has passed through. The cell time comparison of valid cells stored at the head of each queue is performed at each cell transmission timing, and the cells are read in order from the valid cell to which the oldest cell time is added. Even if a cell is dropped due to a bit error, the reordering process can be executed without stopping.

  In addition, when a part of the queue of the MEM (memory) unit that stores the cells for each intermediate-stage buffer that is passed becomes empty when comparing cell times for cell transmission, the queue that has become empty The cell time of the latest invalid cell received from the intermediate buffer corresponding to is added to the cell time comparison target, and the oldest cell time is added among the valid cells to which the cell time older than the invalid cell time is added. Since the effective cell thus read is read, it is possible to prevent the cell reading order from being reversed.

  In that case, if the cell time of the latest invalid cell received from the intermediate buffer corresponding to the emptied Queue is older than the cell time of the first valid cell of the other Queue, reading from the output unit will be Although not performed, if valid cells are input from the intermediate buffer corresponding to the empty Queue and stored in the Queue, and valid cells are stored in all Queues, then at the beginning of each Queue Since it is possible to return to the cell transmission operation based on the cell time comparison of the stored valid cells, this does not stop the reordering process.

  For example, when the cell transmission order is assigned to each cell output and the sequence number is used and managed by the sequence number, if the cell with sequence number 3 is discarded for some reason such as a bit error or buffer overflow in the device, The output unit continues to wait for the cell with the sequence number 3, and the cell with the sequence number 4 is not output from the output unit, that is, the reordering process is stopped. In this embodiment, the reordering is performed. Since the processing is managed based on the cell transmission time and the latest invalid cell information, it is possible to avoid a state in which the Reordering processing cannot be performed due to cell dropping, and to prevent the cell reading order from being reversed.

  As described above, in the present invention, the time information added to the cell is sent with the time information added to the invalid cell when there is no valid cell. It is possible to recognize which time cell has reached each time. That is, the Reordering processing unit refers to the cell time of the first valid cell in the Queue that constitutes the MEM (memory) that accumulates valid cells for each intermediate-stage buffer that has passed through, so that the time of each intermediate-stage buffer It can be seen that up to the cell is sent to the output unit.

  Further, when the queue becomes empty, the reading order is prevented from being reversed by referring to the time information of the latest invalid cell received via the intermediate buffer corresponding to the queue. In that case, if the cell time of the latest invalid cell received from the intermediate buffer corresponding to the emptied Queue is older than the cell time of the first valid cell of the other Queue, reading from the output section is not performed. However, when a valid cell is stored in the empty queue, the cell transmission operation is returned to the cell time comparison of the valid cells stored at the head of each queue.

  Furthermore, invalid cell information stored in the intermediate buffer is overwritten each time a new invalid cell is sent from the input unit, and the time information of the invalid cell in the output unit stored in each intermediate buffer is also the latest invalid. Since the cell is overwritten every time the cell is input, reading of the effective cell stored in the MEM of the output unit is not stopped and the operation is not disabled.

  Therefore, the reordering process stops due to the occurrence of a cell drop due to a bit error or the like in the middle of the switch path, resulting in an inoperable state, as in the case where the cell transmission order from the input unit is transmitted with a sequence number. Absent.

  As described above, in the present invention, time information (cell time) is added to valid cells and invalid cells (empty cells) sent from the input unit as information used for cell order management between the input unit and the output unit, and the output unit Since the reordering process is performed based on the valid cell time information and the latest invalid cell information, the process stops even if a cell drops due to a bit error in the path from the input unit to the output unit. Reordering processing in which cells are transmitted in ascending order of transmission time can be performed without doing so.

1-1-1 to 1-1-L, 4-1-1 to 4-1-4 Input section
1-2, 4-3 Front XBAR Switch
1-3-1 to 1-3-k, 5-1 Intermediate buffer
1-4 Rear XBAR Switch
1-5-1 to 1-5-N, 6-1 Output section
4-2-1 to 4-2-4 Time information addition part
4-4 Time information generator
5-2 Valid / invalid judgment part
5-3 Register
5-4 VOQ (Virtual Output Queue)
5-5 Selection section
6-2 Write controller
6-3 MEM (memory) section
6-4 Read controller
6-5 Reordering process

Claims (9)

L (L is an integer of 2 or more) input units, N (N is an integer of 2 or more) output units, and K (K is 2 or more) from one input unit to one output unit A reordering processing method in a switching device having a plurality of switch paths and a switch section having an intermediate buffer section provided for each switch path,
A cell transmission time for adding each cell transmission time (cell time) to a valid cell transmitted from the input unit to each switch path and an invalid cell inserted and transmitted when there is no valid cell. Information addition step,
The valid cell sent from each input unit and the latest invalid cell are stored in the intermediate buffer unit, and the stored valid cell is sequentially specified for each destination, and an old cell time is added. An intermediate buffer processing step for reading out and sending out the cell and reading out and sending out the latest invalid cell stored when there is no valid cell at the destination,
Based on the cell time added to the valid cell received from each intermediate stage buffer unit and the cell time added to the latest invalid cell, the order of the valid cells is restored and output from the output unit. Reordering processing step,
A reordering processing method in a switch device, comprising:   The cell transmission time information adding step includes a step of counting a cell time every time one cell is transmitted, and a step of sequentially adding the counted cell time to the transmitted valid cell and invalid cell. A reordering processing method in the switch device according to claim 1.   The intermediate buffer processing step receives / overwrites the invalid cell divided in the valid / invalid determination step for valid / invalid determination that separates the valid cell and invalid cell sent from each input unit. Thus, the step of always holding only one latest invalid cell, the step of receiving the valid cell divided in the valid / invalid determination step and storing it in the queue for each destination, sequentially specifying the queue for each destination A step of reading out and outputting a valid cell stored at the beginning thereof, and a step of reading out and outputting the invalid cell being held when the valid cell is not stored in the designated queue. A reordering processing method in the switch device according to claim 1.   The reordering processing step stores the input valid cell in a MEM (memory) unit composed of K Queues for storing each intermediate buffer through which the cell has passed, and the invalidity input A step of overwriting and storing the cell time of each cell for each intermediate stage buffer through which the invalid cell has passed, and sending the cell time comparison of valid cells stored at the head of each queue of the MEM (memory) unit A step of reading in order from the valid cell with the oldest cell time added at each timing, and when a queue without valid cells occurs, the cell time of the invalid cell stored corresponding to the queue is added to the comparison target The cell time comparison, and reading out the valid cell to which the oldest cell time is added among the valid cells to which the cell time older than the cell time of the invalid cell is added. Step of outputting the read enable cell, Reordering processing method in the switch device according to any one of claims 1 to 3, characterized in that it consists of and. L (L is an integer of 2 or more) input units, N (N is an integer of 2 or more) output units, and K (K is 2 or more) from one input unit to one output unit A switch device having a switch unit having an intermediate stage Buffer unit provided for each of the switch paths,
A cell in which the time (cell time) for sending each cell is added to each input unit with respect to an invalid cell inserted and sent when there is no valid cell and valid cell sent to each switch path. Provide sending time information adding means,
The valid cells sent from the input units and the latest invalid cells are stored in the intermediate buffer units, read out from the valid cells to which the old cell time is added, specified sequentially for each destination, and sent out. In addition, when there is no valid cell of the destination, provided an intermediate buffer processing means for reading out and sending out the latest invalid cell,
Reordering processing means for returning the output order of the valid cells based on the cell time added to the received valid cell and the cell time added to the latest invalid cell to each output unit and outputting A switch device provided.   The cell transmission time information adding means outputs a cell time (count value) counted by a counter that counts up the cell time every time one cell is transmitted, and a cell time received from the time information generation unit 6. The switch device according to claim 5, further comprising a time information adding unit that sequentially adds and transmits information to the valid cell and invalid cell input to the input unit.   The intermediate buffer processing means includes a valid / invalid determination unit that separates the input valid cell and the invalid cell, and receives and overwrites the invalid cell divided by the valid / invalid determination unit to update the latest cell. A register that holds only one invalid cell, a VOQ (Virtual Output Queue) that deploys a queue for each destination, receives a valid cell divided by the valid / invalid determination unit, and stores it in the queue for each destination , Sequentially specifying each queue of the VOQ and reading the valid cell stored at the head thereof, and reading the invalid cell stored in the register when the valid cell is not stored in the designated queue The switch device according to claim 5, further comprising: a selection unit that transmits valid cells or invalid cells.   The reordering processing means includes a function of sending the valid cell to a MEM (memory) unit when the valid cell is input, and a cell time added to the invalid cell when the invalid cell is input. A write control unit having a function of sending information of the intermediate stage buffer passed through the invalid cell to a read control unit, and the valid cell input from the write control unit for each intermediate stage buffer passed through the cell The MEM (memory) unit configured with K Queues to be stored and the cell time of the invalid cell input from the write control unit are overwritten and stored for each intermediate stage Buffer through which the invalid cell has passed. The cell time comparison of the effective cells stored at the head of each queue of the MEM (memory) unit is performed at each cell transmission timing, and the effective cells with the oldest cell time added are read in order. Function, when a queue without valid cells occurs, the cell time of the invalid cell stored corresponding to the queue is added to the comparison object, the cell time is compared, and a cell older than the cell time of the invalid cell The read control unit having a function of reading a valid cell to which the oldest cell time is added among valid cells to which time has been added, and a function of outputting the read valid cell. The switch device according to any one of claims 5 to 7. 9. The switch device according to claim 5, wherein the switch device is a load balance type switch including L input units, K intermediate stage buffers, and N output units. Switch device.

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