JP5321344B2 - TRANSMISSION DEVICE, TRANSMISSION METHOD, RECEPTION DEVICE, AND RECEPTION METHOD - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accelerate a processing speed by reducing circuit scale required for bit interleave processing, compared to that of a conventional communication device, while maintaining communication characteristics equal to the prior arts. <P>SOLUTION: A small-sized bit interleaver 11a smaller than a conventional bit interleaver is used to divide bit streams into N sets and to implement bit interleave processing and subsequent primary modulation processing in a primary modulation unit 12a. Then, primary modulated symbols for the N sets obtained by primary modulation are collectively input to a tone interleave IFFT 14a to perform tone interleave and inverse Fourier transform thereon. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

The present invention relates to a transmission apparatus provided with interleaving means for rearranging bits constituting a bit sequence and a receiving apparatus provided with deinterleaving means.

In general, in wireless communication using error correction coding, it is necessary to disperse errors by separating consecutive bit sequences that have been error correction coded in order to avoid transmission errors due to a drop in transmission line gain or high level noise. (Hereinafter, the distance between consecutive error correction coded bits in a certain bit sequence may be referred to as a distance between coded bits or simply as a distance between bits).

In particular, in order to maintain communication quality in multicarrier transmission typified by Orthogonal Frequency Division Multiplexing (OFDM), it is important to avoid continuous errors due to frequency bands in which the channel gain has dropped. . In order to increase the distance between the encoded bits, it is known that it is effective to apply bit interleaving to the encoded bit sequence in the transmission apparatus. In the US wireless LAN (Local Area Network) standard, It is also adopted in certain IEEE802.11a (see Non-Patent Document 1) and the like.

FIG. 30 shows a general conventional OFDM baseband modulation / demodulation block diagram.
In the transmission device, the error correction encoding unit 10 performs error correction encoding on the input information data s10. At this time, when the transmission rate is improved, the coded bit thinning-out process (puncture process) is also performed. Next, the bit interleaver 11 rearranges the encoded bit sequence s11. The primary modulation unit 12 performs primary modulation, such as phase shift keying (Phase Shift Keying: PSK) and quadrature amplitude modulation (QAM), on the interleaved bit sequence s12, and maps bits to primary modulation symbols. To do.

The generated primary modulation symbol sequence s13 is parallelized by the serial-parallel conversion (S / P conversion) unit 13 to the subcarrier signal s14, and is subtracted by the Inverse Fast Fourier Transform (IFFT) unit 14. The carrier signal s14 is converted into a time signal s15. The converted parallel time signal s15 is serialized to the time signal sequence s16 by the parallel-serial conversion (P / S conversion) unit 15, and the GI is inserted at the head of each OFDM symbol by the guard interval (GI) insertion unit. Is inserted and the OFDM baseband signal s17 is output. The OFDM baseband signal s17 is transmitted to the receiving device.

The receiving device receives the OFDM baseband time signal transmitted from the transmitting device. The GI removal unit 20 removes the GI from the OFDM baseband time signal s20, and the S / P conversion unit 21 converts the serial signal s21 into a parallel time signal s22. A fast Fourier transform (FFT) unit 22 converts the time signal s22 into a subcarrier signal s23. The P / S converter 23 serializes the parallel subcarrier signals s23, and the primary demodulator 24 detects mapping bits of each primary modulation symbol. The detected bit sequence s25 is deinterleaved by the bit deinterleaver 25 and rearranged into the correct bit sequence s26. In the error correction decoding unit 26, error correction decoding is applied to the bit sequence s26 and decoded into information data s27.

FIG. 31 shows a general bit interleaver operation. In this example, for simplicity, an interleaver having 4 * 4 memory blocks is used. The coded bit sequence is written sequentially in the horizontal direction from the top row of the memory block that the bit interleaver has, and after all bits have been written, the bits are read sequentially from the leftmost column of the memory block in the vertical direction. Interleaver output. Thereby, the distance between coding bits can be separated. The receiving apparatus can restore a correct encoded bit sequence by performing this inverse operation (bit deinterleaving) on the detected bit sequence after demodulation.

On the other hand, as a measure for realizing error dispersion in multicarrier transmission, there is a tone interleaving technique for rearranging primary modulation symbols mapped to each subcarrier. By tone interleaving, it is possible to disperse transmission errors caused by a drop in transmission path quality in a specific frequency band (see FIG. 32).

Japanese Patent Application Laid-Open No. 2004-228561 describes an idea for realizing tone interleaving by using the circuit structure of the FFT unit and IFFT unit without adding a processing amount as compared with the conventional circuit. Patent Document 2 describes a means for realizing a tone interleaving circuit with a small processing delay and a small circuit scale by devising a method of inputting a baseband signal to the IFFT unit.

33 and 34 show circuits of the normal IFFT section 14 and the FFT section 22, respectively. Here, for simplicity, the number of points in the IFFT unit 14 and the FFT unit 22 is 16. Taking IFFT unit 14 as an example, subcarrier signals 0 to 15 (s14) after S / P conversion are converted into intermediate signal s140 by signal rearrangement called bit reverse order processing in the transmission apparatus. This bit reverse processing is rearrangement for the inverse Fourier transform processing. This intermediate signal s140 becomes an input signal for IFFT butterfly calculation processing. The intermediate signal s140 is converted into time signal sequences a to p (s15) by the IFFT butterfly calculation unit 142. In the FFT unit 22, reverse processing is performed, and FFT butterfly computation is applied to the time signals a to p (s 22) and converted to subcarrier signals 0 to 15 (s 23) by bit reverse processing. Note that the circuit configurations of the IFFT unit 14 and the FFT unit 22 are examples, and the means for realizing them is not limited to this.

35 and 36, an IFFT unit 14t having a tone interleaving function (hereinafter referred to as a tone interleaving IFFT unit) and an FFT unit 22t having a tone deinterleaving function (hereinafter referred to as a tone deinterleaving FFT unit). An example is shown. These refer to the realization means described in Patent Documents 1 and 2. Taking the tone interleave IFFT section 14t as an example, the subcarrier signals 0 to 15 (s14) are rearranged (tone interleave) different from the normal IFFT section 14 by the tone interleaver 14t1, and then the normal IFFT. The same IFFT butterfly computation as that of the unit 14 is applied. Thereby, time signals a ′ to p ′ different from normal IFFT output signals a to p are generated by the tone interleave IFFT unit 14t.

In the tone deinterleave FFT unit 22t, processing in the reverse order as described above is performed, and FFT butterfly computation is applied to the time signals a ′ to p ′, and then the tone interleaver 22t2 performs inverse transformation of the above tone interleave (tone) Deinterleaving) is performed. Thereby, as shown in FIG. 32, the error which arises in a specific subcarrier can be disperse | distributed. The circuit configuration of the tone interleave IFFT unit 14t and the tone deinterleave FFT unit 22t is an example, and means for realizing them is not limited to this.

Japanese Patent Laid-Open No. 10-75227 JP-A-11-298436

IEEE Std. 802.11a, 1999 K. Kambara, et al., Subblock Processing in MMSE-FDE Under Fast Fading Environments, IEEE J. Select. Areas Commun., Vol. 26, No. 2, pp. 359-365, Feb. 2008.

However, the conventional techniques described above and the techniques described in Patent Documents 1 and 2 have the following problems.

When bit interleaving is performed, it is necessary to sufficiently separate the distance between bits in order to achieve good communication characteristics. In order to realize this, a bit interleaver having a large memory length has been conventionally required. In particular, when multi-level modulation such as QAM is applied in primary modulation, a larger memory length is required (see Non-Patent Document 1). As the memory lengths of the interleaver 11 and the deinterleaver 25 are increased, the circuit scale increases, making it difficult to reduce the size of the circuit, increasing the cost, and increasing the power consumption.

Further, the interleaver 11 and the deinterleaver 25 cannot perform subsequent reading unless all data is written in the memory block. Therefore, the larger the memory length, the longer the processing takes, and the processing delays in the transmission device and the reception device There was a problem of inviting.

On the other hand, Patent Documents 1 and 2 describe only means for easily realizing the tone interleaver 11 and the tone deinterleaver 25. By using these to devise signal processing, a circuit for a conventional communication apparatus is described. It was not mentioned that the scale could be reduced and that the processing speed could be improved.

The present invention has been made to solve the above-described problems, and a first object thereof is to perform bit interleaving processing or bit deinterleaving processing as compared with the conventional communication device while maintaining the same communication characteristics as the conventional one. The purpose is to reduce the circuit scale and improve the processing speed.

The transmission apparatus according to the present invention includes an interleaving unit that rearranges a bit sequence of input information data, and a primary modulation unit that obtains a corresponding primary modulation symbol sequence by performing primary modulation on the bit sequence rearranged by the interleaving unit, In a transmission apparatus having a conversion unit that performs inverse Fourier transform on a predetermined number of primary modulation symbols obtained by the primary modulation unit, and a transmission unit that transmits a signal obtained by the conversion unit.
The interleaving means has a size of a bit sequence that can be rearranged at a time smaller than the number of bits corresponding to the predetermined number of primary modulation symbols, and at least a first bit sequence of the input information data according to the size. Separating the bit sequence of the set and the second set, rearranging the bits constituting the first set of bit sequences, rearranging the bits constituting the second set of bit sequences,
The primary modulation means performs primary modulation processing of the rearranged first bit sequence in parallel with rearrangement processing of the second set of bit sequences in the interleaving means, and performs primary modulation processing of the first set of bit sequences. After that, the first modulation symbol sequence corresponding to the first set and the second set of bit sequences is obtained by performing the primary modulation processing of the rearranged second set of bit sequences, respectively. ,
The converting means includes tone interleaving means for rearranging a plurality of primary modulation symbols constituting at least the first set and the second set of primary modulation symbol sequences, and the plurality of primary modulation symbols rearranged by the tone interleaving means. a inverse Fourier transform means for inverse Fourier transform, it is shall be the inverse Fourier transform collectively at least the first and second sets of primary modulation symbol sequence obtained by primary modulation means.

According to the present invention, it is possible to reduce the time required from interleaving to primary modulation while maintaining the same communication characteristics as in the past, and to improve the signal processing speed of the entire communication apparatus.

It is a figure which shows the OFDM baseband modulation / demodulation block made into object by Embodiment 1, 2, and 3. FIG. It is a figure which shows the tone interleave IFFT in Embodiment 1 of this invention. It is a figure which shows the tone deinterleaving FFT in Embodiment 1 of this invention. It is a figure which shows the process from the conventional bit interleaving to primary modulation. It is a figure which shows the process from the conventional primary demodulation to bit deinterleaving. It is a figure which shows the process from the small bit interleaver to the primary modulation in Embodiment 1 of this invention. 6 is a diagram illustrating comparison of processing times from bit interleaving to primary modulation in the transmission apparatus in Embodiment 1. FIG. FIG. 4 is a diagram illustrating a process from primary demodulation to small bit deinterleaving in the first embodiment. FIG. 10 is a diagram showing a comparison of processing times from primary demodulation to error correction decoding in the receiving apparatuses in the first and fifth embodiments. It is a figure which shows the bit reverse order process in 64-point IFFT. It is a figure which shows the bit reverse order process with respect to a subcarrier signal. It is a figure which shows the tone interleaving process concerning Embodiment 2 of this invention. It is a figure which shows the process from the conventional bit interleaving to primary modulation in IEEE802.11a. FIG. 10 is a diagram illustrating a process from bit interleaving to primary modulation according to the second exemplary embodiment; FIG. 11 is a diagram showing a comparison of processing times from primary demodulation to error correction decoding in the receiving apparatuses in the second and third embodiments. It is a figure which shows the bit interleaver at the time of 16QAM modulation in IEEE802.11a. 6 is a diagram showing a bit interleaver at the time of 16QAM modulation compliant with IEEE802.11a in Embodiment 3. FIG. It is a figure which shows the bit interleaver at the time of 64QAM modulation in IEEE802.11a. 6 is a diagram showing a bit interleaver at the time of 64QAM modulation compliant with IEEE802.11a in Embodiment 3. FIG. FIG. 11 is a diagram illustrating an OFDM baseband modulation / demodulation block targeted in a fourth embodiment. It is a figure which shows the process from the conventional bit interleaving to BPSK modulation in IEEE802.11a. FIG. 10 is a diagram illustrating BPSK modulation in the fourth embodiment. It is a figure which shows the conventional SC-FDE transmission baseband modulation / demodulation block. It is a figure which shows the example of a 32 point IFFT circuit. It is a figure which shows the process from the bit interleaving to the primary modulation in the SC-FDE transmitting apparatus. It is a figure which shows the process from the primary demodulation to the bit deinterleaving in the SC-FDE receiver. FIG. 10 is a diagram illustrating an SC-FDE transmission baseband demodulation block in a fifth embodiment. It is a figure which shows the example of a 32 point symbol interleave IFFT circuit. FIG. 10 is a diagram illustrating a process from primary demodulation to bit deinterleaving in the receiving apparatus according to the fifth embodiment. It is a figure which shows the conventional OFDM baseband modulation / demodulation block. It is a figure which shows a general bit interleaver. It is a figure which shows the effect of tone interleaving. It is a figure which shows the example of normal IFFT. It is a figure which shows the example of normal FFT. It is a figure which shows the example of tone interleave IFFT. It is a figure which shows the example of a tone deinterleave FFT.

Embodiments of a communication apparatus according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a block diagram of OFDM baseband modulation / demodulation targeted in the first embodiment. Unlike FIG. 30, in the transmission device, the small bit interleaver 11a having a smaller memory length than the conventional one, the tone interleave IFFT circuit 14a, in the receiving device, the tone deinterleave FFT circuit 22a, and the small bit having a smaller memory length than the conventional one. A deinterleaver 15a is provided. The circuits other than these are the same as those of the conventional OFDM communication apparatus of FIG.

A flow of a series of processes in the transmission device 1 will be described. The error correction encoding unit 10 performs error correction encoding on the input information data s10. At this time, when the transmission rate is improved, the coded bit thinning-out process (puncture process) is also performed. Next, the small bit interleaver 11a rearranges the encoded bit sequence s11. The primary modulation unit 12a performs primary modulation such as PSK or QAM on the interleaved bit sequence s12a, and maps bits to primary modulation symbols.

The generated primary modulation symbol sequence s13a is parallelized to the subcarrier signal s14a by the S / P conversion unit 13, and converted from the subcarrier signal s14a to the time signal s15 by the tone interleave IFFT unit 14a. The parallel time signal s15 is serialized to the time signal sequence s16 by the P / S conversion unit 15, and a GI is inserted at the head of each OFDM symbol by the GI insertion unit 16 to output an OFDM baseband signal s17. The OFDM baseband signal s17 is transmitted to the receiving device 2.

Next, a flow of a series of processes in the receiving device 2 will be described. The receiving device 2 receives an OFDM baseband signal. The GI removal unit 20 removes the GI from the OFDM baseband time signal s20, and the S / P conversion unit 21 converts the serial signal s21 into the parallel signal s22. The tone interleave FFT unit 22a converts the parallel time signal s22 into a subcarrier signal s23a. The P / S converter 23 serializes the subcarrier parallel signal s23a, and the primary demodulator 24a detects a mapping bit of each primary modulation symbol to obtain a detected bit sequence s25. The small bit deinterleaver 25a deinterleaves the detected bit sequence s25 and rearranges it into the correct bit sequence s26. The error correction decoding unit 26 applies error correction decoding to the bit series s26 to obtain information data s27.

The bit interleaver 11a and bit deinterleaver 25a used in the first embodiment have a memory length (memory size) smaller than that of the conventional bit interleaver 11 and bit deinterleaver 25. Here, as an example, the conventional bit interleaver size is 8 * 4 bits, the conventional bit deinterleaver size is 4 * 8 bits, and the small bit interleaver used in Embodiment 1 is 2 * 4 bits. The small bit deinterleaver is 4 * 2 bits.

  The memory size of the bit interleaver 11a is set as follows in relation to the modulation method. The modulation scheme used in the present embodiment is a QPSK (Quadrature PSK) modulation scheme in which 2 bits are mapped to one modulation symbol. Therefore, the vertical size of the bit interleaver 11a is a multiple of 2 bits (2 bits in this embodiment). The horizontal size of the bit interleaver 11a is the same as the horizontal size of the conventional bit interleaver 11. The vertical and horizontal sizes of the bit deinterleaver 25a are set to the horizontal and vertical sizes of the bit interleaver 11a. The horizontal size of the bit deinterleaver 25a is set according to the demodulation method (a multiple of 2 in the case of the QPSK demodulation method in which one modulation symbol is mapped to two bits). This also applies to the following embodiments.

Also, conventional techniques are used for frame synchronization, carrier frequency synchronization, gain adjustment, transmission path estimation, and the like necessary for establishing OFDM communication, and these assumptions are common to the following first to fifth embodiments. .

2 and 3 show the tone interleave IFFT unit 14a and the tone deinterleave FFT unit 22a used in the first embodiment, respectively. For simplicity, the number of points for IFFT and FFT is 16 in the first embodiment. The number of subcarrier signals s14a input to the tone interleave IFFT section 14a and the number of subcarrier signals s23a output from the tone deinterleave FFT section 22a are set to 16, which is the same as the number of points.

The tone interleave IFFT unit 14a provided on the transmission side will be described with reference to FIG. The tone interleave IFFT unit 14a includes a tone interleaver 141a and a butterfly calculation unit 142a. Unlike the subcarrier signal s14 shown in FIG. 33, the index of the subcarrier signal s14a input to the tone interleaver 141a is 0, 4, 8, 12, 1,..., 15 as shown in FIG. It is assumed that the order is as follows.
The tone interleaver 141a performs rearrangement processing on the subcarrier signal s14a to obtain an intermediate signal s140. Here, the rearrangement by the tone interleaver 141a is performed so that the output is the same as the index of the intermediate signal s140 in the normal IFFT unit 14 shown in FIG.

Thereafter, the intermediate signal s140 is converted into a time signal s15 by the butterfly operation unit 142a. In FIG. 2, the time signal s15, which is the output of the tone interleave IFFT unit 14a, is represented by a to p. As described above, the processing of the tone interleaver 141a has the same processing amount as the bit reverse order processing provided in the normal IFFT unit 14, and the calculation amount and processing time do not increase as compared with the conventional IFFT unit 14.

  The tone interleaver 141a used in Embodiment 1 performs rearrangement of the subcarrier signal s14a, but differs from the bit reverse order processing unit 141 provided in the conventional IFFT unit 14a in the following points. That is, the conventional bit reverse order processing unit 141 performs rearrangement necessary for IFFT processing, but the tone interleaver 141a performs mixing by using a small bit interleaver 11a in addition to rearrangement necessary for IFFT processing. Also rearranges to compensate for the decline in effectiveness. It differs from the conventional bit reverse order processing unit 141 in that these two functions are performed by one tone interleaver 141a. This also applies to the following embodiments.

As shown in FIG. 3, the tone deinterleave FFT unit 22a provided on the receiving side is composed of an FFT butterfly calculation unit 221a and a tone deinterleaver 222a. The tone deinterleave FFT unit 22a performs a process in the reverse order to the process of the tone interleave IFFT unit 14a. In other words, the FFT butterfly operation is applied to the time signal s22 composed of a to p to obtain the intermediate signal s220, and further converted into the subcarrier signal s23a by the tone deinterleaver 222a. Here, it is assumed that tone deinterleaving is performed so that the index of the subcarrier signal s23a is the same as that of the subcarrier signal s14a. Similar to the tone interleave IFFT unit 14a described above, the tone deinterleave FFT unit 22a does not increase the amount of computation and processing time compared to the conventional FFT unit 22.

The tone deinterleaver 222a used in Embodiment 1 performs rearrangement of the subcarrier signal s14a, but differs from the bit reverse order processing unit 222 provided in the conventional FFT unit 22 in the following points. That is, the conventional bit reverse order processing unit 222 performs rearrangement necessary for FFT processing, but the tone deinterleaver 222a uses a small bit deinterleaver 25a in addition to the rearrangement necessary for FFT processing. Rearrangement is also performed to compensate for the decrease in the stirring effect caused by. It differs from the conventional bit reverse order processing unit 222 in that these two functions are performed by one tone deinterleaver 222a. This also applies to the following embodiments.

  Next, the process from bit interleaving to primary modulation and the process from primary demodulation to bit deinterleaving will be described by comparing the conventional and this embodiment.

FIG. 4 shows processing processes of the bit interleaver 11 and the primary modulation unit 12 in the conventional transmission apparatus. Hereinafter, in the description of the process from bit interleaving to primary modulation and from primary demodulation to bit deinterleaving in OFDM, one OFDM symbol will be described. In the first embodiment, QPSK modulation is performed as primary modulation. In the conventional OFDM transmission apparatus, the 32-bit bit sequence {b _{0 to} b ₃₁ } subjected to error correction coding is subjected to bit interleaving by the 8 * 4 bit interleaver 11, QPSK modulation is performed by the primary modulator 12, and the primary Modulation symbol sequences {d ₀ , d ₁ ,..., D ₁₅ } are generated in order. The generated primary modulation symbol sequence is input to the normal IFFT unit 14 via the S / P conversion unit 13.

FIG. 5 shows a processing process in the primary demodulator 24 and the bit deinterleaver 25 in the conventional receiving apparatus. In the primary demodulator 24 subcarrier signal sequence _{{x 0, x 1, ···} , x 15} predecode bit sequence {y _{0 from, y 4, y 8, y} 12, y 1, ···, y 31 } Are rearranged by the bit deinterleaver 25 in the order of {y ₀ , y ₁ , y ₂ , y ₃ , y ₄ ,..., Y ₃₁ }, and error correction decoding processing is performed.

In the bit interleaving and bit deinterleaving processing, reading cannot be performed until the writing of the bits is completed, and reading / writing requires a processing time proportional to the interleaver size. In particular, when multilevel conversion is performed by primary modulation such as 16QAM and 64QAM, a larger bit interleaver and bit deinterleaver are required, which requires much time. This problem becomes particularly serious in a receiving apparatus that performs error correction decoding processing, which may cause processing delay.

FIG. 6 shows a processing process of the small bit interleaver 11a and the primary modulation unit 12a in the transmission apparatus according to the first embodiment. In the first embodiment, the coded bit sequence _{s11 {b 0 ~b 7},} {b 8 ~b 15}, {b 16 ~b 23}, 4 sets of _{{b 24 ~b 31} (#} 1~ Dividing into # 4), each group is sequentially subjected to bit interleaving and QPSK modulation.
For example, for the first set (# 1), the small bit interleaver 11a converts the encoded bit sequence {b ₀ , b ₁ , b ₂ , b ₃ , b ₄ , b ₅ , b ₆ , b ₇ } to {b ₀ , b ₁ , b ₂ , b ₃ , b ₄ , b ₅ , b ₆ , b ₇ }. After rearranging in the order of ₀ , b ₄ , b ₁ , b ₅ , b ₂ , b ₆ , b ₃ , b ₇ }, the primary modulation unit 12a performs QPSK modulation, and a primary modulation symbol sequence {d ₀ , d ₄ , D ₈ , d ₁₂ } are output. At this time, since the size of the bit interleaver 11a is 1/4 of the conventional size, the writing time and reading time of the small bit interleaver 11a are also 1/4. When the reading of the first set (# 1) from the small bit interleaver 11a is completed, the next second set (# 2) of the encoded bit sequence {b _{8 to} b ₁₅ } is immediately input. The third set (# 3) and the fourth set (# 4) of encoded bit sequences are processed in the same procedure.

  The bit interleaver 11a is smaller than the conventional bit interleaver 11, but this can be explained as follows in relation to the tone interleave IFFT unit 14a. Conventionally, the bit interleaver 11 having a size sufficient to process the number of bits (32 bits in the case of QPSK modulation) corresponding to the number (16) of the subcarrier signals s14 input to the IFFT unit 14 at once. Used (8 * 4 bits). In contrast, the number of bits (bit interleaver size 2 * 4 bits) that can be interleaved by the bit interleaver 11a of the present embodiment at the same time is the number of subcarrier signals s14a input to the tone interleave IFFT unit 14a ( It is smaller than the number of bits corresponding to 16) (32 bits in the case of QPSK modulation). This also applies to the following embodiments.

Thus, by reducing the size of the bit interleaver 11a and shortening the read / write time, it is possible to improve the operation rate of the bit interleaver and to improve the transmission processing speed as a whole (see FIG. 7). That is, in this embodiment, since the size of the bit interleaver 11a is 1/4 of that of the conventional bit interleaver 11, the writing time of each set of encoded bit sequences is Ta / 4. Further, during the primary modulation of the first set (# 1) of the encoded bit sequence (primary modulation # 1), the second set (# 2) of the encoded bit sequence to the bit interleaver 11a in parallel. And reading from the bit interleaver 11a. Therefore, the time required to complete the interleaving and primary modulation of the four sets of encoded bit sequences is Ta / 4 + Tb + Tc. Here, Ta is the write time of the conventional bit interleaver 11, Tb is the time from the start of reading of the conventional bit interleaver 11 to the start of the primary modulation process, and Tc is the time required for the modulation process of the conventional primary modulation unit 12 It is. In the present embodiment, the time is shortened by 3Ta / 4 compared to the conventional case.

4 and 6, as compared with the conventional bit interleaver 11, the small bit interleaver 11a according to the present embodiment reduces the memory length to ¼, so that the circuit scale can be reduced.
As can be seen from FIG. 6, the QPSK modulation symbol sequences obtained by finishing all four sets of signal processing are in the order of {d ₀ , d ₄ , d ₈ , d ₁₂ , d ₁ ,..., D ₁₅ }. However, the above-described tone interleave IFFT unit 14a (FIG. 2) performs appropriate rearrangement, and the same OFDM modulation signal as that of the conventional art can be output.

  When the bit interleaver 11a is made smaller, the stirring effect is lower than that of the conventional bit interleaver 11. However, the tone interleaver 141a provided in the tone interleave IFFT 14a performs rearrangement to compensate for the stirring effect. It is possible to achieve the effect as usual or higher. In other words, the present embodiment is characterized in that the interleaving is performed in two stages of the bit interleaver 11a and the tone interleaver 141a. This also applies to the following embodiments.

FIG. 8 shows a processing process of the primary demodulator 24a and the bit deinterleaver 25a in the receiving apparatus according to this embodiment.
The subcarrier signal s23a, which is the output from the tone deinterleave FFT unit 22a shown in FIG. 3, is P / S converted and then input to the primary demodulation unit 24a. The primary demodulated input signal sequence (subcarrier signal sequence) s24 input to the primary demodulator 24a is in the order of {x ₀ , x ₄ , x ₈ , x ₁₂ , x ₁ ,..., X ₁₅ }. Yes. Similar to the above transmission processing, the primary demodulated input signal sequence s24 is converted to {x ₀ , x ₄ , x ₈ , x ₁₂ }, {x ₁ , x ₅ , x ₉ , x ₁₃ }, {x ₂ , x ₆ , It is divided into four groups of x ₁₀ , x ₁₄ }, {x ₃ , x ₇ , x ₁₁ , x ₁₅ }, and primary demodulation and bit deinterleaving are sequentially performed on each group.

For example, for the first set (# 1), the primary demodulator 24a performs QPSK demodulation of the subcarrier signal sequence {x ₀ , x ₄ , x ₈ , x ₁₂ }, and the pre-decoding bit sequence {y ₀ , y ₄ , _{y 1, y 5, y 2} , y 6, y 3, to detect the y _7}. The detected bit sequence before decoding is rearranged in the order of {y ₀ , y ₁ , y ₂ , y ₃ , y ₄ , y ₅ , y ₆ , y ₇ } by the small bit deinterleaver 25a, and then error correction decoding processing Input to the unit 26.
At this time, similarly to the above-described bit interleaver 11a, the size of the bit deinterleaver 25a is 1/4 of the conventional size, so that the write time and read time of the small bit deinterleaver 25a are also 1/4. Bit deinterleaver 25a, when the reading of the first set is completed, a second set of pre-decoding bit sequence {y ₈ immediately _{follows, y 12, y 9, y} 13, y 10, y 14, y 11 , Y ₁₅ }.

  The primary demodulation process in the primary demodulation unit 24a is executed at a timing synchronized with the writing process of the small bit deinterleaver 25a. That is, at the timing when the writing process to the small bit deinterleaver 25a for the first set is completed, primary demodulation of the second set of pre-decoding bit sequences is started (FIG. 9). The primary demodulator 24a of the present embodiment is different from the conventional primary demodulator 24 in that such synchronization is performed. This also applies to the following embodiments.

  The bit deinterleaver 25a is smaller than the conventional bit deinterleaver 25, and this can be explained as follows in relation to the tone deinterleave FFT unit 22a. Conventionally, a bit deinterleaver 25 having a size sufficient to process the number of bits (32 bits in the case of QPSK modulation) corresponding to the number (16) of subcarrier signals s23 output from the FFT unit 22 at a time. (4 * 8 bits). On the other hand, the number of bits (bit deinterleaver size 2 * 4 bits) that can be deinterleaved at once by the bit deinterleaver 25a of the present embodiment is the subcarrier signal output from the tone deinterleave FFT unit 22a. It is smaller than the number of bits corresponding to the number of s23a (16) (32 bits in the case of QPSK modulation). This also applies to the following embodiments.

As shown in FIG. 9, by reducing the size of the bit deinterleaver 25a and shortening the read / write time, the operating rate of the bit deinterleaver can be improved, and the reception processing speed can be improved as a whole. That is, in this embodiment, since the size of the bit deinterleaver 25a is 1/4 of that of the conventional bit deinterleaver 25, the write time of the bit sequence before decoding of each set is Tf / 4.

Further, while the first set (# 1) of the pre-decoding bit sequence is being read from the bit deinterleaver 25a (small bit deinterleaver read # 1), the primary demodulation of the second set (# 2) is performed in parallel. (# 2) and part of the error correction decoding process of the pre-decoding bit sequence of the first set (# 1) can be performed. Therefore, the time required to complete primary demodulation and deinterleaving for four sets of subcarrier signal sequences is Te + Tf / 4 + Tg + Th. Here, Te is the time from the start of conventional primary demodulation processing to the start of writing of the bit deinterleaver 25, Tf is the writing time of the conventional bit deinterleaver 25, and Tg is the start of reading of the conventional bit deinterleaver 25. From the start to the error correction decoding process, Th is the time required for the conventional error correction decoding process. In the present embodiment, the time is shortened by 3 Tf / 4 as compared with the prior art.

This technique is particularly effective in a receiving apparatus that performs error correction decoding processing. In general, error correction decoding processing such as Viterbi decoding has a large calculation load and is likely to cause processing delay. In addition, in order to obtain the decoding results sequentially, a certain amount of decoder input data is required, so this method, which enables decoder input earlier than before, greatly contributes to the improvement of the reception processing speed.
5 and 8, as compared with the conventional bit deinterleaver 25, the small bit deinterleaver 25a of the present method can reduce the memory length to 1/4, and the circuit scale can be reduced.

When the bit deinterleaver 25a is made smaller, the stirring effect is lower than that of the conventional bit deinterleaver 25. However, the tone deinterleaver 222a provided in the tone deinterleave FFT 22a performs rearrangement to compensate for the stirring effect. By this, it is possible to make the stirring effect the same as or higher than the conventional one. In other words, the present embodiment is characterized in that the deinterleaving is performed in two stages of the tone deinterleaver 222a and the bit deinterleaver 25a. This also applies to the following embodiments.

In the first embodiment, the case where OFDM is used as the transmission method is illustrated. However, the present invention is not limited to this, and any other transmission method may be used as long as it is a multicarrier transmission method.
In the first embodiment, transmission / reception processing using the tone interleave IFFT unit 14a and the tone deinterleave FFT 22a is illustrated. However, the present invention is not limited to this, and any means that realizes the tone interleaving function and the tone deinterleaving function may be used as long as it does not increase the circuit scale and processing time of the entire transmitting apparatus and receiving apparatus.

In the first embodiment, the communication apparatus includes an FFT unit or IFFT unit, and the number of points in the FFT unit and IFFT unit is 16. However, the present invention is not limited to this, and time / frequency conversion may be performed by discrete Fourier transform (DFT) or discrete inverse Fourier transform (Inverse DFT: IDFT). In this specification, processes such as FFT and DFT are collectively referred to as Fourier transform processing or time-frequency conversion processing, and processes such as IFFT and IDFT are collectively referred to as inverse Fourier transform processing or frequency-time conversion processing. Call. Any number of points may be used as long as it is an integer value of 1 or more.

In the first embodiment, the number of subcarrier signals is 16, which is the same as the number of points in the FFT section and IFFT section. However, the present invention is not limited to this, and an arbitrary number of subcarrier signals may be used. For example, when the number of subcarrier signals is smaller than the number of points of FFT and IFFT, as specified in the wireless LAN standard IEEE802.11a (Non-Patent Document 1), null carriers (DC carriers and guards not used for transmission) are used. A band or the like) may be provided, and a pilot carrier may be inserted.

In the first embodiment, the size of the conventional bit interleaver 11 is 8 * 4, the size of the conventional bit deinterleaver 25 is 4 * 8, and the size of the small bit interleaver 11a of the present invention is 2 * 4. The case where the size of the small bit deinterleaver 25a is set to 4 * 2 and the memory length is set to 1/4 as compared with the conventional example is illustrated. However, the present invention is not limited to this, and the interleaver size may be arbitrary, and the small bit interleaver 11a and the small bit deinterleaver 25a only need to have a larger circuit scale than the conventional bit interleaver 11 and bit deinterleaver 25.

In the first embodiment, the case where QPSK is used as the primary modulation scheme has been illustrated. However, the present invention is not limited to this, and any digital modulation method may be used.
In the first embodiment, the primary demodulation output (error correction decoding input) {y ₀ , y ₁ , y ₂ , y ₃ , y ₄ ,..., Y ₃₁ } is described as a bit before decoding. However, not limited to this, {y ₀ , y ₁ , y ₂ , y ₃ , y ₄ ,..., Y ₃₁ } may be hard decision bits, and soft decisions such as bit likelihood and bit log likelihood ratios. Value may be used.

In the first embodiment, a single-input single-output (SISO) system is assumed as a communication system. However, the present invention is not limited to this. For example, in wireless communication, a MIMO (Multiple-Input Multiple-Output) system may be used.
The first embodiment can be applied regardless of wired communication or wireless communication.

As described above, in Embodiment 1, since the small bit interleaver 11a is used, the processing time from the bit interleaving to the primary modulation can be shortened. In addition, the circuit scale can be reduced.
Further, the tone interleaver 141a performs rearrangement to compensate for the stirring effect of the small bit interleaver 11a, so that the stirring effect can be maintained as usual or improved as compared with the conventional apparatus.
Furthermore, since the tone interleaver 141a performs rearrangement to compensate for the stirring effect of the small bit interleaver 11a in addition to the rearrangement necessary for IFFT processing by one circuit, the circuit scale and processing time can be reduced. .
The receiving device has the same effect.

Embodiment 2. FIG.
The second embodiment according to the present invention has a basic configuration of the OFDM baseband modulation / demodulation block shown in FIG. However, in the second embodiment, the number of points of the tone interleave IFFT unit 14a and the tone deinterleave FFT unit 22a is different from that of the first embodiment. The second embodiment conforms to the wireless LAN standard IEEE802.11a. Thereby, the effect in actual operation of the present invention is shown.

FIG. 10 shows an example of the bit reverse order processing unit 141 or 222 included in the normal IFFT unit 14 and the FFT unit 22. In IEEE802.11a, a 64-point IFFT unit 14 generally performs frequency-time signal conversion, and an FFT unit 22 performs time-frequency signal conversion. Here, the subcarrier numbers are set to -32 to 31 in accordance with the IEEE802.11a specification.
FIG. 11 shows how the subcarrier signals are rearranged by the bit reverse order processing unit 141 included in the conventional IFFT unit 14. In IEEE802.11a, subcarrier numbers -32 to -27, 0, and 27 to 31 are used as subcarriers (null subcarriers) that are not used for transmission. Of the remaining subcarriers, subcarrier numbers -21, -7, 7, and 21 are used for pilot signals, and the other 48 subcarriers are used for data signals. Here, the pilot signal is expressed as p ₇ , p ₂₁ , p ₋₇ , and p _−21, and the data subcarrier signal is expressed as d ₀ to d ₄₇ .

FIG. 12 shows the state of tone interleaving in tone interleaving IFFT section 14a used in the second embodiment. Unlike the conventional IFFT input of FIG. 11, the 48 data subcarrier signals d _{0 to} d ₄₇ to be input are {d ₀ , d ₃ , d ₆ , d ₉ ,. d ₄₅ , d ₁ , d ₄ , d ₇ ,..., d ₄₇ }. The signal order is different from the conventional IFFT input because the processing of the small bit interleaver 11a is different from the conventional one. The processing of the small bit interleaver 11a will be described later.
On the other hand, the rearrangement is performed so that the tone interleaver output is in the same order as the bit reverse processing output of the conventional IFFT in FIG.

Next, the process from bit interleaving to primary modulation and the process from primary demodulation to bit deinterleaving will be described by comparing the conventional and this embodiment.
FIG. 13 shows a process from bit interleaving to primary modulation in a conventional IEEE802.11a compliant OFDM transmitter. Here, QPSK modulation is performed as primary modulation. In the conventional IEEE802.11a-compliant OFDM transmitter, the error correction coded bit sequence 96 bits b _{0 to} b ₉₅ are bit-interleaved by the 6 * 16-bit interleaver 11, QPSK modulation is performed, and the primary modulation symbol sequence {d ₀ , D ₁ ,..., D ₄₇ } are generated in order. The generated primary modulation symbol sequence is input to a normal IFFT unit 14 (bit reverse order processing in FIG. 11) via S / P conversion.

FIG. 14 shows processes from small bit interleaving to primary modulation in the transmission apparatus according to the second embodiment. The small bit interleaver size is 2 * 16. The encoded bit sequence of the number of bits processed at one time in the conventional interleaver is divided into three groups {b _{0 to} b ₃₁ }, {b _{32 to} b ₆₃ }, and {b _{64 to} b ₉₅ } Similarly to the first embodiment, each group is sequentially subjected to bit interleaving and QPSK modulation.

For example, for the first set (# 1), encoded bits {b ₀ , b ₁ , b ₂ ,..., B ₃₁ } are converted into {b ₀ , b ₁₆ , b ₁ , b by the small bit interleaver 11a. ₁₇ , b ₂ , b ₁₈ ,..., B ₁₅ , b ₃₁ }, then QPSK modulation is performed, and the primary modulation symbol sequence {d ₀ , d ₃ , d _{6 ,.} } Is output. At this time, since the bit interleaver size is 1/3 of the conventional size, the write time and read time of the small bit interleaver 11a are also 1/3. When reading from the first set (# 1) small bit interleaver 11a about is completed, it is possible to enter a coded bit b ₃₂ ~b ₆₃ of the second set immediately follows (# 2). It performs processing of coded bits _{b 64} ~b ₉₅ of the third set to the same procedure (# 3).
In this process, the first set (# 1) of coded bit sequences can be primarily modulated in parallel while the second set (# 2) of coded bits are interleaved. The same applies to the other sets. Therefore, the entire processing time can be shortened.

Thus, by reducing the size of the bit interleaver and shortening the read / write time, the operating rate of the bit interleaver can be improved, and the transmission processing speed can be improved as a whole. 13 and 14, as compared with the conventional bit interleaver, the small bit interleaver of this method can reduce the memory length to 1/3, and the circuit scale can be reduced.

As can be seen from FIG. 14, the QPSK modulation symbols obtained by finishing all three sets of signal processing are in the order of {d ₀ , d ₃ , d ₆ ,..., D ₄₇ }. This is the reason why the IFFT input of the tone interleave IFFT unit 14a used in the second embodiment is different from the conventional IFFT input. However, the above-described tone interleave IFFT unit 14a (FIG. 11) performs appropriate rearrangement, and the same OFDM modulation signal as that of the conventional art can be output.

The receiving device performs a reception process corresponding to the transmission process described above. Specifically, the primary demodulated input signal sequence (subcarrier signal sequence) s24a input to the primary demodulator 24a is divided into three sets, and primary demodulation and bit deinterleaving are sequentially performed on each set.

Thereby, a bit deinterleaver can be reduced in size, reading / writing time can be shortened, and the operation rate of a bit deinterleaver can be improved (refer FIG. 15). That is, in the second embodiment, since the size of the bit deinterleaver 25a is 1/3 that of the conventional bit deinterleaver 25, the write time of the bit sequence before decoding of each set is Tj / 3.

Further, while reading the pre-decoding bit sequence of the first set (# 1) (compact bit deinterleaver read # 1), the primary demodulation (# 2) of the subcarrier signal sequence of the second set (# 2) is performed in parallel. 2) and part of the error correction decoding process of the pre-decoding bit sequence of the first set (# 1) can be performed. Therefore, the time required for completing the primary demodulation and deinterleaving of the three sets of subcarrier signal sequences is Ti + Tj / 3 + Tk + Tl. Here, Ti is the time from the start of the conventional primary demodulation process to the start of writing of the bit deinterleaver 25, Tj is the writing time of the conventional bit deinterleaver 25, and Tk is the data reading of the conventional bit deinterleaver 25. The time from the start to the start of the error correction decoding process, Tl is the time required for the conventional error correction decoding process. In the present embodiment, the time is shortened by 2 Tj / 3 as compared with the prior art.

  The bit interleaver 11a is smaller than the conventional bit interleaver 11, but this can be explained as follows in relation to the tone interleave IFFT unit 14a. Conventionally, the bit interleaver 11 having a size sufficient to process the number of bits (96 bits in the case of QPSK modulation) corresponding to the number (48) of data subcarrier signals s14 input to the IFFT unit 14 at a time. (6 * 16 bits). On the other hand, the number of bits (bit interleaver size 2 * 16 bits) that can be interleaved by the bit interleaver 11a of this embodiment at a time is the number of data subcarrier signals s14a input to the tone interleave IFFT unit 14a. It is less than the number of bits corresponding to (48) (96 bits in the case of QPSK modulation).

  The bit deinterleaver 25a can be described as follows. Conventionally, a bit deinterleaver having a size sufficient to process the number of bits (96 bits in the case of QPSK modulation) corresponding to the number (48) of data subcarrier signals s23 output from the FFT unit 22 at a time. 25 was used (16 * 6 bits). On the other hand, the number of bits (bit deinterleaver size 16 * 2 bits) that can be deinterleaved at once by the bit deinterleaver 25a of the present embodiment is the subcarrier signal output from the tone deinterleave FFT unit 22a. It is smaller than the number of bits corresponding to the number of s23a (48) (96 bits in the case of QPSK modulation).

It can be easily understood that the reception processing speed can be improved as a whole and the circuit scale can be reduced.
In the second embodiment, the case where QPSK is used as the primary modulation scheme has been illustrated. However, the present invention is not limited to this, and other modulation schemes such as BPSK (Binary Phase Shift Keying), 16QAM, and 64QAM defined in IEEE802.11a as described later may be used.

In the second embodiment, transmission / reception processing using the tone interleave IFFT unit 14a and the tone deinterleave FFT 22a is illustrated. However, the present invention is not limited to this, and any means that realizes the tone interleaving function and the tone deinterleaving function may be used as long as it does not increase the circuit scale and processing time of the entire transmitting apparatus and receiving apparatus.

In the second embodiment, the communication apparatus includes an FFT unit or IFFT unit, and the number of points of FFT and IFFT is 64. However, the present invention is not limited to this, and time / frequency conversion may be performed by DFT or IDFT. In this specification, processes such as FFT and DFT are collectively referred to as Fourier transform processing or time-frequency conversion processing, and processes such as IFFT and IDFT are collectively referred to as inverse Fourier transform processing or frequency-time conversion processing. Call. Any number of points may be used as long as it is an integer value of 1 or more.
The primary demodulation output and the error correction decoding unit input in the second embodiment are not limited to hard decision bits, but may be soft decision values such as bit likelihood and bit log likelihood ratio.

In the second embodiment, a SISO radio system using a single antenna is assumed as a communication system. However, the present invention is not limited to this, and a MIMO system may be used. In particular, in the wireless LAN standard IEEE802.11n being developed, the bit interleaver shape and the bit interleaver shape are different from those in the second embodiment, but the same transmission / reception processing procedures as those in the second embodiment are applicable.

As described above, since the small bit interleaver 11a is used in the second embodiment, the processing time from bit interleaving to primary modulation can be shortened. In addition, the circuit scale can be reduced.
Further, the tone interleaver 141a performs rearrangement to compensate for the stirring effect of the small bit interleaver 11a, so that the stirring effect can be maintained as usual or improved as compared with the conventional apparatus.
Furthermore, since the tone interleaver 141a performs rearrangement to compensate for the stirring effect of the small bit interleaver 11a in addition to the rearrangement necessary for IFFT processing by one circuit, the circuit scale and processing time can be reduced. .
The receiving device has the same effect.

Embodiment 3 FIG.
The third embodiment of the communication apparatus according to the present invention basically has the OFDM baseband modulation / demodulation block diagram shown in FIG. The third embodiment conforms to the wireless LAN standard IEEE802.11a as in the second embodiment, but differs in that 16QAM and 64QAM are used as the primary modulation scheme. Thereby, the effect in actual operation of the present invention is shown. Below, it demonstrates centering around a bit interleaver.

FIG. 16 shows a conventional bit interleaver 11 at the time of 16QAM modulation defined by IEEE802.11a. Conventionally, bit interleaving is realized by writing the input bits b _{0 to} b ₁₉₁ into a 12 * 16-bit memory block as shown in FIG. 16 and sequentially reading out from the leftmost column in the vertical direction. For writing to the bit interleaver, writing to the 2 * 16 memory block is one cycle, and this is repeated six times. In the 16QAM modulation process after reading, 4 bits are mapped to one modulation symbol.

Therefore, as shown in FIG. 17, a small bit interleaver of 4 * 16 bits is prepared in the third embodiment, and bit interleaving and primary modulation are divided into three times as in the second embodiment. To do. By introducing the tone interleaving function of the second embodiment, an OFDM baseband signal can be generated after the primary modulation as in the second embodiment. In the receiving apparatus, as in the second embodiment, by introducing the tone deinterleaving function, the 16QAM primary demodulation and the bit deinterleaving can be divided into three times to reduce the circuit scale and the processing time. It is easily understood what can be achieved.

FIG. 18 shows a conventional bit interleaver in 64QAM modulation defined by IEEE802.11a. Conventionally, bit interleaving is realized by writing the input bits b _{0 to} b ₂₈₇ into an 18 * 16-bit memory block as shown in FIG. 18 and sequentially reading out from the leftmost column in the vertical direction. In this writing to the bit interleaver, writing to the memory block of 3 * 16 bits is one cycle, and this is repeated 6 times. In the 64QAM modulation process after reading, 6 bits are mapped to one modulation symbol.

In the third embodiment, as shown in FIG. 19, a 6 * 16-bit small bit interleaver is prepared, and bit interleaving and primary modulation are divided into three times as in the second embodiment. By introducing the tone interleaving function of the second embodiment, an OFDM baseband signal can be generated after the primary modulation as in the second embodiment. In the receiving apparatus, as in the second embodiment, by introducing the tone deinterleaving function, 64QAM primary demodulation and bit deinterleaving can be performed by dividing into three times, thereby reducing circuit scale and processing time. It is easily understood what can be achieved.

The memory size of the bit interleaver 11a used in the third embodiment is set as follows in relation to the modulation method.
That is, when the modulation scheme used is a 16QAM modulation scheme in which 4 bits are mapped to one modulation symbol, the vertical size of the bit interleaver 11a is a multiple of 4 bits as shown in FIG. The horizontal size of the bit interleaver 11a is the same as the horizontal size of the conventional bit interleaver 11. The vertical and horizontal sizes of the bit deinterleaver 25a are set to the horizontal and vertical sizes of the bit interleaver 11a.
When the modulation scheme to be used is a 64QAM modulation scheme in which 6 bits are mapped to one modulation symbol, the vertical size of the bit interleaver 11a is a multiple of 6 bits as shown in FIG. The horizontal size of the bit interleaver 11a is the same as the horizontal size of the conventional bit interleaver 11. The vertical and horizontal sizes of the bit deinterleaver 25a are set to the horizontal and vertical sizes of the bit interleaver 11a.

Compared to the case of QPSK modulation described in the second embodiment, the conventional bit interleaver 11 and bit deinterleaver 25 in 16QAM modulation and 64QAM modulation require a larger memory length, and more bits are read and written. It took time. By implementing the third embodiment, these problems can be alleviated, and the circuit scale reduction amount and the processing time reduction amount are larger than those of the QPSK case of the second embodiment.

The primary demodulation output and error correction decoding unit input in the third embodiment are not limited to hard decision bits, but may be soft decision values such as bit likelihood and bit log likelihood ratio.
In the third embodiment, a SISO radio system using a single antenna is assumed as a communication system. However, the present invention is not limited to this, and a MIMO system may be used. In particular, in the wireless LAN standard IEEE802.11n being developed, the bit interleaver shape and the bit interleaver shape are different from those in the third embodiment, but the same transmission / reception processing procedure as in the third embodiment is applicable.

As described above, since the small bit interleaver 11a is used in the third embodiment, the processing time from bit interleaving to primary modulation can be shortened. In addition, the circuit scale can be reduced.
Further, the tone interleaver 141a performs rearrangement to compensate for the stirring effect of the small bit interleaver 11a, so that the stirring effect can be maintained as usual or improved as compared with the conventional apparatus.
Furthermore, since the tone interleaver 141a performs rearrangement to compensate for the stirring effect of the small bit interleaver 11a in addition to the rearrangement necessary for IFFT processing by one circuit, the circuit scale and processing time can be reduced. .
The receiving device has the same effect.

Embodiment 4 FIG.
The communication apparatus according to Embodiment 4 of the present invention has a basic configuration of the OFDM baseband modulation / demodulation block shown in FIG. The fourth embodiment is similar to the second and third embodiments in conformity with the wireless LAN standard IEEE802.11a, but is different in that BPSK is used as the primary modulation scheme.
Further, in the present embodiment, unlike the communication apparatus shown in FIG. 1, the small bit interleaver 11a and the small bit deinterleaver 25a are omitted, and the error correction coded bits are directly BPSK-primarily modulated and received by the transmission apparatus. In the apparatus, the BPSK primary demodulated data is directly passed to the error correction decoding processing unit 26. Each block except these is the same as FIG.

FIG. 21 shows a process from conventional bit interleaving to BPSK primary modulation at the time of BPSK modulation defined by IEEE802.11a. Conventionally, bit interleaving is realized by writing input bits b _{0 to} b ₄₇ into a 3 * 16-bit memory block as shown in FIG. 21 and sequentially reading out from the leftmost column in the vertical direction. As can be seen from FIG. 21, the writing to the bit interleaver 11 is a period of writing to the 1 * 16-bit memory block, and this is repeated three times. In the BPSK modulation process after reading, one bit is mapped to one modulation symbol.

In the fourth embodiment, as shown in FIG. 20, the bit interleaver is omitted, and the direct BPSK primary modulation is sequentially performed. FIG. 22 shows a state in which coded bits b _{0 to} b ₄₇ are directly passed from the error correction coding unit 10 to the BPSK primary modulation unit 12b to perform BPSK modulation. At this time, the output BPSK modulation signal is {d ₀ , d ₃ , d ₆ , d ₉ ,..., D ₄₇ }, but by introducing the tone interleaving function of the second embodiment (FIG. 12). After the primary modulation, an OFDM baseband signal can be generated as in the second and third embodiments.

That is, the tone interleave IFFT unit 14a includes a tone interleaver 141a and an IFFT butterfly operation unit, and the tone interleave IFFT unit 14a performs BPSK modulation signals {d ₀ , d ₃ , d ₆ , d ₉ ,. ., D ₄₇ } is rearranged (tone interleaving). After that, IFFT is performed by the IFFT butterfly calculation unit, and P / S conversion and GI insertion are performed.
In the BPSK modulation method, one bit is mapped to one modulation symbol, so that the bit interleaver and the bit deinterleaver can be omitted.

In the receiving apparatus, as in the second and third embodiments, by introducing the tone deinterleaving function, the output of the BPSK primary demodulation unit 24b can be directly passed to the error correction decoding unit 26, and decoding can be started immediately. Is easily understood. The tone deinterleaver 22a has an FFT butterfly computation unit and a tone deinterleaver. The output of the BPSK primary demodulation unit 24b is subjected to FFT by the FFT butterfly computation unit and rearranged by the tone deinterleaver (tone deinterleave). Is made. Thereafter, BPSK primary demodulation and error correction decoding are performed.

  The tone interleaver 141a according to the fourth embodiment performs tone interleaving for rearranging the subcarrier signal s14a at the frequency signal level in addition to the rearrangement for IFFT processing performed by the bit reverse order processing unit 141 of the conventional IFFT unit 14. It has a function as a process. Further, the tone deinterleaver 222a performs tone deinterleave processing for rearranging the subcarrier signal s14a at the frequency signal level in addition to the rearrangement for the FFT processing as performed by the bit reverse order processing unit 222 of the conventional FFT unit 22. It has the function of. Therefore, even if the small bit interleaver 11a and the small bit deinterleaver 25a are omitted, the entire apparatus has a stirring effect.

The primary demodulation output and error correction decoding unit input in the fourth embodiment are not limited to hard decision bits, but may be soft decision values such as bit likelihood and bit log likelihood ratio.
In the fourth embodiment, a SISO radio system using a single antenna is assumed as a communication system. However, the present invention is not limited to this, and a MIMO system may be used. In particular, in the wireless LAN standard IEEE802.11n being developed, the bit interleaver shape and the bit interleaver shape are different from those in the fourth embodiment, but the same transmission / reception processing procedure as in the fourth embodiment is applicable.

  In this embodiment, a BPSK modulation method has been described as an example of a modulation method for mapping one bit to one modulation symbol, but FSK (Frequency Shift Keying) and OOK (On Off Keying) can also be applied as other modulation methods. .

As described above, in the fourth embodiment, a tone interleaving function and a tone deinterleaving function are introduced into an IEEE802.11a-compliant OFDM communication apparatus, and by using these, bit interleaving and bit deinterleaving are performed during BPSK modulation. It can be omitted. As a result, the signal processing time can be significantly reduced as compared with the conventional case, and at the same time, the circuits required for the conventional bit interleaving and bit deinterleaving can be omitted.

Embodiment 5 FIG.
So far, the example used for multi-carrier transmission has been described, but in the fifth embodiment, broadband single carrier transmission (Single Carrier: SC) using frequency domain equalization (FDE) (hereinafter referred to as “Frequency Domain Equalization: FDE”). A communication device that performs (referred to as SC-FDE), particularly a receiving device, will be described.

FIG. 23 shows a conventional SC-FDE baseband modulation / demodulation block diagram. Here, 40 modulation symbols in which a cyclic prefix (CP) of 8 modulation symbols is added to the head of 32 modulation symbols are defined as 1 block, and transmission / reception processing of 1 block will be described. However, the number of these symbols is an example, and the CP length and the block length are not limited to this. Further, as described in Non-Patent Document 2, a known signal called a unique word may be added instead of CP.

First, a flow of a series of processes in a communication device that performs conventional SC-FDE will be described.
In the transmission device, the error correction encoding unit 30 performs error correction encoding on the input information data s30. At this time, when the transmission rate is improved, the coded bit thinning-out process (puncture process) is also performed. Next, the bit interleaver 31 rearranges the encoded bit sequence s31. The primary modulation unit 32 performs primary modulation such as PSK and QAM on the interleaved bit sequence s32 and maps bits to primary modulation symbols. CP is added by the CP insertion unit 33, and the SC baseband signal s34 is output.

In the receiving apparatus, the CP removing unit 40 removes the CP from the SC baseband time signal s40, and the S / P conversion unit 41 converts the serial signal s41 into the parallel signal s42. The FFT unit 42 converts the time signal s42 into a frequency signal s43. Equalization is performed in the FDE unit 43 and converted into a time signal s45 in the IFFT unit 44. The P / S converter 45 serializes the time signal s45, and the primary demodulator 46 detects mapping bits of each primary modulation symbol. The detected bit sequence s47 is deinterleaved by the bit deinterleaver 47 and rearranged into the correct bit sequence s48. In the error correction decoding unit 48, error correction decoding is applied to the sequence s48 and decoded into information data s49.

FIG. 24 shows an IFFT unit 44 used in the SC-FDE receiver of FIG. Unlike the IFFT units described in the first and second embodiments, the frequency signals f _{0 to} f ₃₁ (s44) are first subjected to IFFT butterfly computation by the IFFT butterfly computation unit 44 and converted to a time signal s440. Thereafter, the time signal s440 is rearranged in a bit reversed order processing section 442 is performed, it is assumed that the correct order of the time signal _x 0 ~x ₃₁ (s45) is obtained.

FIG. 25 shows a process from bit interleaving to primary modulation in a conventional transmission apparatus. Here, it is assumed that QPSK modulation is performed, and the size of the bit interleaver 31 and the bit deinterleaver 47 is 8 * 8 bits. The error correction coded sequences b _{0 to} b ₆₃ (s31) are rearranged by the 8 * 8 bit interleaver 31, and the QPSK primary modulation unit 32 generates QPSK modulation symbols d _{0 to} d ₃₁ (s33).

FIG. 26 shows a process from primary demodulation to bit deinterleaving in a conventional receiving apparatus. The output {x _{0 to} x ₃₁ } (s 46) of the P / S converter 45 is input to the primary demodulator 46, and the bits before decoding {y ₀ , y ₈ , y ₁₆ , y ₂₄ ,..., Y ₅₅ , y ₆₃ } (s47) is detected. The pre-decoding bits are rearranged by the 8 * 8-bit deinterleaver 47, and {y ₀ , y ₁ , y ₂ , y ₃ ,..., Y ₆₃ } (s48) are input to the error correction decoding unit 48. Is done.

FIG. 27 shows a baseband demodulation block diagram of the SC-FDE receiver according to the fifth embodiment. 23 differs from the reception block diagram of FIG. 23 in that a symbol interleave IFFT unit 44a is used instead of the IFFT unit 44, and a small bit deinterleave unit 47a of 8 * 2 bit size is used instead of the 8 * 8 bit deinterleave unit 47. This is the point used. Each part except these is the same as the conventional receiving block of FIG. The transmitter is the same as the conventional one.

FIG. 28 shows symbol interleave IFFT section 44a in the fifth embodiment. The processing of IFFT butterfly operation unit 441a is the same as that of conventional IFFT unit 44 in FIG. 24, but symbol interleaving is performed thereafter, and time signal s45a is converted into {x ₀ , x ₄ , x ₈ , x as shown in FIG. ₁₂ , x ₁₆ ,..., X ₅₅ , x ₆₃ }.
FIG. 29 shows a process from primary demodulation to bit deinterleaving using the symbol interleave IFFT 44a. Since the output of the symbol interleave IFFT unit 44a shown in FIG. 28 becomes the primary demodulation input s46a, the primary demodulation input s46a is {x ₀ , x ₄ , x ₈ , x ₁₂ ,..., X ₂₇ , x ₃₁ }. It is in order. As in the first embodiment, the primary demodulation input s46a is converted into {x ₀ , x ₄ , x ₈ , x ₁₂ ,..., X ₂₈ }, {x ₁ , x ₅ , x ₉ , x ₁₃ ,. _{, x 29}, {x 2} , x 6, x 10, x 14, ···, x 30}, {x 3, x 7, x 11, x 15, ···, the four sets of x _31} Dividing and sequentially performing primary demodulation and bit deinterleaving for each set.

For example, for the first set (# 1), QPSK demodulation is performed on {x ₀ , x ₄ , x ₈ , x ₁₂ ,..., X ₂₈ }, and the bits before decoding {y ₀ , y ₈ , y ₁ , y ₉ ,..., y ₇ , y ₁₅ } are detected. The data is rearranged in the order of {y ₀ , y ₁ , y ₂ , y ₃ ,..., Y ₁₄ , y ₁₅ } by a small bit deinterleaver of 8 * 2 bit size, and then input to the error correction decoding unit 48. . At this time, since the size of the bit deinterleaver 47a is ¼ of the conventional size, the writing time and reading time of the small bit deinterleaver are also ¼, and the first set is read from the small bit deinterleaver. Is completed, the primary demodulation output {x ₁ , x ₅ , x ₉ , x ₁₃ ,..., X ₂₉ } of the next second set (# 2) can be immediately input to the small bit deinterleaver. it can. Similar processing is performed for the third group (# 3) and the fourth group (# 4).
In the case of this procedure, the first set of primary demodulation processing can be performed in parallel while the second set of pre-decoding bits are deinterleaved. The same applies to the other sets. Therefore, the entire processing time can be shortened.

As described above, the fifth embodiment introduces a symbol interleaving function to a wideband SC-FDE receiving apparatus, and implements a signal processing procedure (primary demodulation and bit deinterleaving) using these functions. Even for transmission, the received signal processing time can be reduced compared to the conventional case, and at the same time, the circuit scale required for bit deinterleaving can be reduced. That is, since the small bit deinterleaver 47a is used, the processing time from primary demodulation to bit deinterleaving can be shortened. In addition, the circuit scale can be reduced.

Further, the symbol interleaver 442a performs rearrangement to supplement the stirring effect of the small bit interleaver 47a, so that the stirring effect can be maintained as usual or improved as compared with the conventional apparatus.
Furthermore, since the symbol interleaver 442a performs rearrangement to compensate for the mixing effect of the small bit interleaver 47a in addition to the rearrangement necessary for IFFT processing by one circuit, the circuit scale and processing time can be reduced. .
As in the first to fourth embodiments, the operating rate of the bit deinterleaver can be improved and the reception processing speed can be improved as a whole (see FIG. 9).

In the fifth embodiment, a case where single carrier transmission without applying spread spectrum is exemplified. However, the present invention is not limited to this, spread spectrum may be performed, and weighting in the frequency domain may be performed in the transmission apparatus.

In the fifth embodiment, the reception process using the symbol interleave IFFT unit 44a is illustrated. However, the present invention is not limited to this, and any means that implements a symbol interleaving function and that does not increase the circuit scale and processing time of the entire receiving apparatus may be used.
In the fifth embodiment, the receiving apparatus uses FFT and IFFT, and the number of points (number of symbols) is 32. However, the present invention is not limited to this, and time / frequency conversion may be performed by DFT or IDFT. In this specification, processes such as FFT and DFT are collectively referred to as Fourier transform processing or time-frequency conversion processing, and processes such as IFFT and IDFT are collectively referred to as inverse Fourier transform processing or frequency-time conversion processing. Call. Any number of points may be used as long as it is an integer value of 1 or more.

In the fifth embodiment, the size of the conventional bit interleaver and bit deinterleaver is set to 8 * 8, the size of the small bit deinterleaver of the present invention is set to 8 * 2, and the memory length is reduced to 1 /. The case of 4 was illustrated. However, the present invention is not limited to this, and the interleaver size may be arbitrary, and the small bit interleaver and the small bit deinterleaver need not have a larger circuit scale than the conventional bit interleaver and bit deinterleaver.

In the fifth embodiment, the case where QPSK is used as the primary modulation scheme is illustrated. However, the present invention is not limited to this, and any digital modulation method may be used. In particular, when BPSK modulation is performed as the primary modulation scheme, the bit deinterleaver can be omitted by using the symbol interleaving function as in the fourth embodiment.
In the fifth embodiment, the primary demodulation output (error correction decoding input) {y _{0 to} y ₆₁ } is described as a pre-decoding bit. However, not limited to this, {y _{0 to} y ₆₁ } may be hard decision bits, or may be soft decision values such as bit likelihood and bit log likelihood ratio.

In the fifth embodiment, the SISO system is assumed as the communication system. However, the present invention is not limited to this, and may be implemented by a MIMO system, for example, in wireless communication.
The fifth embodiment can be applied regardless of wired communication or wireless communication.

The present invention has been described based on the embodiments. It is understood by those skilled in the art that these embodiments are exemplifications, and that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. By the way.

As described above, the communication device according to the present invention is useful for a communication device that requires error correction coding, bit interleave processing, and Fourier transform processing or inverse Fourier transform processing.

DESCRIPTION OF SYMBOLS 1 ... Transmission apparatus 2 ... Reception apparatus 10, 30 ... Error correction encoding part 11, 31 ... Bit interleaver 11a ... Small bit interleaver 12, 12a, 32 ... Primary modulation Unit 12b... BPSK primary modulation unit 13, 21, 41... S / P conversion unit 14, 44... IFFT unit 14t, 14a ... tone interleave IFFT unit 14t1, 141a ... tone interleaver 14t2 142a, 441, 441a ... IFFT butterfly computing units 141, 222, 442 ... Bit reverse order processing unit 442a ... Symbol interleavers 15, 23, 45 ... P / S conversion unit 16 ... GI insertion unit 20 ... GI removal unit 22, 42 ... FFT unit 22t, 22a ... tone deinterleave FFT units 22t1, 221 ... FFT butterfly computing units 22t2, 222a ... tone deinterleaving units 24, 24a, 46 ... primary demodulation unit 24b ... BPSK primary demodulation units 25, 47 ... bit deinterleaver 25a ... Small bit deinterleaver 26, 48 ... error correction decoding unit 33 ... CP insertion unit 40 ... CP removal unit s10, s30 ... information signal s11, s31 ... error correction coding bit s12 , S32 ... bit interleaver output bit s12a ... small bit interleaver output bits s13, s13a, s33 ... primary modulation signals s14, s14a ... transmission subcarrier signals s15, s16, s17 ... OFDM Transmission time signals s20, s21, s22 ... OFDM reception time signals s23, s23a, s24, s2 a ... received subcarrier signals s25, s25a, s47, s47a ... primary demodulated output signals s26, s48 ... error correction decoded input signals s27, s49 ... decoded result s34 ... single carrier transmitted signal s40 , S41, s42 ... single carrier reception time signal s43 ... single carrier reception frequency signal s44 ... frequency domain equalization output signals s45, s46 ... equalization time signals s45a, s46a ... symbols Time signals s140, s440, s440a ... IFFT intermediate signal s220 ... FFT intermediate signal after interleaved IFFT

Claims (11)

Interleaving means for rearranging the bit sequence of the input information data;
Primary modulation means for obtaining a corresponding primary modulation symbol sequence by performing primary modulation on the bit sequence rearranged by the interleaving means;
Transform means for collectively performing a reverse Fourier transform on a predetermined number of primary modulation symbols obtained by the primary modulation means;
Transmitting means for transmitting the signal obtained by the converting means;
In a transmission device having
The interleaving means has a size of a bit sequence that can be rearranged at a time smaller than the number of bits corresponding to the predetermined number of primary modulation symbols, and at least a first bit sequence of the input information data according to the size. After separating the bit set of the first set and the second set, rearranging the bits constituting the first set of bit sequences, rearranging the bits constituting the second set of bit sequences,
The primary modulation means performs primary modulation processing of the rearranged first bit sequence in parallel with the rearrangement processing of the second bit sequence in the interleaving means, and the first set of bit sequences. After performing the primary modulation processing, the first modulation processing corresponding to the first set and the second set of bit sequences is performed by performing the primary modulation processing of the rearranged second bit sequence. Obtaining a primary modulation symbol sequence;
The converting means includes tone interleaving means for rearranging a plurality of primary modulation symbols constituting at least the first set and the second set of primary modulation symbol sequences, and the plurality of primary orders rearranged by the tone interleaving means. A transmission apparatus comprising: inverse Fourier transform means for performing inverse Fourier transform on the modulation symbols, and performing inverse Fourier transform on at least the first set and second set of primary modulation symbol sequences obtained by the primary modulation means. . The converting means includes
By performing the inverse Fourier transform processing of the primary modulation symbols constituting the first and second sets of primary modulation symbol sequences as the sub-carrier signal transmitting apparatus according to claim 1, wherein the obtaining a multicarrier signal . The transmission apparatus according to claim 1 or 2 , wherein the size of the bit sequence that can be rearranged at one time by the interleaving unit is set according to a modulation scheme used by the primary modulation unit. An interleaving step for rearranging the bit sequence of the input information data;
A primary modulation step of obtaining a corresponding primary modulation symbol sequence by performing primary modulation on the bit sequence rearranged in the interleaving step;
A transform step for collectively performing an inverse Fourier transform on a predetermined number of primary modulation symbols obtained in the primary modulation step;
A transmission step of transmitting the signal obtained in the conversion step;
A transmission method comprising:
The interleaving step uses an interleaver having a bit sequence size that can be rearranged at a time smaller than the number of bits corresponding to the predetermined number of primary modulation symbols, and the bit sequence of the input information data according to the size After at least the first set and the second set of bit sequences are separated from each other, the bits constituting the first set of bit sequences are rearranged, and then the bits constituting the second set of bit sequences are rearranged. ,
The primary modulation step performs primary modulation processing of the rearranged first bit sequence in parallel with rearrangement processing of the second bit sequence in the interleaving step, and the first set of bit sequences. After performing the primary modulation processing, the first modulation processing corresponding to the first set and the second set of bit sequences is performed by performing the primary modulation processing of the rearranged second bit sequence. Obtaining a primary modulation symbol sequence;
The converting step includes a tone interleaving step for rearranging a plurality of primary modulation symbols constituting at least the first set and the second set of primary modulation symbol sequences, and the plurality of primarys rearranged by the tone interleaving step. A transmission method comprising: an inverse Fourier transform step of performing inverse Fourier transform on the modulation symbols, and performing inverse Fourier transform on at least the first set and the second set of primary modulation symbol sequences obtained in the primary modulation step. . A plurality of time signals received and Fourier transformed to obtain a frequency signal sequence consisting of a predetermined number of frequency signals;
Primary demodulation means for obtaining a corresponding bit sequence by first demodulating the frequency signal sequence obtained by the conversion means;
Deinterleaving means for rearranging the bits constituting the bit sequence;
In a receiving device having
The transforming means includes Fourier transforming means for collectively Fourier transforming the plurality of time signals, and tone deinterleaving means for rearranging the predetermined number of frequency signals obtained by the Fourier transforming means to obtain the frequency signal sequence. Prepared,
The primary demodulating means separates at least a first set and a second set of frequency signal sequences from the frequency signal sequence obtained by the tone deinterleaving means, and performs a primary demodulation process of the first set of frequency signal sequences. Thereafter, by performing a primary demodulation process of the second set of frequency signal sequences, a first set and a second set of bit sequences respectively corresponding to the first set and the second set of frequency signal sequences are obtained,
The deinterleaving means rearranges the bits constituting the first set of bit sequences, wherein the size of the bit sequence that can be rearranged at a time is smaller than the number of bits corresponding to the predetermined number of frequency signals. Performing in parallel with the primary demodulation processing of the second set of frequency signal sequences in the primary demodulating means, and after rearranging the bits constituting the first set of bit sequences, configure the second set of bit sequences A receiving apparatus that performs rearrangement of bits. The time signal is a multi-carrier signal;
The frequency signal is a subcarrier signal;
6. The receiving apparatus according to claim 5 , wherein the converting means obtains a plurality of corresponding subcarrier signals by performing Fourier transform on the plurality of multicarrier signals. 7. The receiving apparatus according to claim 5 , wherein the size of the bit sequence that can be rearranged at one time by the deinterleaving unit is set according to a demodulation method used by the primary demodulating unit. A plurality of received time signals are collectively Fourier transformed to obtain a frequency signal sequence consisting of a predetermined number of frequency signals;
A primary demodulation step of obtaining a corresponding bit sequence by first demodulating the frequency signal sequence obtained in the conversion step;
A deinterleaving step for rearranging the bits constituting the bit sequence;
In a receiving method comprising:
The transforming step includes a Fourier transforming step for collectively Fourier transforming the plurality of time signals, and a tone deinterleaving step for rearranging the predetermined number of frequency signals obtained by the Fourier transforming step to obtain the frequency signal sequence. With
In the primary demodulation step, at least a first set and a second set of frequency signal sequences are separated from the frequency signal sequence obtained in the tone deinterleaving step, and a primary demodulation process of the first set of frequency signal sequences is performed. Thereafter, by performing a primary demodulation process of the second set of frequency signal sequences, a first set and a second set of bit sequences respectively corresponding to the first set and the second set of frequency signal sequences are obtained,
The deinterleaving step uses a deinterleaver whose size of bit sequences that can be rearranged at a time is smaller than the number of bits corresponding to the predetermined number of frequency signals, and the bit sequences that constitute the first set of bit sequences. Rearrangement is performed in parallel with the primary demodulation processing of the second set of frequency signal sequences in the primary demodulation step, and after rearrangement of the bits constituting the first set of bit sequences, the second set of bit sequences The receiving method is characterized by rearranging the bits constituting the. Error correction coding means for performing error correction coding on input information data;
Corresponding by performing a primary modulation on the bit sequence obtained by the error correction coding means without changing the order of the bits of the bit sequence, using a modulation scheme that maps one bit to one modulation symbol. Primary modulation means for obtaining a primary modulation symbol sequence to be
Tone interleaving means for rearranging a predetermined number of primary modulation symbols obtained by the primary modulation means;
Inverse Fourier transform means for inverse Fourier transforming a predetermined number of primary modulation symbols rearranged by the tone interleaving means;
Transmitting means for transmitting the signal obtained by the inverse Fourier transform means;
I have a,
The tone interleaving means includes
In order to obtain the same signal as the second signal obtained by the inverse Fourier transform in the case where it is assumed that the primary modulation is performed after rearranging the bits of the bit sequence in a predetermined method, the first order is obtained. A transmission apparatus characterized by rearranging the predetermined number of primary modulation symbols obtained by a modulation means . Fourier transform means for obtaining a plurality of corresponding frequency signals by collectively Fourier-transforming the received plurality of time signals;
Tone deinterleaving means for rearranging the plurality of frequency signals obtained by the Fourier transform means;
Primary demodulation means for obtaining a corresponding bit sequence by first demodulating the plurality of frequency signals rearranged by the tone deinterleaving means using a demodulation method for mapping one frequency signal to 1 bit;
Error correction decoding means for performing error correction decoding using the bit sequence obtained by the primary demodulation means without changing the arrangement order of the bits constituting the bit sequence ;
I have a,
The tone deinterleaving means is
When it is assumed that the error correction decoding is performed after rearranging the bits of the bit sequence by a predetermined method, the same bit sequence as the second bit sequence obtained by the rearrangement by the predetermined method is obtained by the primary demodulation. As described above , the receiving apparatus performs rearrangement of the plurality of frequency signals obtained by the Fourier transform means . First transforming means for obtaining a corresponding frequency signal by Fourier transforming the received single carrier signal;
Frequency domain equalization means for equalizing the frequency signal;
A second transforming unit that obtains a predetermined number of time signals by collectively performing an inverse Fourier transform on the plurality of frequency signals subjected to the equalization processing;
Primary demodulating means for primarily demodulating a time signal sequence comprising the predetermined number of time signals to obtain a corresponding bit sequence;
Deinterleaving means for rearranging the bits constituting the bit sequence;
In a receiving device having
The second conversion means includes
Inverse Fourier transform means for performing inverse Fourier transform on the plurality of frequency signals together, and symbol interleaving means for rearranging the predetermined number of time signals obtained by the inverse Fourier transform means,
The primary demodulating means separates at least a first set and a second set of time signal sequences from the time signal sequence, performs a primary demodulation process of the first set of time signal sequences, and then performs the second set of time signals. By performing a primary demodulation process of the sequence, a first set and a second set of bit sequences corresponding to the first set and the second set of time signal sequences are obtained,
The deinterleaving means has a bit sequence size that can be rearranged at a time smaller than the number of bits corresponding to the predetermined number of time signals, and performs the rearrangement of the bits of the first set of bit sequences. Performing in parallel with the primary demodulation processing of the second set of time signal sequences in the demodulating means, and after rearranging the bits constituting the first set of bit sequences, the bits constituting the second set of bit sequences A receiving apparatus characterized by performing rearrangement.

Images