JP5315517B2 - Information processing apparatus and virtual circuit writing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive and high performance computer for a large-scaled arithmetic operation which can be used for individuals. <P>SOLUTION: A information processor includes: a memory for storing an application program for performing a prescribed arithmetic operation about an arithmetic object; an arithmetic unit array 40 configured of a plurality of arithmetic units arranged so as to be connected to directly perform data communication between the adjacent arithmetic units correspondingly to each problematic region of the arithmetic object, and configured to transmit/receive arithmetic result data about each problematic region between the adjacent arithmetic units, wherein arithmetic circuits to be used for executing the application program are reconfigured to perform an arithmetic operation corresponding to each problematic region; a host processor for executing the application program, and for acquiring arithmetic result data about each problematic region from each arithmetic unit configuring the arithmetic device array 40, and for calculating the arithmetic result of the arithmetic object; and a bus for communicating data among the memory, host processor and the arithmetic unit array 40. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to an information processing apparatus and an information processing method, and in particular, information processing suitable for application to a computer that performs processing of an enormous amount of calculation using a rewritable programmable logic device (PLD). The present invention relates to an apparatus and a virtual circuit writing method.

  In recent years, a large-scale computing environment has been highly developed, and computation techniques using HPC (high-performance computing) are used in a wide range of fields such as biology, chemistry, astronomy, and engineering. HPC combines a plurality of computer systems and provides a computing environment as one system. Even if the performance of one computer system is low, the entire system can be operated at high speed.

  For example, there is a supercomputer as an example of HPC. Conventionally, a supercomputer has been configured with a dedicated processor and a dedicated architecture. However, as shown in FIG. 1, the supercomputer is configured with an architecture in which a large number of general-purpose microprocessors 1 are connected via a bus 2 and executed in parallel. Things are appearing.

  Some HPCs have a configuration in which ICs (Integrated Circuits) are arranged, such as a grid configuration using a general-purpose PC (Personal Computer) and a grid configuration using a GPGPU (General Purpose Graphics Processing Unit).

  In addition, research that performs high-performance operations, such as FPGAs (Field Programmable Gate Array) and other architectures that are configured in parallel architecture using reconfigurable semiconductor integrated circuits (LSI: Large Scale Integration) Also came to be seen. In particular, cluster-type computers configured for large-scale computation are called RHPC (Reconfigurable High Performance Computing) and HPRCs (High-Performance Reconfigurable Computers). Such reconfigurable hardware is generally called a programmable logic device (PLD) and is widely distributed from a small number of products to mass-produced products.

  For example, the present applicant has proposed a hardware / software (hw / sw) complex using a PCI type FPGA board called a hardware module (hwModule) (see, for example, Patent Document 1). .

  The hw / sw complex uses a hardware module FPGA as a virtual circuit (hwNet) and inherits a class that hides the detailed control of the virtual circuit called a hardware object (hwObject). It is a system that can easily use resources. Features of this hardware / software complex include versatility, parallel distributed processing, and connection to external devices.

  That is, the virtual circuit in the FPGA can be controlled directly from the software, and the problem for each application is calculated by the fastest virtual circuit by writing an appropriate virtual circuit created for the target application in the FPGA. Is possible.

In general, when the same operation is executed by software and a hardware circuit, it is empirically known that execution by the hardware circuit is 30 to several hundred times faster than the case of software. For example, current microprocessors operate at a frequency of 3 GHz, but cheaper FPGAs are the best speed at which 200 MHz operation is normally obtained. Therefore, for the software execution by the microprocessor, the virtual circuit by the FPGA effectively corresponds to the microprocessor operating from 6 GHz (200 MHz × 30) to 20-40 GHz. Furthermore, by adding a plurality of arithmetic circuits in the FGPA, the performance can be improved by a factor of ten, and a performance equivalent to 60 GHz to 400 GHz is expected.
Japanese Patent No. 3845021

  A feature common to the above-described HPC is that an application program is divided into a form that can be executed in parallel, and is assigned to an arithmetic device that can be executed in parallel for execution. Since the HPC having such a configuration is expensive and is used for problem areas with different numbers of people, the HPC has a general configuration, that is, an arbitrary data transfer path can be realized between general-purpose microprocessors. Designed. Conceptually, the microprocessor 1 is connected via a common communication path such as the bus 2 shown in FIG. However, any calculation result is transferred to each distributed microprocessor 2 via the bus 2, and the bus neck becomes a performance bottleneck.

  As described above, in the form as shown in FIG. 1, the overhead of the bus 2, which is a common communication path, increases. Therefore, in order to eliminate the overhead of the bus 2, a switch box 5 as shown in FIG. In the switch box 5, data from an arbitrary microprocessor is selected and sent to the optimum microprocessor. Some use FPGA instead of the microprocessor, but the configuration of the bus 2 and the switch box 5 is the same.

  However, with these methods, the power consumption becomes enormous, and it has been difficult to achieve higher speeds. In addition, in order to realize high speed and low power consumption in the communication path, it is considered to use optical communication capable of broadband data communication, but it becomes expensive. Also, since it becomes an expensive supercomputer, it is difficult to prepare a large number of units from the financial aspect, and it is difficult for many users to make reservations and use them in time division, so there is a problem that the waiting time until use becomes long Has occurred.

  In addition, as for the application example of the hw / sw complex described in Patent Document 1, studies on hwModule network support have been made so far. However, some applications that require large-scale parallelization, such as numerical simulation, require data transfer between computers at a very high speed. The required performance was not met. In other words, data transfer is restricted by the electrical characteristics of the communication path for the improvement of the internal calculation speed, and it has not been possible to obtain an inexpensive and high-speed communication path.

  The present invention has been made in view of such a situation, and makes it possible to provide an inexpensive and high-performance computer for large-scale computation that can be used for personal use.

In the information processing apparatus of the present invention, a plurality of arithmetic devices are arranged in accordance with the structure to be operated, and data is directly transferred between the arithmetic devices without performing a bus at the time of executing the arithmetic, and the arithmetic result is taken out from each arithmetic device. The bus is used only when sending data to the host processor or inputting data from the host processor.
Specifically, an information processing apparatus according to one aspect of the present invention includes a memory, an arithmetic device array, a host processor, and a bus.
The memory stores an application program that performs a predetermined calculation on the calculation target.
The arithmetic device array is composed of a plurality of arithmetic devices. The plurality of arithmetic devices are arranged so as to be directly communicable between adjacent arithmetic devices corresponding to each problem area to be calculated, and are used for executing the application program. An arithmetic circuit that performs an operation corresponding to the area is reconfigured, and operation result data by the arithmetic circuit is transmitted and received between the adjacent arithmetic devices for the problem area.
The host processor previously determines an adjacent computing device as a transfer destination of computation result data for each computing device constituting the computing device array, executes the application program, and configures each computing device array Calculation result data for each problem area is acquired from the calculation device, and the calculation result is calculated for the calculation target.
A bus communicates data between the memory, the host processor, and the computing device array.
Then, virtual circuit data writing for writing the arithmetic circuit to the arithmetic unit based on virtual circuit write data including virtual circuit data corresponding to each problem area to be calculated is sent from the host processor to the arithmetic unit. After writing the circuit and writing the virtual circuit data write circuit, the arithmetic device transfers the virtual circuit write data to the adjacent arithmetic device in accordance with the write order included in the virtual circuit write data.

  According to the information processing apparatus of one aspect of the present invention, a plurality of arithmetic devices are arranged in accordance with the structure to be calculated, and data is directly transferred between the arithmetic devices without interposing a bus when executing the arithmetic operation. Then, the calculation result calculated by each calculation device is taken out and sent to the host processor via the bus. All the arithmetic devices only need to execute the process of transferring data only to the adjacent arithmetic devices, and the data transfer interval is shortened.

Further, the virtual circuit writing method according to one aspect of the present invention is provided for each of a plurality of arithmetic devices arranged so as to be directly communicable between adjacent arithmetic devices corresponding to each problem area to be calculated. Te, based on the virtual circuits write data containing a virtual circuit data corresponding to each of the problem areas of the operation target sent from the host processor, write the virtual circuit data write circuit for writing an arithmetic circuit.
Next, after writing the virtual circuit data write circuit to the arithmetic device, the arithmetic device transfers the virtual circuit write data to the adjacent arithmetic device in accordance with the write order included in the virtual circuit write data.
Next, after the writing of the virtual circuit data writing circuit is completed for all the arithmetic devices, the virtual circuit data writing circuit is the arithmetic device from which the virtual circuit data writing circuit was last written to the first written arithmetic device. Write the arithmetic circuit .

  According to the virtual circuit writing method of one aspect of the present invention, after a virtual circuit data writing circuit for writing an arithmetic circuit is first written to a plurality of arithmetic devices constituting the arithmetic device array, the virtual circuit writing method is performed. The arithmetic circuit is written in all the arithmetic devices from the arithmetic device in which the circuit data writing circuit was last written to the arithmetic device in which the circuit data was written first. Therefore, there is no possibility that the arithmetic circuit cannot be written in the middle.

  As described above, according to the present invention, an inexpensive and high-performance computer for large-scale computation that can be used for personal use can be realized. As a result, even an individual can use a computer that can easily perform a large-scale calculation according to the application, and the waiting time can be reduced.

Hereinafter, an example of the best mode for carrying out the present invention will be described with reference to the accompanying drawings. The explanation will be made in order according to the following items.
1. 1. Concept of arithmetic device array according to one embodiment of the present invention 2. Connection with adjacent computing device Outline of information processing apparatus 4. 4. Overall configuration of information processing apparatus 5. Configuration of host processor 6. Arrangement of arithmetic unit (arithmetic board, writing / input / output board) 7. Arithmetic processing by the arithmetic device array 8. Write processing to arithmetic unit 9. Arithmetic device array according to another embodiment of the present invention Arithmetic device array according to still another embodiment of the present invention

[1. Concept of arithmetic device array according to one embodiment of the present invention]
An information processing apparatus according to the present invention applies a technique described in Patent Document 1 (Japanese Patent Application Laid-Open No. 2003-208311) to an HPC such as a supercomputer, and serves as a basis for performing a large-scale operation in a scalable manner. The PLD array (arithmetic unit array) in which a large number of PLDs are interconnected to each other is reflected. The arithmetic device array has a configuration in which, for example, a large-scale FPGA is mounted as a PLD, and small FPGA cards (arithmetic devices) equipped with a large amount of external IO (input / output units) are arranged in a grid pattern.

  That is, when the calculation object has a one-dimensional, two-dimensional, or three-dimensional structure, adjacent calculation devices are directly connected in accordance with those structures and arranged in one, two, or three dimensions, and the calculation object is generated. The numerical value or its data change is directly transferred to the adjacent arithmetic unit. Therefore, all the arithmetic devices only need to execute the process of transferring data only to the adjacent arithmetic device, and the data transfer section is shortened, so that the data transfer processing is prevented from becoming a bottleneck of the processing capability of the information processing device. To do. Also, power consumption is reduced.

  Since an RC-LSI (Reconfigurable LSI) such as an FPGA can configure a circuit in accordance with a calculation target, a high-performance calculation means using a dedicated circuit can be obtained relatively inexpensively. In the example of the embodiment described below, an example in which an FPGA is used as an arithmetic unit will be described. However, the present invention is not limited to this example as long as it is a reconfigurable PLD in a broad sense, and a CPLD (Complex Programmable Logic Device). ) Etc. can be applied.

FIG. 3 shows an example of a physical or logical structure to be calculated.
The calculation target 6 is a fluid model, a liquid model, or the like, and can take any one-dimensional, two-dimensional, or three-dimensional structure. Specific examples of computation targets include, for example, the ALMA project currently being promoted in the fields of astronomy and physics, gravity wave detection, reactor design in the next generation fusion demonstration reactor, and high energy physics. The internal reaction prediction simulation of the next generation accelerator, various visualization simulations in the earth science field (specifically, visualization of fault models, etc.), and meteorology, the expansion of the simulation field for medium- to long-term forecasts has been raised as requests. Yes. In the aerospace field, there are also demands from fields such as functional design of satellites, simulation at the International Space Station, construction of a base for the future moon, risk simulation in manned Mars exploration.

  For example, one of the equations often used in electromagnetism and semiconductor engineering is the Poisson equation, which is an elliptic partial differential equation. When solving this equation by the difference method, it is necessary to solve simultaneous equations for the number of grid points in the region. The lattice width may be arbitrary, but it is reflected in the accuracy, so how to solve a large simultaneous equation efficiently becomes a problem. In the problem area to be solved, the lattice points increase if the lattice point interval is narrowed, and therefore a large-scale calculation is required.

  The calculation target 6 shown in FIG. 3 is an example of a three-dimensional structure, and when performing calculation processing on the calculation target 6 using the information processing apparatus of the present invention, the calculation target 6 is converted into a plurality of lattice problem areas 6. Divide into -1. In this example, the calculation target 6 is divided into problem areas of 4 (X direction) × 3 (Y direction) × 3 (Z direction) = 36. Then, as shown in FIG. 4, a plurality of arithmetic devices 40-1 are arranged for the calculation target 6 so as to correspond to each problem area 6-1 of the calculation target 6 to constitute the calculation device array 40. . For example, the calculation of individual problem areas 6-1 represented by diagonal lines is performed by the arithmetic unit 40-1 at the corresponding position, also represented by diagonal lines. Therefore, in this example, the arithmetic device array 40 is configured by using the same 36 arithmetic devices 40-1 as the problem area 6-1.

  In each problem area, an interaction with an adjacent problem area is performed, and a physical quantity is propagated to the adjacent problem area, so that corresponding data transfer is performed between adjacent arithmetic devices corresponding to the physical phenomenon. . Specifically, in one problem area, a large number of data to be calculated are on the grid points 6-1A, 6-1B, 6-1C,..., And the calculation by the corresponding calculation device is an area. When the boundary is reached, the calculation result is transferred from the calculation device to the adjacent calculation device.

  As described above, according to the present invention, high-performance data processing capability is maintained by assigning arithmetic devices corresponding to the physical shape and characteristics of the divided problem areas and transferring data directly between adjacent arithmetic devices. Yes.

  On the other hand, in the conventional method, the physical configuration is fixed and the data transfer on the communication path becomes a bottleneck, and the performance of the arithmetic device cannot be sufficiently exerted on the operation target. Also, in normal cases, data transfer between arithmetic devices becomes a bottleneck, and the high-speed performance of the communication path cannot be used. In order to improve it, if the highest performance communication path such as an optical cable is prepared, the entire system must be expensive.

  In the present invention, the communication path for connecting and connecting the arithmetic devices according to the calculation target increases in a scalable manner, so that it is not necessary to use a high-performance and high-priced communication path. In addition, since the data transfer destination is up to an adjacent computing device, the processing load on the communication path is small and the power consumption can be reduced.

[2. Connection with adjacent processing unit]
The information processing apparatus of the present invention is configured so that data can be directly transferred between adjacent arithmetic devices as described above. Hereinafter, the form of connection with this adjacent arithmetic unit will be described with reference to FIGS.

  FIG. 5 is a diagram showing the connector arrangement of the arithmetic device (arithmetic board). FIG. 6 is a diagram showing the interconnection of arithmetic devices (arithmetic boards). FIG. 7 is an exploded perspective view of the arithmetic device.

As shown in FIG. 5 to FIG. 7, the arithmetic device 40-1 in the present embodiment includes a pair of arithmetic boards 50 and a write / input / output board 60 (a write / input board 60 described in the claims). An example of a board).
The arithmetic board 50 includes an FPGA 51 to which an arithmetic circuit or the like (corresponding to an arithmetic circuit described in claims) is mainly written, a memory 52 functioning as a main storage device, and a plurality of connectors (connection terminals). ) Is provided. The write / input / output board 60 includes an FPGA 61 in which a write circuit for writing an arithmetic circuit and the like to the FPGA of the arithmetic board 50 and an input / output circuit for data transfer are written, a memory 62 functioning as a main storage device, and a plurality of The board (60A) on which the connector (connection terminal) is installed. Each connector is provided at a predetermined position on each side of the substrate 50A of the arithmetic board 50 and the substrate 60A of the writing / input / output board 60. Details of functions of the arithmetic board 50 and the writing / input / output board 60 will be described later.

  The arithmetic board 50 can be connected to each other by the plurality of connectors. For example, as shown in FIG. 6, the calculation board 50 is connected to the front connection connector 53 </ b> F directly with the rear connection connector 53 </ b> B disposed in front of the calculation board 50. Data can be directly transferred to the arranged arithmetic board 50. Similarly, the rear connection connector 53B, the left connection connector 53L, the right connection connector 53R, the upper connection connector 53U, and the lower connection connector 53D are respectively connected to the rear, left, It can be connected to the calculation board 50 located on the right, top, and bottom so that data can be directly transferred.

  In addition, the arithmetic board 50 includes a connector 54 for connecting to the writing / input / output board 60. By directly connecting the connector 54 to the connector 64 of the corresponding writing / input / output board 60, data is directly transmitted between the two boards. Enable transfer.

  The arithmetic board 50 is connected directly to the connector in the front-rear and left-right directions to enable high-speed transfer. In addition, the upper and lower terminals of the adjacent connection terminals, that is, the connectors are laid out in the same corresponding locations so as to be suitable for stacking. However, considering the waste heat of each board, it is preferable to connect the upper and lower terminals via a cable instead of being directly connected.

  In the board 60A of the writing / input / output board 60, a cutout 60A1 is formed at a position corresponding to the connector 53D for lower connection of the corresponding computing board 50 in accordance with the shape of the connector 53D. The side where the notch 60A1 of the writing / input / output board 60 is formed is shorter than the length of the side where the connectors 63B and 63F are provided. Through this notch 60A1, the connector 53D for lower connection of the arithmetic board 50 can penetrate the board 50A of the corresponding write / input / output board 60 and can be connected to the arithmetic board 50 arranged therebelow.

  When the notch 60A1 is formed in the writing / input / output board 60, the side where the connectors 63B and 63F are provided is short, so the area of the substrate 60A is reduced, leading to material saving and cost reduction. Since the connector 53D of the arithmetic board 50 only needs to be able to penetrate the writing / input / output board 60, for example, the writing / input / output board 60 having the same area and shape as the arithmetic board 50 is replaced with a through hole instead of the notch 60A1. May be provided.

  In the example shown in FIG. 7, the connectors 53F, 53R, and 54 are male connectors with convex core wire connections, and the connectors 53B, 53L, and 64 are female connectors with concave core wire connections. It is not limited to this example.

[3. Overview of information processing equipment]
Next, an outline of an information processing apparatus using the arithmetic device array having the above-described configuration will be described.

  As described above, the information processing apparatus of the present invention is configured by applying the semiconductor circuit control apparatus described in Patent Document 1. That is, in the present invention, an RC-LSI that is not involved in the internal configuration of a PLD such as an FPGA but that can dynamically rewrite a circuit (a so-called “virtual circuit”) is used. A plurality of RC-LSIs (corresponding to arithmetic units) are arranged in accordance with the structure to be operated, and adjacent RC-LSIs are directly connected to each other to form an arithmetic unit array, thereby forming an RC-LSI. It is configured to be able to transfer data directly without using a bus.

  With this configuration, in the present invention as well as the semiconductor circuit control device described in Patent Document 1, the hardware object model obtained by wrapping virtual circuits with objects has the same appearance as a normal software object. And can be used freely in the program. Following the method of deriving from the objects in the object library, a hardware object library is prepared. Processes suitable for dedicated circuits, such as image recognition and speech recognition processes that place importance on parallelism, and processes that require constant observation, are read out from the library to the RC-LSI and processed as hardware objects. However, since the hardware object is a circuit, the timing and synchronization must be controlled based on a predetermined synchronization signal. In addition, a memory and an RC-LSI are prepared in the arithmetic unit so that the necessary number of objects enclosing the virtual circuit can be secured according to the target of calculation.

FIG. 8 is a diagram showing an overview of an information processing apparatus according to an embodiment of the present invention.
The information processing apparatus according to the present embodiment includes, for example, a host processor 11 including a CPU, a memory 12 that constructs an actual memory space, and a PLD 13 that constructs a virtual circuit space.

  The application (application program) 21 includes a hardware object 26 including a circuit that realizes optimum performance in addition to an object realized by software. The computer that executes the application 21 arranges the software program part of the application on a memory (memory element) 12 that realizes a memory space, and connects this to the host processor 11 that executes the software via a system bus. At the same time, a standard bus connecting a plurality of PLDs 13 is connected to the host processor 11. These buses are collectively referred to as bus 14.

  The PLD 13 is an actual hardware component into which the hardware net 29 of the circuit portion is written when an application is activated and the hardware object 26 is activated during operation. A circuit space is constituted by a large number of LSIs in the same manner as the memory elements. The PLD 13 corresponds to an FPGA (see FIG. 7) mounted on an FPGA mounted on a hardware module 30 described later and an arithmetic device 40-1 constituting the arithmetic device array 40.

  When the application 21 is activated, the application 21 is first arranged in the memory 12. When the processing of the program proceeds and a constructor statement that generates a hardware object (hwObject) 26 is executed, the hardware object 26 is arranged across the memory 12 and the PLD 13 (both as a set). Here, hwObject-1 and hwObject-2 constructor statements are executed to generate two hardware objects 26. The application 21 includes hwObject-1 and hwObject-2. A hardware driver (hwDD) 27 and a hardware net 29 exist corresponding to each hardware object 26. The hardware driver 27 is generated in the memory 12. On the other hand, the hardware net 29 is generated and erasable in the PLD 13 which is a virtual circuit space so that data can be directly transferred.

FIG. 9 is a diagram showing a flow of control outline between the host processor and the hardware network.
Here, the processing continues until a read / write request to the hardware object 26 is transmitted from the application 21 to the hardware network 29 in sequence, and a response is returned. At this time, the hardware net 29 performs a parallel operation. The application 21 instructs the hardware object 26 to execute, and performs the next process, for example, the execution of another hardware object 26 without waiting for a response. A process for checking whether the processing of the hardware net 29 is completed is performed, and the value of the member variable of the hardware object 26 is read. As described above, the parallelism of the hardware object 26, that is, the embedded circuit including the arithmetic circuit can be appropriately used in a form suitable for the parallel processing at the level of the application 21.

The basic operation of the information processing apparatus will be described below.
First, when the application 21 is activated, the OS secures an area necessary for the execution of the application 21 so that the application 21 can exclusively use it, and passes control to the application 21. The startup / initialization program of the application 21 starts up a basic part necessary for communication with the OS such as event management and message management used in the program, and management within the application 21. At this time, the management control part necessary for managing the hardware object 26 is also incorporated into the application part.

  When a statement that generates the hardware object 26 is executed during the operation of the application, the hardware object 26 is generated including a hardware driver 27 that is an IO processing unit in the memory area. At the same time, a hardware net 29 as a circuit is written in the PLD 13 so that the hardware object 26 can be used exclusively. The circuit data of the hardware net 29 is written in the PLD 13 by describing the operation specifications of the hardware net 29 in an operation description language and using a high-level / logic synthesis / placement / wiring tool that is a design automation tool. Circuit data can be created in advance and registered in the circuit library. Here, it can be easily considered that the hardware net 29 is written in advance, the circuit is simply activated when the hardware object 26 is generated, and the circuit writing time is shortened.

  Once created, the hardware object 26 continues to exist until a statement that causes the hardware object 26 to disappear is executed or the application 21 is terminated. When a statement that reads from or writes to the hardware object 26 is executed during the operation of the application 21, if it is a member variable or member function related to the hardware net 29, the statement is sent via the hardware driver 27. IO processing for the hardware net 29 is performed.

[4. Overall Configuration of Information Processing Device "
FIG. 10 is a diagram illustrating an overall configuration of the information processing apparatus.
The information processing apparatus according to the present embodiment includes, for example, a host processor 11, a memory 12 as a main storage device, a hardware module 30 that is a virtual circuit space, and an arithmetic device that performs an operation on each problem area to be calculated. And an array 40.
The arithmetic device array 40 is a kind of hardware module and has a three-dimensional structure in the example shown in FIG. 4, but is represented here in a two-dimensional structure for convenience of explanation. In addition, the host processor 11, the memory 12, and the hardware module 30 can perform high-speed data transfer through a bus 14 of a predetermined standard (PCI standard or the like).

  As shown in the figure, most of the software programs are stored in the memory 12 and executed by the host processor 11. Circuits for various types of control and processing are virtualized and provided as a hardware network (hwNet) in a hardware component named a hardware module 30 placed on the bus 14 and requires a host processor 11 It is temporarily written at the time. Then, a virtual circuit such as an arithmetic circuit is written to the FPGA in each arithmetic device 40-1 of the arithmetic device array 40 by the virtual circuit written in the hardware module 30. The virtual circuit written in the hardware module 30 and each arithmetic unit 40-1 is initialized for erasure or reuse when it becomes unnecessary.

  The details of the generation / deletion procedure will be described later, but are performed by a constructor and a destructor operator in the same manner as a software object. The hardware module 30 and the arithmetic unit array 40 are recognized as memory-type devices, and reading / writing to the hardware object 26 is performed in the same manner as an object created on the memory 12. The hardware module 30 and the arithmetic unit array 40 provide the virtual circuit space in which the hardware object 26 can be freely created as real parts in the same way that an object can be freely created in the memory space. Therefore, in particular, the arithmetic device array 40 prepares a large number of arithmetic devices 40-1 in advance so as to create a large virtual circuit space in accordance with the operation target. The calculation model using the hardware object 26 treats a virtual circuit as an object and provides an interface for embedding a hardware net 29 in the application 21.

  In the present embodiment, a hardware module 30 which is a hardware board as shown in FIG. 10 is introduced as one element constituting the reconfigurable system. For example, the hardware module 30 is configured to connect a standard bus interface (BI) 31, a local memory (LM) 32, a local processor (LP) 33, an FPGA 34, and an input / output interface 35 so that data can be transferred. .

  The LP 33 is configured by an RC-LSI such as an FPGA and controls the hardware module 30. That is, a hardware net (an example of a writing circuit for writing virtual circuit data) is written into the FPGA 34 by the JTAG method while using the LM 32 by the LP 33. The FPGA 34 writes the hardware net 29 (virtual circuit such as an arithmetic circuit) to the FPGA in each arithmetic device 40-1 of the arithmetic device array 40 via the input / output interface 35 and the communication path 36. Each virtual circuit written in each arithmetic device 40-1 of the arithmetic device array 40 functions as a hardware net 29.

  The BI 31 controls communication between the host processor 11 and the hardware net 29 (FPGA 34, arithmetic device array 40) by a hardware driver control instruction to be described later. The hardware module 30 (including the arithmetic device array 40) is recognized as a memory device, and is connected to the bus 14 (for example, PCI) in the same form as the memory and incorporated in the information processing device (computer). At this time, a device driver called a hardware module driver is incorporated into each arithmetic device 40-1 of the arithmetic device array 40 by the OS, and a memory area is allocated. RC-LSIs in a large number of hardware modules (computing device 40-1) constitute a virtual circuit space so that a large number of memory chips constitute a uniform and flat memory space.

  Note that the LP 33 and the FPGA 34 also have a function as an input / output circuit that transfers data transmitted from the host processor 11 to the arithmetic device array 40 and transfers data transmitted from the arithmetic device array 40 to the host processor 11. .

  The virtual circuit data from the host processor 11 is transferred to the FPGA of each arithmetic device 40-1 in the arithmetic device array 40 via the hardware module 30 as shown in FIG. A hardware net 29 can be arranged in each of 40-1. Although details will be described later, for example, the output of the first hwNet-1 written in the FPGA 51 of the arithmetic device “00” is transferred to the arithmetic device “01”, and the output is transferred to the hwNet− written in the FPGA 51 of the arithmetic device “01”. When 2 is read, hwNet-1 and hwNet-2 (see FIG. 8) can operate simultaneously to perform pipeline processing.

  Further, the load on the host processor 11 can be reduced by the LP 33. That is, the hardware network 29 that is frequently used and written to the FPGA 51 of each arithmetic unit 40-1 can be written by sending a write command to the LP 33 through the BI 31.

[5. Host processor configuration]
FIG. 11 shows a hierarchical configuration diagram of the host processor.
The host processor 11 includes an application 21, an object manager 22, a hardware module driver 23, an OS 24, and a bus 25. In this example, an example including three applications 21 is shown, but an appropriate number of applications can be provided. Each application 21 includes a set of one or a plurality of hardware objects 26, a hardware driver 27, and an interface 28 that controls input / output between the application 21 and the hardware driver 27.

  Each hardware driver 27 is defined for each hardware net 29 and controls input / output operations of the hardware net 29 (via the hardware module 30). The hardware driver 27 includes, for example, hwNet terminal information, hwNet control information such as write / read, enable, output enable, hwObject number, hwNet number, hwModule (arithmetic unit) number, and assigned PLD number (arithmetic unit). (It is not necessary when the device and hwModule correspond one-to-one), hwNet allocation terminal number, local (local) memory allocation address, local memory allocation area size, hwNet status, hwNet command, hwNet communication area address in main memory, hwNet communication Communication control information such as area size and hwNet communication area current address is incorporated. These pieces of information are stored in the hardware net library together with the hardware net circuit information. When the hardware object 26 is generated and the hardware net 29 is loaded, the hwModule (arithmetic unit) number, hwNet number, PLD number, etc. are obtained and the hardware driver 27 is one of the hardware objects 26. Is generated as a part.

  When the hardware module 30 and the arithmetic unit array 40 are incorporated into an information processing apparatus (computer), the hardware module driver 23 shown in the figure is permanently stored in the OS 24 as a device driver based on the attached device information. Registered in The hardware module driver 23 controls communication with the hardware module 30 connected to the computer bus. For example, when a PCI bus is used as the bus 14, PCI device information and the like are allocated from the OS. Whenever the information processing apparatus is started up, the hardware module driver 23 is incorporated in advance in the OS. On the other hand, contrary to the hardware module driver 23, the hardware driver 27 of the hardware object 26 is incorporated into the hardware module driver 23 only when the hardware net 29 exists. The OS 24 does not sense the hardware driver 27. On the other hand, the hardware object 26 side views the hardware driver 27 as a device driver incorporated in the OS, and accesses the hardware net 29. At this time, it is not necessary to consider which hardware module 30 and the arithmetic unit array 40 are accessed.

  As described above, in the present invention, the OS 24 side can stably control and monitor as a device driver in which the hardware module driver 23 is always incorporated, so that the stability of the system can be guaranteed. it can. On the other hand, since the hardware driver 27 is assigned only when necessary from the application 21 side, the degree of freedom to use the hardware net 29 is greatly increased.

[6. Arithmetic unit (arithmetic board, writing / input / output board) configuration]
FIG. 12 is a block diagram illustrating functions after the virtual circuit is written in the arithmetic device (arithmetic board, writing / input / output board). Hereinafter, the arithmetic board 50 and the writing / input / output board 60 will be described in this order with reference to FIG.

  The arithmetic board 50 includes at least an FPGA 51 in which a virtual circuit space is formed and a memory 52 in which a memory space is formed. The memory 52 temporarily stores virtual circuit data and calculation target data corresponding to the problem area to be calculated, transmitted from the host processor 11 via the hardware module 30, and calculation result data by each circuit. . In addition, the memory 52 temporarily stores information that is not necessary for calculation, such as information regarding lattice points that are not being calculated in a certain problem area.

  The internal structure of the FPGA is well known. For example, a large number of logic blocks consisting of combinational circuits and sequential circuits of about 4 inputs that can form any logic are arranged in a grid, and the wiring between them is connected with a simple switch block. Then, a virtual circuit having a desired function is reconfigured by switching the switch. Then, data is input through the input / output block I / O, the operation result is output, and the like by the logic block in which the virtual circuit is reconfigured.

  The FPGA 51 in this embodiment includes a memory control circuit 55, a parallel operation circuit 56 (an example of an operation circuit), an operation target data input / output circuit 57, an operation result data input / output circuit 58, and adjacent FPGA data transfer circuits 59X, 59Y, and 59Z. A circuit including is written. All the circuits including the parallel arithmetic circuit 56 are written by the FPGA 61 mounted on the write / input / output board 60. Hereinafter, these circuits including the arithmetic circuit are collectively referred to as “arithmetic circuit and the like”.

  The memory control circuit 55 is a circuit that reads and writes various data stored in the memory 52 and realizes data transfer between the memory 52 on the arithmetic board 50 and each virtual circuit.

  The parallel arithmetic circuit 56 includes a plurality of logic blocks 56A, 56B,... And performs an operation corresponding to the problem area to be calculated. For example, when the operation target is a continuous physical problem, a parallel circuit is reconstructed that calculates simultaneous equations obtained by discretizing differential equations defined on each lattice point in the problem area. Further, when the operation target is indicated by a multi-branch and a graph structure, a parallel circuit that performs calculation while following the node branch is reconfigured.

The physical quantity f at the lattice point (i, j, k) in the problem area is expressed by the following formula when the calculation target is three-dimensional, and an equation given by the physical quantity on the adjacent grid can be defined.
f (i, j, k) = F (i-1, j-1, k-1, i, j, k, i + 1, j + 1, k + 1)

Now, assuming that the number of grid points on one side of the problem area is N, the number of grid points in the problem area increases three-dimensionally, but increases two-dimensionally at the boundary surface. It is proportional to the third power (˜N ³ ) and proportional to 6 / N ² at the boundary surface. Therefore, the grid point / boundary surface (˜N ³ / 6N ² ) = N / 6 with respect to the calculation amount. Therefore, in order to balance the amount of calculation between the two and the calculation means, the number of the boundary planes for the parallel calculation circuits for N lattice points may be N / 6 or more. For example, if the logical block 56A corresponds to a lattice point in the area and the logical block 56B corresponds to a boundary surface, the number of logical blocks 56A is set to N / 6 or more of the number of logical blocks 56B.

  The calculation target data input / output circuit 57 is a circuit to which calculation target data sent from the hardware module 30 under the control of the host processor 11 is input via the write / input / output board 60. The input operation target data is stored in the memory 52 via the memory control circuit 55 and used for processing by the parallel operation circuit 56 and the like. The calculation target data includes parameters used for calculation, such as a calculation target range, a problem area, a calculation result transfer destination, calculation conditions, and the like.

  Note that the parameters (calculation conditions, calculation targets, problem areas, etc.) of the calculation target data may be changed while being stored in the memory 52, that is, at the stage of being sent from the host processor 11. In such a case, the calculation target data input / output circuit 57 adds the address information storing the calculation target data in the memory 52 to the calculation target data stored halfway in the memory 52, and transmits the result to the host processor 11. You may do it. In such a case, the host processor 11 compares the calculation target data after the change of each arithmetic device with the calculation target data returned from each arithmetic device, and applies the calculation only for the arithmetic target data that has been truly changed. Since retransmission to the apparatus is sufficient, it is possible to save communication path resources and reduce the time required for retransmission processing.

  The calculation result data input / output circuit 58 stores calculation result data after completion of calculation by the parallel calculation circuit 56 of the calculation board 50 or data such as parameters used for calculation in the memory 52 via the memory control circuit 55. And a circuit for transmitting to the corresponding writing / input / output board 60. In addition to the calculation result by the parallel calculation circuit 56, the calculation result data includes the number of the calculation board (arithmetic unit), each lattice point information of the problem area, calculation result data corresponding to the calculation point data, and the like. The calculation result data is transferred to a predetermined adjacent calculation board based on the “calculation result transfer destination” included in the calculation target data.

  Note that the calculation may be stopped halfway due to a change in the parameter of the calculation target data being calculated or a change in the simulation method. In such a case, the calculation result data input / output circuit 58 adds the address information storing the calculation result data in the memory 52 to the calculation result data stored in the memory 52 halfway, and transmits the result to the host processor 11. You may do it. In this case, the host processor 11 can analyze the calculation target by using the calculation results up to the middle of each calculation device. Furthermore, the calculation result up to that point may be read from the host processor 11 (memory 12). As a result, it is possible to use the result of the calculation performed halfway, so that only the part that needs a new calculation needs to be calculated, and the time required for the calculation can be shortened.

  The adjacent FPGA data transfer circuit 59 </ b> X is a circuit that transmits / receives data to / from the operation board 50 adjacent in the X direction (front and rear) via each connector and transfers the data to the parallel operation circuit 56. In the data exchanged with the adjacent calculation board 50, in addition to the calculation result by the adjacent calculation board 50, the number of the calculation board (arithmetic unit) of the transmission source is realized in order to realize transmission / reception of data across the region boundary. , Each piece of grid point information and corresponding calculation result data are included. Similarly, the adjacent FPGA data transfer circuit 59Y transmits and receives data to and from the operation board 50 adjacent in the Y direction (left and right), and the adjacent FPGA data transfer circuit 59Z transmits and receives data to and from the operation board 50 adjacent in the Z direction (up and down). The data transfer from each adjacent FPGA data transfer circuit 59X, 59Y, 59Z to the adjacent arithmetic unit 40-1 is based on the clock signal (CLK) sent from the host processor 11 via the hardware module 30. The timing is adjusted by the device 40-1.

  Next, the writing / input / output board 60 will be described. As shown in FIG. 6, in order to connect adjacent arithmetic boards 50 and write an arithmetic circuit or the like to a rewritable semiconductor device, a writing circuit for writing is necessary.

  The writing / input / output board 60 includes at least an FPGA 61 in which a virtual circuit space is formed and a memory 62 in which a memory space is formed. The memory 62 stores virtual circuit data and calculation target data corresponding to the problem area to be calculated transmitted from the host processor 11 via the hardware module 30, calculation result data transmitted from the calculation board 50, Circuit operation result data and the like are temporarily stored.

  The FPGA 61 in the present embodiment is controlled by the FPGA 34 of the hardware module 30 under the control of the memory control circuit 65, the write circuit 66 (an example of a virtual circuit data write circuit), a virtual circuit data input / output circuit 67, and various data inputs / outputs. Circuit 68 is written. In the following, various data input / output circuits 68 may be included in the “arithmetic circuit and the like”.

  The memory control circuit 65 is a circuit that reads and writes various data stored in the memory 62 and realizes data transfer between the memory 62 on the writing / input / output board 60 and each virtual circuit.

  The write circuit 66 is a circuit that writes each virtual circuit to the FPGA 51 of the calculation board 50 based on the virtual circuit data corresponding to the problem area to be calculated transmitted from the hardware module 30 under the control of the host processor 11. . Depending on the contents of instructions from the host processor 11, the virtual circuit to be written to the FPGA 51 of each arithmetic board 50 may be changed for each problem area, or the virtual circuit has the same logical configuration and is different for each problem area by changing the operation target parameter. In some cases, an operation result is obtained.

  The virtual circuit data input / output circuit 67 is a circuit that controls to input virtual circuit data transmitted from the hardware module 30 and to transfer the virtual circuit data to a designated write / input / output board 60.

  The various data input / output circuits 68 receive virtual circuit data and calculation target data sent from the hardware module 30 and store them in the memory 62 via the memory control circuit 65 or transfer them to the corresponding calculation board 50. It is a circuit to do. In addition, this is a circuit for transmitting calculation result data of a problem area, calculation result data of each circuit, and the like sent from the corresponding calculation board 50 to the host processor 11 via the hardware module 30.

  Note that the writing circuit 66 and the virtual circuit data input / output circuit 67 of the writing / input / output board 60 may be erased when the writing of the arithmetic circuit or the like to the corresponding arithmetic board 50 is completed. In this case, resources of the FPGA 61 of the write / input / output board 60 can be saved. Of course, the write circuit 66 and the virtual circuit data input / output circuit 67 may be left as long as there are still sufficient resources even if various data input / output circuits 68 are written in the FPGA 61.

[7. Arithmetic processing by arithmetic device array]
Next, the outline of the arithmetic processing will be described by taking the arithmetic device array 40 shown in FIG. 10 as an example.
As a premise, a virtual circuit which is hwNet29 is arranged on the arithmetic board 50 and the writing / input / output board 60 of each arithmetic device 40-1 constituting the arithmetic device array 40 according to the problem area to be operated by each (see FIG. 12). ) Is written. The order in which the calculations are performed is determined based on the physical phenomenon or characteristics to be calculated. Here, the calculation is started from the calculation device “00”, the calculation device “10”, and the calculation device “20” and moved in the horizontal direction in order, the terminal calculation device “03”, the calculation device “13”, the calculation device Assume that the calculation is terminated at “23”.

  The initial values of the parameters to be calculated for each problem area to be calculated are assigned to the calculation boards 50 of the 12 calculation devices constituting the calculation device array 40, that is, the calculation devices “00” to “23”. The data is input and temporarily stored in the memory 52. Further, the memory 52 stores information on “transfer destination of calculation results” to be transferred by the calculation device.

  The parallel arithmetic circuit 56 (see FIG. 12) in the arithmetic board 50 of the arithmetic devices “00”, “10”, and “20” receives an instruction from the host processor 11 input via the hardware module 30, Alternatively, calculation is started for each corresponding problem area at a timing triggered by a predetermined signal or condition. Each generated calculation result data is stored in each memory 52.

  Subsequently, each of the arithmetic devices “00”, “10”, “20” uses the operation result data stored in the memory 52 as a clock signal (CLK) transmitted by the host processor 11 (or a clock generation unit (not shown)). Synchronously, from the adjacent FPGA data transfer circuit 59X (see FIG. 12) to the calculation devices “01”, “11”, and “21”, which are “transfer destinations of calculation results”, respectively, via the connector 53R (see FIG. 7). Forward.

  In the arithmetic devices “01”, “11”, and “21”, each adjacent FPGA data transfer circuit 59X receives the operation result data from the arithmetic devices “00”, “10”, and “20” via the connector 53L. Then, using the received calculation result data, the calculation target parameter value, and the calculation result at the previous calculation time stored in each calculation device, the parallel calculation circuits of the calculation devices “01”, “11”, and “21” are used. 56 generates new calculation result data and stores them in the respective memories 52.

  Similarly, the arithmetic devices “01”, “11”, and “21” transfer the respective arithmetic result data to the arithmetic devices “02”, “12”, and “22” according to the information of “calculation result transfer destination”. To do. In the calculation devices “02”, “12”, and “22”, the calculation result data and calculation target parameter values received from the calculation devices “01”, “11”, and “21”, and the calculation devices are stored in each calculation device. The parallel calculation circuit 56 generates new calculation result data using the calculation results at the previous calculation time, and stores them in the respective memories 52.

  The arithmetic devices “02”, “12”, and “22” transfer the respective arithmetic result data to the arithmetic devices “03”, “13”, and “23” according to the information of “calculation result transfer destination”. In the arithmetic devices “03”, “13”, and “23”, each arithmetic result data and arithmetic target parameter value received from the arithmetic devices “02”, “12”, and “22” are stored in each arithmetic device. Using the calculation results at the past calculation time, the parallel calculation circuits 56 of the calculation devices “03”, “13”, and “23” generate new calculation result data and store them in the respective memories 52.

  After the arithmetic processing is completed in all the arithmetic devices “00” to “23”, processing for transmitting the operation result data to the host processor 11 is executed. First, the parallel arithmetic circuit 56 in each arithmetic board 50 of the arithmetic device “00” to the arithmetic device “23” generates arithmetic result data for the problem area in charge, and then outputs the arithmetic result data to the arithmetic result data input / output circuit 58. To the corresponding write / input / output board 60 via the connector 54.

  In each of the writing / input / output boards 60 of the arithmetic devices “00” to “23”, various data input / output circuits 68 receive the arithmetic result data from the corresponding arithmetic board 50 via the connector 64. The various data input / output circuits 68 transfer the received calculation result data to the hardware module 30 through the communication path 36 in synchronization with the clock signal (CLK).

  In the hardware module 30, calculation result data received from the calculation devices “00” to “23” of the calculation device array 40 is sent from the FPGA 34 to the local processor 33. The local processor 33 transfers operation result data from the standard bus interface 31 to the host processor 11 via the bus 14.

  The host processor 11 that has acquired the operation result data for each problem area from each of the operation devices 40-1 constituting the operation device array 40 performs the operation of the entire operation object based on the operation device number corresponding to the operation result data. Run. Then, the physical structure, logical structure, characteristics, etc. of the entire operation target as shown in FIG. 3 are analyzed and output to a display device (not shown).

  According to the arithmetic device 40-1 including the arithmetic board 50 and the writing / input / output board 60 having the above-described configuration, the arithmetic result data obtained by the arithmetic board 50 of the arbitrary arithmetic device 40-1 is used as the arithmetic board of the adjacent arithmetic device 40-1. 50 directly. In other words, data transfer for computation does not go through the bus.

Further, the bus is only used when the calculation result data and the like by the respective calculation devices 40-1 of the calculation device array 40 are taken out and transmitted to the host processor 11 and when virtual circuit data and calculation target data are received from the host processor 11. (For example, bus 14) is used.
With this configuration, it is possible to avoid the data transfer process between the adjacent arithmetic devices 40-1 from becoming a bottleneck of the processing capability of the information processing device.

  It should be noted that the transfer of the operation result data from each operation device of the operation device array 40 to the host processor 11 is performed in conjunction with the process of storing the operation result data in the memory after the operation of the problem area is completed in each operation device. It is good to make it. In this case, since the operation result data is transferred to the host processor 11 in order from the operation device that has completed the operation, data congestion is suppressed, and overhead in each communication path including the bus 14 is reduced. be able to.

  According to the information processing apparatus prototyped by the present applicant, when an arithmetic unit array is configured using 128 sets of arithmetic units, about 0.7 teraflops (TFLOPS) is achieved.

[8. Write processing to arithmetic unit]
Next, with reference to FIG. 13 and FIG. 14, the writing process of the arithmetic circuit etc. with respect to each arithmetic unit which comprises an arithmetic unit array is demonstrated. FIG. 13 is a flowchart showing write processing such as an arithmetic circuit. FIG. 14 shows a state transition at the time of writing processing such as an arithmetic circuit.

  As shown in FIG. 10, the first write circuit is on the host processor 11, and virtual circuits such as arithmetic circuits are written to the arithmetic devices 40-1 of the arithmetic device array 40 from the host processor 11 step by step. . However, if the writing circuit is not configured in the virtual circuit, the virtual circuit cannot be written in the next stage (adjacent) arithmetic unit 40-1. On the other hand, since a writing circuit is unnecessary at the time of calculation, it is desirable to delete it when writing of the virtual circuit is completed. Therefore, it is necessary to write a writing circuit or a connection circuit for writing to all the arithmetic devices 40-1 so that writing is possible, and then replace the terminal arithmetic device 40-1 with an arithmetic circuit or the like. is there. This process is performed by software operating on the host processor 11 along the flow shown in FIG.

  First, the host processor 11 transmits virtual circuit write data based on the operation target stored in the memory 12 to the hardware module 30 via the bus 14 and the standard bus interface 31 (step S1). The virtual circuit writing data includes at least information on “number of arithmetic unit” corresponding to each problem area to be calculated, “virtual circuit data” corresponding to the number, and “write order”. At this stage, the virtual circuit is not written in the arithmetic board 50 and the writing / input / output board 60 constituting the arithmetic device 40-1 (FIG. 14A).

  The host processor 11 writes the virtual circuit write data to the local processor 33 made of FPGA in the hardware module 30 (step S2).

  The local processor 33 in which the virtual circuit write data is written writes the virtual circuit write data into the FPGA 34 for controlling the arithmetic device array in the hardware module 30 (step S3).

  The FPGA 34 to which the virtual circuit write data is written transmits the virtual circuit write data to the predetermined arithmetic device 40-1 of the arithmetic device array 40 through the input / output interface 35 and the communication path 36 (step S4).

The FPGA 34 reconfigures the write circuit 66 and the virtual circuit data input / output circuit 67 based on the virtual circuit data in the FPGA 61 of the write / input / output board 60 of the arithmetic device 40-1. Further, various data input / output circuits 68 are reconfigured. In the write / input / output board 60 in which the write circuit 66 and the virtual circuit data input / output circuit 67 are written, the input virtual circuit write data is input to the adjacent arithmetic device 40 in accordance with the write order included in the virtual circuit write data. 1 is transferred to the write / input / output board 60 (step S5). At this time, the write circuit 66 and the virtual circuit data input / output circuit 67 are written in the write / input / output board 60 (FIG. 14B).

  Referring to FIG. 10 as an example, as an example, the writing circuit 66 etc. in the order of the arithmetic device “00” → the arithmetic device “10”, “01” → the arithmetic devices “20”, “11”, “22” →. Will be written. In the example shown in FIG. 10, the arithmetic devices are arranged in two dimensions. However, if the arithmetic devices are arranged in three dimensions, the writing process may be developed in three dimensions.

  Each time the host processor 11 writes the write circuit 66 or the like to the write / input / output board 60, the host processor 11 acquires an end signal (flag) indicating the completion of writing from the write / input / output board 60 for operation confirmation. Then, the host processor 11 determines whether or not the reconfiguration of the write circuit and the like has been completed for the write / input / output boards 60 of all the arithmetic devices 40-1 (step S6).

  If writing by the writing circuit 66 or the like has not been completed for all the writing / input / output boards 60, the processing returns to step S5 and the writing processing is continued.

  On the other hand, when writing is completed for all the writing / input / output boards 60, the writing circuit 66 of the writing / input / output board 60 at the end of the computing device array 40 is connected to the FPGA 51 of the corresponding computing board 50, such as the parallel computing circuit 56, A virtual circuit (see FIG. 12) is written (step S7).

Then, the write circuits 66 corresponding to all the write / input / output boards 60 are connected to the FPGA 51 of the corresponding write calculation board 50 according to the write order information included in the input virtual circuit write data, and the virtual circuits such as the parallel calculation circuit 56. Are written (step S8).

  For example, the parallel arithmetic circuit 56 is replaced in the order of the arithmetic device “23” → the arithmetic device “22”, “13” → the arithmetic devices “21”, “12”, “03” →. In the example shown in FIG. 10, the arithmetic devices are arranged in two dimensions. However, if the arithmetic devices are arranged in three dimensions, the writing process may be developed in three dimensions.

  The host processor 11 acquires an end signal (flag) indicating completion of writing from the arithmetic board 50 each time the parallel arithmetic circuit 56 or the like is written to the arithmetic board 50. Based on the end signal, the host processor 11 determines whether or not the writing of the parallel arithmetic circuit 56 and the like has been completed for the arithmetic boards 50 of all the arithmetic devices 40-1 (step S9).

  If writing has not been completed for all the arithmetic boards 50, the processing returns to step S8, and the writing processing of the parallel arithmetic circuit 56, etc. is continued.

  On the other hand, when the writing is completed for all the arithmetic boards 50, the writing of the virtual circuit to the arithmetic device 40-1 of the arithmetic device array 40 is ended. At this time, the writing circuit 66 and the virtual circuit data input / output circuit 67 are written in the writing / input / output board 60, and the parallel arithmetic circuit 56 is written in the arithmetic board 50 (FIG. 14C).

  Since it takes approximately 40 ms to rewrite one arithmetic device, the entire arithmetic device array can be rewritten in a few seconds.

  Since the FPGA is a gate array, the number of gates is limited. In addition, since a writing circuit is unnecessary at the time of calculation, it is desirable to delete it when the writing of the virtual circuit is completed. Therefore, while the parallel arithmetic circuit 56 and the like are written to the arithmetic board 50, the virtual circuit data writing circuit is written and input sequentially from the arithmetic device 40-1 written last to the arithmetic device 40-1 written first. The write circuit 66 and the virtual circuit data input / output circuit 67 written in the FPGA 61 of the output board 60 are erased. At this time, various data input / output circuits 68 are written in the write / input / output board 60, and the parallel arithmetic circuit 56 and the like are written in the arithmetic board 50 (FIG. 14D).

  Further, the write circuit 66 and the virtual circuit data written in the FPGA 61 of the write / input / output board 60 are sequentially written from the arithmetic device 40-1 in which the virtual circuit data write circuit is written last to the arithmetic device 40-1 in which the virtual circuit data is written first. Although the input / output circuit 67 is erased, the present invention is not limited to this example. That is, it is only necessary for the host processor 11 to confirm whether or not the write operation of the arithmetic circuit or the like is normal for all the arithmetic devices 40-1, and in an appropriate order, the write circuit 66 of the write / input / output board 60 and the virtual circuit data input / output The circuit 67 may be deleted.

  Further, in the above-described example, the virtual circuit data input / output circuit 67 and the various data input / output circuits 68 are separately configured, but may be integrally configured as a data transfer circuit or the like.

FIG. 15 shows the state of the arithmetic device array after writing a virtual circuit such as an arithmetic circuit.
In this example, the arithmetic board 50-1 of the first arithmetic device and the arithmetic board 50-2 of the second arithmetic device adjacent to each other are connected and adjacent to the write / input / output board 60-1 of the first arithmetic device. The write / input / output board 60-2 of the second arithmetic unit is connected. It is assumed that the first arithmetic device is connected to the hardware module 30 (host processor 11 side) via a hardware module.

  Calculation result data generated by the parallel calculation circuit 56 of the calculation board 50-1 of the first calculation device is transmitted from the various data input / output circuits 68 of the corresponding write / input / output board 60-1 to the hardware module 30. Then, the data is transferred from the hardware module 30 to the host processor 11 via the bus 14.

  On the other hand, the operation result data generated by the parallel operation circuit 56 of the operation board 50-2 of the second operation device is first sent from the various data input / output circuits 68 of the corresponding write / input / output board 60-2 to the host processor 11 side. Is sent to the write / input / output board 60-2 of the second arithmetic unit close to Then, the calculation result data of the second arithmetic unit is transmitted to the hardware module 30 via the communication path 36 by the various data input / output circuits 68 of the writing / input / output board 60-2, and the hardware module 30 To the host processor 11 via the bus 14.

  In this example, for the sake of convenience of explanation, the processing for transferring the calculation result data between two adjacent arithmetic devices has been described. However, even between a larger number of arithmetic devices or a plurality of arithmetic devices arranged in three dimensions. The basics of technical thought are the same.

  According to the present embodiment configured as described above, if all the arithmetic devices (FPGA, etc.) constituting the arithmetic device array execute processing for transferring data such as arithmetic results only to adjacent arithmetic devices. In many cases, it is possible to avoid the data transfer process from becoming a bottleneck of the processing capability of the information processing apparatus.

  In addition, since the conventional arithmetic unit performs all data transfer via the bus, the power consumption becomes enormous, which has been an obstacle to realizing high-speed data transfer. Since the data transfer between the arithmetic devices is performed by the connector direct connection without using the bus, the power consumption can be reduced as compared with the case of using the bus.

  Conventionally, optical communication has been used in order to realize high speed and low power consumption in a communication path. However, in this embodiment, improvement in processing capability and low consumption are achieved without using optical communication. Since power is realized, an information processing apparatus for large-scale computation can be provided at a low cost. Therefore, even an individual can use a computer for large-scale computation without waiting for a reservation.

[9. Arithmetic device array according to another embodiment of the present invention]
In the arithmetic device array 40 having a three-dimensional structure, as shown in FIG. 12, the arithmetic board 50 of one arithmetic device 40-1 has three pairs of adjacent FPGA data transfer circuits. By electrically changing the connection destination of the adjacent FPGA data transfer circuit, the two-dimensional area can be folded into the three-dimensional area. That is, by electrically controlling each arithmetic device of the arithmetic device array configured in three dimensions, it can be used as a two-dimensional or three-dimensional arithmetic device array.

  For example, the arithmetic device array 70 shown in FIG. 16 has a configuration in which four arithmetic device arrays 71, 72, 73, and 74 arranged in the XY region are sequentially connected. It is possible to change the direction of the XY region in the Z direction by connecting to the Z direction computing device in the terminal computing device, for example, the X end computing device, and proceed in the reverse direction in the upper layer computing device array.

  That is, the arithmetic devices 71-1, 71-2, 71-3 located at the X end of the arithmetic device array 71 and the arithmetic devices 72-10, 72-11 located at the X end of the corresponding lower arithmetic device array 72. , 72-12 are connected by a cable 76. On the other hand, in the relationship between the arithmetic device array 72 and the arithmetic device array 73, the X end on the opposite side of the connecting portion between the arithmetic device array 71 and the arithmetic device array 72 is connected. Similarly, in the relationship between the arithmetic device array 73 and the arithmetic device array 74, the X end on the opposite side of the connecting portion between the arithmetic device array 72 and the arithmetic device array 73 is connected.

  As a result, the arithmetic device array 71 in the uppermost layer passes through the arithmetic device array 72 and the arithmetic device array 73 from the arithmetic devices 74-1, 71-2, 71-3 in the arithmetic device array 74 in the lowermost layer. The arithmetic devices 71-10, 71-11, 71-12 are connected in two dimensions, and the arithmetic device array 70 can be configured in a two-dimensional region.

  These connection modes are determined by the host processor 11 according to the operation target. In other words, the host processor 11 determines which of the plurality of arithmetic devices constituting the arithmetic device array is to be connected, and sends the determined item to each arithmetic device as the “transfer destination of the arithmetic result”. To do.

  In this way, even in an arithmetic device array physically arranged in three dimensions using a connector, it is possible to perform an operation by convolving a problem area that is a lower-order (two-dimensional, one-dimensional) calculation target. By writing a desired arithmetic circuit or the like in each arithmetic device, the connection can be electrically changed without changing the physical connection with the adjacent arithmetic device.

[10. Arithmetic device array according to still another embodiment of the present invention]
Next, an arithmetic device array in the case where the operation target satisfies the periodic boundary condition will be described.
When the calculation target satisfies the periodic boundary condition, a plurality of hardware nets constituting the arithmetic device array, that is, the arithmetic devices located at the periodic boundary among the arithmetic devices are electrically connected to form a torus shape (ring) To do.

  For example, in the two-dimensional arithmetic unit array 80 shown in FIG. 17, the final stage arithmetic units 80-10, 80-11, and 80-12 corresponding to the periodic boundary and the first stage arithmetic unit 80 corresponding to one periodic boundary. −1, 80-2, 80-3 are electrically connected via the connector 81. At this time, it is a matter of course that the connector of each arithmetic device is applied using flexible wiring so that the delay time generated between the arithmetic devices is the same. In this way, the operation result data of each of the arithmetic devices 80-10, 80-11, and 80-12 is repeatedly returned to the arithmetic devices 80-1, 80-2, and 80-3 that perform the operation first. Can be processed. In the example shown in FIG. 17, the case where the two-dimensional periodic boundary condition is satisfied has been described, but it is needless to say that the present invention can also be applied when the three-dimensional periodic boundary condition is satisfied.

  The embodiment described above is a specific example of a preferred embodiment for carrying out the present invention, and therefore various technically preferable limitations are given. However, the present invention is not limited to these embodiments unless otherwise specified in the above description of the embodiments. Therefore, for example, the materials used in the above description, the amount used, the processing time, the processing order, and the numerical conditions of each parameter are only suitable examples, and the dimensions, shapes, and The arrangement relationship and the like are also schematic showing an example of the embodiment. Therefore, the present invention is not limited to the above-described embodiments, and various modifications and changes can be made without departing from the scope of the present invention.

  For example, in the arithmetic device 41-1 shown in FIG. 12, the arithmetic board 50 and the write / input / output board 60 are provided with the memory 52 and the memory 62, respectively, but these may be replaced by one. For example, the memory 62 may not be mounted and only the memory 52 may be used. A large-scale memory board may be prepared instead of the memory 52 and the memory 62, or a large-capacity recording device such as a hard disk may be provided.

It is a block diagram which shows the outline | summary of the conventional system. It is the schematic where it uses for description of a switch box. It is a schematic diagram which shows an example of a calculation object. It is the schematic which shows the arithmetic unit array which concerns on one embodiment of this invention. It is a figure which shows connector arrangement | positioning of the arithmetic unit (arithmetic board) which concerns on one embodiment of this invention. It is a figure where it uses for description of the interconnection of the arithmetic unit (arithmetic board) which concerns on one embodiment of this invention. It is a disassembled perspective view of the arithmetic unit which concerns on one embodiment of this invention. It is a figure which shows the outline | summary of the information processing apparatus which concerns on one embodiment of this invention. It is a figure which shows the control outline between the host processor which concerns on one embodiment of this invention, and a hardware network. It is the schematic which shows the whole structure of the information processing apparatus which concerns on one embodiment of this invention. It is a block diagram which shows the hierarchy of the host processor which concerns on one embodiment of this invention. It is a block diagram which shows the function of the arithmetic unit (arithmetic board, write / input / output board) which concerns on one embodiment of this invention. It is a flowchart which shows write-in processing of arithmetic circuits etc. which concern on one embodiment of this invention. AD is a figure which shows the state transition at the time of writing of arithmetic circuits etc. which concern on one embodiment of this invention. It is a figure which shows the state after writing of the arithmetic circuit etc. which concern on one embodiment of this invention. It is a figure which shows the arithmetic unit array in the case of convolving a two-dimensional area | region with the three-dimensional area | region which concerns on other embodiment of this invention. It is a figure which shows the arithmetic unit array in the case of satisfy | filling the periodic boundary conditions based on further another embodiment of this invention.

Explanation of symbols

  6-1A to 6-1C ... lattice points, 11 ... host processor, 12 ... memory, 13 ... PLD, 14 ... bus, 21 ... application, 22 ... object manager, 23 ... hardware module driver, 25 ... bus , 26 ... hardware object, 27 ... hardware driver, 28 ... interface, 29 ... hardware net, 30 ... hardware module, 31 ... standard bus interface, 32 ... local memory, 33 ... local processor, 34 ... FPGA, 35 ... I / O interface, 36 ... communication path, 40 ... arithmetic unit array, 40-1 ... arithmetic unit, 50 ... arithmetic board, 51 ... FPGA, 52 ... memory, 53F, 53B, 53L, 53R, 53U 53D, 54 ... connector, 55 ... memory control circuit 56 ... Parallel operation circuit, 56A, 56B ... Logic block, 57 ... Operation target data input / output circuit, 58 ... Operation result data input / output circuit, 59X, 59Y, 59Z ... Adjacent FPGA data transfer circuit, 60 ... Write / input / output board , 60A1 ... notches, 61 ... FPGA, 62 ... memory, 63F, 63B, 64 ... connectors, 65 ... memory control circuit, 66 ... write circuit, 67 ... virtual circuit data input / output circuit, 68 ... various data input / output circuits

Claims (8)

A memory for storing an application program for performing a predetermined calculation on a calculation target;
Corresponding to each problem area to be calculated, the calculation devices are arranged so as to be directly communicable between adjacent calculation devices, and are used for executing the application program to perform the calculation corresponding to each problem area. An arithmetic device array comprising a plurality of arithmetic devices in which an arithmetic circuit is reconfigured and transmits and receives operation result data by the arithmetic circuit for the problem area between adjacent arithmetic devices;
The arithmetic unit determines the adjacent computing device as previously processed data destination for each arithmetic unit constituting the array, executes the application program, the operation result data for each problem area from the arithmetic unit And a host processor for calculating a calculation result for the calculation target;
The memory, between the host processor and the arithmetic unit array, viewed including a bus for communicating data, and
A virtual circuit data writing circuit for writing the arithmetic circuit to the arithmetic device based on virtual circuit write data including virtual circuit data corresponding to each problem area to be calculated, sent from the host processor. After writing the virtual circuit data write circuit, the arithmetic device transfers the virtual circuit write data to an adjacent arithmetic device according to the write order included in the virtual circuit write data . In previous SL plurality of arithmetic unit, after the writing of the virtual circuit data write circuit for all the arithmetic unit terminates, the virtual circuit data write circuit wherein all the last written arithmetic unit until first written arithmetic units The information processing apparatus according to claim 1, wherein the arithmetic circuit is written in the arithmetic apparatus. The information processing apparatus according to claim 2, wherein the arithmetic device includes a pair of arithmetic devices including an arithmetic board to which the arithmetic circuit is written and a writing board to which the virtual circuit data writing circuit is written. In the plurality of arithmetic devices constituting the computing device array, with write No write the arithmetic circuit to the arithmetic board, writes the data input and output circuit for transferring data to said host processor and receiving the writing board according Item 4. The information processing device according to Item 3. The computing board of the computing device includes a first connector for connecting to adjacent computing boards in the vertical and horizontal directions, and a second connector for connecting to the writing board that makes a pair. , Comprising a third connector for connecting to the paired arithmetic boards,
The arithmetic circuit of the arithmetic board transmits / receives the arithmetic result data to / from the arithmetic circuit of the adjacent arithmetic board via the first connector, and the write circuit of the write board via the second and third connectors The information processing apparatus according to claim 4, wherein data is transmitted to and received from the data input / output circuit. The information processing apparatus according to claim 5, wherein the host processor controls a predetermined arithmetic board among a plurality of arithmetic boards constituting the arithmetic device array to be electrically connected via a first connector. When the calculation target satisfies the periodic boundary condition, the host processor electrically connects the arithmetic devices corresponding to the periodic boundary among the plurality of arithmetic devices constituting the arithmetic device array via the first connector. The information processing apparatus according to claim 5. Each problem of the calculation target sent from the host processor to each of the plurality of calculation devices arranged so as to be directly communicable between adjacent calculation devices corresponding to each problem area of the calculation target a step of based on the virtual circuit writing data including the virtual circuit data corresponding to the area, write the virtual circuit data write circuit for writing an arithmetic circuit,
After writing the virtual circuit data write circuit to the arithmetic device, the arithmetic device transfers the virtual circuit write data to an adjacent arithmetic device according to the write order included in the virtual circuit write data;
After the writing of the virtual circuit data writing circuit for all the arithmetic devices, the arithmetic circuit for all the arithmetic devices from the arithmetic device in which the virtual circuit data writing circuit was last written to the first arithmetic device to be written Writing step;
A virtual circuit writing method including:

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