JP5314731B2 - Method and computer system for synchronizing basic input / output program between data processing devices - Google Patents

Description

  The present invention relates to a method and a computer system for synchronizing a basic input / output program (BIOS) between data processing apparatuses.

  In a storage device using a storage medium such as a magnetic disk, a magneto-optical disk, or an optical disk, the storage medium is actually accessed at the request of the data processing apparatus. When the data processing device uses a large amount of data, a storage device including a plurality of storage devices and a control device is used.

  Such a storage apparatus employs a redundant configuration in order to improve the reliability of stored data and the reliability of the apparatus. Furthermore, the storage control device is composed of a data processing device including a CPU. The CPU provides various services such as resource allocation and protection, program execution, input / output operations, and file operations to the user by an OS (Operating System) which is a control program of the CPU.

  The basic part of the OS for realizing these services is called a kernel. In recent OSs, particularly personal computer OSs, a part for controlling hardware and a part for other parts are created as separate module groups so that a common OS can operate even with different hardware. This hardware control part is called a BIOS (Basic Input / Output System), and the other part is called a kernel.

  The BIOS checks the hardware of the computer system and sets up an environment in which the kernel can use the hardware. Conventionally, such a BIOS is bound to firmware and stored in a memory at a time, so that it is prevented that different versions operate (for example, see Patent Document 1).

Japanese Patent Laid-Open No. 11-306007

  On the other hand, even with a CPU of a certain model number, a CPU improved by the occurrence of a bug or the like has the same model number, so it is necessary to frequently update the BIOS version number by so-called CPU stepping change, so the BIOS is not bound by firmware. CPU binding is required. In other words, when a CPU stepping change occurs, the BIOS needs to be newer than the BIOS corresponding to the mounted CPU.

  In the prior art, when the memory storing the BIOS is destroyed due to a power failure or the like during writing for updating the BIOS, the system operation may be disabled. That is, even if the BIOS is loaded from the memory storing the BIOS into the main memory, the BIOS of the memory is currently in operation, so if a power failure or the like occurs, the BIOS before writing is lost during the writing, and the system Operation becomes impossible.

  In addition, even if the writing is successful, at the time of power recovery, power recovery processing is performed with a BIOS different from the previous BIOS, and in consideration of this, there is a restriction that it is necessary to change the BIOS, and BIOS update The range of is limited.

  Accordingly, an object of the present invention is to provide a basic system between data processing devices for preventing the system from being disabled even if the basic input / output programs of a pair of data processing devices are synchronized during system operation. An object of the present invention is to provide an input / output program synchronization method and a computer system.

  Another object of the present invention is to provide a basic input / output program synchronization method between data processing apparatuses and a computer system for preventing the system from being disabled even if rewriting of the basic input / output program fails. Is to provide.

To achieve this object, the synchronization method of the present invention comprises a pair of data in which a CPU, a memory, a peripheral device, a pair of program memories each storing a basic input / output program, and a service processor are connected by a bus. A method for synchronizing basic input / output programs of a processing device, wherein the CPU is set in the memory of the service processor as an operating side when the data processing device is started up. Executing the boot processing of the pair of data processing devices, and during the operation of the data processing device, the first data processing device of the pair of data processing devices is the service processor of the second data processing device of the pair of data processing devices. Second version number of the basic input / output program in the program memory set in the operating side stored in the memory A first version number of the basic input / output program in the program memory set in the operating side stored in the memory of the service processor of the first data processing device; Comparing the second version number with the second version number, and if the comparison shows that the first version number is older than the second version number, the first data processing device A first input / output program in a program memory set on the operating side of the processing device is received from the second data processing device and written to the program memory on the standby side of the first data processing device a step, when the first data processing apparatus, in which the step of determining whether the writing of the first step is successful, the writing of the first step was successful, Set the serial the program memory of the standby side of the first data processing device at the next startup, the steps of the first data processing apparatus to notify that prompts a reboot, the first data processing apparatus, again Upon startup, the program memory set at the next startup is set to the operating side, and the CPU of the first data processing device writes the written basic input / output program in the program memory set to the operating side A step of executing the boot process, a step of notifying the first data processing device of an abnormality when the writing of the first step fails, and the comparison shows that the first version number is When the version number is newer than 2, the first data processing device is connected to the basic input / output program of the program memory set on the operating side of the first data processing device. A second step of transferring the program to the second data processing device and writing it to the program memory on the standby side of the second data processing device; and if the writing of the second step is successful, the second step When the second data processing apparatus restarts, the step of executing the boot process of the basic input / output program written in the program memory on the standby side and the writing of the second step fail, The second data processing apparatus notifies the abnormality.

The computer system of the present invention has a pair of data processing devices connected to each other, and each of the data processing devices stores a CPU, a memory, a peripheral device, and a basic input / output program. The program memory and the service processor are connected by a bus, and when the data processor is started up, the basic input of one program memory is set in the memory of the service processor. The first data processing device of the pair of data processing devices executes the boot process of the output program, and the service processor of the second data processing device of the pair of data processing devices is in operation. The second version number of the basic input / output program in the program memory set in the operating side stored in the memory of And the first data processing device includes a first version number of the basic input / output program stored in the memory of the service processor of the first data processing device. The second version number is compared. If the comparison shows that the first version number is older than the second version number, the first data processing device The basic input / output program of the program memory on the operating side is received from the second data processing device, written to the program memory on the standby side of the first data processing device, and the writing of the first step is performed successful or determines the, when said writing of the first step is successful, the program memory of the standby side of the first data processing apparatus set at the next startup, the first data Signals that processor prompts a reboot, the first data processing device, the restart, to set the program memory that is set on the next startup the operating side, of the first data processing device When the CPU executes the boot process of the written basic input / output program in the program memory set on the operating side and the write in the first step fails, the first data processing device If the first version number is newer than the second version number by the comparison and the first version number is newer than the second version number, the first data processing unit is connected to the program memory on the operating side of the first data processing unit. The basic input / output program is transferred to the second data processing device, written to the program memory on the standby side of the second data processing device, and the second data processing device. When the writing in the second step is successful, the boot process of the basic input / output program written in the program memory on the standby side is executed by restart, and the writing in the second step fails. In such a case, the second data processing apparatus notifies an abnormality.

  In the present invention, each data processing device redundantly manages a basic input / output program (BIOS) with a pair of program memories, and compares the BIOS version numbers when the BIOS of the data processing device is synchronized. If they are different, the two program memories are not updated at the same time, but are written only to the standby side, and the currently operating BIOS is not rewritten. Therefore, it is possible to prevent the system from being disabled due to synchronization.

  In addition, since only the standby program memory is updated, it is possible to prevent the power recovery process from being performed with a BIOS different from that before the power failure when a power failure occurs during update writing.

  Furthermore, the present invention preferably further comprises the step of permitting the waiting memory to be switched to the operating state when the BIOS update to the waiting memory is successful. Thereby, it can be assured to switch to the updated BIOS.

  In the present invention, it is preferable to further include a step of switching the permitted memory to the waiting state when the hardware is started, and switching the permitted memory to the waiting state. Thereby, it is possible to automatically switch to the updated BIOS.

  Furthermore, the present invention preferably further includes a step of writing and making the BIOS of the memory switched during operation into the memory switched during standby after the switching. As a result, the BIOS of another memory that has not been updated can also be updated.

  Furthermore, the present invention preferably further includes a step of preventing the waiting memory from being switched to the operating state when the update of the BIOS to the waiting memory fails. As a result, automatic switching to the BIOS whose update has failed can be prevented, and unnecessary switching can be prevented.

  Furthermore, the present invention preferably further includes a step of preventing the memory switched during the standby from being switched during the operation when the writing of the BIOS into the memory switched during the standby fails. . As a result, automatic switching to the BIOS that has failed in redundancy can be prevented, and unnecessary switching can be prevented.

  Furthermore, in the present invention, it is preferable that a step of performing a BIOS update of a standby memory of other hardware connected to the hardware is further performed in response to a BIOS update of the standby memory of the hardware. Have. Thereby, BIOS update of a pair of hardware can be performed simultaneously.

  Further, the present invention preferably further includes a step of performing a BIOS synchronization process with other hardware connected to the hardware. This makes it possible to match the BIOS version numbers between hardware.

  As described above, according to the present invention, in the present invention, each data processing device redundantly manages the basic input / output program (BIOS) with a pair of program memories, and the version of each BIOS is synchronized with the BIOS of the data processing device. Compare the numbers, and if the version numbers are different, do not update the two program memories at the same time, write only to the standby side, and do not rewrite the currently running BIOS. It is possible to prevent the system from becoming unbootable.

  In addition, since only the standby program memory is updated, it is possible to prevent the power recovery process from being performed with a BIOS different from that before the power failure when a power failure occurs during update writing.

It is a block diagram of the storage system of one embodiment of this invention. It is a block diagram of the storage program of FIG. It is explanatory drawing of the redundant management information of RSP of FIG. FIG. 2 is a process flow diagram of the BIOS of FIG. 1. It is explanatory drawing of the BIOS update of one embodiment of this invention. FIG. 6 is a BIOS update process flowchart of FIG. 5. FIG. 7 is a flowchart of the BIOS flash write process in FIG. 6. FIG. 2 is a processing flow diagram of the RSP at the time of CM activation in FIG. FIG. 2 is a BIOS redundancy processing flow diagram of FIG. 1. It is operation | movement explanatory drawing of the BIOS update process of FIG. FIG. 8 is an operation explanatory diagram of the BIOS flash write process of FIG. 7. It is operation | movement explanatory drawing of the BIOS redundancy process of FIG. It is a BIOS synchronization process flow figure of other embodiment of this invention. It is operation | movement explanatory drawing of the BIOS synchronization process between CM of FIG.

  Hereinafter, embodiments of the present invention will be described in the order of storage system, BIOS redundancy management processing, inter-CM BIOS synchronization processing, and other embodiments.

[Storage system]
FIG. 1 is a configuration diagram of a storage system according to an embodiment of the present invention, showing a RAID (Redundant Array of Inexpensive Disk) system using a magnetic disk. As shown in FIG. 1, the storage system includes a pair of magnetic disk controllers (hereinafter referred to as controllers) 1 and 2, and a number of magnetic disk devices 50- connected to the pair of controllers 1 and 2 via lines l1 and l2. 1 to 50-m, 52-1 to 52-n.

  The controllers 1 and 2 are systems that are connected to a host or server directly or via a network device, and can read and write a large amount of data from the host or server to a RAID disk drive (magnetic disk device) at high speed and randomly. The pair of controllers 1 and 2 have the same configuration, CA (Channel Adapter) 11, 12, 21, and 22, CM (Centralized Module) 10, 15 to 19, 20, 25 to 29, and DA (Device Adapter) 13, 14, 23, and 24 function modules.

  CAs (Channel Adapters) 11, 12, 21, and 22 are circuits that control the host interface connecting the hosts, and include, for example, a fiber channel circuit (FC) and a DMA (Direct Memory Access) circuit. DA (Device Adapter) 13, 14, 23, and 24 are circuits for exchanging commands and data with the disk device in order to control the disk devices 50-1 to 50-m and 52-1 to 52-m. For example, it includes a fiber channel circuit (FC) and a DMA circuit.

  The CM (Centralized Module) includes CPUs 10 and 20, bridge circuits 17 and 27, memories (RAM) 15 and 25, compact flash (registered trademark) memories 16 and 26, IO bridge circuits 18 and 28, and a pair BIOS flash memories 32, 33, 42, and 43 are included. Further, the CM includes RSP (Remote Service Processor) 34 and 44 and external connection LAN ports 36 and 46. The memories 15 and 25 are backed up by a battery and used as main memory.

  The CPUs 10 and 20 are connected to the memories 15 and 25, the compact flash (registered trademark) memories 16 and 26, and the IO bridge circuits 18 and 28 via the bridge circuits 17 and 27. The memories 15 and 25 are used as work areas of the CPUs 10 and 20, and the compact flash (registered trademark) memories 16 and 26 store programs executed by the CPUs 10 and 20. As this program, a kernel, a file access program (read / write program), a RAID management program, and the like are stored.

  A pair of BIOS flash memories 32, 33, 42, and 43 are provided for redundancy, and one is used for operation and the other is used for standby, and stores BIOS (described later in FIG. 4). The CPUs 10 and 20 execute this program and execute read / write processing, RAID management processing, and the like.

  The PCI buses 35 and 45 are connected via the bridge circuits 17 and 27 to the CPUs 10 and 20, the compact flash (registered trademark) memories 15 and 25, the pair of BIOS flash memories 32, 33, 42 and 43, the RSP 34 and 44, and the LAN port. 36 and 46 are connected.

  The RSPs 34 and 44 are constituted by processors that perform various remote services. In this embodiment, the RSPs 34 and 44 perform redundancy management of the BIOS flash memories 32, 33, 42, and 43. The LAN ports 36 and 46 are for connection to an external LAN (Local Area Network).

  PCI (Personal Computer Interface) buses 31 and 41 connect the CAs 11, 12, 21, and 22 to the DAs 13, 14, 23, and 24, and via the IO bridge circuits 18 and 28, the CPUs 10 and 20, the memory 15, 25 is connected. Further, PCI-node link bridge (PNB) circuits 30 and 40 are connected to the PCI buses 31 and 41.

  The PCI-node link bridge circuit 30 of the controller 1 is connected to the PCI-node link bridge circuit 40 of the controller 2 and exchanges commands and data between the controllers 1 and 2.

  The controller 1 is in charge of, for example, the disk devices 50-1 to 50-m, and the controller 2 is in charge of, for example, the disk devices 52-1 to 52-n. In FIG. 1, the disk devices 50-1 to 50-m and 52-1 to 52-n have a RAID5 configuration.

  FIG. 2 is an example of a program stored in the compact flash (registered trademark) memory 16, 26 of FIG. 1, and includes a kernel 102, system control 104, power control 106, configuration management 108, maintenance task 110, flash driver 112, It is composed of an RSP driver 114 and the like. The kernel 102 is an OS, and other than the kernel 102 is firmware.

  FIG. 3 is an explanatory diagram of the BIOS redundancy management information stored in the NVRAM (nonvolatile random access memory) of the RSPs 34 and 44 in FIG. 1, and the boot mode 120 stores the BIOS boot mode (FAST / SLOW). The current mode 122 stores the currently operating BIOS number #. The BIOS SW 124 stores the BIOS number # that is activated at the next activation. The standby BIOS version number 126 stores the standby BIOS version number.

  FIG. 4 is a process flow diagram of the BIOS stored in the BIOS flash memory of FIG. As described above, the BIOS checks the hardware used by the OS (kernel) and sets the environment in which the OS (kernel) can use the hardware. Therefore, it is performed before the OS is loaded.

  (S10) The BIOS to be started by the RSPs 34 and 44 is set. First, when the reset of the CPUs 10 and 20 is released, the CPUs 10 and 20 start the BIOS of the BIOS flash memory 32 (or 33) or 42 (or 43). The block is read, and initialization of the RSPs 34 and 44, that is, a setting that allows the BIOS to use the functions of the RSPs 34 and 44 is performed at the head of the BIOS Bootblock. Next, the CPUs 10 and 20 are initialized. That is, register settings, machine check initialization, and the like are performed so that the CPUs 10 and 20 can be used.

  (S12) Each chip set (each bridge circuit 17, 18, 27, 28, etc.) is initialized (Disable, register setting, etc.). Also, initialization of the memories 15 and 25 (to make them usable, diagnosis and ECC check, etc.) is performed.

  (S14) After initialization of the memories 15 and 25 and the chip set, the BIOS is loaded from the BIOS flash memory to the memories 15 and 25. Next, initialization of the PCI devices (CA 11, 12, 21, 22, DA 13, 14, 23, 24, LAN ports 36, 46) connected to the PCI buses 31, 35, 41, 45 is performed.

  (S16) Further, other devices are initialized as necessary.

  (S18) Next, various tables are created and the boot is terminated. As a result, the kernel or the like is loaded from the compact flash (registered trademark) memories 16 and 26 to the memories 15 and 25, and the program is started.

  In the storage system of FIG. 1, in the controllers 1 and 2, the cache memories arranged in the memories 15 and 25 each store a part of the data of the disk device in charge and store the write data from the host. The CPUs 10 and 20 receive a read request from the host via the CAs 11, 12, 21, and 22, refer to the cache memory, determine whether access to the physical disk is necessary, and if necessary, issue a disk access request. Requests to DAs 13, 14, 23, and 24. In response to a write request from the host, the CPUs 10 and 20 write the write data to the cache memory, and request the DAs 13, 14, 23, and 24 to write back internally and the like.

[BIOS redundancy management processing]
As described above, each of the controllers 1 and 2 is physically mounted with two BIOS flash memories (Flash ROM). The same version number of BIOS is stored in these two flash memories, and even if one BIOS flash memory (Flash ROM) 32, 42 is not bootable, the same version number BIOS is started from the other 33, 43. Redundancy management (to be described later with reference to FIG. 8) is performed.

  This BIOS redundancy is performed by BIOS redundancy processing firmware (described later in FIG. 9) after the BIOS processing is completed. The BIOS to be activated is switched by the processors of the RSPs 34 and 44.

  First, BIOS update will be described with reference to FIGS. 5, 6, 7, and 10 to 12. As shown in FIG. 5, the flash write to the BIOS flash memory (Flash ROM) 33 is performed from firmware using a user interface.

  That is, a personal computer (hereinafter referred to as a PC) 6 is connected to the LAN port 36 of the controller 1 via the hub 7 and is executed by the processing shown in FIGS. FIG. 6 is a flow chart of the BIOS update instruction process.

  (S20) A BIOS update instruction is issued from the CGI screen of the PC 6. That is, the BIOS update screen is displayed and an update is instructed.

  (S21) The maintenance task 110 executed by the CPU 10 of the controller 1 acquires the BIOS version number from the configuration, and notifies the CGI of the PC 6 of it.

  (S22) In the CGI of the PC 6, the notified BIOS version number currently in operation is displayed on the CGI screen. After confirmation by the user, the CGI of the PC 6 transfers the BIOS ROM Image to the maintenance task 110 executed by the CPU 10.

  (S23) The maintenance task 110 checks the checksum of the BIOS ROM image received from the CGI, and if it is abnormal, notifies the CGI of the abnormality. If not abnormal, the CGI is notified of the transferred BIOS version number.

  (S24) In CGI, if a checksum error occurs on the CGI screen, a message to that effect is displayed.

  (S25) If the CGI is normal, the BIOS version number received from the maintenance task is displayed on the screen, and a final confirmation is made whether the BIOS can be updated.

  (S26) If continuing, the CGI sends a flashlight instruction to the maintenance task 110. The maintenance task 110 receives the flash write instruction and executes the BIOS flash write process of FIG.

  FIG. 7 is a flowchart of the flash write process executed by the maintenance task.

  (S30) Upon receiving the BIOS flash write instruction, the maintenance task 110 obtains the flash memory number (32 or 33 in FIG. 1) of the currently operating BIOS from the Current SW 122 of the NVRAM (see FIG. 3) in the RSPs 34 and 44. To do.

  (S32) Next, the maintenance task 110 invalidates the version number of the standby BIOS version number 126 in the NVRAM (see FIG. 3) in the RSPs 34 and 44. This prevents automatic switching of the BIOS flash ROM.

  (S34) The waiting BIOS flash memory is obtained from the flash memory number of the currently operating BIOS in step S30, and the function prepared by the kernel 102 is used to store the BIOS flash ROM that is not currently operating (standby side). Then, the transferred BIOS is flash-written. At this time, the BIOS Boot Block part is also flash-written.

  (S36) The maintenance task 110 determines whether the flash write has been completed normally.

  (S38) If the maintenance task 110 determines that the flash write has been normally completed, the flash flashed BIOS flash ROM number is added to the BIOS number to be activated at the next startup of the BIOS SW 124 in the NVRAM (see FIG. 3) in the RSPs 34 and 44. Set. The maintenance task 110 sets the flash-written BIOS version number in the standby BIOS version number 126 of the NVRAM (see FIG. 3) in the RSPs 34 and 44, and validates the rewritten flash ROM. Therefore, at the next startup, the rewritten BIOS is selected. Further, it notifies the Web that the BIOS update has been completed normally, and confirms it with the CGI of the PC 6. And it ends.

  (S40) On the other hand, if it is detected in step S36 that a flash write error has occurred during BIOS update, the system control 104 is notified that the standby BIOS flash memory is abnormal, and an error has occurred. Set the controller to a state that requires preventive maintenance (for example, the status lamp is set to Orange). Then, the CGI screen of the PC 6 is notified that the BIOS update has failed. In this case, since the BIOS SW 124 and the standby BIOS version number 126 are not updated, automatic switching to the BIOS flash ROM in which an error has occurred can be prevented.

  Thus, at the time of BIOS update, the flash write is not performed on the two BIOS flash ROMs at the same time, but only on the standby side. This is because it is dangerous to rewrite the currently operating BIOS. In other words, when the flash write fails, the currently operating BIOS is not rewritten, so that it can be started with the currently operating BIOS, and it is possible to prevent the system from being disabled.

  Also, if a power failure occurs during flash write, the power recovery process will be performed with a different BIOS than before the power failure, and Fast Boot must be guaranteed between BIOSes with different version numbers. . Fast Boot means that when the power failure occurs, the data in the cache area of the memory 15 and 25 in the controller is retained by battery backup, so that the memory initialization is performed in order to guarantee the data on the cache when power is restored. This mode is omitted and starts up the controller. Here, if the BIOS version is different across a power failure / recovery, the hardware initialization procedure is different, and the memory data cannot be guaranteed.

  Further, in the model in which the two controllers 1 and 2 in FIG. 1 are connected, the command and information received from the PC 6 by the controller 1 are transmitted via the PNBs 30 and 40 in the same manner as the maintenance task 110 of the controller 1 in FIG. 2 and the maintenance task 110 of the controller 2 performs the same operation. Therefore, the standby BIOS flash ROM of the controller 2 is also updated at the same time.

  In this case, at the time of BIOS update, if only one controller fails in the BIOS update, the CGI screen of the PC 6 is notified that the BIOS update has failed. The BIOS that is started up at the next startup of the controller that failed to update cannot be switched, and is started up with the current BIOS. In this state, the BIOS of the two controllers is not made redundant, but is made redundant as will be described later with reference to FIG. 13 at the next power-on.

  Next, the BIOS switching process when the controller is activated will be described. FIG. 8 is a flowchart of the RSP BIOS activation process when the controller is activated.

  (S50) When the controller is restarted at an appropriate timing, the RSPs 34 and 44 obtain the Boot mode (Fast / Slow) from the boot mode 120 of the NVRAM (see FIG. 3) in the RSPs 34 and 44. The Fast boot mode is a mode that is activated by the BIOS that was activated last time due to power recovery after a power failure. On the other hand, the slow boot mode is a mode that starts with the BIOS rewritten by normal power-on or the like.

  (S52) The RSPs 34 and 44 determine the boot mode, and if it is FAST, the process proceeds to step S56. That is, step S54 is jumped, and the BIOS before power failure is used to ensure consistency at power recovery.

  (S54) On the other hand, if it is determined as Slow, the BIOS number to be activated at the next activation of the BIOS SW 124 of the NVRAM (see FIG. 3) in the RSP 34, 44 is obtained, and the Current SW 122 of the NVRAM (see FIG. 3) in the RSP 34, 44 is obtained. To the obtained BIOS number. Therefore, the boot BIOS is switched to the rewritten BIOS.

  (S56) The RSPs 34 and 44 activate the BIOS set in the Current SW 122 of the NVRAM (see FIG. 3).

  In this manner, at the time of start-up, the BIOS is switched to the updated BIOS except when power is restored. When power is restored, the previous BIOS is activated.

  FIG. 9 is a flow chart of BIOS redundancy processing executed by power control.

  (S60) When the BIOS processing (FIG. 4) is completed, the BIOS redundancy processing in the power control 106 is executed by the BIOS SW 124 that is activated at the next activation of the BIOS SW 124 in the NVRAM (see FIG. 3) in the RSPs 34 and 44, and the Current SW 122. Get the currently running BIOS number.

  (S62) It is determined whether the BIOS number that is activated when the BIOS SW 124 is activated next time matches the BIOS number that is currently operating in the Current SW 122. If they do not match, it is not started with the next designated BIOS, such as when power is restored after a power failure.

  (S64) If the BIOS numbers match, it is checked whether the standby BIOS version number 126 of the RSPs 34 and 44 is invalid. If the standby BIOS version is invalid, the standby BIOS is abnormal and the process proceeds to redundancy in step S68.

  (S66) If the standby BIOS is not invalid, the version numbers of both the operating BIOS and the standby BIOS are compared to determine whether they match. If they match, the versions of both BIOS are the same, so redundancy is not necessary and the process ends.

  (S68) If they do not match, redundancy is necessary, and the active BIOS Image is flash-written to the standby BIOS flash memory. At this time, the BIOS ROM image to be written uses the data of the currently operating BIOS flash ROM. Then, the standby BIOS version number of the NVRAM of the RSPs 34 and 44 is set, the standby side is validated, and the redundancy process ends.

  10 to 12 are explanatory diagrams of the operation. As shown in FIG. 10, the transfer BIOS is written in the memories 15 and 25 by the processing of FIG. When the flash write is permitted in FIG. 6, as shown in FIG. 11, the transfer BIOS of the memories 15 and 25 is written in the BIOS flash ROMs 32 and 42 on the standby side in the process of FIG. As shown in FIG. 12, when the controller is activated, the standby side is activated by the processing of FIG. 8, and the operating BIOS flash ROMs 33 and 43 are on the standby side. Further, the BIOS of the BIOS flash ROMs 32 and 42 changed during operation is written into the BIOS flash ROMs 33 and 43 changed during standby by the processing of FIG.

  If a flash write error occurs at the time of BIOS redundancy in step S68, there is no problem in the operation of the controller itself, so the system starts up in a ready state. Set to status (status lamp is Orange). Further, the standby side is not validated so as not to automatically switch to the BIOS flash ROM in which an error has occurred.

  In addition, if the BIOS does not start normally after rebooting after updating the BIOS (if the new BIOS does not start normally), the BIOS flash ROM is not automatically switched and the front panel is used. Switch to the old BIOS version. By not starting up, the user knows that the new BIOS has not started up normally.

  Further, in normal operation, even if one of the two BIOS flash ROMs becomes abnormal, the BIOS can be activated with the other flash ROM. As this switching method, the BIOS flash ROM is switched by an instruction from the user interface.

  As an automatic switching method, the RSPs 34 and 44 detect Heart Beat Error (no response from the BIOS) during the BIOS boot block process, and switch the BIOS flash ROM. However, the BIOS flash ROM is switched only when the standby BIOS is usable (valid), and when it is not usable, the BIOS flash ROM is degraded without switching. After the switching occurs, if the BIOS processing is completed and the firmware can be started, the BIOS redundancy processing described with reference to FIG. 9 is executed.

[BIOS synchronization processing between CMs]
Next, a BIOS synchronization process between CMs (Centralized Modules) shown in FIG. 1 when two controllers are installed as shown in FIG. 1 will be described. For example, as shown in FIG. 14, when CM2 of controller 2 has failed and replaced with CM2 ', BIOS synchronization is performed between CM1 of controller 1 and CM2' of controller 2, and at the time of CM replacement Eliminate discrepancies in BIOS versions.

  When the BIOS of the Slave CM (for example, the CM of the controller 2) is updated, the BIOS is automatically restarted and started with a new BIOS. When the BIOS of the Master CM (for example, the CM of the controller 1) has been updated, this is notified to the user without performing automatic Reboot.

  FIG. 13 is a flow chart of BIOS synchronization processing between CMs.

  (S70) The master CM starts the BIOS synchronization process. First, the BIOS version number of the slave CM is acquired.

  (S72) The master CM compares the BIOS version number of the master CM with the BIOS version number of the slave CM. If they match, the BIOS synchronization is unnecessary and the process ends.

  (S74) By comparison, when the BIOS version number of the master CM is smaller than the BIOS version number of the slave CM, that is, when the BIOS of the master CM is old, the BIOS update of the master CM is necessary. First, the master CM requests the slave CM to transfer BIOS data.

  (S76) In the slave CM, the BIOS is read from the BIOS flash ROM in operation of the slave CM and transferred to the master CM.

  (S78) The master CM writes the transferred BIOS to the standby BIOS flash ROM. As a result, the old BIOS version is updated.

  (S80) The master CM determines whether the BIOS write is successful, and if successful, notifies the user that the BIOS has been updated and needs to be restarted. Therefore, the BIOS update is completed by restarting. Conversely, if the BIOS write fails, the standby BIOS flash ROM of the master CM is abnormal, so that the master CM is targeted for preventive maintenance and the abnormality is notified to the user.

  (S82) On the contrary, if the BIOS version number of the master CM is larger than the BIOS version number of the slave CM, that is, if the BIOS of the master CM is new, the BIOS update of the slave CM is necessary. First, the master CM reads the BIOS from the BIOS flash ROM in operation of the master CM and transfers it to the slave CM.

  (S84) The slave CM writes the transferred BIOS to the standby BIOS flash ROM. As a result, the old BIOS version is updated. Further, the write result is notified to the master CM.

  (S86) The master CM determines from the notification result whether the BIOS write has succeeded, and if successful, the slave CM is restarted and the BIOS update is completed. Conversely, when the BIOS write fails, the standby BIOS flash ROM of the slave master CM is abnormal, so that the slave CM is targeted for preventive maintenance and the abnormality is notified to the user.

  In this way, the new BIOS is synchronized between CMs.

[Other embodiments]
In the above-described embodiment, the RAID having a redundant configuration as shown in FIG. 1 has been described. However, the present invention can be applied to storage systems having other redundant configurations. As the physical disk, a magnetic disk, an optical disk, a magneto-optical disk, and various storage devices can be applied.

  Although the application of the storage system has been described, the present invention can be applied to other controllers and data processing devices as well as the storage. Furthermore, although the example of two CMs has been described, the present invention can be applied to one CM, and the flash memory is used for storing the BIOS. However, other nonvolatile rewritable memories can be used.

  As mentioned above, although this invention was demonstrated by embodiment, in the range of the meaning of this invention, this invention can be variously deformed, These are not excluded from the scope of the present invention.

  (Supplementary note 1) In an environment in which the OS can use hardware, the BIOS for setting the hardware is used while one of a pair of memories for storing each is operating and the other is used for standby; and the BIOS of the one memory A BIOS redundancy management method comprising the steps of: switching to a BIOS of the waiting memory when the CPU cannot be booted; and executing updating of the BIOS by writing to the waiting memory.

  (Supplementary note 2) The BIOS redundancy according to supplementary note 1, further comprising a step of permitting the standby memory to be switched to the active state when the update of the BIOS to the standby memory is successful. Management method.

  (Supplementary note 3) The BIOS redundancy of Supplementary note 2, further comprising the step of switching the active memory to the standby state while the permitted standby memory is in operation when the hardware is started up Management method.

  (Supplementary Note 4) The BIOS redundancy according to Supplementary Note 3, further comprising a step of writing and making the BIOS of the memory switched during operation into the memory switched during the standby after the switching. Management method.

  (Supplementary note 5) The BIOS redundancy according to supplementary note 1, further comprising a step of preventing the standby memory from being switched to the active state when the update of the BIOS to the standby memory fails. Management method.

  (Supplementary note 6) The method further includes the step of preventing the memory switched during standby from being switched during operation when the writing of the BIOS to the memory switched during standby fails. The redundant management method of BIOS according to appendix 4.

  (Supplementary note 7) The BIOS redundancy management method according to supplementary note 3, wherein execution of the switching is prevented when the hardware activation is power recovery.

  (Supplementary note 8) The BIOS redundancy management method according to supplementary note 4, wherein execution of the redundancy is prevented when the hardware is powered up.

  (Additional remark 9) It further has the step which performs the BIOS update of the waiting memory of the other hardware connected with the hardware according to the BIOS update of the waiting memory of the hardware The redundant management method of BIOS according to appendix 1.

  (Supplementary note 10) The BIOS redundancy management method according to supplementary note 1, further comprising a step of performing a BIOS synchronization process with other hardware connected to the hardware.

  (Supplementary Note 11) A pair of memories each storing a hardware including a CPU and a BIOS for setting the hardware in an environment in which an OS can use the hardware, and the pair of memories when starting the hardware And a service processor for switching to the BIOS of the waiting memory when the BIOS of the one of the memories is used for standby and the BIOS of the one of the memories is not bootable, and the CPU updates the BIOS Is executed by writing to the waiting memory.

  (Supplementary note 12) The data processing according to supplementary note 11, wherein the service processor permits the standby memory to be switched to the active state when the update of the BIOS to the standby memory is successful. apparatus.

  (Supplementary note 13) The data processing according to supplementary note 12, wherein, when the hardware is activated, the service processor switches the authorized memory to the standby state while the authorized standby memory is in operation. apparatus.

  (Supplementary note 14) The data processing device according to supplementary note 13, wherein after the switching, the CPU writes the BIOS of the memory switched during operation into the memory switched during standby, and makes the memory redundant. .

  (Supplementary note 15) The data processing device according to supplementary note 11, wherein the CPU prevents the standby memory from being switched to the active state when the update of the BIOS to the standby memory fails. .

  (Supplementary Note 16) The CPU prevents the memory switched during the standby from being switched during the operation when the writing of the BIOS into the memory switched during the standby fails. The data processing apparatus according to attachment 14.

  (Additional remark 17) It has the other hardware connected with the said hardware, and is waiting for the other hardware connected with the said hardware according to the BIOS update of the said waiting memory of the said hardware The data processing apparatus according to appendix 11, wherein the BIOS update of the memory is executed.

  (Supplementary note 18) The data processing device according to supplementary note 11, wherein the hardware performs a BIOS synchronization process with other hardware connected to the hardware.

  (Supplementary Note 19) A pair of memories each storing a hardware including a CPU and a BIOS for setting the hardware in an environment in which an OS can use the hardware, and the pair of memories when the hardware is activated A storage controller having a service processor for switching to the BIOS of the standby memory when the BIOS of the one memory is used for standby and the BIOS of the one memory is not bootable. A storage system, wherein the CPU of the storage control device executes the BIOS update by writing to the waiting memory.

  (Supplementary note 20) The service processor of the storage control device permits the standby memory to be switched to the active state when the BIOS update to the standby memory is successful. The storage system of appendix 19.

  (Supplementary Note 21) The service processor of the storage control device is characterized in that, when the hardware is started, the permitted standby memory is operating and the active memory is switched to the standby. The storage system of appendix 20.

  (Supplementary note 22) The CPU of the storage control device writes, and makes redundant, the BIOS of the memory switched during operation to the memory switched during standby after the switching. 21 storage systems.

  (Supplementary note 23) The CPU of the storage control device prevents the standby memory from being switched to the active state when the update of the BIOS to the standby memory fails. 19 storage systems.

  (Supplementary Note 24) The CPU of the storage control device prevents the memory switched during standby from being switched during operation when the writing of the BIOS to the memory switched during standby fails. The storage system according to appendix 22, characterized by the above.

  (Supplementary Note 25) The storage device and another storage control device that is connected to the storage control device and controls the storage device, and according to a BIOS update of the standby memory of the storage control device, The storage system according to appendix 19, wherein the BIOS update of the standby memory of another storage control apparatus is executed.

  (Supplementary Note 26) The storage device further includes another storage control device that is connected to the storage device and controls the storage device, and the storage control device synchronizes the BIOS with the other storage control device. The storage system according to appendix 19, characterized by performing processing.

1, 2 Storage controller 7 Hub 6 Personal computer 11, 12, 21, 23 Channel adapter 13, 14, 23, 24 Device adapter 10, 20 CPU
15, 25 Memory 16, 26 Program memory 32, 33, 42, 43 BIOS flash ROM
34,44 RSP
30, 40 PCI-node bridge circuit 31, 41 PCI bus 36, 46 LAN port 50-1 to 50-m, 52-1 to 52-n Physical disk device (storage device)

Claims (6)

A method of synchronizing a basic input / output program of a pair of data processing devices in which a CPU, a memory, a peripheral device, a pair of program memories each storing a basic input / output program, and a service processor are connected by a bus,
Executing the boot process of the basic input / output program in one program memory set on the operating side in the memory of the service processor at the time of activation of each of the data processing devices;
The operating side in which the first data processing device of the pair of data processing devices is stored in the memory of the service processor of the second data processing device of the pair of data processing devices during the operation of the data processing device Reading the second version of the basic input / output program in the program memory set to
The first data processing device includes a first version number of the basic input / output program stored in the memory of the service processor of the first data processing device, and a second version of the basic input / output program in the program memory. Comparing the version number of
According to the comparison, when the first version number is older than the second version number, the first data processing device has the program memory set on the operating side of the second data processing device. A first step of receiving a basic input / output program from the second data processing device and writing it to the program memory on the standby side of the first data processing device;
The first data processing device determining whether the writing of the first step is successful;
If writing in the first step is successful , setting the program memory on the standby side of the first data processing device at the next start -up and notifying that the first data processing device prompts restart When,
The first data processing device sets the program memory set at the next startup by the restart to the operating side, and the CPU of the first data processing device sets the program to the operating side Executing a boot process of the written basic input / output program in the memory;
The first data processing device notifying an abnormality when the writing in the first step fails;
According to the comparison, when the first version number is newer than the second version number, the first data processing device has the program memory set on the operating side of the first data processing device. A second step of transferring a basic input / output program to the second data processing device and writing to the program memory on the standby side of the second data processing device;
If the writing of the second step is successful, the second data processing device reboots to execute the boot process of the basic input / output program written to the program memory on the standby side;
A method of synchronizing basic input / output programs between data processing devices, comprising: a step of notifying an abnormality of the second data processing device when writing in the second step fails. The data processing according to claim 1, wherein the boot process includes a process of setting the CPU, the memory, the peripheral device, the service processor, and the bus in an environment in which the CPU can execute an OS. A method for synchronizing basic I / O programs between devices. The step of notifying that the restart is urged includes the step of setting the program memory on the standby side of the first data processing device to a BIOS number to be activated at the next activation,
2. The data processing apparatus according to claim 1, wherein the step of executing the boot process by restarting the first data processing apparatus includes a step of setting a BIOS number to be activated at the time of the activation to the operating side. To synchronize basic I / O programs. Having a pair of interconnected data processing devices;
Each of the data processing devices is configured by connecting a CPU, a memory, a peripheral device, a pair of program memories storing basic input / output programs, and a service processor via a bus,
At the start of each of the data processing devices, the CPU executes a boot process of the basic input / output program in one program memory set to the operating side in the memory of the service processor,
The operating side in which the first data processing device of the pair of data processing devices is stored in the memory of the service processor of the second data processing device of the pair of data processing devices during the operation of the data processing device A second version number of the basic input / output program in the program memory set to
The first data processing device includes a first version number of the basic input / output program stored in the memory of the service processor of the first data processing device, and a second version of the basic input / output program in the program memory. Compare the version number of
If the comparison shows that the first version number is older than the second version number, the first data processing device is connected to the basic input / output of the program memory on the operating side of the second data processing device. A program is received from the second data processing device, written to the program memory on the standby side of the first data processing device, it is determined whether the writing in the first step is successful, and the first If the step writing is successful, the program memory on the standby side of the first data processing device is set at the next start-up, the first data processing device is instructed to be restarted, and the first data processing device is notified . The data processing device sets the program memory set at the next startup by the restart to the operating side, and the CPU of the first data processing device is set to the operating side Run the boot process of the written basic input output program of the program memory, if the writing of the first step fails, the first data processing apparatus notifies an abnormality,
If the comparison shows that the first version number is newer than the second version number, the first data processing device is configured to output the basic input / output of the program memory on the operating side of the first data processing device. The program is transferred to the second data processing device and written to the program memory on the standby side of the second data processing device, and the second data processing device has successfully written in the second step. If the second data processing apparatus executes the boot process of the basic input / output program written in the program memory on the standby side by restart and the write in the second step fails, A computer system characterized by notifying an abnormality. The first and second data processing devices set the CPU, the memory, the peripheral device, the service processor, and the bus in an environment in which the CPU can execute an OS by the boot process. The computer system of claim 4 characterized in that: Each of the pair of data processing devices constitutes a storage control device,
The computer system according to claim 4, further comprising: a plurality of storage devices connected to each of the storage control devices.

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