JP5314056B2 - Data transfer control device, data transfer control method, and program therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent memory access performance of data to be transferred from being degraded when the data to be transferred do not satisfy an address boundary condition in a storage device which performs data transfer between storage devices over a packet switched network. <P>SOLUTION: A data transfer control apparatus includes: a transfer instruction execution unit which outputs a data read request requesting a transmitting-side memory to read out transfer data for the unit of transmitting-side memory access on the basis of a data transfer instruction containing at least a transmitting-side transfer starting address and a receiving-side transfer starting address; and a transfer packet generation unit which generates and outputs a transfer packet by dividing the transfer data outputted from the transmitting-side memory on a boundary of the unit of receiving-side memory access in response to the data read request on the basis of the transmitting-side transfer starting address, the receiving-side transfer starting address, the unit of receiving-side memory access and a transfer packet size when transferring data from the transmitting side to the receiving side. <P>COPYRIGHT: (C)2012,JPO&amp;INPIT

Description

  The present invention relates to a data transfer control device, a data transfer control method, and a program therefor relating to data transfer between devices.

  Various related techniques relating to data transfer between storage devices are known.

  For example, when transferring data between two storage devices, the control method is simpler and faster transfer is possible when the data to be transferred satisfies the address boundary condition than when the data does not satisfy the address boundary condition. Is well known. Here, the data to be transferred satisfies the address boundary condition means that the transfer start address between the storage devices coincides with the read / write address boundary of the transfer data in each storage device.

  However, the address boundary condition is always satisfied depending on the hardware limitation of the storage device (for example, the limitation due to the configuration of the memory element to be used) and the memory usage method of the software (for example, the determination method of the storage location of the transfer data). Not necessarily. In such a case, the required memory access performance may not be obtained.

  A technique for solving such problems is described in Patent Document 1. The data transfer device described in Patent Document 1 includes three or more buffers for temporarily storing transfer data. This buffer is an accessible buffer at an arbitrary timing as long as data of an arbitrary size does not compete between the transmission side and the reception side. Further, the data transfer device includes a transfer source side control unit and a transfer destination side control unit that perform data transfer by sequentially switching the buffers between the transfer source storage device and the transfer destination storage device. The data transfer device having such a configuration is provided with the transfer source storage device even when the transfer start address of the storage device, either or both of the transfer source and the transfer destination, does not satisfy the address boundary condition The data transfer from the data transfer device to the data transfer device and the data transfer from the data transfer device to the transfer destination storage device are executed in parallel. Thus, this data transfer apparatus realizes high-speed data transfer.

JP 7-105128 A

  However, the technique disclosed in Patent Document 1 is such that, in an apparatus that performs data transfer via a packet switching network, when the data to be transferred does not satisfy the address boundary condition, the memory access performance of the data to be transferred is not deteriorated. The problem of doing is not solved. The reason is that in the data transfer device of Patent Document 1, a transfer source and a transfer destination directly transfer data via a buffer, and transfer data of a predetermined size is stored in a packet and sequentially transferred. This is because the exchange method is not supported.

  An object of the present invention is to provide a data transfer control device, a data transfer control method, and a program therefor that solve the above-described problems.

The data transfer control device of the present invention requests the transmission side memory to read the transfer data in units of the transmission side memory access based on a data transfer instruction including at least the transmission side transfer start address and the reception side transfer start address. A transfer instruction execution unit for outputting a data read request;
Based on the transmission side transfer start address, the reception side transfer start address, a reception side memory access unit, and a transfer packet size when transferring the data from the transmission side to the reception side, the transmission side in response to the data read request A transfer packet generation unit that generates the transfer packet by dividing the transfer data output from the side memory at the boundary of the reception side memory access unit, and outputs the transfer packet.

In the data transfer control method of the present invention, an apparatus for transferring data via a packet switching network includes:
Based on a data transfer command including at least a transmission-side transfer start address and a reception-side transfer start address, a data read request is output to request the transmission-side memory to read transfer data in a transmission-side memory access unit,
Based on the transmission side transfer start address, the reception side transfer start address, a reception side memory access unit, and a transfer packet size when transferring the data from the transmission side to the reception side, the transmission side in response to the data read request The transfer data output from the side memory is divided at the boundary of the reception side memory access unit to generate a transfer packet and output it.

A program according to the present invention requests a transmission side memory to read out transfer data in units of transmission side memory access based on a data transfer instruction including at least a transmission side transfer start address and a reception side transfer start address. Output
Based on the transmission side transfer start address, the reception side transfer start address, a reception side memory access unit, and a transfer packet size when transferring the data from the transmission side to the reception side, the transmission side in response to the data read request The transfer data output from the side memory is divided at the boundary of the reception side memory access unit to generate a transfer packet and cause the computer to execute a process of outputting.

  The present invention solves the problem of preventing the memory access performance of data to be transferred from deteriorating when the data to be transferred does not satisfy the address boundary condition in an apparatus that performs data transfer via a packet switching network. Has the effect of becoming possible.

It is a block diagram which shows the structure of the 1st Embodiment of this invention. It is a figure which shows the example of the data transfer command in the 1st Embodiment of this invention. It is a figure which shows the example of the data reading request | requirement in the 1st Embodiment of this invention. It is a figure which shows the example of a part of transmission side memory of the 1st Embodiment of this invention. It is a figure which shows the example of a part of receiving side memory of the 1st Embodiment of this invention. It is a flowchart which shows the operation | movement of the 1st Embodiment of this invention. It is a flowchart which shows the operation | movement of the 1st Embodiment of this invention. It is a figure which shows the specific example of a current address and a limit address in the 1st Embodiment of this invention. It is a figure which shows the example of the 1st transfer packet 631 in the 1st Embodiment of this invention. It is a figure which shows the example of the 2nd transfer packet 632 in the 1st Embodiment of this invention. It is a figure which shows the example of the 3rd transfer packet 633 in the 1st Embodiment of this invention. It is a figure which shows the example of the 4th transfer packet 634 in the 1st Embodiment of this invention. It is a block diagram which shows the structure of the data transfer control apparatus which makes a computer perform a predetermined | prescribed process with the program of the 1st Embodiment of this invention. It is a block diagram which shows the structure of the data transfer system of the 2nd Embodiment of this invention. It is a figure which shows the example of the data transfer command 650 in the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the data transfer control apparatus of the 2nd Embodiment of this invention. It is a figure which shows the example of the data buffer number in the 2nd Embodiment of this invention. It is a figure which shows the example of 1 packet information in the 2nd Embodiment of this invention. It is a figure which shows the example of the receiving side packet address in the 2nd Embodiment of this invention. It is a figure which shows the example of the correction information in the 2nd Embodiment of this invention. It is a figure which shows the example of the memory request information in the 2nd Embodiment of this invention. It is a figure which shows the example of the transmission side memory access unit data in the 2nd Embodiment of this invention. It is a figure which shows the example of the data buffer storage data in the 2nd Embodiment of this invention. It is a flowchart which shows the operation | movement of the 2nd Embodiment of this invention. It is a figure which shows the operation | movement which stores the transfer data in the data buffer in the 2nd Embodiment of this invention. It is a figure which shows the example of a part of transmission side memory of the 2nd Embodiment of this invention. It is a figure which shows the example of a part of receiving side memory of the 2nd Embodiment of this invention. It is a figure which shows the procedure of calculation of a storage element number, and determination of a storage buffer number in the 2nd Embodiment of this invention. It is a figure which shows the procedure of calculation of a storage element number, and determination of a storage buffer number in the 2nd Embodiment of this invention. It is a figure which shows the transfer packet produced | generated in the data transfer between the memory | storage devices when the subject is not solved of related technology. It is a figure which shows the operation | movement of writing to the receiving side memory of transfer packet data in the data transfer between memory | storage devices when the subject is not solved of related technology.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing the configuration of the first exemplary embodiment of the present invention. As shown in FIG. 1, the data transfer control device 300 according to the present embodiment includes a transfer command execution unit 330 and a transfer packet generation unit 350.

  The transfer command execution unit 330 requests a transmission side memory (not shown) to read transfer data in units of transmission side memory access based on a data transfer command including at least a transmission side transfer start address and a reception side transfer start address. A data read request is output. Also, the transfer command execution unit 330 outputs the transmission side transfer start address and the reception side transfer start address included in the data transfer command to the transfer packet generation unit 350. FIG. 2 is a diagram illustrating an example of a data transfer instruction. As shown in FIG. 2, the data transfer instruction 610 includes at least a transmission side transfer start address 611 and a reception side transfer start address 612. FIG. 3 is a diagram illustrating an example of a data read request. As shown in FIG. 3, the data read request 620 includes at least a read address 621.

  The transfer packet generation unit 350 transmits a transfer packet size (a transfer-side transfer start address 611, a reception-side transfer start address 612, a reception-side memory access unit (eg, 64 bytes), and transfer packet size when transferring transfer data from the transmission side to the reception side ( For example, based on 128 bytes), the transfer data output from the transmission side memory in response to the data read request 620 is divided at the boundary of the reception side memory access unit to generate and output a transfer packet.

  Next, the operation of the present embodiment will be described in detail with reference to FIGS.

  The address boundary between the transmission side transfer start address 611 and the reception side transfer start address 612 is an 8-byte boundary.

  The transmission side memory access unit and the reception side memory access unit are 64 bytes. Therefore, the address boundary of the transmission side memory access boundary address and the reception side memory access boundary address is a 64-byte boundary.

  The transmission-side transfer start address 611 is “A + 8” obtained by adding “8 (8-byte address increment value)” to a certain transmission-side memory access boundary address [A]. Note that “[A]” indicates that “A” is a value of a certain transmission side memory access boundary address (hereinafter, the same applies to other elements).

  The receiving-side transfer start address 612 is “B + 40” obtained by adding “40 (address increment value for 40 bytes)” to a certain receiving-side memory access boundary address [B].

  The transfer packet size is 128 bytes. That is, the size of the data buffer (not shown) for generating the transfer packet is 128 bytes. Note that the transfer packet generation unit 350 includes a plurality of data buffers.

  In the following description, the total transfer size indicating the amount of data transferred based on the data transfer command 610 is 64 × 58 = 3712 bytes. The transfer size may be included in the data transfer command, or may be held in advance in a storage unit (not shown) of the data transfer control device 300.

  FIG. 4 is a diagram illustrating an example of a part of the transmission-side memory in which transfer data is stored.

  In FIG. 4, transfer data is shown with identifiers D0 to D57 for each data unit of an 8-byte boundary that is the address boundary of the transmission-side transfer start address 611 (hereinafter, this data unit is referred to as element data). . Referring to FIG. 4, element data D0 (element data to which an identifier of D0 is attached, the same applies hereinafter) to element data D57 are transmitted from the transmission side memory access boundary address 371 [A] of the transmission side memory 370 to the transmission side memory access boundary. It is included in eight transmission side memory access units starting with each address 371 [A + 64 * 7].

  FIG. 5 is a diagram illustrating an example of a part of the reception-side memory in which transfer data is stored. Referring to FIG. 5, element data D0 to element data D57 are eight reception sides starting from the transmission side memory access boundary address 381 [B] of the reception side memory 380 to the transmission side memory access boundary address 381 [B + 64 * 7], respectively. It is included in the memory access unit.

  In the description of this operation, a data buffer that stores transfer data of a transfer packet to be transmitted first is called a current data buffer, and a data buffer that stores transfer data of a transfer packet to be transmitted next is called a next data buffer.

  Based on the above, the operation will be described below.

  6 and 7 are flowcharts showing the operation of this embodiment.

  First, the transfer command execution unit 330 acquires the transmission side memory access boundary address 371 [A] including the transmission side transfer start address 611 [A + 8] as the read address 621 (S402).

  Next, the transfer instruction execution unit 330 outputs a data read request 620 including the read address 621 (S404).

  Next, the transfer packet generator 350 receives the transfer data output from the transmission side memory 370 in response to the data read request 620 output in S404 (S406). If an example is shown based on the above-mentioned assumption, for example, when this step is performed for the first time, the transfer data to be received is element data D0 to D6. For example, when this step is performed for the second time, the transfer data to be received is element data D7 to D14. For example, when this step is executed for the third time, the transfer data to be received is element data D15 to D22.

  Next, the transfer packet generation unit 350 adds the reception-side transfer start address 612 [B + 40] and the address increment value corresponding to the size of the transfer data already written in the current data buffer, and calculates the current address (S408). . Taking an example based on the above assumption, for example, when this step is performed for the first time, the current address is B + 40. For example, when this step is executed for the second time, the current address is B + 40 + 56. For example, when this step is executed for the third time, the current address is B + 40 + 56 + 64.

  Next, when the address in the current data buffer in which the next transfer data is written is associated with the current address, the transfer packet generator 350 changes the “address corresponding to the current address” to “maximum address + 1”. The current data buffer address corresponding to the largest “address corresponding to the receiving-side memory access boundary address” is calculated as a limit address (S410). FIG. 8 is a diagram illustrating a specific example of the current address and the limit address.

  Referring to FIG. 8, an example based on the above-mentioned assumption will be described. For example, when this step is performed for the first time, the next transfer data is element data D0. The current data buffer address 352 for writing the transfer data is “0”. When this current data buffer address 352 is made to correspond to the current address 353 [B + 40], the receiving side memory corresponding to the current data buffer address 352 “0” to the current data buffer maximum +1 address 354 [8 * 16] Among the access boundary addresses, the maximum corresponding reception side memory access boundary address 355 which is the largest reception side memory access boundary address is “B + 64 * 2”. The current data buffer address 356 corresponding to the maximum corresponding receiving side memory access boundary address 355, that is, the limit address 357 is “8 * 11”.

  For example, when this step is performed for the second time, the next transfer data is the element data D7. The limit address is “8 * 11”, which is the current data buffer address corresponding to the receiving-side memory access boundary address [B + 64 * 2]. For example, when this step is executed for the third time, the next transfer data is the element data D15, and the limit address is the current data buffer maximum +1 address 354 corresponding to the receiving side memory access boundary address [B + 64 * 4]. “8 * 16”.

  Next, the transfer packet generation unit 350 checks whether or not the transfer data received in S406 falls below the limit address (S412). If it falls below the limit address (YES in S412), the process proceeds to S414. If it does not fall below the limit address (NO in S412), the process proceeds to S420. If an example is shown based on the above-mentioned premise, for example, when this step is performed for the first time, the second time, and the third time, YES in S412, NO in S412 and YES in S412, respectively.

  In S414, the transfer packet generation unit 350 writes the transfer data output from the transmission side memory 370 in response to the data read request 620 output in S404 in the current data buffer for packet generation (S414). If an example is shown based on the above-mentioned premise, for example, when this step is executed for the first time, the transfer data to be written to the current data buffer is element data D0 to D6. For example, when this step is performed for the second time, the current data buffer is the next data buffer, and the transfer data to be written to the current data buffer is the element data D15 to D18.

  Next, the transfer packet generation unit 350 checks whether or not the transfer data has been written up to the address immediately before the limit address of the current data buffer (transfer data write completion) (S416). If written (YES in S416), the process proceeds to S430. If not written (NO in S416), the process proceeds to S418. If an example is shown based on the above-mentioned assumption, for example, when this step is performed for the first time, the second time, and the third time, NO in S416, YES in S416, and NO in S416, respectively.

  Next, the transfer packet generation unit 350 checks whether or not the last transfer data (that is, the element data D57) has been written (the last write is completed) (S418). If written (YES in S418), the process proceeds to S430. If not written (NO in S418), the process proceeds to S432.

  In S420, the transfer packet generator 350 sends the transfer data output from the transmission-side memory 370 in response to the data read request 620 output in S404 to the transfer data that does not fit within the limit address. The data is divided into transfer data (S420). Subsequently, the transfer packet generation unit 350 writes the transfer data corresponding to less than the limit address in the current data buffer (S421). Subsequently, the transfer packet generation unit 350 writes the transfer data that has not been written to the current data buffer, that is, the transfer data that does not fall below the limit address, to the next data buffer (S422). If an example is shown based on the above-mentioned premise, for example, when this step is executed for the first time, the transfer data to be written to the current data buffer is element data D0 to D6. For example, when this step is performed for the second time, the transfer data to be written to the current data buffer is element data D7 to D10, and the transfer data to be written to the next data buffer is element data D11 to D14.

Next, the transfer packet generation unit 350 generates a transfer packet by adding the reception memory write address of the head data (for example, element data D0) to the transfer data (for example, element data D0 to D10) in the current data buffer. And output (S423). FIG. 9 is a diagram illustrating an example of the first transfer packet 631. As shown in FIG. 9, in the transfer packet 631, “B + 40” that is the reception side transfer start address 612 is added as the reception side memory write address, and element data D0 to D10 are stored. FIG. 10 is a diagram illustrating an example of the second transfer packet 632. As shown in FIG. 10, the transfer packet 632 adds the transfer data length (for example, 88) transferred by the first transfer packet 631 to the reception-side transfer start address 612 [B + 40] as the reception-side memory write address. The value (ie, “B + 64 * 2” which is the receiving side memory access boundary address) is added, and element data D11 to D26 are stored.
FIG. 11 is a diagram illustrating an example of the third transfer packet 633. The details of the transfer packet 633 may be considered in the same manner as the transfer packet 632, and thus the description thereof is omitted.

  Next, the transfer packet generator 350 confirms whether or not the last transfer data (that is, the element data D57) has been written in the next data buffer (S424). If written (YES in S424), the process proceeds to S430. If not written (NO in S424), the process proceeds to S426.

  In S426, the transfer packet generator 350 sets the next data buffer as the current data buffer, and further sets the next data buffer as the next data buffer (S426). Then, the process proceeds to S434.

  In S430, the transfer packet generation unit 350 adds the transfer data (for example, element data D0 to D10) in the current data buffer to the reception side transfer start address as the write address of the head data (ie, element data D0) to the reception side memory. A transfer packet with 612 added is generated and output (S430). FIG. 12 is a diagram illustrating an example of the fourth transfer packet 634. The details of the transfer packet 633 may be considered in the same manner as the transfer packet 632, and thus the description thereof is omitted.

  Next, the transfer command execution unit 330 confirms whether or not reading of transfer data for the total transfer size transferred in the processing of the data transfer command 610 has been completed (S432). If completed (YES in S432), the process ends. If not completed (NO in S432), the process proceeds to S434.

  In S434, the transfer instruction execution unit 330 updates the read address 621 and outputs a data read request 620 (S434). Then, the process proceeds to S404. The transfer instruction execution unit 330 adds an address increment value (for example, 64) for the transmission side memory access unit (64 bytes) to the read address 621 of the data read request 620 output previously, thereby reading the read address 621. Update.

  The data transfer control device 300 according to the present embodiment operates as described above.

  Note that when the transfer packet transmitted by the data transfer control device 300 is received, the storage device on the receiving side operates as follows.

  First, the storage device on the receiving side receives the transfer packet 631 transmitted by the data transfer control device 300 via, for example, the inter-node network.

  Next, the storage device on the receiving side writes the element data D0 to D10 based on “B + 40” indicated as the receiving side memory write address of the receiving side memory 380 based on the transfer packet 631. The areas in which the element data D0 to D2 and the element data D3 to D10 are written are not included in the reception-side memory access boundary address, that is, included in one reception-side memory access unit. Therefore, the storage device on the receiving side writes the transfer data received by the transfer packet 631 with a minimum of two write operations.

  Thereafter, the storage device on the receiving side processes the transfer packets 632 to 634 in the same manner.

  Next, a case where the data transfer control device 300 is configured to cause a computer to execute predetermined processing by a program will be described.

  FIG. 13 is a block diagram illustrating a configuration of a data transfer control device 300 (also referred to as a computer) that causes a computer to execute predetermined processing using a program.

  Referring to FIG. 13, the data transfer control device 300 includes a CPU (Central Processing Unit) 302, a disk device 303, a storage unit 304, an upper interface unit 305, and an inter-node network interface unit 306.

  The CPU 302 expands the program stored in the disk device 303 to the storage unit 304, for example, and executes processing based on the flowcharts shown in FIGS. 6 and 7 based on the expanded program.

  The disk device 303 stores a program that causes a computer to execute the processing of the data transfer control device 300 described above.

  The storage unit 304 stores the program and control information for operating the program, and stores transfer data as the above-described transmission-side memory and a transfer packet as a data buffer.

  The upper interface unit 305 transmits and receives to / from a circuit device or apparatus that issues a data transfer command based on an instruction from the CPU 302.

  The inter-node network interface unit 306 transmits and receives to and from the inter-node network based on instructions from the CPU 302. Here, the node corresponds to the transmission side node or the reception side node accommodating the data transfer apparatus 300 shown in FIG. 1, and the inter-node network is a network to which the transmission side node or the reception side node is connected.

  The effect of the present embodiment described above is to prevent the memory access performance of the data to be transferred from deteriorating when the data to be transferred does not satisfy the address boundary condition in the apparatus that performs data transfer via the packet switching network. It is a point that becomes possible.

The reason is that the transfer instruction execution unit 330 reads the transfer data in units of the transmission side memory access based on the transmission side transfer start address 611 and the reception side transfer start address 612, and the transfer packet generation unit 350 This is because, based on the start address 611, the reception side transfer start address 612, the reception side memory access unit, and the transfer packet size, the transfer data is divided at the boundary of the reception side memory access unit to generate the transfer packet. .
[Second Embodiment]
Next, a second embodiment of the present invention will be described in detail with reference to the drawings. Hereinafter, the description overlapping with the above description is omitted as long as the description of the present embodiment is not obscured.

  First, the outline of the operation of the data transfer system to which the data transfer control device according to this embodiment is applied will be described.

  FIG. 14 is a block diagram showing the configuration of the data transfer system 10 to which the data transfer control device according to this embodiment is applied. Referring to FIG. 14, in the data transfer system 10, a communication node 100 and a communication node 110 are connected by an inter-node network 120.

  The communication node 100 includes a requester 101, a memory 103, and a data transfer control device 200.

  The requester 101 issues a data transfer instruction by issuing a data transfer command to the data transfer control device 200.

  The memory 103 stores transfer data 104.

  The communication node 110 includes a memory 113 and a reception side packet transfer control unit 112.

  The memory 113 stores transfer data 114.

  The inter-node network 120 performs communication by at least packet switching.

  Note that the communication node 100 may further include an element similar to the element included in the communication node 110. The communication node 110 may further include an element similar to the element included in the communication node 100.

  Each of the communication node 100 and the communication node 110 may be one or more arbitrary numbers.

  In the following description, the communication node 100 is described as a transmission side node, and the communication node 110 is described as a reception side node. Therefore, in the following description, the memory 103 is a transmission side memory 370 as shown in FIG. 4, and the memory 113 is a reception side memory 380 as shown in FIG.

  First, the requester 101 outputs a data transfer command to the data transfer control device 200. FIG. 15 is a diagram illustrating an example of the data transfer instruction 650. As shown in FIG. 15, the data transfer instruction 650 includes a transmission side transfer start address 611, a reception side transfer start address 612, and a total transfer size 613.

  Next, the data transfer control device 200 that has received the data transfer command 650 decomposes the total transfer size 613 into the sizes of transfer packets for inter-node transfer, and reads the transfer data 104 from the memory 103.

  Subsequently, the data transfer control device 200 generates, for example, transfer packets 105 to 108 (corresponding to the transfer packets 631 to 634 shown in FIGS. 9 to 12, but the storage positions of the element data are not necessarily the same), and the inter-node network Transmit to the network 120.

  Next, the reception side packet transfer control unit 112 of the communication node 110 receives the transfer packets 105 to 108 transmitted by the transmission side node as transfer packets 115 to 118 from the inter-node network 120.

  Next, the reception side packet transfer control unit 112 writes the received transfer data 104 to the memory 113 as transfer data 114 for each transfer packet.

  In the generation of the transfer packets 105 to 108 described above, first, the data transfer control device 200 stores the transfer data 104 read from the memory 103 relative to the transfer packet for each element data having 8 bytes as one unit. A number indicating the position (hereinafter referred to as an element number) is added. The element number may be added to the read data by the memory 103 and output to the data transfer control device 200.

  Subsequently, the data transfer control device 200 corrects the element number so that the boundary between the transfer packets 105 to 108 matches the memory access boundary of the memory 113.

  Subsequently, the data transfer control device 200 divides the transfer data 104 based on the corrected element number and stores it in the transfer packet.

  The above is the outline of the operation of the data transfer system to which the data transfer control device 200 according to this embodiment is applied.

  Next, details of the data transfer control device 200 according to the present embodiment will be described.

  FIG. 16 is a block diagram showing the configuration of the data transfer control device 200 according to this embodiment.

Referring to FIG. 16, the data transfer control device 200 according to the present embodiment includes an instruction reception issue unit 210, a packet division unit 220, a memory request issue unit 230, an element number correction unit 240, a packet data alignment unit 250, and a transfer packet issue. Section 260, correction information generation section 280, and element number assignment section 290. Compared to the first embodiment, in the data transfer control device 200 according to the present embodiment, the command reception issue unit 210, the packet division unit 220, and the memory request issue unit 230 are included in the transfer command execution unit 330 of the first embodiment. Correspondingly, the packet data aligning unit 250 and the transfer packet issuing unit 260 correspond to the transfer packet generating unit 350 of the first embodiment. Furthermore, in the data transfer control device 200 according to the present embodiment, an element number correction unit 240, a correction information generation unit 280, and an element number assignment unit 290 are added as compared to the first embodiment. Receives a data transfer instruction 650 from the requester 101 shown in FIG. Then, the command reception issue unit 210 outputs the transmission side transfer start address 611, the reception side transfer start address 612, and the total transfer size 613 to the packet division unit 220 based on the received data transfer command 610. In addition, the command reception issuance unit 210 outputs the transmission side transfer start address 611 and the reception side transfer start address 612 to the correction information generation unit 280.

  Based on the received transmission-side transfer start address 611, reception-side transfer start address 612, and total transfer size 613, the packet division unit 220 reads the read address of the memory 103 shown in FIG. (Hereinafter, referred to as “transmission side packet address”) and a write address (hereinafter, referred to as “reception side packet address”) of the reception side memory are generated.

  Further, the packet division unit 220 outputs a data buffer request for aligning transfer data for one packet to the packet data alignment unit 250. Next, the packet division unit 220 receives the data buffer number output by the packet data alignment unit 250 as a response to the data buffer request. FIG. 17 is a diagram illustrating an example of the data buffer number 641 output from the packet data alignment unit 250.

  Note that transfer data read in units of memory access on the transmission side may be divided into two packets and stored. Therefore, the packet division unit 220 requests and acquires two data buffer numbers 641 for the current data buffer number and the next data buffer number. Thereafter, the packet division unit 220 uses the current next data buffer number as the current data buffer number of the next transfer packet, newly acquires the data buffer number 641 and uses it as the next data buffer number.

Next, the packet dividing unit 220 outputs 1-packet information 643 that is memory access information in units of packets to the memory request issuing unit 230. FIG. 18 is a diagram illustrating an example of 1-packet information 643. As shown in FIG. 18, one packet information 643 includes a transmission side packet address 671, a current data buffer number 672, and a next data buffer number 673.
At the same time, the packet dividing unit 220 outputs the packet address on the packet side that is the header information of the transfer packet to the packet data alignment unit 250. FIG. 19 is a diagram illustrating an example of the reception-side packet address 642 output by the packet dividing unit 220.

  The correction information generation unit 280 calculates correction information (also referred to as m) based on the transmission-side transfer start address 611 and the reception-side transfer start address 612. FIG. 20 is a diagram illustrating an example of the correction information 675 calculated by the correction information generation unit 280. The correction information 675 includes a value indicating the difference between the transmission side transfer start address 611 and the memory access boundary address of the transmission side memory access unit including the transmission side transfer start address 611, the reception side transfer start address 612, and the reception side memory access including the difference. This is a difference from a value indicating the difference from the unit memory access boundary address in terms of the number of elements. Then, the correction information generation unit 280 outputs the calculated correction information 675 to the element number correction unit 240.

  Based on the received 1-packet information 643, the memory request issuing unit 230 generates memory request information for each transmission-side memory access unit. FIG. 21 is a diagram illustrating an example of the memory request information 644. As shown in FIG. 21, the memory request information 644 includes a current data buffer number 672, a next data buffer number 673, and an in-packet request number 674. The in-packet request number 674 is a number indicating, in 0 origin, the order of memory read requests in one packet issued by the memory request issuing unit 230 a plurality of times when the transfer size of one packet is larger than the memory access unit on the transmission side. is there.

  Subsequently, the memory request issuing unit 230 outputs a memory read request including the transmission side memory access boundary address 371 to the memory 103 based on the transmission side packet address 671. At the same time, the memory request issuing unit 230 outputs the memory request information 644 to the element number giving unit 290.

  In response to the received memory read request, the memory 103 outputs, to the element number assigning unit 290 of the data transfer control device 200, the transfer data in the transmission side memory access unit read based on the address specified by the memory read request. To do.

  The element number assigning unit 290 generates transmission-side memory access unit data from the transfer data received from the memory 103, and outputs it to the element number correcting unit 240. FIG. 22 is a diagram illustrating an example of the transmission-side memory access unit data 645. As shown in FIG. 22, the transmission-side memory access unit data 645 includes an element number 686 and a plurality of sets of corresponding element data 640, a current data buffer number 672, a next data buffer number 673, and an in-packet request number 674. .

  The element number assigning unit 290 receives the transmission data in the transmission side memory access unit transmitted from the memory 103 and generates the transmission side memory access unit data 645 as follows, for example. First, the element number assigning unit 290 assigns element numbers 686 with 0 origin to the element data 640 included in the received transfer data in ascending order of the addresses stored in the memory 103. Next, the element number assigning unit 290 arranges the assigned element number 686 and the corresponding element data 640 in pairs, and further adds the current data buffer number 672, the next data buffer number 673, and the in-packet request number 674. To do.

  Note that the element number assigning unit 290 may be included in the memory 103.

  The element number correction unit 240 generates data buffer storage data and outputs it to the packet data alignment unit 250.

  FIG. 23 is a diagram illustrating an example of the data buffer storage data 647. Referring to FIG. 23, data buffer storage data 647 includes a plurality of sets of storage buffer number 649, storage element number 688, and element data 640.

  Based on the transmission-side memory access unit data 645 received from the element number assignment unit 290 and the correction information 675 received from the correction information generation unit 280, the element number correction unit 240 performs data buffer storage data 647 as follows. Is generated. First, the data buffer storage data 647 corrects the element number 686 based on the in-packet request number 674 and the correction information 675 to calculate the storage element number 688. Subsequently, the element number correction unit 240 determines the storage buffer number 649 of the data buffer that stores the element data 640 based on the current data buffer number 672, the next data buffer number 673, and the storage element number 688. Subsequently, the element number correction unit 240 adds the storage element number 688 and the storage buffer number 649 to each element data 640.

  The element number correction unit 240 includes, for example, a data buffer storage element number calculation circuit corresponding to each element data included in the transmission side memory access unit, and calculates the storage element number 688 corresponding to each element data in parallel. May be.

  The packet data alignment unit 250 includes data buffers 251 to 254. Each of the data buffers 251 to 254 has a data buffer number 641 of “0” to “4”.

  In response to the received data buffer request, the packet data alignment unit 250 outputs one of the data buffer numbers 641 among the unused data buffers 251 to 254. Further, the packet data alignment unit 250 receives the data buffer storage data 647, and based on the storage buffer number 649 and the storage element number 688 added to each element data 640, the packet data alignment unit 250 takes the corresponding position in the corresponding data buffer. Element data 640 is stored.

  The transfer packet issuing unit 260 adds the reception side packet address 642 as header information to the data in the data buffer in which the element data has been stored, and transmits the packet to the internode network 120 shown in FIG. Then, the transfer packet issuing unit 260 releases the data buffer when the transmission process is completed.

  Next, the operation of the present embodiment will be described in detail with reference to the drawings. Note that the premise in the description of the operation of the present embodiment is that the data buffers 251 to 254 are included in the packet data alignment unit 250 and the transmission side memory is different from the premise in the description of the operation of the first embodiment. 370 and the receiving side memory 380 correspond to the memory 103 and the memory 113, respectively.

  FIG. 24 is a flowchart showing the operation of this embodiment.

  First, based on the received data transfer command 650, the command reception / issuing unit 210 sends the transmission side transfer start address 611, the reception side transfer start address 612, and the total transfer size 613 to the packet division unit 220, and the correction information generation unit 280. The transmission side transfer start address 611 and the reception side transfer start address 612 are output to (S502).

  Next, the packet dividing unit 220 generates a transmission side packet address 671 and a reception side packet address 642 based on the received transmission side transfer start address 611, reception side transfer start address 612, and total transfer size 613 ( S504). Specifically, the packet division unit 220 generates a transmission side packet address 671 and a reception side packet address 642 in units of 128 bytes from the 64-byte boundary address including the transfer data for the total transfer size.

  To give an example based on the above-mentioned assumption, the packet dividing unit 220 generates a transmission side packet address 671 [A + 64 * n (n = 0, 2, 4, 6)] and receives a reception side packet address 642 [B + 64 *. n (n = 0, 2, 4, 6)] is generated.

  Next, the packet division unit 220 acquires the data buffer number from the packet data alignment unit 250 (S506). Note that the packet division unit 220 acquires two data buffer numbers 641 for the current data buffer number 672 and the next data buffer number 673 when executing S506 for the first time. Then, when executing S506 for the second time or later, the packet dividing unit 220 sets the current next data buffer number 673 as the next current data buffer number 672, and one data buffer number for the next next data buffer number 673. 641 is newly acquired.

  Here, the case where the two data buffers 251 to 254 of the current data buffer and the next data buffer are necessary will be specifically described.

  FIG. 25 is a diagram illustrating an operation of storing transfer data read from the memory 103 in a data buffer.

  Each of the memory read data 651 to 654 is transfer data read from the memory 103 (that is, the transmission side memory 370 shown in FIG. 4) based on the transmission side packet address 671.

  The transfer packet data 661 to 663 are transfer data stored in the data buffers 251 to 254 in units of writing to the memory 113 (that is, the reception side memory 380 shown in FIG. 5).

  As shown in FIGS. 4 and 5, the transmission-side transfer start address 611 [A + 8] and the reception-side transfer start address 612 [B + 40] have a shift in the 8-byte boundary position within the memory access boundary.

  In such a case, for example, the packet data alignment unit 250 divides the memory read data 652 into transfer packet data 661 and transfer packet data 662 and stores them in the data buffers 251 to 254.

  Therefore, the packet division unit 220 outputs the one packet information 643 including the current data buffer number 672 and the next data buffer number 673.

  Next, the packet dividing unit 220 generates 1-packet information 643 that is memory access information in units of packets, and outputs the packet information 643 to the memory request issuing unit 230 (S508).

  Subsequently, the packet division unit 220 outputs the reception side packet address 642 to the packet data alignment unit 250 (S510).

  Next, the correction information generation unit 280 calculates correction information 675 based on the transmission-side transfer start address 611 and the reception-side transfer start address 612, and outputs the calculated correction information 675 to the element number correction unit 240. (S512). Below, an example is shown based on the above-mentioned premise.

  As shown in FIG. 4, the transmission side transfer start address 611 is “A + 8”, and the number of elements of the difference “8” from the memory access boundary address [A] of the transmission side memory access unit including this is “1”. is there.

  As shown in FIG. 5, the receiving side transfer start address 612 is “B + 40”, and the number of elements of the difference “40” from the memory access boundary address [B] of the receiving side memory access unit including this is “5”. is there. Therefore, the correction information generation unit 280 calculates the correction information 675 [4 (5-1 = 4)].

  For example, when the transfer data is stored in the transmission side memory 370 as illustrated in FIG. 26 and the transfer data is stored in the reception side memory 380 as illustrated in FIG. 27, the correction information generation unit 280 includes the correction information 675. Is calculated as follows. However, FIG. 26 is a diagram illustrating an example of a part of the transmission side memory 370. FIG. 27 is a diagram illustrating an example of a part of the reception-side memory 380. 26, when the transmission-side transfer start address 611 is “A + 40” and the reception-side transfer start address 612 is “B + 8” as shown in FIG. 27, the correction information generation unit 280 corrects the correction information 675 [−4 ( 1-5 = −4)] is calculated.

  Next, the memory request issuing unit 230 generates memory request information 644 for each transmission side memory access unit, outputs the memory request information 644 to the element number assigning unit 290, and outputs a memory read request to the memory 103 (S514). In the case of the above premise, the memory request issuing unit 230 executes transmission of the memory request information 644 in units of memory access and the corresponding memory read request twice based on the received one packet information 643.

  In response to the received memory read request, the memory 103 outputs the transfer data in the transmission side memory access unit read based on the address specified in the memory read request to the data transfer control device 200 (S516).

  Next, the element number assigning unit 290 generates the transmission side memory access unit data 645 and outputs it to the element number correcting unit 240 (S518).

  Next, the element number correction unit 240 generates the data buffer storage data 647 and outputs it to the packet data alignment unit 250 (S520).

  Below, based on the above-mentioned premise, a specific example of calculation of the storage element number 688 and determination of the storage buffer number 649 included in the data buffer storage data 647 will be described below. FIG. 28 and FIG. 29 are diagrams showing procedures for calculating the storage element number 688 and determining the storage buffer number 649.

  First, the element number correction unit 240 reads 1 from the element number 686 (j) and the in-packet request number 674 (h) included in the received transmission-side memory access unit data 645 as the transmission-side packet address 671. The packet element number 687 (k) is calculated (k = j + h * 8). Specifically, the element number correction unit 240 calculates “0” to “7” as the element number 687 for each packet of the element data of the memory read data 651, and 1 packet of each element data of the memory read data 652 “8” to “15” are calculated as the minute element numbers 687.

  Next, the element number correction unit 240 corrects the element number 687 for one packet with the correction information 675 (k + m), and calculates the storage element number 688. Specifically, the element number correction unit 240 calculates “4” to “11” as the storage element number 688 of each element data of the memory read data 651 and stores the storage element number 688 of each element data of the memory read data 652. As a result, “12” to “19” are calculated.

  Here, since the maximum packet size is 128 bytes, the maximum value of the storage element number 688 is “15”. Therefore, the element number correction unit 240 converts the storage element numbers 688 calculated as “16” to “19” into “0” to “3”.

  Thus, the element number correction unit 240 calculates the storage element number 688.

  Next, the element number correction unit 240 determines “0” that is the current data buffer number 672 as the storage buffer number 649 from the first element data 640 to the element data 640 whose storage element number 688 is “15”. At the same time, the element number correction unit 240 determines “1” which is the next data buffer number 673 as the storage buffer number 649 from the element data 640 having the storage element number 688 of “0” to the last element data 640.

  Thereafter, the element number correction unit 240 processes the memory read data 653 and subsequent data corresponding to the next one packet information 643 in the same manner. The current data buffer number 672 corresponding to the memory read data 653 is the same as the next data buffer number 673 corresponding to the memory read data 651 and the memory read data 652. Therefore, the element data 640 having the storage element number 688 of “4” to “11” in the memory read data 653 is followed by the element data 640 having the storage element number 688 of the memory read data 652 of “0” to “3”. The data buffer number 641 is stored in the data buffer 252 with “1”.

  The packet data alignment unit 250 receives the data buffer storage data 647 and stores the element data 640 in the corresponding data buffer based on the storage buffer number 649 and the storage element number 688 added to each element data 640.

  Next, the transfer packet issuing unit 260 adds the reception side packet address 642 as header information to the data in the data buffer in which the element data has been stored, and transmits the packet to the inter-node network 120 as a transfer packet (S522). The transfer packet issuing unit 260 releases the data buffer when the transmission process is completed.

  Next, the packet division unit 220 confirms whether or not the 1-packet information 643 has been output (transfer data transmission completion) for all the transmission-side packet addresses 671 generated in S504 (S524). If the transmission is completed (YES in S524), the process ends. If transmission has not been completed (NO in S524), the process proceeds to S506.

  The effect of the present embodiment described above is that the time for generating a transfer packet can be shortened in addition to the effect of the first embodiment.

  The reason is that the element number assigning unit 290 assigns an element number 686 to each element data 640, the element number correcting unit 240 corrects each element number 686 in parallel to calculate the storage element number 688, and the packet data aligning unit This is because 250 generates a transfer packet based on the storage element number 688.

  In the following, in an apparatus that performs data transfer via a packet switching network, for example, because it is not configured as in the first or second embodiment, the memory access performance of the data to be transferred is not reduced. The case where the problem has not been solved will be specifically described. The preconditions are the same as the preconditions described above.

  FIG. 30 is a diagram illustrating a transfer packet generated in the data transfer between the storage devices in which the problem has not been solved.

  As shown in FIG. 30, first, the transmission side storage device (not shown) reads data from the transmission side memory 370 based on the transmission side transfer start address 611. Next, the transmission side storage device generates transfer packet data divided in units of the read data, such as first transfer packet data to fourth transfer packet data.

  Next, the transmission side storage device receives the first transfer packet to the fourth transfer packet (not shown) including the first transfer packet data to the fourth transfer packet data through the packet switching network (not shown). Transfer to the side storage device (not shown).

  FIG. 31 is a diagram illustrating an operation of writing transfer packet data to the reception-side memory 380 in the reception-side storage device.

  The receiving side storage device executes, for example, memory writing of the first transfer packet three times (memory writing 1 to 3 of the first transfer packet) based on the receiving side transfer start address 612, for example, memory writing of the second packet. Execute 3 times (second transfer packet memory write 1 to 3). Also, for example, the memory transfer 3 of the first transfer packet and the memory write 1 of the second transfer packet are written to the same memory access unit, and the other memory write is awaited during one memory write. .

  For example, when generating a transfer packet that reduces the number of writes in the receiving side storage device based on the receiving side transfer start address, the sending side storage device performs memory read twice for the same address. There is a need. As a result, the memory access performance on the transmission side storage device side is degraded.

  As described above, in a storage device that performs data transfer between storage devices via a packet switching network, for example, when the storage device is not configured as in the first or second embodiment, the memory access performance of the data to be transferred is increased. The problem of not reducing it is not solved.

  Each component described in each of the above embodiments does not necessarily have to be individually independent. For example, for each component, a plurality of components may be realized as one module, or one component may be realized as a plurality of modules. Each component is configured such that a component is a part of another component, or a part of a component overlaps a part of another component. Also good.

  Further, in each of the embodiments described above, a plurality of operations are described in order in the form of a flowchart, but the described order does not limit the order in which the plurality of operations are executed. For this reason, when each embodiment is implemented, the order of the plurality of operations can be changed within a range that does not hinder the contents.

  Furthermore, in each embodiment described above, a plurality of operations are not limited to being executed at different timings. For example, another operation may occur during the execution of a certain operation, or the execution timing of a certain operation and another operation may partially or entirely overlap.

  Furthermore, in each of the embodiments described above, a certain operation is described as a trigger for another operation, but the description does not limit all relationships between the certain operation and the other operations. For this reason, when each embodiment is implemented, the relationship between the plurality of operations can be changed within a range that does not hinder the contents. The specific description of each operation of each component does not limit each operation of each component. For this reason, each specific operation | movement of each component may be changed in the range which does not cause trouble with respect to a functional, performance, and other characteristic in implementing each embodiment.

  Each component in each embodiment described above may be realized by hardware, software, or a mixture of hardware and software, if necessary. May be.

  Further, the physical configuration of each component is not limited to the description of the above embodiment, and may exist independently, may exist in combination, or may be configured separately. May be.

DESCRIPTION OF SYMBOLS 100 Communication node 101 Requester 103 Memory 104 Transfer data 105-108 Transfer packet 110 Communication node 112 Reception side packet transfer control part 113 Memory 114 Transfer data 115 Transfer packet 120 Inter-node network 200 Data transfer control apparatus 210 Command reception issue part 220 Packet Dividing unit 230 Memory request issuing unit 240 Element number correcting unit 250 Packet data alignment unit 251 to 254 Data buffer 260 Transfer packet issuing unit 280 Correction information generating unit 290 Element number giving unit 300 Data transfer control device 302 CPU
303 Disk Device 304 Storage Unit 305 Upper Interface Unit 306 Inter-Node Network Interface Unit 330 Transfer Command Execution Unit 350 Transfer Packet Generation Unit 352 Current Data Buffer Address 353 Current Address 354 Current Data Buffer Maximum + 1 Address 355 Maximum Corresponding Receiver Memory Access Boundary Address 356 Current data buffer address 357 Limit address 370 Transmit memory 371 Transmit memory access boundary address 380 Receive memory 381 Transmit memory access boundary address 610 Data transfer instruction 611 Transmit transfer start address 612 Receive transfer start address 613 Total transfer size 620 Data read request 621 Read address 631 Transfer packet 632 Transfer packet 633 Transfer packet 634 Transfer packet 640 Element data 641 Data buffer number 642 Reception side packet address 643 1 packet information 644 Memory request information 645 Transmission side memory access unit data 647 Data buffer storage data 649 Storage buffer number 650 Data transfer instruction 651-654 Memory read Data 661 to 663 Transfer packet data 671 Transmission side packet address 672 Current data buffer number 673 Next data buffer number 674 Request number in packet 675 Correction information 686 Element number 687 Element number for one packet 688 Storage element number

Claims (10)

Based on a data transfer instruction including at least a transmission-side transfer start address and a reception-side transfer start address, execution of a transfer instruction that outputs a data read request that requests the transmission-side memory to read transfer data in units of transmission-side memory access And
Based on the transmission side transfer start address, the reception side transfer start address, a reception side memory access unit, and a transfer packet size when transferring the data from the transmission side to the reception side, the transmission side in response to the data read request The transfer data output from the side memory is divided at the boundary of the reception side memory access unit, and the transfer data is divided to the maximum within a range not exceeding the transfer packet size and to the reception side memory of the transfer data A transfer packet generation unit that generates and outputs a transfer packet for a packet switching network including a write address of An element for giving each element data an element number indicating the order of element data within the transmission side memory access unit, with the data divided in units of address boundaries that can be the transmission side transfer start address as element data. A numbering unit;
The number of the element data included in the difference between the transmission side transfer start address and the boundary address of the transmission side memory access unit including the boundary, the boundary of the reception side memory access unit including the reception side transfer start address and the reception side transfer start address A correction information generation unit that calculates, as correction information, the number of differences from the number of element data included in the difference from the address,
The transfer packet generation unit corrects the element number based on the correction information and converts it into a storage element number,
The data transfer control device according to claim 1, further comprising: a packet data alignment unit that stores the transfer data in the transfer packet based on the storage element number. The element number assigning unit, when the transfer packet size is n (n is a natural number) times the transmission-side memory access unit, the transfer data of the transmission-side memory access unit read from the transmission-side memory. A request number from 0 to n-1 is periodically associated with each element data and given to each element data,
The element number correction unit adds a number obtained by multiplying the element number by the request number and the number of element data corresponding to the transmission side memory access unit, and the added element number is based on the correction information. The data transfer control device according to claim 2, wherein the data is converted into the storage element number after correction. A device that transfers data via a packet switching network
Based on a data transfer command including at least a transmission-side transfer start address and a reception-side transfer start address, a data read request is output to request the transmission-side memory to read transfer data in a transmission-side memory access unit,
Based on the transmission side transfer start address, the reception side transfer start address, a reception side memory access unit, and a transfer packet size when transferring the data from the transmission side to the reception side, the transmission side in response to the data read request The transfer data output from the side memory is divided at the boundary of the reception side memory access unit, and the transfer data is divided to the maximum within a range not exceeding the transfer packet size and to the reception side memory of the transfer data Generate and output a packet for packet switching that includes the write address of A device that transfers data via a packet switching network
To the transfer data, as element data, data that is delimited in units of address boundaries that can be the transmission-side transfer start address, an element number indicating the element data order within the transmission-side memory access unit is given to each element data,
The number of the element data included in the difference between the transmission side transfer start address and the boundary address of the transmission side memory access unit including the boundary, the boundary of the reception side memory access unit including the reception side transfer start address and the reception side transfer start address Calculating the number of differences from the number of element data included in the difference from the address as correction information,
Based on the correction information, the element number is corrected and converted into a storage element number,
The data transfer control method according to claim 4, wherein the transfer data is stored in the transfer packet based on the storage element number. A device that transfers data via a packet switching network
When the transfer packet size is n (n is a natural number) times the transmission-side memory access unit, 0 to n−1 for each transfer data of the transmission-side memory access unit read from the transmission-side memory. The request numbers are periodically associated with each element data,
The correction of the element number is performed by adding a number obtained by multiplying the element number by the request number and the number of element data corresponding to the transmission side memory access unit, and the added element number is based on the correction information. The data transfer control method according to claim 5, wherein the data is corrected and converted into the storage element number. Based on a data transfer command including at least a transmission-side transfer start address and a reception-side transfer start address, a data read request is output to request the transmission-side memory to read transfer data in a transmission-side memory access unit,
Based on the transmission side transfer start address, the reception side transfer start address, a reception side memory access unit, and a transfer packet size when transferring the data from the transmission side to the reception side, the transmission side in response to the data read request The transfer data output from the side memory is divided at the boundary of the reception side memory access unit, and the transfer data is divided to the maximum within a range not exceeding the transfer packet size and to the reception side memory of the transfer data A program that causes a computer to execute a process that generates and outputs a transfer packet for a packet-switched network that includes the write address of the packet .
To the transfer data, as element data, data that is delimited in units of address boundaries that can be the transmission-side transfer start address, an element number indicating the element data order within the transmission-side memory access unit is given to each element data,
The number of the element data included in the difference between the transmission side transfer start address and the boundary address of the transmission side memory access unit including the boundary, the boundary of the reception side memory access unit including the reception side transfer start address and the reception side transfer start address Calculating the number of differences from the number of element data included in the difference from the address as correction information,
Based on the correction information, the element number is corrected and converted into a storage element number,
8. The program according to claim 7, which causes a computer to execute a process of storing the transfer data in the transfer packet based on the storage element number. When the transfer packet size is n (n is a natural number) times the transmission-side memory access unit, 0 to n−1 for each transfer data of the transmission-side memory access unit read from the transmission-side memory. The request numbers are periodically associated with each element data,
The correction of the element number is performed by adding a number obtained by multiplying the element number by the request number and the number of element data corresponding to the transmission side memory access unit, and the added element number is based on the correction information. The program according to claim 8, which causes a computer to execute a process of correcting and converting to the storage element number. A data transfer system including a communication node equipped with the data transfer control device according to claim 1.

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