JP5306930B2 - Compound storage device - Google Patents

Description

  The present invention relates to a composite storage device including a plurality of storage media having different data processing speeds.

  In the past, for the purpose of increasing the access speed to the hard disk, "Semiconductor memory is combined with the hard disk, the hard disk is continuously accessed to continuous addresses, and the semiconductor memory is randomly accessed. (For example, refer to Japanese Patent Application Laid-Open No. 2007-293564, etc.) ”or“ Combining a hard disk with a semiconductor memory and controlling access to the hard disk and the semiconductor memory in response to an external access request (for example, Japanese Patent Application Laid-Open No. 2005-2005). -190187, etc.) ”,“ If a semiconductor memory is combined with a hard disk and external data can be stored in the semiconductor memory, the external data is compressed and stored in the semiconductor memory, and the external data cannot be stored in the semiconductor memory. If the external data is Be stored in de disc (see, for example, JP-A-2003-150415) "has been proposed.

JP 2007-293564 A JP 2005-190187 A JP 2003-150415 A

  By the way, in recent years, when one hard disk is logically divided and each divided area is assigned to a plurality of users to use the hard disk, or one hard disk is logically divided and a different operating system is installed for each divided area. There is a case. In such a case, there is a case where it is desired to increase the access speed for a specific divided area.

  An object of the present invention is to make it possible to increase the data processing speed for a specific divided area of a hard disk logically divided into a plurality of divided areas.

  A composite storage device according to a first aspect includes a first storage medium, a second storage medium, and a storage area association unit. Here, the first storage medium is, for example, a hard disk. The second storage medium is, for example, a semiconductor memory (flash memory or the like). In the first storage medium, the storage area is logically divided into a plurality of divided areas. The second storage medium has a storage capacity that is equal to or greater than the storage capacity of at least one of the plurality of divided areas. The second storage medium has a data processing speed higher than that of the first storage medium. The storage area association unit associates the storage area of the second storage medium with at least one of the divided areas of the first storage medium having a storage capacity equal to or less than the storage capacity of the second storage medium.

  For this reason, in this composite storage device, the reading process and the writing process for the divided area associated with the storage area of the second storage medium are performed at a higher speed than the first storage medium. ) Can be performed in the storage area of the second storage medium. Therefore, in this composite storage device, the data processing speed for a specific divided area of the first storage medium (for example, a hard disk) can be increased.

  In addition, when the reading process is performed on the divided area associated with the storage area of the second storage medium, the data stored in the divided area needs to be copied to the storage area of the second storage medium.

A composite storage device according to a second aspect of the present invention is the composite storage device according to the first aspect of the present invention, further comprising a first process target determining unit. When at least one of the reading process and the writing process is requested for the divided area, the first processing target determining unit determines the process if the storage area of the second storage medium is associated with the divided area. The target is determined to be the second storage medium, and if the storage area of the second storage medium is not associated with the divided area, the target of processing is determined to be the first storage medium.
Therefore, in this composite storage device, the data processing speed for a specific divided area of the first storage medium (for example, a hard disk) can be increased.

  A composite storage device according to a third invention is the composite storage device according to the second invention, further comprising an address association unit, a data synchronization unit, and a synchronization state determination unit. The address association unit associates the physical address of the second storage medium with the address management method of the first storage medium. The data synchronization unit is a divided area (hereinafter referred to as “corresponding division”) in which data stored in the storage area of the second storage medium (hereinafter referred to as “second storage medium data”) and the storage area of the second storage medium are associated with each other. The data stored in the “region”) (hereinafter referred to as “corresponding divided region data”) is synchronized. The synchronization state determination unit determines whether or not the second storage medium data and the corresponding divided area data are in a synchronized state. The first process target determining unit is configured to associate the storage area of the second storage medium with the divided area and perform synchronization when at least one of the reading process and the writing process is requested for the divided area. When the state determination unit determines that the second storage medium data and the corresponding divided area data are in a synchronized state, the processing target is determined as the second storage medium, and the storage area of the second storage medium is set as the divided area. And the synchronization state determination unit determines that the second storage medium data and the corresponding divided area data are not in a synchronized state, while maintaining the address, the entire corresponding divided area data is stored in the second storage medium. The target of the reading process is determined as the first storage medium while the copy process is performed in the storage area, and the target of the writing process is determined as the second storage medium, and the storage area of the second storage medium is associated with the divided area. It is If not determine the processing target in the first storage medium.

  Therefore, in this composite storage device, it is possible to increase the data processing speed for the corresponding divided area while always synchronizing the second storage medium data and the corresponding divided area data.

A composite storage device according to a fourth aspect of the present invention is the composite storage device according to the first aspect of the present invention, wherein the storage area association unit can switch the divided areas associated with the storage areas of the second storage medium. The composite storage device further includes an address association unit and a data copy processing unit. The address association unit associates the physical address of the second storage medium with the address management method of the first storage medium. The data copy processing unit maintains the address after erasing data stored in the storage area of the second storage medium when the divided area associated with the storage area of the second storage medium is switched by the storage area association unit All data stored in the switched divided area (hereinafter referred to as “new divided area”) is copied to the storage area of the second storage medium. Here, “erasing data” includes not only actually erasing data but also setting a flag indicating erasure of the data without actually erasing the data.
For this reason, in this composite storage device, for example, it is possible to speed up reading processing and writing processing for a plurality of divided regions by shifting the time.

A composite storage device according to a fifth aspect of the present invention is the composite storage device according to the fourth aspect of the present invention, further comprising a second process target determining unit. When at least one of the read process and the write process is requested for the new divided area during the copy process, the second process target determining unit determines the target of the read process as the first storage medium and writes it. The processing target is determined as the second storage medium.
Therefore, in this composite storage device, the reading process and the writing process for the divided area can be normally performed even during the copying process.

A composite storage device according to a sixth aspect of the present invention is the composite storage device according to the first aspect of the present invention, wherein the storage area association unit is a divided area of the first storage medium having a storage capacity larger than the storage capacity of the second storage medium. The storage area of the second storage medium can also be selectively associated with (hereinafter referred to as “large capacity divided area”). The composite storage device further includes a disk cache function expression unit. When the storage area correlating unit associates the storage area of the second storage medium with the large-capacity divided area, the disk cache function expressing unit deletes the data stored in the storage area of the second storage medium, The storage area of the storage medium is caused to function as a disk cache.
Therefore, in this composite storage device, the second storage medium can be effectively used as a disk cache even for the large-capacity divided area of the first storage medium.

  A composite storage device according to a seventh aspect is the composite storage device according to the first aspect, wherein the first storage medium has a plurality of divided areas having the same storage capacity as the storage area of the second storage medium. Thus, the storage area is logically divided. Further, the second storage medium is always a target of at least the writing process of the reading process and the writing process. The storage area association unit can switch the divided area associated with the storage area of the second storage medium. When the divided area associated with the storage area of the second storage medium is switched by the storage area associating section, the data synchronization unit converts the data stored in the divided area associated with the storage area of the second storage medium into the first 2. Synchronize with data stored in the storage area of the storage medium.

  Therefore, in this composite storage device, the data processing speed for a specific divided area of the first storage medium (for example, a hard disk) can be increased, and the time series of the data stored in the second storage medium can be increased. Backups can be created in each of a plurality of divided areas.

A composite storage device according to an eighth aspect of the present invention is the composite storage device according to any one of the first through seventh aspects, further comprising an information display unit. The information display unit displays the information on the divided areas associated with the storage areas of the second storage medium by the storage area association unit on the data display device.
Therefore, in this composite storage device, the user can grasp the state of the divided area associated with the storage area of the second storage medium.

It is a functional block diagram of the composite storage device according to the embodiment of the present invention. It is a figure showing the correspondence of each partition table of the master boot record in the composite storage device concerning embodiment of this invention, and the division area of a switching management table. It is a figure showing the correspondence of each partition table of a master boot record and an extended partition boot record in a compound storage device concerning modification (B), and a division field of a change management table.

  -First embodiment-

As shown in FIG. 1, the composite storage device 10 according to the first embodiment of the present invention mainly includes a communication control unit 11, a data transfer control unit 12, a user interface unit 13, and a data storage unit 14. Yes. Hereinafter, these components will be described in detail below.
<Details of components of composite storage device>
(1) Communication control unit

The communication control unit 11 is a communication interface such as ATA, SATA, SCSI, SAS, USB, IEEE1394, or LAN, and plays a role of controlling communication connection with the information processing apparatus 20.
(2) Data Storage Unit As shown in FIG. 1, the data storage unit 14 mainly includes a hard disk unit 141 and a semiconductor memory unit 142.

  As shown in FIG. 1, the hard disk unit 141 mainly includes a hard disk interface unit 141a and a hard disk storage area 141b.

  The hard disk interface unit 141a is, for example, a communication interface such as ATA, SATA, SCSI, SAS, USB, IEEE1394, and serves as a bridge between the data transfer control unit 12 and the hard disk storage area 141b.

  The hard disk storage area 141b is partitioned into four divided areas SR1, SR2, SR3, SR4 in the present embodiment. In the present embodiment, the first divided region SR1 has the same storage capacity as the semiconductor memory storage region 142b. The second divided region SR2 has a storage capacity that is one third that of the first divided region SR1. In addition, the third storage division SR3 has a storage capacity that is two-thirds of the first division region SR1, that is, twice the storage capacity of the second division region SR2. The fourth divided region SR4 has a storage capacity five times that of the first divided region SR1.

  In addition, a partition table is provided in the MBR region SR0 as shown in FIG. In these partition tables, partition location information including partition start location information is described. Then, the switching management table Ts acquires the position information from the MBR area SR0, assigns the position information of the semiconductor memory storage area 142b to the hard disk storage area 141b, and the storage capacity of the divided areas SR1, SR2, SR3, SR4. Information of a comparison result with the storage capacity of the semiconductor memory storage area 142b is created.

  The semiconductor memory unit 142 is, for example, a flash memory, DRAM, SRAM, MRAM, or the like, and mainly includes an interface conversion unit 142a and a semiconductor memory storage area 142b as shown in FIG.

The interface conversion unit 142a allows the semiconductor memory storage area 142b to be accessed by the same address management method as the hard disk storage area 141b. Note that, as such a specific method, for example, the physical address of the semiconductor memory unit 142 is associated with the address management method (for example, the CHS method, the LBA method, etc.) of the hard disk unit 141 (for example, semiconductor memory such as SSD). And emulating the unit 142 as the hard disk unit 141).
(3) Data transfer control unit

  When the information processing device 20 is communicatively connected to the communication control unit 11, the data transfer control unit 12 causes the information processing device 20 to recognize that “the information processing device 20 is communicatively connected to the hard disk unit 141”. . That is, the information processing apparatus 20 connected to the composite storage device 10 always makes a read process request and a write process request to the hard disk unit 141.

  The data transfer control unit 12 is provided with a switching control unit 121. Then, as shown in FIG. 2, this switching control unit 121 creates and stores a switching management table Ts based on information in the MBR region SR0, and each divided region SR1, SR2, SR3, SR4 and the semiconductor memory The association with the area 142b is controlled. In the switching management table Ts, as shown in FIG. 2, various position information including the start positions of the divided areas SR1, SR2, SR3, SR4, the storage capacity of the divided areas SR1, SR2, SR3, SR4 and the semiconductor Information SI of the comparison result with the storage capacity of the memory storage area 142b (for example, flag information indicating that the storage capacity of the divided areas SR1, SR2, SR3, SR4 is larger than the storage capacity of the semiconductor memory storage area 142b), Information SF of a selection flag indicating a location to which the semiconductor memory storage area 142b is allocated to the hard disk storage area 141b, a synchronized position in the address space of the hard disk unit 141 (from the divided areas SR1, SR2, SR3, SR4 to the semiconductor memory storage area 142b) Copy information address location) information, hard disk part Such as 41 and information indicating whether the semiconductor memory section 142 is replaced (RAID-related information) is stored.

When the storage capacity of the divided regions SR1, SR2, SR3 associated with the semiconductor memory unit 142 is less than or equal to the storage capacity of the semiconductor memory unit 142, the data transfer control unit 12 removes the semiconductor memory unit 142 from the divided region. It is set as a storage unit having the same storage capacity as SR1, SR2, SR3. That is, the information processing apparatus 20 recognizes the divided areas SR1, SR2, SR3 and the semiconductor memory storage area 142b as storage areas having the same capacity and the same address space.
(4) User Interface Unit As shown in FIG. 1, the user interface unit 13 mainly includes a changeover switch unit 131 and an information display unit 132.

  The changeover switch unit 131 is a mechanical changeover switch, and plays a role of switching the allocation position of the semiconductor memory unit 142 to the divided regions SR1, SR2, SR3, SR4. In this embodiment, the switch position of the changeover switch unit 131 and the selection flag of the changeover management table Ts (see FIG. 2) are matched.

The information display unit 132 stores information on the divided areas SR1, SR2, SR3, SR4 associated with the semiconductor memory storage area 142b, and the semiconductor memory storage area 142b and the divided areas SR1, SR2, SR3, SR4. Information on the data synchronization state is displayed on a display device (not shown) of the information processing device 20.
<Read / write processing>

The details of the read / write processing in the composite storage device during normal operation, when the power is turned on, and when the divided areas are switched will be described separately for cases where there is a semiconductor memory storage area correspondence and for cases where there is no correspondence.
(1) Normal read / write processing a. Read / write processing for divided areas associated with semiconductor memory storage areas

  When the data transfer control unit 12 recognizes that the semiconductor memory storage area 142b has a storage capacity equal to or greater than the storage capacity of the divided areas SR1, SR2, SR3, the data transfer control unit 12 performs read processing and write processing on the semiconductor memory unit 142. Do.

  On the other hand, when the data transfer control unit 12 recognizes that the semiconductor memory storage region 142b has a storage capacity less than the storage capacity of the divided region SR4, the data transfer control unit 12 erases the data in the semiconductor memory storage region 142b and the semiconductor memory unit 142 is operated as a disk cache for the divided area SR4. In this embodiment, “data erasure” means not only that data is actually erased, but also that a flag indicating erasure of the data is simply set without actually erasing the data. .

  When the data transfer control unit 12 operates the semiconductor memory unit 142 as a disk cache, the data transfer control unit 12 transfers the data in the divided region SR4 to the information processing device 20 and stores the data in the divided region SR4 in the semiconductor memory. Copy processing is performed at the same address position in the area 142b, and then read processing is performed on the semiconductor memory unit 142.

Further, the data transfer control unit 12 performs a writing process on the semiconductor memory storage area 142b. When the data transfer control unit 12 recognizes that the semiconductor memory storage area 142b is saturated with data, the data transfer control unit 12 writes data to the same address position in the divided area SR4 at an arbitrary timing in order from the old data in the semiconductor memory storage area 142B. Then, new data is overwritten at the position of the data that has been written back to the divided area SR4 of the semiconductor memory storage area 142B.
b. Read / Write Processing for Partitioned Areas Not Associated with Semiconductor Memory Storage Areas The data transfer control unit 12 performs read processing and write processing for the hard disk unit 141.
(2) Read / write processing at power-on a. Read / write processing for divided areas associated with semiconductor memory storage areas

  When the data transfer control unit 12 recognizes that the semiconductor memory storage area 142b has a storage capacity equal to or greater than the storage capacity of the divided areas SR1, SR2, SR3, first, the data stored in the semiconductor memory storage area 142b; It is determined whether or not the data stored in divided areas SR1, SR2 and SR3 are synchronized. When the data transfer control unit 12 determines that the data in both storage areas are synchronized, the data transfer control unit 12 performs a reading process and a writing process on the semiconductor memory unit 142.

  On the other hand, if the data transfer control unit 12 determines that the data in both storage areas are not synchronized, the data transfer control unit 12 copies the data in the divided areas SR1, SR2, SR3 to the semiconductor memory storage area 142b. At this time, the data transfer control unit 12 stores the data at the same address position as the data of the divided areas SR1, SR2, SR3 in the semiconductor memory storage area 142b.

  When a read processing request is made from the information processing apparatus 20 to the divided areas SR1, SR2, SR3 during the copy process, the data transfer control unit 12 transfers the data in the divided areas SR1, SR2, SR3 to the information processing apparatus. 20, the data in the divided areas SR 1, SR 2, SR 3 are copied to the same address location in the semiconductor memory storage area 142 b, and then the semiconductor memory unit 142 is read out.

  Further, when a write process request is made to the divided areas SR1, SR2, SR3 from the information processing apparatus 20 during the copy process, the data transfer control unit 12 performs a write process on the semiconductor memory unit 142. . In such a case, the data transfer control unit 12 holds the write address and data size information of the write data, and performs a write-back process on the divided regions SR1, SR2, SR3 at an arbitrary timing.

On the other hand, when the data transfer control unit 12 recognizes that the semiconductor memory storage area 142b has a storage capacity less than the storage capacity of the divided areas SR1, SR2, SR3, the data transfer control unit 12 erases the data in the semiconductor memory storage area 142b. At the same time, the semiconductor memory unit 142 is operated as a disk cache. The disk cache operation is as described above.
b. Read / Write Processing for Partitioned Areas Not Associated with Semiconductor Memory Storage Areas The data transfer control unit 12 performs read processing and write processing for the hard disk unit 141.
(3) Read / write processing when switching divided areas a. Read / write processing for divided areas associated with semiconductor memory storage areas

  When the data transfer control unit 12 recognizes that the semiconductor memory storage area 142b has a storage capacity equal to or greater than the storage capacity of the divided areas SR1, SR2, SR3, the data transfer control unit 12 is associated with the semiconductor memory storage area 142b before switching the divided areas. The data in the semiconductor memory storage area 142b is written back to the same address position of the divided areas SR1, SR2, SR3, and the data in the semiconductor memory storage area 142b is erased, and the newly associated divided areas SR1, SR2, SR2 Data in SR3 is copied to the semiconductor memory storage area 142b. At this time, the data transfer control unit 12 stores the data at the same address position as the data of the divided areas SR1, SR2, SR3 in the semiconductor memory storage area 142b.

  When a read processing request is made from the information processing apparatus 20 to the divided areas SR1, SR2, SR3 during the copy process, the data transfer control unit 12 transfers the data in the divided areas SR1, SR2, SR3 to the information processing apparatus. 20, the data in the divided areas SR 1, SR 2, SR 3 are copied to the same address location in the semiconductor memory storage area 142 b, and then the semiconductor memory unit 142 is read out.

  Further, when a write process request is made to the divided areas SR1, SR2, SR3 from the information processing apparatus 20 during the copy process, the data transfer control unit 12 performs a write process on the semiconductor memory unit 142. . In such a case, the data transfer control unit 12 holds the write address and data size information of the write data, and performs a write-back process on the divided regions SR1, SR2, SR3 at an arbitrary timing.

On the other hand, when the data transfer control unit 12 recognizes that the semiconductor memory storage region 142b has a storage capacity less than the storage capacity of the divided region SR4, the data transfer control unit 12 erases the data in the semiconductor memory storage region 142b and the semiconductor memory unit 142 is operated as a disk cache. The disk cache operation is as described above.
b. Read / Write Processing for Partitioned Areas Not Associated with Semiconductor Memory Storage Areas The data transfer control unit 12 performs read processing and write processing for the hard disk unit 141.
<Characteristics of the composite storage device according to the first embodiment>
(1)

In the composite storage device 10 according to the embodiment of the present invention, the reading process and the writing process for the divided areas SR1, SR2, SR3 associated with the semiconductor memory storage area 142b are performed at a higher speed than the hard disk unit 141 ( This can be performed in the semiconductor memory storage area 142b in which read processing, write processing, and the like are possible. Therefore, in this composite storage device 10, the data processing speed for a specific divided area of the hard disk unit 141 can be increased.
(2)

In composite storage device 10 according to the embodiment of the present invention, when power is turned on, data transfer control unit 12 has semiconductor memory storage area 142b having a storage capacity equal to or greater than the storage capacity of divided areas SR1, SR2, SR3. First, it is determined whether the data stored in the semiconductor memory storage area 142b is synchronized with the data stored in the divided areas SR1, SR2, SR3. When the data transfer control unit 12 determines that the data in both storage areas are synchronized, the data transfer control unit 12 performs a reading process and a writing process on the semiconductor memory unit 142. On the other hand, if the data transfer control unit 12 determines that the data in both storage areas are not synchronized, the data transfer control unit 12 copies the data in the divided areas SR1, SR2, SR3 to the semiconductor memory storage area 142b. Therefore, in this composite memory device 10, the data processing speed for divided regions SR1, SR2, SR3 is increased while the data in semiconductor memory storage region 142b and the data in divided regions SR1, SR2, SR3 are always synchronized. can do.
(3)

In the composite memory device 10 according to the embodiment of the present invention, the switching control unit 121 can switch the divided regions SR1, SR2, SR3, SR4 associated with the semiconductor memory storage region 142b. For this reason, in the composite storage device 10, for example, the reading process and the writing process for the plurality of divided regions SR1, SR2, SR3, SR4 can be speeded up by shifting the time. Specifically, the divided areas SR1, SR2, SR3, SR4 are assigned to a plurality of users, and the user's favorite operating system is assigned to the assigned divided areas SR1, SR2, SR3, SR4. Can be installed to speed up the operating system of each user at an appropriate timing. Note that it is very excellent in cost performance that such a high-speed operating system can be realized by a relatively small capacity semiconductor memory.
(4)

In composite storage device 10 according to the embodiment of the present invention, copy processing is performed when power is turned on and when divided regions are switched, and read processing is performed on divided regions SR1, SR2, and SR3 from information processing device 20 during the copy processing. When there is a request or a write processing request, the data transfer control unit 12 transfers the data in the divided areas SR1, SR2, SR3 to the information processing device 20 and transmits the data in the divided areas SR1, SR2, SR3 to the semiconductor memory storage area. Copy processing is performed at the same address position of 142b, and then read processing is performed on the semiconductor memory unit 142. In such a case, the data transfer control unit 12 performs a writing process on the semiconductor memory unit 142. For this reason, in the composite storage device 10, the reading process and the writing process for the divided areas SR1, SR2, SR3 can be normally performed even during the copying process.
(5)

In the composite storage device 10 according to the embodiment of the present invention, the semiconductor memory unit 142 can be effectively used as a disk cache for the divided region SR4 having a storage capacity larger than the storage capacity of the semiconductor memory storage region 142b. .
(6)

The composite storage device 10 according to the embodiment of the present invention is provided with an information display unit 132. This information display unit 132 is stored in information on the divided areas SR1, SR2, SR3, SR4 associated with the semiconductor memory storage area 142b, and in the semiconductor memory storage area 142b and the divided areas SR1, SR2, SR3. Information on the synchronization state of the data to be displayed on the display device of the information processing device 20 For this reason, in this composite storage device 10, the user can grasp the states of the divided regions SR1, SR2, SR3, SR4 associated with the semiconductor memory storage region 142b.
<Modification of First Embodiment>
(A)

In the composite storage device 10 according to the first embodiment, the changeover switch unit 131 is a mechanical changeover switch. However, the changeover switch unit may be a changeover switch program that operates on the information processing device 20.
(B)

In the composite storage device 10 according to the first embodiment, as shown in FIG. 2, each of the divided areas SR1, SR2, SR3, SR4 is associated with each partition table in the MBR area SR0. Thus, each of the divided areas SR1, SR2, SR3, SR4 may be associated with not only the partition table in the MBR area SR0 but also the partition table in the EPBR area.
(C)
Although not particularly mentioned in the first embodiment, the hard disk unit 141 and the semiconductor memory unit 142 may be configured to be detachable.
(D)

Although not specifically mentioned in the first embodiment, a RAID function such as mirroring may be constructed by adding a RAID function to the hard disk interface 141a of the hard disk unit 141.
(E)

Although not particularly mentioned in the first embodiment, when a data write process is performed on the semiconductor memory unit 142 in a normal state, the storage address information and size information of the data are stored in the semiconductor memory storage area 142b. And the data may be written back to the divided regions SR1, SR2, SR3 at an arbitrary timing.
If the write-back process is not performed as described above, the hard disk storage area 141b can be returned to the initial state at any time.
When the hard disk unit 141 is detachable, the hard disk unit 141 needs to be detached after the write-back process is completed.
(F)

In the composite memory device 10 according to the first embodiment, the first divided region SR1 has the same storage capacity as the semiconductor memory storage region 142b, and the second divided region SR2 has a storage capacity that is one-third that of the first divided region SR1. The third storage division SR3 has a storage capacity that is two thirds of the first division region SR1, that is, twice the storage capacity of the second division region SR2, and the fourth division region SR4 is 5 times the first division region SR1. Although the hard disk storage area 141b is partitioned so as to have a double storage capacity, the hard disk storage area 141b may be arbitrarily partitioned.
(G)

In the composite memory device 10 according to the first embodiment, when the semiconductor memory storage area 142b has a storage capacity less than the storage capacity of the divided areas SR1, SR2, SR3, SR4, the data in the semiconductor memory storage area 142b is erased. At the same time, the semiconductor memory unit 142 is operated as a disk cache, but the semiconductor memory unit 142 may not be allocated to the divided region SR4.
(H)

In the composite storage device 10 according to the first embodiment, when the semiconductor memory storage area 142b has a storage capacity less than the storage capacity of the divided area SR4, the semiconductor memory unit 142 is operated as a disk cache, and the semiconductor memory storage area When 142b is saturated with data, the data transfer control unit 12 performs overwriting processing with new data in order from the oldest data, but the data transfer control unit 12 starts with the data with the lowest access frequency from the information processing device 20. It may be set to perform overwrite processing with new data.
(I)

In the composite storage device 10 according to the first embodiment, when a read processing request is made to the divided areas SR1, SR2, SR3 from the information processing apparatus 20 during the copy process at power-on and divided area switching, data transfer is performed. The control unit 12 performs the read process on the semiconductor memory unit 142 after copying the data in the divided regions SR1, SR2, SR3 to the same address position in the semiconductor memory storage region 142b. It is possible to transfer the data of SR3 to the information processing apparatus 20 and copy the data of the divided areas SR1, SR2, SR3 to the same address position in the semiconductor memory storage area 142b.
(J)

In the composite storage device 10 according to the first embodiment, when a write processing request is made to the divided areas SR1, SR2, SR3 from the information processing apparatus 20 during the copy process at power-on and divided area switching, The transfer control unit 12 performs a writing process on the semiconductor memory unit 142, holds a write address and data size information of the write data, and applies to the divided regions SR1, SR2, SR3 at an arbitrary timing. The write-back process is performed, but the write-back process may not be performed. In such a case, there is an advantage that the divided regions SR1, SR2, SR3 can be returned to the initial state at any time.
(K)

Although not specifically mentioned in the first embodiment, for example, a program for realizing the activation sequence is stored in the MBR region SR0, and the divided regions SR1, SR2, SR3, SR4 are selected and selected by the program. The semiconductor memory storage area 142b may be automatically associated with the divided areas SR1, SR2, SR3, SR4. Note that the program in the MBR region SR0 may be a program that calls a program main body for realizing the above startup sequence. In such a case, the selection status of the divided areas SR1, SR2, SR3, SR4 may be displayed on the display screen of the information processing apparatus 20. In this way, for example, the user can speed up the divided areas SR1, SR2, SR3, SR4 in which the boot operating system is installed by the semiconductor memory storage area 142b only by selecting the boot operating system. It becomes possible.
-Second embodiment-

The composite storage device according to the second embodiment of the present invention uses a large-capacity hard disk unit as an automatic backup destination of a low-capacity semiconductor memory unit. Specifically, in this composite storage device, a high-speed semiconductor memory unit 142 is usually used as a storage medium, and a semiconductor memory storage area is used during a time when there is no read processing request or write processing request (for example, at midnight or a holiday). All data 142b is backed up to the large-capacity hard disk unit 141. This composite storage device has the same configuration and function as the composite storage device 10 according to the first embodiment, except for the method of dividing the hard disk storage area 141b and the read / write processing method. Hereinafter, a hard disk storage area dividing method and a read / write processing method, which are different from the composite storage device 10 according to the first embodiment, will be described in detail.
<How to divide the hard disk storage area>

In the present embodiment, at the time of initial setting, switching control unit 121 edits MBR region SR0 of hard disk unit 141 to create a plurality of divided regions having the same storage capacity as semiconductor memory storage region 142b.
<Read / write processing method>

  In the present embodiment, in principle, the data transfer control unit 12 performs a read / write process on the semiconductor memory unit 142 in response to a read / write process request from the information processing apparatus 20.

In the present embodiment, the switching control unit 121 automatically switches the divided area associated with the semiconductor memory storage area 142b every predetermined time. The data transfer control unit 12 stores the memory in the semiconductor memory at a predetermined timing (for example, timing when there is no read / write processing request) every time the divided region associated with the semiconductor memory storage region 142b is switched by the switching control unit 121. All data in the area 142b is copied to the divided area.
<Backup restore mode>
The backup data restoration process secured as described above is performed from the information processing apparatus 20 to the hard disk unit 141.
<Characteristics of Compound Storage Device According to Second Embodiment>

In the composite storage device according to the embodiment of the present invention, the hard disk storage area 141b is logically divided so that there are a plurality of divided areas having the same storage capacity as the storage capacity of the semiconductor memory section 142, and the data transfer control section 12, the semiconductor memory unit 142 is read / written in response to a read / write processing request from the information processing apparatus 20 in principle. The data transfer control unit 12 stores the memory in the semiconductor memory at a predetermined timing (for example, timing when there is no read / write processing request) every time the divided region associated with the semiconductor memory storage region 142b is switched by the switching control unit 121. All data in the area 142b is copied to the divided area. For this reason, in this composite storage device, it is possible to speed up the read / write processing for a specific divided area of the hard disk unit 141, and to perform time-series backup of data stored in the semiconductor memory unit 142 in a plurality of times. Each can be created in a divided area. Therefore, the user can easily return the work state to any past work state.
<Modification of Second Embodiment>
(A)

In the composite storage device according to the second embodiment, every time the divided area associated with the semiconductor memory storage area 142b is switched by the switching control section 121, the data transfer control section 12 performs all data in the semiconductor memory storage area 142b at a predetermined timing. The data transfer control unit 12 performs copy processing from the divided area associated with the semiconductor memory storage area 142b to the semiconductor memory storage area 142b at a predetermined timing, and the data in both storage areas is copied. You may make it synchronize.
(B)

Although not specifically mentioned in the second embodiment, the hard disk unit 141 may stop the spindle until a backup command signal is transmitted from the data transfer control unit 12.
(C)

In the composite storage device according to the second embodiment, backup data restoration processing is performed from the information processing device 20 to the hard disk unit 141. During the backup restoration processing, the data transfer control unit 12 responds to a read processing request. Transfers the data in the divided area to the information processing apparatus 20 and copies it to the same address position in the semiconductor memory storage area 142b. In response to a write processing request, the data transfer control unit 12 stores the write data in the semiconductor memory You may make it write in the area | region 142b.
(D)

Although not particularly mentioned in the second embodiment, the data transfer control unit 12 edits the partition table information of the MBR region SR0 of the hard disk unit 141 and the information associated therewith, and only the divided region assigned at that time is edited. The information processing apparatus 20 may be shown.
(E)
Although not particularly mentioned in the second embodiment, the divided area may be set as a divided area where the operating system can be activated.
(F)
Modifications (A) to (D) of the first embodiment may be adopted.

DESCRIPTION OF SYMBOLS 10 Composite memory | storage device 11 Communication control part 12 Data transfer control part 13 User interface part 14 Data storage part 20 Information processing apparatus 121 Switching control part 131 Changeover switch part 132 Information display part 141 Hard disk part 141a Hard disk interface part 141b Hard disk storage area 142 Semiconductor Memory unit 142a Interface conversion unit 142b Semiconductor memory storage areas SR1, SR2, SR3, SR4 Divided areas

  The composite storage device according to the present invention has a feature that the data processing speed for a specific divided area of a hard disk logically divided into a plurality of divided areas can be increased. To different users and speed up the processing of data processing requests only from a specific user, or install different operating systems in each of multiple divided areas to speed up the operation of the operating system selected by the user It is particularly useful for such applications.

Claims (10)

A first storage medium in which the storage area is logically divided into a plurality of divided areas;
A second storage medium having a storage capacity equal to or greater than the storage capacity of at least one of the plurality of divided areas, the data processing speed being higher than the data processing speed of the first storage medium;
And a storage area associating unit for associating the storage area of the second storage medium to at least one of the divided region of the divided region of the first storage medium having a storage capacity following storage capacity of the second storage medium Including
The composite storage device, wherein the storage area association unit is capable of switching the divided areas associated with the storage areas of the second storage medium.   When the divided area associated with the storage area of the second storage medium is switched, the storage area of the second storage medium has a storage capacity equal to or greater than the storage capacity of the divided area associated with the second storage medium. The copy process, the read process, the write process, and the write-back process are executed if they are present, and the second storage medium is operated as a disk cache if they are not present. The composite storage device described. The composite storage device according to claim 1, wherein when the storage capacity of the second storage medium is exceeded, the data of the first storage medium is overwritten in order .   When at least one of the reading process and the writing process is requested for the divided area, if the storage area of the second storage medium is associated with the divided area, the processing target is the first A first processing target determining unit that determines the second storage medium and determines that the processing target is the first storage medium when the storage area of the second storage medium is not associated with the divided area; The composite storage device according to claim 1. An address association unit for associating the physical address of the second storage medium with the address management method of the first storage medium;
Data stored in the storage area of the second storage medium (hereinafter referred to as “second storage medium data”) and data stored in the divided area associated with the storage area of the second storage medium (hereinafter referred to as “second storage medium data”). A data synchronization unit that synchronizes with "corresponding divided area data"),
A synchronization state determination unit that determines whether or not the second storage medium data and the corresponding divided area data are in a synchronized state;
The first process target determining unit
When at least one of read processing and write processing is requested for the divided area,
When the storage area of the second storage medium is associated with the divided area, and the synchronization state determination unit determines that the second storage medium data and the corresponding divided area data are in a synchronized state Determines the target of the processing as the second storage medium,
When the storage area of the second storage medium is associated with the divided area and the synchronization state determination unit determines that the second storage medium data and the corresponding divided area data are not in a synchronized state , While the address is maintained, all the corresponding divided area data is copied to the storage area of the second storage medium, the target of the read process is determined as the first storage medium, and the target of the write process is Decide on the second storage medium,
The composite storage device according to claim 4 , wherein when the storage area of the second storage medium is not associated with the divided area, the processing target is determined as the first storage medium. The storage area association unit is capable of switching the divided areas associated with the storage areas of the second storage medium,
An address association unit for associating the physical address of the second storage medium with the address management method of the first storage medium;
When the divided area associated with the storage area of the second storage medium is switched by the storage area associating unit, the data stored in the storage area of the second storage medium is erased and the address is maintained. The composite storage according to claim 1, further comprising: a data copy processing unit that copies all data stored in the switched divided area (hereinafter referred to as “new divided area”) to a storage area of the second storage medium. apparatus. When at least one of a read process and a write process is requested for the new divided area during the copy process, the target of the read process is determined as the first storage medium and the target of the write process The composite storage device according to claim 6, further comprising a second processing target determination unit that determines the second storage medium as a second storage medium. The storage area associating unit also applies the second storage medium to the divided area (hereinafter referred to as “large capacity divided area”) of the first storage medium having a storage capacity larger than the storage capacity of the second storage medium. It is possible to selectively associate storage areas,
When the storage area of the second storage medium is associated with the large-capacity divided area by the storage area association unit, the data stored in the storage area of the second storage medium is erased, and then the second storage The composite storage device according to claim 1, further comprising a disk cache function expressing unit that causes the storage area of the medium to function as a disk cache. In the first storage medium, the storage area is logically divided such that there are a plurality of divided areas having the same storage capacity as the storage capacity of the second storage medium,
The second storage medium is always subject to at least the writing process of the reading process and the writing process,
The storage area associating unit can switch the divided area to be associated with the storage area of the second storage medium,
When the divided area associated with the storage area of the second storage medium is switched by the storage area association unit, the data stored in the divided area associated with the storage area of the second storage medium is The composite storage device according to claim 1, further comprising a data synchronization unit configured to synchronize with data stored in a storage area of the second storage medium. 10. The composite according to claim 1, further comprising: an information display unit configured to display, on a data display device, information on the divided area associated with the storage area of the second storage medium by the storage area association unit. Storage device.