JP5303943B2 - Arithmetic processing device and control method of arithmetic processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a processor for preventing the deterioration of the execution speed of a program even when register pill processing is generated. <P>SOLUTION: In this processor, a value stored in a logical register: L register 0 is stored in a physical register which is not associated with a logical register 110 by register renaming among physical registers 120. A P register XX among the physical registers 120 is not associated with the logical register, but in an "empty" state. Therefore, the value stored in the logical register: L register 0 is stored in the physical register: P register XX, and the processing of a save instruction is completed. Also, the association of the address X described in the save instruction with the physical register: P register XX is reflected on a lookup table 140. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

The present invention relates to a control method for an arithmetic processing device and a processing unit equipped with a physical register more than the number of logical registers specified in the instruction set architecture.

  Conventionally, a processor is provided with a register as a mechanism for improving the processing speed. When the instruction is executed by the processor, the storage medium is accessed according to the description of the instruction. Of these storage media, the processor can access the registers at a higher speed than the cache and main memory. Because of this characteristic, a technique for generating a program that preferentially stores a frequently used value or a reused value in a register (register promotion) is widely applied. When a program is generated using appropriate register promotion, the program execution time can be shortened by reducing the number of accesses to the cache and main memory and increasing the frequency of access to high-speed registers.

  In recent processors, more physical registers than the number of logical registers specified in the processor instruction set architecture (ISA) are installed, and program execution is performed by utilizing these physical registers using a register renaming mechanism. Techniques for speeding up are often used. In the register renaming mechanism, conversion from a logical register number to a physical register number is performed, but the correspondence between the logical register number and the physical register number is not fixed, and the association is dynamically performed at the time of program execution.

  For example, assume that instructions that access the same logical register A are executed in the order of instruction A → instruction B. In an ordinary program, the A value stored in the logical register A is read out in the instruction A, and then the B value is stored in the logical register A in the instruction B. Many processes that are divided and shared by.

  When the register renaming mechanism is provided, different physical registers are associated with the shared logical registers in the program description as described above. That is, different physical registers are allocated to the logical register A that reads the A value in the instruction A and the logical register A that stores the B value in the instruction B, respectively. Since a different physical register is set for each instruction, the instruction B can store the B value without waiting for the end of the instruction A, and the parallelism of the program can be improved (for example, the following patent document) 1).

JP 2001-229022 A

  However, even if register promotion is performed as in the past, the number of registers is limited, so that all necessary values cannot be stored in the registers. Therefore, even a value that is scheduled to be reused must be stored in the cache or the main memory due to a shortage of the number of registers, resulting in a problem that the execution speed of the program decreases.

  When there is a shortage of registers, processing called register spill is generally performed. The register spill saves (stores) the value recorded in the register to the stack area of the cache or main memory, and restores the original register from the saved stack area when the same value is needed ( Load). Therefore, when a register spill occurs, access to the cache and main memory (store / load) is required, resulting in a problem that the program execution time becomes long.

  In order to reduce the register spill, a method of increasing the number of registers is effective. However, since the instruction set architecture of the processor is constructed based on a specific number of registers, when the number of registers is increased, the instruction set architecture needs to be significantly changed. Such a significant change in the instruction set architecture is practically difficult.

  In the case of Patent Document 1, the program execution speed is improved by register renaming. However, since all register values described in the instruction are to be renamed, the number of physical registers is larger than the number of logical registers. Regardless, there was a problem that the physical registers were easily exhausted.

An object of the present invention is to provide an arithmetic processing apparatus and a control method for the arithmetic processing apparatus that can prevent a decrease in the execution speed of a program even if a register spill occurs, in order to solve the above-described problems caused by the prior art. And

  In order to solve the above-described problems and achieve the object, the processor, the register access method, and the register access program include physical registers equal to or more than the number of logical registers defined in the instruction set architecture, and the logical registers are stored in the physical registers. A register renaming mechanism for converting, managing correspondence information indicating correspondence between the logical register and the physical register, and updating the correspondence information when the correspondence between the logical register and the physical register is changed It is a requirement to have a function to perform. Further, when a save instruction is executed to save the value stored in the designated logical register in a storage medium such as cache or main memory, the physical information corresponding to the designated logical register is referred to with reference to the correspondence information. The value stored in the register is read out, and the read value is stored in an empty physical register that is not used at the time, and at the time of the storage, the address of the other storage medium is set after the execution of the save instruction. A correspondence with a physical register in which a value is newly stored is added to the correspondence information.

  According to the processor, the register access method, and the register access program, when a save instruction corresponding to a register spill is executed, it is actually stored in an address specified by the save instruction, that is, in a storage medium such as a cache or main memory. A value is stored in an empty physical register in the physical register without storing the value. Since the correspondence between the physical register in which the value is newly stored and the address specified by the save instruction is added to the correspondence information, the instruction set architecture can be used without drastically changing.

  In addition, the processor, the register access method, and the register access program refer to the correspondence information when a saved value restoration instruction is executed to store a value saved by the save instruction in a newly specified logical register. Reading the value stored in the physical register by the save instruction, storing the read value in a physical register corresponding to the newly specified logical register, and at the time of the update, the save value restoring instruction After the execution, the correspondence between the physical register from which the stored value is read and the address of the other storage medium may be deleted from the correspondence information by the access control means.

  According to this processor, register access method, and register access program, a value stored in a physical register is read by a save instruction that saves a previously executed register value, and a logical register specified by a save value restoration instruction is supported. Stored in the physical register. In the saved value restoration instruction executed here, the address of the main memory or the like is described as the place where the register value is saved, but the value from the physical register in which the saved value is stored by referring to the correspondence information. Can be restored.

  In addition, the processor, the register access method, and the register access program, when the save instruction is executed, if there is no free physical register that is not used at the time, the physical register corresponding to the designated logical register. The value stored in the register may be stored in the other storage medium.

  According to this processor, register access method, and register access program, even when a save instruction is executed, if there is no free physical register, the value is stored in another storage medium as described in the save instruction. .

  In addition, the processor, the register access method, and the register access program described above detect whether the usage state of each physical register is unused or used, and in the case of further use, the register renaming converts it into a logical register. A physical register that has been detected to be unused at the time of register renaming is provided with processing for detecting whether a corresponding value is stored or a value saved by the save instruction is stored. If not, after the value stored in the physical register is stored in the other storage medium described in the save instruction, the physical register is associated with the logical register, and the register After performing the naming, the correspondence between the address of the other storage medium and the physical register is deleted from the correspondence information. It may be.

  According to this processor, register access method, and register access program, if there is no free physical register at the time of register renaming, the physical register in which the save value is stored is preferentially used for register renaming. At this time, the save value stored in the physical register is stored in another storage medium described in the save instruction.

  In addition, the processor, the register access method, and the register access program, when the save value restore instruction is executed, if there is no value stored in the physical register by the save instruction, the save value restore instruction The value stored in the address of another storage medium described in the above may be read.

According to this processor, register access method and register access program,
If there is no value stored in the physical register by the save instruction even though the save value restoration command is executed, the save value is stored in another storage medium. Is read.

According to the arithmetic processing device and the control method of the arithmetic processing device, it is possible to prevent a decrease in the execution speed of the program even if a register spill occurs.

Exemplary embodiments of an arithmetic processing unit and a control method for the arithmetic processing unit will be described below in detail with reference to the accompanying drawings.

(Overview of register access processing)
First, an outline of the register access processing according to this embodiment will be described. FIG. 1 is an explanatory diagram showing an overview of register access processing according to the present embodiment. As shown in FIG. 1, instructions described in the execution program 101 are sequentially executed inside the processor. In the execution program 101, in the case of an instruction for accessing a register, an access destination register name is described, and these virtual registers are called logical registers 110. Here, the number of logical registers is 16.

  In the present embodiment, more physical registers 120 than the number of logical registers 110 are mounted on the processor. The physical register 120 is associated with the logical register 110 by register renaming. Here, the number of physical registers is 64. Further, as exemplified in the description of register renaming, the association between the logical register and the physical register is dynamically performed, and the association is changed as time elapses. Correspondence information between logical registers and physical registers by register renaming is held in the processor as a correspondence table 140.

  Here, it is assumed that a save instruction for saving the register value is executed in the execution program 101. The save instruction describes that the value stored in the L register 0 of the logical register 110 is stored in the address X of the cache / main storage memory (storage area other than the register) 130. The value stored in the L register 0 of the logical register 110 is actually a value stored in the physical register P register 00 associated with the L register 0 by register renaming. Conventionally, the value stored in the L register 0 (P register 00) is stored in the cache / main memory 130 as described in the save instruction.

  However, in this embodiment, the value stored in the L register 0 is stored in a physical register that is not associated with the logical register 110 by register renaming among the physical registers 120. In the case of FIG. 1, among the physical registers 120, the P register XX is not associated with a logical register and is in an “empty” state. Therefore, a value normally saved from the L register 0 to the address X (a save value) is stored in the P register XX, and the processing of the save instruction is completed. At this time, the correspondence table 140 reflects that the address X described in the save instruction is associated with the P register XX.

  In this way, in the case of the present embodiment, the processing that originally had to access the address X of the cache / main memory 130 is completed by accessing the physical register 120. Therefore, it is possible to prevent an increase in access time due to execution of the save instruction. A specific configuration and processing contents for realizing the register access processing described above will be described below.

(Processor configuration)
First, the configuration of a processor for performing register access processing according to the present embodiment will be described. In the following description, a part related to the register access process is extracted from the processor configuration. Further, since other configurations inside the processor are well known, description thereof is omitted here.

  FIG. 2 is a block diagram showing an outline of the configuration of the processor. As shown in FIG. 2, the processor 200 includes a command cache 201, a decoding unit 202, a rename unit 203, a schedule unit 204, and an execution unit 205 as configurations for executing the register access processing according to the present embodiment. It has.

  The instruction cache 201 stores an instruction to be executed by the processor 200. When the processor 200 receives an execution instruction, the instruction is input to the decoding unit 202. The decoding unit 202 decodes the input instruction and inputs the decoded instruction to the rename unit 203.

  The rename unit 203 is a function for realizing the register access processing according to the present embodiment. FIG. 3 is a block diagram showing the configuration of the rename unit. As illustrated in FIG. 3, the rename unit 203 includes a rename control unit 301, a logical register / physical register correspondence table 302, an address / physical register correspondence table 303, and a physical register state table 304.

  The rename control unit 301 includes, as basic functions, a rename processing function that converts a logical register 110 number into a physical register 120 number, and an update processing function that updates the correspondence between the logical register 110 and the physical register 120 as necessary. It has. The correspondence information between the logical register 110 and the physical register 120 associated with each other by the rename control unit 301 is stored as a logical register / physical register correspondence table 302.

  In addition to the basic processing described above, the rename control unit 301 stores the address and value of the cache / main memory 130 described in the save instruction when executing the save instruction, which is a feature of the present embodiment. Correlation with the register 120 is performed. The correspondence information between the address of the cache / main memory 130 and the physical register 120 associated with each other by the rename control unit 301 is stored as an address-physical register correspondence table 303.

  Further, the rename control unit 301 has a function of managing the usage status of the physical register 120, and the usage status of the physical register 120 is stored as a physical register status table 304. The use of the physical register status table 304 will be described in detail later.

  As described above, the instruction converted by the rename unit 203 is input to the execution unit 205 after the execution timing is adjusted by the schedule unit 204. The execution unit 205 executes the input instruction.

(Generation of save instruction by compiler)
Next, a compiler that generates the execution program 101 executed by the processor 200 will be described. As described above, the instruction read from the instruction cache 201 of the processor 200 includes a save instruction. Specifically, the save instruction is an instruction that saves the value stored in the physical register 120 in the cache / main memory 130, and the value saved in the cache / main memory 130 by the save instruction again. It refers to both the instruction to restore the physical register 120. Here, a method for generating the execution program 101 including the save instruction using a dedicated compiler will be described.

  FIG. 4 is an explanatory diagram showing a save instruction generation procedure by the compiler. As shown in FIG. 4, the source file 401 is input to the compiler 410. Similar to a normal compiler, the compiler 410 compiles a source file 401 input using various routines to generate an execution program 101. The compiler 410 includes a register value saving / restoring instruction generation routine among these various routines.

  As described in the correspondence table 411, this register value saving / restoring instruction generation routine generates a spill-store instruction instead of generating a store instruction as an instruction for saving a register value to the stack. Conventionally, a spill-load instruction is generated instead of generating a load instruction as an instruction for restoring from the stack. As described above, the save instruction is generated by the register value save / restore instruction generation routine, thereby generating the execution program 101 including the save instruction. By using the compiler 410 in this manner, there is an advantage that the user can easily adjust the save instruction generation conditions by changing the setting of the register value save / restore instruction generation routine.

(Register access processing including save instruction: basic processing)
Next, a register access process including a save instruction executed by the processor 200 having the above-described configuration will be described. FIG. 5 is an explanatory diagram illustrating an example of a register access process including a save instruction.

  In FIG. 5, first, the instruction spill-store reg-A [addr-X] is executed. As described with reference to FIG. 4, the spill-store instruction is an instruction for saving a register value. Normally, when the register value is saved, the register value is stored in the cache / main memory 130. However, in the spill-store instruction, a register value is stored in a physical register that is not used for register renaming in the physical register 120 instead of the cache / main memory 130. In the execution of the instruction spill-store reg-A [addr-X] in FIG. 5, the value of reg-A is stored in the physical register 17. This saving process is immediately reflected in the address-physical register correspondence table 303 after the instruction is executed.

  In FIG. 5, the instruction spill-load [addr-X] reg-B is then executed. As described with reference to FIG. 4, the spill-load instruction is an instruction for restoring the register value saved by the spill-store instruction. Here, as shown in the address-physical register correspondence table 303, the value saved by the spill-store in addr-X is stored in the physical register 17, so reg-B is associated with the physical register 17. Alternatively, the value stored in the physical register 17 is read and stored in the physical register associated with reg-B.

  The process described above is a basic process among the register access processes including the save instruction. In this way, the process can be completed without accessing the cache / main memory 130, even though the address of the cache / main memory 130 is described in the instruction sequence.

(Register access processing including save instruction: exception processing)
Next, a process when an exceptional event other than the basic process described above occurs with the execution of the execution program 101 will be described.

1) When physical registers are insufficient when executing a save instruction First, as an exception process, there is a process when a physical register is insufficient when executing a save instruction. For example, assume that the instruction spill-store reg-A [addr-X] is executed. In this case, the physical register 120 that replaces the cache / main memory 130 is not assigned. Then, the value stored in reg-A is stored in addr-X of the cache / main memory 130 as it is. At this time, there is no need to update the address-physical register correspondence table 303.

2) When physical registers run short during register renaming The next exception handling is processing when physical registers run short during register renaming. In this case, the physical register 120 storing the saved value is released in place of the cache / main memory 130 by the save instruction.

  FIG. 6 is an explanatory diagram showing a process for storing a saved value when a physical register is insufficient. As shown in the address-physical register correspondence table 303 in FIG. 6, the value stored in the addr-X of the cache / main memory 130 is normally stored in the physical register 17. When the physical register 17 is released, the value stored in the physical register 17 is stored in addr-X of the cache / main memory 130 which is a normal storage destination. After the physical register 17 is released, the correspondence information between addr-X and the physical register 17 in the address-physical register correspondence table 303 is cleared.

3) The saved value is not stored in the physical register The next exception processing is processing when the saved value corresponding to the saved value restoration instruction is not stored in the physical register 120. For example, assume that the instruction spill-load [addr-X] reg-B is executed. In this case, it is determined that the save value is not stored in the physical register 120. Therefore, the value stored in the addr-X of the cache / main memory 130 is read out in the same way as a normal load instruction. At this time, it is not necessary to update the address-physical register correspondence table 303.

(Physical register usage flag)
As described above, in the case of basic processing, a free register must be found out of the physical registers 120 composed of a plurality of registers and assigned as a saving register. Also, when exception processing 2) occurs, the register storing the save value must be found out of the physical register 120 and released for register renaming.

  In the present embodiment, as a method for finding a necessary register from the physical register 120 according to the use state, a use state flag of the physical register is used. FIG. 7 is an explanatory diagram showing the setting of the status flag of the physical register. As shown in FIG. 7, a binary status flag is assigned to each register constituting the physical register 120. There are three types of status flags, “00, 01, 10”. 00 = unused, 01 = used by register renaming, 10 = used by save instruction.

  For example, when register renaming is executed, the register of the status flag 00 is first searched. In the case of FIG. 7, the P register 13 of the status flag 00 is found and used for register renaming. If there is no register for the status flag 00 as in the above exception processing 2), the register for the status flag 10 is found and used for register renaming.

  Also, when the save instruction is executed, the register of the status flag 00 is searched first. FIG. 8 is an explanatory diagram illustrating an example of storage in a physical register. As shown in FIG. 8, if the physical register 120 has a register for the status flag 00 (here, P registers 12 and 13), the save value is stored in any one of these registers. In FIG. 8, since the save value is stored in the P register 12, the status flag of the P register 12 is updated to 10. When the saved value restoration instruction is executed, the value is stored in the physical register 120 associated with the logical register 110, so that the status flag is updated to 01.

  This status flag is collectively stored in the physical register status table 304 described with reference to FIG. Therefore, when it is desired to find the physical register 120 in a desired state according to the processing to be executed (register renaming, save instruction, etc.), the physical register state table 304 may be referred to. Further, by storing the status flag in the physical register status table 304, the status flag can be used without reducing the number of recordable bits of the physical register 120.

  As described above, according to the present embodiment, when the instruction is executed by the processor 200, the physical register 120 is minimized as much as possible in order to minimize access to the cache or the main memory having a lower access speed than the physical register. Register access processing is performed to use. Therefore, even if a register spill occurs, it is possible to prevent a decrease in the program execution speed.

  The register access method described in this embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. This program is recorded on a computer-readable storage medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the storage medium by the computer. The program may be a transmission medium that can be distributed via a network such as the Internet.

  In addition, the processor 200 described in this embodiment includes a special-purpose IC (hereinafter simply referred to as “ASIC”) such as a standard cell or a structured ASIC (Application Specific Integrated Circuit), or a PLD (Programmable Logic Device) such as an FPGA. ) Can also be realized. Specifically, for example, the processor 200 is manufactured by defining the function of the processor 200 described above (inserting each code of the function block) by the HDL description, logically synthesizing the HDL description and giving it to the ASIC or PLD. can do.

  The following additional notes are disclosed with respect to the embodiment described above.

(Appendix 1) Physical registers greater than the number of logical registers specified in the instruction set architecture;
Register renaming for associating the logical register with the physical register, and renaming control means for generating correspondence information representing a correspondence between the logical register and the physical register;
Updating means for updating the correspondence information when an instruction in the instruction set architecture is executed and the correspondence between the logical register and the physical register is changed;
Accessing a physical register corresponding to the logical register with reference to the correspondence information updated by the updating means when executing an instruction related to access to any logical register among the instructions in the instruction set architecture And an access control means for
The access control means, when a save instruction is executed to save the value stored in the designated logical register from the logical register to another storage medium having a lower access speed than the physical register, The value stored in the physical register corresponding to the specified logical register is read by reference, and the read value is stored in the physical register that is not associated with any logical register.
The update means adds a correspondence between the address of the other storage medium after execution of the save instruction and a physical register in which the value read by the access control means is stored in the correspondence information. .

(Supplementary Note 2) The access control means, when a saved value restoration instruction for storing a value saved by the save instruction in a newly specified logical register in the instruction set architecture is executed. The value stored in the physical register by the save instruction is read with reference to, and the read value is stored in the physical register corresponding to the newly specified logical register,
The update means deletes the correspondence between the physical register from which the stored value is read and the address of the other storage medium from the correspondence information by the access control means after the execution of the saved value restoration instruction. The processor according to appendix 1, wherein:

(Supplementary Note 3) When the save instruction is executed, the access control means uses the value stored in the designated logical register if the physical register not associated with any logical register exists. The processor according to appendix 1 or 2, wherein the processor is stored in the storage medium.

(Appendix 4) Provided with detecting means for detecting whether the usage state of each physical register is unused or used,
The renaming control means associates the logical register described in the instruction with the physical register detected as unused by the detecting means. The processor described.

(Supplementary Note 5) The access control means is described in the save value restore instruction if there is no value stored in the physical register by the save instruction even though the save value restore instruction is executed. The processor according to any one of appendices 2 to 4, wherein a value stored in an address of another storage medium is read.

(Appendix 6) It is detected whether the usage state of each physical register is unused or used, and in the case of further use, a value corresponding to the logical register is stored by the register renaming, or Detecting means for detecting whether the value saved by the save instruction is stored;
The renaming control means, when there is no physical register detected as unused by the detection means, the value stored in the physical register by the access control means described in the save instruction After storing in another storage medium, the physical register and the logical register are associated with each other,
The update means deletes the correspondence between the address of the other storage medium and the physical register from the correspondence information after execution of the register renaming. Processor.

(Appendix 7) A register access method in a processor having physical registers equal to or more than the number of logical registers specified in the instruction set architecture,
Register renaming for associating the logical register with the physical register, and generating correspondence information representing a correspondence between the logical register and the physical register;
An execution step of sequentially executing instructions described in the instruction set architecture;
When the execution step executes a save instruction for saving the value stored in the specified logical register from the logical register to another storage medium having a lower access speed than the physical register, refer to the correspondence information. Reading a value stored in a physical register corresponding to the designated logical register, and storing the read value in a physical register not associated with any logical register;
An additional step of adding, to the correspondence information, information including the correspondence between the physical register in which the value read out by the save value storage step and the address of the other storage medium are stored;
A register access method comprising:

(Supplementary note 8) When the read value is stored by the execution step after the read value is stored in the save value storage step, the save value restoration instruction is executed to store the newly saved value in the designated logical register.
With reference to the correspondence information to which the correspondence is added by the adding step, the value stored in the physical register by the save value storing step is read, and the read value is the physical corresponding to the newly specified logical register. The saved value restoration process stored in the register,
A deletion step of deleting the correspondence between the physical register from which the stored value has been read out by the saved value restoration step and the address of the other storage medium from the correspondence information;
The register access method according to appendix 7, wherein the register access method is included.

(Supplementary Note 9) The save value storing step stores the value stored in the designated logical register in the other storage medium when there is no physical register that is not associated with any logical register. 9. The register access method according to appendix 7 or 8, which is characterized by the following.

(Additional remark 10) The detection process which detects whether the use state of each physical register is unused or used before the said renaming process,
The renaming process associates the logical register described in the instruction set architecture with the physical register detected as unused by the detection process. The register access method described in 1.

(Supplementary Note 11) If the saved value restoring step is executed when the saved value restoring instruction is executed by the executing step and there is no value stored in the physical register by the saved instruction, the saved value restoring command is executed. 11. The register access method according to any one of appendices 8 to 10, wherein a value stored in an address of another storage medium described in the item (4) is read.

(Supplementary note 12) Before the renaming step, it is detected whether the usage state of each physical register is unused or used. A detection step of detecting whether a value is stored or a value saved by the save instruction is stored;
It is detected whether the use state of each physical register is unused or used, and in the case of further use, a value corresponding to the logical register is stored by the register renaming, or the save instruction A detection step for detecting whether the value saved by the
In the renaming process, if there is no physical register detected as unused by the detection process, the value stored in the physical register is stored in the other storage medium described in the save instruction. After that, the physical register is associated with the logical register,
Any one of appendixes 7 to 11, further comprising a deletion step of deleting the correspondence between the address of the other storage medium and the physical register from the correspondence information after executing the register renaming by the renaming step. The register access method according to any one of the above.

(Supplementary note 13) A register access program for causing a computer to control access to the physical register in a processor having physical registers equal to or more than the number of logical registers defined in the instruction set architecture,
The computer,
Register renaming for associating the logical register with the physical register, and generating renaming control means for representing correspondence between the logical register and the physical register;
Updating means for updating the correspondence information after execution of the instruction when an instruction in the instruction set architecture is executed and the correspondence between the logical register and the physical register is changed;
Accessing a physical register corresponding to the logical register with reference to the correspondence information updated by the updating means when executing an instruction related to access to any logical register among the instructions in the instruction set architecture Function as an access control means,
Further, the access control means is configured to execute the response when a save instruction is executed to save the value stored in the designated logical register from the logical register to another storage medium having a lower access speed than the physical register. Read the value stored in the physical register corresponding to the specified logical register with reference to the information, store the read value in the physical register that is not associated with any logical register,
The update means adds a correspondence between the address of the other storage medium after execution of the save instruction and the physical register in which the value read by the access control means is stored in the correspondence information. Access program.

(Additional remark 14) The said access control means is the said correspondence information, when the save value restoration command which stores the value saved by the said save command in the newly designated logic register among the said instruction set architecture is performed. The value stored in the physical register by the save instruction is read with reference to, and the read value is stored in the physical register corresponding to the newly specified logical register,
The update means deletes the correspondence between the physical register from which the stored value is read and the address of the other storage medium from the correspondence information by the access control means after the execution of the saved value restoration instruction. 14. The register access program according to appendix 13, wherein

(Supplementary Note 15) When the save instruction is executed, the access control means uses the value stored in the designated logical register if the physical register that is not associated with any logical register. 15. The register access program according to appendix 13 or 14, wherein the register access program is stored in the storage medium.

(Supplementary note 16)
Furthermore, it functions as a detection means for detecting whether the usage state of each physical register is unused or used,
The renaming control unit associates a logical register described in the instruction set architecture with a physical register detected as unused by the detection unit. Register access program described in 1.

(Supplementary Note 17) If the value stored in the physical register is not stored in the physical register by the save instruction even though the save value restore instruction is executed, the access control means is described in the save value restore instruction. The register access program according to any one of appendices 14 to 16, wherein a value stored in an address of another storage medium is read.

(Supplementary note 18)
Further, it is detected whether the use state of each physical register is unused or used, and in the case of further use, a value corresponding to the logical register is stored by the register renaming, or Function as a detection means for detecting whether the value saved by the save instruction is stored,
The renaming control means, when there is no physical register detected as unused by the detection means, the value stored in the physical register by the access control means described in the save instruction After storing in another storage medium, the physical register and the logical register are associated with each other,
The update means deletes the correspondence between the address of the other storage medium and the physical register from the correspondence information after execution of the register renaming. Register access program.

It is explanatory drawing which shows the outline | summary of the register access process concerning this Embodiment. It is a block diagram which shows the outline | summary of a structure of a processor. It is a block diagram which shows the structure of a rename part. It is explanatory drawing which shows the production | generation procedure of the save instruction by a compiler. It is explanatory drawing which shows an example of the register access process containing a save instruction. It is explanatory drawing which shows the storing process of the save value at the time of a physical register shortage. It is explanatory drawing which shows the setting of the status flag of a physical register. It is explanatory drawing which shows the example of a storage to a physical register.

Explanation of symbols

DESCRIPTION OF SYMBOLS 110 Logical register 120 Physical register 200 Processor 201 Instruction cache 202 Decoding part 203 Rename part 204 Schedule part 205 Execution part 301 Rename control part 302 Logical register-physical register correspondence table 303 Address-physical register correspondence table 304 Physical register state table

Claims (4)

In an arithmetic processing unit connected to a main storage device for storing data,
  Cache memory to hold data,
  A plurality of physical registers equal to or greater than the number of defined logical registers, each holding usage status information representing usage status;
  A generation unit that associates any one of the plurality of logical registers with any one of the plurality of physical registers, and generates inter-register correspondence information that represents a correspondence relationship between the associated logical register and the physical register;
  When a register use instruction using any of the plurality of logical registers is executed, a physical register corresponding to the logical register used by the register use instruction is used based on the inter-register correspondence information, and a designated logic A register stored in a physical register corresponding to the specified logical register based on the inter-register correspondence information when a save instruction for saving the register value stored in the register to the cache memory or the main storage device is executed A controller that stores the read register value in a physical register that is not associated with any logical register based on usage state information held by each of the plurality of physical registers after reading the value;
  When the correspondence relationship between the logical register and the physical register is changed as a result of the execution of the register use instruction, the inter-register correspondence information is updated, and the save instruction is executed and then designated for the save instruction. And an update unit for adding a correspondence relationship between the address of the cache memory or the main storage device and the physical register in which the register value read by the control unit is stored to the correspondence information between register memories. Arithmetic processing device. The controller is
  When executing a restore instruction that stores a register value saved in any of the plurality of physical registers in a specified logical register by executing the save instruction, based on the inter-register correspondence information, Read the register value stored in the physical register that was not associated with any logical register, store it in the physical register corresponding to the specified logical register,
  The update unit
  After execution of the restoration instruction, the correspondence relationship between the address of the cache memory or the main storage device and the physical register in which the register value read by the control unit is stored is deleted from the inter-register memory correspondence information. The arithmetic processing apparatus according to claim 1. The arithmetic processing unit includes:
  As usage status information held by each of the plurality of physical registers, unused, usage status in which register values saved by the save instruction are stored, or usage in which register values of associated logical registers are stored Have one of the states,
  The generator is
  When there is no unused physical register and there is a physical register in which the register value saved by the save instruction is stored based on the usage state information held by each of the plurality of physical registers, The register value stored in the physical register storing the register value saved by the save instruction is stored in the address of the cache memory or the main storage device specified for the save instruction, and then the specified Associating a logical register with the corresponding physical register,
  The update unit
  After associating the designated logical register with the corresponding physical register, the correspondence relationship between the address of the cache memory or the main storage device and the physical register in which the register value saved by the save instruction is stored 3. The arithmetic processing apparatus according to claim 1, wherein the arithmetic processing apparatus is deleted from the register memory correspondence information. An operation having a cache memory connected to a main storage device for storing data and holding data, and a plurality of physical registers equal to or more than a plurality of defined logical registers respectively holding use state information indicating the use state In a control method of a processing device,
  The generation unit included in the arithmetic processing unit associates any one of the plurality of logical registers with any one of the plurality of physical registers, and stores inter-register correspondence information indicating a correspondence relationship between the associated logical register and the physical register. Generate and
  When a register use instruction using any of the plurality of logical registers is executed, the control unit included in the arithmetic processing unit corresponds to the logical register used by the register use instruction based on the inter-register correspondence information. When a save instruction is executed that uses a physical register to save a register value stored in a specified logical register to the cache memory or the main storage device, the specified logical register based on the inter-register correspondence information After reading the register value stored in the physical register corresponding to, based on the usage status information held by each of the plurality of physical registers, the read register value is stored in a physical register that is not associated with any logical register. Store and
  When the correspondence relationship between the logical register and the physical register is changed as a result of execution of the register use instruction, the update unit of the arithmetic processing unit updates the inter-register correspondence information and the save instruction is executed. After that, a correspondence relationship between the address of the cache memory or the main storage device designated for the save instruction and the physical register storing the register value read by the control unit is added to the correspondence information between register memories A control method for an arithmetic processing unit, comprising: an updating unit that performs the processing.

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