JP5295941B2 - Signal processing circuit - Google Patents

Description

  The output voltage of the chopper amplifier is a voltage in which an offset voltage whose polarity is inverted in a predetermined cycle is superimposed on the amplified DC voltage. The present invention relates to a processing circuit that removes the influence of an offset voltage from an output voltage of a chopper amplifier.

When a sensor or the like outputs a minute DC voltage, a method of amplifying with a chopper amplifier 500 shown in FIG. 9 is frequently used. In the case of FIG. 9, the case where the sensor outputs two types of DC voltages Vsm (t) and Vsp (t) is illustrated. The true effective signal voltage of the sensor is the difference between the two (Vsp (t) − The case of Vsm (t)) is illustrated. The truly effective signal voltage (Vsp (t) -Vsm (t)) output by the sensor varies with the elapsed time.
For example, as shown in FIG. 10, the output voltage V1 (t) of the chopper amplifier circuit 500 is a DC voltage obtained by amplifying the sensor effective output voltage (Vsp (t) -Vsm (t)) (however, with respect to the elapsed time). A voltage on which an offset voltage whose polarity is inverted at a predetermined cycle is superimposed. In FIG. 10, G1 is an amplification factor, Vref is a reference voltage, and ΔVos is an offset voltage whose polarity is inverted in a predetermined cycle. Vs (t) in FIG. 10 is a value that varies according to the effective output voltage of the sensor. If the effective output voltage of the sensor varies with time, it varies correspondingly. In the case of FIG. 10, since the speed at which the value of Vs (t) changes is slower than the period in which the positive / negative of the offset voltage is reversed, the value of Vs (t) is shown not to fluctuate. . If illustrated over a longer period of time, the value of Vs (t) varies.

  In order to obtain the voltage Vs (t) corresponding to the effective output voltage of the sensor from the output voltage V1 (t) of the chopper amplifier circuit 500, the influence of the offset voltage whose polarity is inverted from the output voltage V1 (t) in a predetermined cycle. Need to be removed. Therefore, as shown in FIG. 9, the output voltage V1 (t) of the chopper amplifier circuit 500 is input to the low-pass filter circuit 600, the offset voltage changing at high speed is cut, and Vs (t) changing at low speed is obtained. The technique to obtain is used a lot. This prior art is described in detail in Non-Patent Document 1.

  Patent Document 1 proposes a technique for removing the influence of switching noise by sampling (sampling) the output voltage V1 (t) of a chopper amplifier at a plurality of times and averaging the plurality of sampled voltages. Yes. In this technique, the influence of switching noise is avoided by shifting the switching timing of the chopper amplifier (the polarity of the offset voltage is inverted in conjunction with this) and the sampling timing (for example, paragraph 0009).

JP 2008-219404 A

“Design of a fixed OP amplifier circuit” p287-p288, FIGS. 10-30, Ikuo Okamura, CQ Publisher

As shown in FIG. 10, the conventional technique using the low-pass filter circuit 600 described in Non-Patent Document 1 still has a problem that the influence of the offset voltage whose polarity is inverted at a predetermined cycle cannot be removed.
According to the sampling technique described in Patent Document 1, the influence of switching noise can be avoided, but there remains a problem that the influence of the offset voltage whose polarity is inverted at a predetermined period cannot be removed. In addition, since the process of performing the averaging operation after the sampling operation is repeated intermittently, there remains a problem that the processed voltage cannot be output continuously.

  The present invention provides a processing circuit capable of better removing the influence of an offset voltage (positive and negative polarity is periodically inverted) included in an output voltage of a chopper amplifier.

The signal processing circuit of the present invention inputs a signal voltage from a sensor or the like, and outputs a voltage obtained by superimposing a voltage obtained by amplifying the signal voltage with an offset voltage whose polarity is inverted in a predetermined cycle, and an output of the chopper amplifier A voltage corresponding to an operation result including a first sample and hold circuit that samples and holds the voltage at a predetermined period and outputs the sampled and held voltage, and a process of adding the output voltage of the chopper amplifier and the output voltage of the first sample and hold circuit. An arithmetic circuit for outputting, and a second sample and hold circuit for sampling and holding the output voltage of the arithmetic circuit at a predetermined cycle and outputting the sampled and held voltage are provided. The second sample and hold circuit may sample and hold the output voltage of the arithmetic circuit itself, or may sample and hold a voltage obtained by further processing the output voltage of the arithmetic circuit.
The cycle in which the polarity of the offset voltage is inverted, the sampling cycle of the first sample hold circuit, and the sampling cycle of the second sample hold circuit are all the same cycle. However, the timing at which the polarity of the offset voltage superimposed on the output voltage of the chopper amplifier is inverted is the first timing, the timing at which the first sample and hold circuit samples and holds is the second timing, and the timing at which the second sample and hold circuit samples and holds the timing. Is the third timing, the third timing is set within a period from the first timing to the second timing.
Here, the first timing means not the time when the offset voltage starts to reverse but the time when the reverse is finished. In addition, the second timing and the third timing refer to the time when the updating is completed, not when the value sampled and held by the sample and hold circuit is started.

  According to the signal processing circuit described above, during the period from the first timing to the second timing, the offset voltage included in the output voltage of the chopper amplifier is positive and negative, and the voltage sampled and held by the first sample hold circuit. The relationship between the positive and negative of the included offset voltage is reversed. Since the arithmetic circuit performs an operation including a process of adding a voltage including an offset voltage whose polarity is reversed, the arithmetic circuit outputs a voltage in which the positive / negative offset voltage is canceled. If the output voltage of the arithmetic circuit is sampled within the period from the first timing to the second timing, a voltage in which the positive and negative offset voltages are canceled can be detected. That is, it is possible to remove the influence of the offset voltage and take out a voltage corresponding to the effective output voltage of the sensor. The same applies to the case where the voltage obtained by further processing the output voltage of the arithmetic circuit is sampled and held by the second sample and hold circuit, and it is possible to take out the voltage corresponding to the effective output voltage of the sensor by removing the influence of the offset voltage. Become.

  As will be described with reference to FIG. 5, the chopper amplifier may be a two-input type similar to that of FIG. 9, or may be a one-input type described with reference to FIGS. 1 and 7.

When the difference between two types of signal voltages is an effective sensor voltage, a two-input chopper amplifier may be used as illustrated in FIG. 5, or a one-input chopper amplifier as illustrated in FIG. Two may be used.
When using a two-input type chopper amplifier, a chopper amplifier that inputs two types of signal voltages and outputs a voltage obtained by superimposing a voltage obtained by amplifying the difference between the two types of signal voltages with an offset voltage that reverses positive and negative at a predetermined cycle. Is used.

  When two 1-input type chopper amplifiers are used, a chopper amplifier and a first sample and hold circuit for inputting and processing the first signal voltage, a chopper amplifier for inputting and processing the second signal voltage, and the first One sample hold circuit is provided. In this case, a value obtained by adding the output voltage of the chopper amplifier that processes the first signal voltage and the output voltage of the first sample hold circuit, the output voltage of the chopper amplifier that processes the second signal voltage, and the first sample hold circuit. An arithmetic circuit that outputs a voltage corresponding to a difference from a value obtained by adding the output voltages is used.

  When the difference between the two types of signal voltages is an effective sensor voltage, the influence of the offset voltage may be removed from the voltage obtained by amplifying the difference between the two types of signal voltages. Alternatively, the influence of the offset voltage may be removed from each amplified voltage of each chopper amplifier, and then the voltage difference may be taken out.

  According to the processing circuit of the present invention, the influence of the offset voltage included in the output voltage of the chopper amplifier can be almost completely removed, and the voltage obtained by amplifying the signal voltage can be taken out.

1 is a diagram showing a schematic configuration of a signal processing circuit 100 according to a first embodiment of the present invention. The figure which shows the principle by which offset voltage (DELTA) Vos is canceled in the signal processing circuit. 2 is a diagram showing an internal configuration of a signal processing circuit 100. FIG. 4 is a time chart showing processing contents of the signal processing circuit 100. The figure which shows schematic structure of the signal processing circuit 100a which concerns on 2nd Example of this invention. The figure which shows the internal structure of the signal processing circuit 100a. The figure which shows schematic structure of the signal processing circuit which concerns on 3rd Example of this invention. The figure which shows the internal structure of the signal processing circuit which concerns on 3rd Example. The figure which shows the structure of a prior art. The time chart which shows the processing content by a prior art.

Hereinafter, in order to clearly describe the operation and effects of the present invention, embodiments of the present invention will be described in the following order.
A. B. Configuration and operation of signal processing circuit according to first embodiment of the present invention B. Configuration and Operation of Signal Processing Circuit According to Second Embodiment of the Invention Configuration and operation of signal processing circuit according to third embodiment of the present invention

A. Configuration of a signal processing circuit according to the first embodiment of the present invention:
FIG. 1 is a diagram showing a schematic configuration of a signal processing circuit 100 according to a first embodiment of the present invention. FIG. 2 is an explanatory diagram illustrating the principle by which the offset voltage ΔVos (offset error) is canceled by the signal processing circuit 100. FIG. 3 is a diagram illustrating an internal configuration of the signal processing circuit 100.

The signal processing circuit 100 receives a signal voltage Vs (t) output from a sensor or the like, and outputs an output voltage V1 (t) based on the analog reference voltage Vref, and an output voltage of the chopper amplifier 500. A first sample and hold circuit 110 that outputs a sampled and held voltage V2 (t) by sampling and holding at a predetermined period, a voltage obtained by inverting the output voltage V1 (t) of the chopper amplifier 500 with reference to Vref, and a first sample An adder circuit 120 that outputs a voltage V3 (t) obtained by adding a voltage obtained by inverting the output voltage V2 (t) of the hold circuit 110 with reference to Vref, and an output voltage V3 (t) of the adder circuit 120 Is sampled and held at a predetermined period to output a sampled and held voltage Vout (t). Here, (t) indicates a value that changes with the elapsed time. The output voltage V1 (t) of the chopper amplifier 500 is a voltage obtained by superimposing an offset voltage whose polarity is inverted at a predetermined cycle on a voltage obtained by amplifying the input voltage Vs (t).
The cycle in which the polarity of the offset voltage by the chopper amplifier 500 is inverted, the sampling cycle of the first sample hold circuit 110, and the sampling cycle of the second sample hold circuit 130 are all the same cycle. However, the timing at which the polarity of the offset voltage superimposed on the output voltage of the chopper amplifier 500 is inverted is the first timing, the timing at which the first sample and hold circuit 110 samples and holds is the second timing, and the second sample and hold circuit 130 performs sampling. When the holding timing is the third timing, the third timing is set within the period from the first timing to the second timing. The first timing means not the time when the offset voltage starts to reverse but the time when the reverse is finished. In addition, the second timing and the third timing refer to the time when the updating is completed, not when the value sampled and held by the sample and hold circuit is started.

(1) of FIG. 2 illustrates the voltage V1 (t) output from the chopper amplifier 500. The output voltage V1 (t) is an offset at which positive and negative are inverted at a predetermined cycle to a voltage obtained by amplifying the signal voltage Vs (t) (a voltage obtained by multiplying the signal voltage Vs (t) by -G) and the reference voltage Vref. The voltage ΔVos is superimposed. The -G is the amplification factor of the chopper amplifier 500, and the reference voltage Vref is a reference voltage applied to the chopper amplifier 500 as shown in FIG. In addition, the offset voltage ΔVos is inverted between positive and negative in synchronization with a first timing signal applied to the chopper amplifier 500 at a predetermined period. In the case of FIG. 2, the positive / negative of the offset voltage ΔVos superimposed on the output voltage V1 (t) is inverted at timings t3, t6, t9, and t12. Actually, the polarity of the offset voltage ΔVos does not invert at the moment when the timing signal is applied to the chopper amplifier 500, but inversion starts when the timing signal is applied, and the inversion ends after a predetermined time. The first timing CLK1 here refers to the timing at which the inversion ends. A timing signal applied to the chopper amplifier 500 to invert the polarity of the offset voltage ΔVos is applied to the chopper amplifier 500 at a timing earlier than the first timing CLK1 by a predetermined time.
The horizontal line of (1) in FIG. 2 is a voltage obtained by adding the reference voltage Vref to the voltage (−G × Vs (t)) obtained by amplifying the signal voltage Vs (t), and is a value that changes with time. However, the change time is longer than the period of the first timing CLK1, and is represented by a horizontal line when represented by the time scale shown in the figure.

2 shows the voltage V2 (t) output from the first sample and hold circuit 110. FIG. The first sample hold circuit 110 holds and outputs the value of the voltage V1 (t) at the input timing of the second timing signal CLK2. In the case of FIG. 2, the second timing signal CLK2 is applied to the first sample and hold circuit 110 at timings t2, t5, t8, and t11. Obviously, during the period from t3 to t5, from t6 to t8, from t9 to t11, and from t12 to t14, the positive and negative of the offset voltage ΔVos superimposed on the output voltage V1 (t) of the chopper amplifier 500, The sign of the offset voltage ΔVos superimposed on the output voltage V2 (t) of the first sample and hold circuit 110 is reversed. That is, the timing at which the polarity of the offset voltage superimposed on the output voltage V1 (t) of the chopper amplifier 500 is reversed is the first timing (t3, t6, t9, t12), and the timing at which the first sample hold circuit 110 performs sample hold. Assuming the second timing (t2, t5, t8, t11), the offset voltage superimposed in the period from the first timing to the second timing (t3 to t5, t6 to t8, t9 to t11, t12 to t14) The sign of ΔVos is inverted.
Actually, it takes time to update the sample hold value by the first sample hold circuit 110. The second timing here refers to the time when the updating of the value sampled and held by the first sample and hold circuit 110 is started, not when the value has been updated. The timing signal for starting to update the value sampled and held by the first sample and hold circuit 110 is applied to the first sample and hold circuit 110 at a timing earlier than the second timing CLK2 by a predetermined time.

  (3) in FIG. 2 shows the voltage V3 (t) output from the adder circuit 120. Apparently, in the period from the first timing to the second timing (t3 to t5, t6 to t8, t9 to t11, t12 to t14), the influence of the offset voltage ΔVos whose polarity is inverted is canceled and + 2G × Vs It can be seen that a voltage equal to (t) + Vref is output. Here, although referred to as an addition circuit, the reference voltage Vref included in each of V1 (t) and V2 (t) is not added. It is sufficient that the adder circuit here outputs a value that directly corresponds to the sum of at least V1 (t) and V2 (t), and is not limited by the magnitude of the bias voltage, and V1 (t) And the inverted voltage of V2 (t) may be added. The adder circuit 120 of this embodiment adds the inverted voltage of V1 (t) and the inverted voltage of V2 (t).

(4) in FIG. 2 shows the voltage Vout (t) output from the second sample and hold circuit 130. The second sample hold circuit 110 holds and outputs the value of the voltage V3 (t) at the input timing of the third timing signal CLK3. In the case of FIG. 2, the third timing signal CLK3 is applied to the second sample and hold circuit 130 at timings t4, t7, t10, and t13. Apparently, timing t4 is in the period from t3 to t5, timing t7 is in the period from t6 to t8, timing t10 is in the period from t9 to t11, and timing 13 is in the period from t12 to t14 . If the third timing for sample and hold by the second sample and hold circuit 130 is set within the period from the first timing to the second timing, the output Vout (t) of the second sample and hold circuit 130 is affected by the offset voltage ΔVos. It can be seen that the voltage is canceled out.
Actually, it takes time to update the sample hold value in the second sample hold circuit 130. The third timing here is not the time when the value sampled and held by the second sample and hold circuit 130 starts to be updated, but the time when the update is completed. The timing signal for starting to update the value sampled and held by the second sample and hold circuit 130 is applied to the second sample and hold circuit 130 at a timing earlier than the third timing CLK3 by a predetermined time.

  The output voltage Vout during the period t1 to t4 is equal to V3 (t1). The output voltage Vout during the period t4 to t7 is equal to V3 (t4), and its value corresponds to the average value of Vs (t2) and Vs (t4) on a one-to-one basis. It can be seen that the average value of Vs (t2) and Vs (t4) can be calculated from the value of Vout (t4 to t7). Similarly, the output voltage Vout during the period t7 to t10 is equal to V3 (t7), and its value corresponds to the average value of Vs (t5) and Vs (t7) on a one-to-one basis. It can be seen that the average value of Vs (t5) and Vs (t7) can be calculated from the value of Vout (t7 to t10). Similarly, the output voltage Vout during the period t10 to t13 is equal to V3 (t10), and its value corresponds to the average value of Vs (t8) and Vs (t10) on a one-to-one basis. It can be seen that the average value of Vs (t8) and Vs (t10) can be calculated from the value of Vout (t10 to t13).

  The second timings t2, t5, t8, and t11 sampled by the first sample and hold circuit 110 can be taken immediately before the first timings t3, t6, t9, and t12 at which the polarity of the offset voltage is subsequently inverted. For example, the timing t2 can be set immediately before the timing t3, the timing t5 can be set immediately before the timing t6, the timing t8 can be set immediately before the timing t9, and the timing t11 can be set immediately before the timing t12. Then, it can be understood that the period from the first timing to the second timing is set longer. That is, the period from the first timing to the second timing is the period immediately before the timing t3 to t6, the period immediately before the timing t6 to t9, and the period immediately before the timing t9 to t12. That is, if the second timing is set immediately before the first timing, the entire period is substantially the period from the first timing to the second timing, and from the output voltage V3 (t) of the adder circuit 120 in almost the entire period. The influence of the offset voltage can be eliminated. In this case, the third timing for sample and hold by the second sample and hold circuit 130 can be set relatively freely.

  FIG. 3 is an explanatory diagram showing the internal configuration of the signal processing circuit 100. The chopper amplifier 500 includes an operational amplifier CA1 and two resistors R1 and R2. A signal voltage Vs (t) output from a sensor or the like is input to the non-inverting input terminal (+) of the operational amplifier CA1. The resistors R1 and R2 are connected in series between the output terminal of the operational amplifier CA1 and the reference voltage Vref. The voltage between the resistors R1 and R2 is input to the inverting input terminal (−) of the operational amplifier CA1. The resistor R2 is a feedback resistor that applies negative feedback to the chopper amplifier CA1. A first timing signal is applied to the operational amplifier CA1 at a predetermined period. FIG. 4 shows the output voltage V1 (t) of the chopper amplifier 500, and it can be seen that an offset voltage whose polarity is inverted in a predetermined cycle is superimposed. Timings t3 and t6 indicate the first timing CLK1 at which the polarity of the offset voltage ΔVos has been inverted. Actually, the polarity of the offset voltage ΔVos does not invert at the moment when the first timing signal is applied to the chopper amplifier 500, but inversion starts when the first timing signal is applied, and the inversion ends after a predetermined time. . The first timing CLK1 here refers to the timing at which the inversion ends. The first timing signal applied to the chopper amplifier 500 in order to invert the polarity of the offset voltage ΔVos is applied to the chopper amplifier 500 at a timing earlier than the first timing CLK1 by a predetermined time.

  The first sample and hold circuit 110 includes a switch S1, a capacitor C1, and an operational amplifier A1. The first sample and hold circuit 110 samples (samples) a voltage V1 (t) that changes with time at a predetermined period, and outputs a sampled value.

  The switch S1 is turned on in response to the rising edge of the second timing signal and turned off in response to the falling edge. When the switch S1 is turned on, it is charged until the voltage of the capacitor C1 becomes equal to the voltage V1 (t) at that time. The second timing signal falls at the time when the capacitor C1 finishes charging, and the switch S1 is turned off. The capacitor C1 holds the value of V1 (t) at the timing of the falling edge of the second timing signal. The second timing CLK2 here corresponds to the timing at which the value sampled and held by the first sample and hold circuit 110 has been updated. That is, it refers to the timing of the falling edge of the second timing signal. The operational amplifier A1 is used as a voltage follower because the output voltage is fully fed back to the inverting input terminal. As a result, the output voltage V2 (t) of the operational amplifier A1 becomes equal to the voltage of the capacitor C1. The operational amplifier A1 functions as a high impedance element that prohibits discharging of the capacitor C1.

  The adder circuit 120 includes an operational amplifier A2 and three resistors R3a, R3b, and R4. The output voltage V1 (t) of the chopper amplifier 500 is connected to the inverting input terminal (−) of the operational amplifier A2 via the resistor R3b. Further, the output voltage of the first sample hold circuit 110 is connected via the resistor R3a. V2 (t) is connected. The resistor R4 is connected between the inverting input terminal and the output terminal of the operational amplifier A2, and functions as a feedback resistor for negative feedback. The reference voltage Vref is input to the non-inverting input terminal (+) of the operational amplifier A2. The adder circuit 120 adds the voltage obtained by inverting the output voltage V1 (t) of the chopper amplifier 500 with reference to Vref and the voltage obtained by inverting the output voltage V2 (t) of the first sample hold circuit 110 with reference to Vref. The added voltage V3 (t) is output with reference to Vref.

  In this example, the gain G2 of the adder circuit 120 is 1.0. The gain can be set freely. As shown in FIG. 4, the output signal V3 (t) of the adder circuit 120 causes a transient phenomenon in the output voltage V1 (t) of the chopper amplifier 500 and the output voltage V2 (t) of the first sample hold circuit 110. The period includes a large amount of noise, but is stable in other periods, and the influence of the offset voltage that reverses positive and negative is eliminated.

  Similar to the first sample and hold circuit 110, the second sample and hold circuit 130 includes a switch S2, a capacitor C2, and an operational amplifier A3. The second sample and hold circuit 130 samples (samples) a voltage V3 (t) that changes with time at a predetermined period, and outputs a sampled value.

  The switch S2 is turned on in response to the rising edge of the third timing signal and turned off in response to the falling edge. When the switch S2 is turned on, it is charged until the voltage of the capacitor C2 becomes equal to the voltage V3 (t) at that time. The third timing signal falls and the switch S2 is turned off at the time when the capacitor 2 finishes charging. The capacitor C2 holds the value of V3 (t) at the falling timing of the third timing signal. The third timing CLK3 here corresponds to the timing at which the value sampled and held by the second sample and hold circuit 130 has been updated. That is, it refers to the timing of the falling edge of the third timing signal. The operational amplifier A3 is used as a voltage follower because the output voltage is fully fed back to the inverting input terminal. As a result, the output voltage Vout (t) of the operational amplifier A3 becomes equal to the voltage of the capacitor C2. The operational amplifier A3 functions as a high impedance element that prohibits discharging of the capacitor C2.

The second sample and hold circuit 130 is different from the first sample and hold circuit 110 in that a resistor R5 is provided between the non-inverting input terminal of the operational amplifier A3 and the switch S2. The resistor R5 is a resistor equipped for the purpose of reducing noise caused by a steep voltage fluctuation at the non-inverting input terminal of the operational amplifier A3.
In the first sample and hold circuit 110, no resistor is connected between the switch S1 and the capacitor C1 in order to charge the capacitor C1 to a voltage equal to V1 (t) in a short time. In the first sample hold circuit 110, the time from the rising edge to the falling edge of the second timing signal can be shortened. By shifting the ON period of the switch S1 and the ON period of the switch S2, the noise generated in the first sample and hold circuit 110 can be prevented from being sampled by the second sample and hold circuit 130.

  In the signal processing circuit 100 according to the embodiment of the present invention, the second period between the first timing CLK1 at which the polarity of the offset voltage ΔVos is inverted and the second timing CLK2 at which the switch S1 of the first sampling and holding circuit 110 is turned off. The time relationship is set to the third timing CLK3 at which the switch S2 of the sampling hold circuit 130 is turned off. As a result, a voltage that offsets the influence of the offset voltage ΔVos is output from the second sampling and holding circuit 130. The influence of the offset voltage ΔVos can be almost completely removed.

B. Second embodiment
FIG. 5 shows a schematic configuration of a signal processing circuit 100a according to the second embodiment of the present invention, and FIG. 6 shows an internal configuration of the signal processing circuit 100a. The chopper amplifier 500a of the signal processing circuit 100a has a pair of operational amplifiers CA1 and CA2, and amplifies the difference between the two types of DC voltages Vsm (t) and Vsp (t). The signal processing circuit 100a is useful when the sensor outputs two types of DC voltages Vsm (t) and Vsp (t), and the difference between the two indicates the actual detection target state.
The chopper amplifier in the present invention is not limited to a one-input one-output amplifier, and includes an amplifier that inputs and amplifies a plurality of types of voltages.

C. Third embodiment
FIG. 7 shows a schematic configuration of a signal processing circuit according to the third embodiment of the present invention. The signal processing circuit of the third embodiment is useful when the sensor outputs two types of DC voltages Vsm (t) and Vsp (t), and the difference between the two indicates the actual detection target state.
In the third embodiment, for the first signal voltage Vsm (t), a chopper amplifier 600a that outputs the output voltage Vm1 (t) amplified by inputting the first signal voltage Vsm (t), and a chopper amplifier A first sample-and-hold circuit 610a that samples and holds the output voltage Vm1 (t) of 600a at a predetermined period and outputs the sampled and held voltage Vm2 (t) is provided. Further, for the second signal voltage Vsp (t), a chopper amplifier 600b that outputs the output voltage Vp1 (t) amplified by inputting the second signal voltage Vsp (t), and an output voltage of the chopper amplifier 600b A first sample hold circuit 610b is provided which samples and holds Vp1 (t) at a predetermined period and outputs a sampled and held voltage Vp2 (t).
Furthermore, the signal processing circuit of the third embodiment includes an arithmetic circuit 630. The arithmetic circuit 630 outputs the output voltage Vm1 (t) of the chopper amplifier 600a that processes the first signal voltage Vsm (t), the output voltage Vm2 (t) of the first sample hold circuit 610a, and the second signal voltage Vsp (t). Is input to the output voltage Vp1 (t) of the chopper amplifier 600b and the output voltage Vp2 (t) of the second sample and hold circuit 610b, and a voltage obtained by adding Vm1 (t) and Vm2 (t) to Vp1 (t) And a voltage corresponding to the voltage difference of the voltage obtained by adding Vp2 (t). That is, the arithmetic circuit 630 outputs a voltage indicating a value represented by (Vm1 (t) + Vm2 (t)) − (Vp1 (t) and Vp2 (t)) with reference to Vref. The arithmetic circuit 630 includes a process of adding the output voltage of the chopper amplifier 600a and the output voltage of the first sample hold circuit 610a, and a process of adding the output voltage of the chopper amplifier 600b and the output voltage of the first sample hold circuit 610b. Perform the calculation that
Furthermore, the signal processing circuit of the third embodiment includes a second sample and hold circuit 640 that samples and holds the output voltage of the arithmetic circuit 630 at a predetermined period and outputs a sampled voltage Vout (t).
The other explanation is the same as that of the first embodiment, and the duplicate explanation is omitted.

  FIG. 8 shows the internal configuration of the signal processing circuit of the third embodiment. The operational amplifier 700a and the like constitute a chopper amplifier 600a, the switch SW1 and the operational amplifier 710a and the like constitute a first sample and hold circuit 610a, the operational amplifier 700b and the like constitute a chopper amplifier 600b, and the switch SW2 and the operational amplifier 710b and the like constitute a first sample and hold. A circuit 610b is configured. The arithmetic circuit 630 is constituted by the resistors R63 and R64, the operational amplifier 730, and the like. Further, the second sample hold circuit 640 is configured by the switch SW3, the operational amplifier 740, and the like.

According to the signal processing circuit of the third embodiment, the output voltage Vm1 (t) of the chopper amplifier 600a is obtained by superimposing an offset voltage whose polarity is inverted at a predetermined cycle on the voltage obtained by amplifying the first signal voltage Vsm (t). It has become. Since the output voltage Vm1 (t) and the voltage Vm2 (t) sampled and held by the first sample and hold circuit 610a are added, the influence of the offset voltage is removed from the output voltage output from the arithmetic circuit 630. Yes. Similarly, the output voltage Vp1 (t) of the chopper amplifier 600b is a voltage obtained by amplifying the second signal voltage Vsp (t) and an offset voltage whose polarity is inverted at a predetermined cycle. Since the output voltage Vp1 (t) and the voltage Vp2 (t) sampled and held by the first sample hold circuit 610b are added, the influence of the offset voltage is removed from the output voltage output from the arithmetic circuit 630. Yes. The arithmetic circuit 630 is a voltage obtained by removing the influence of the offset voltage from the voltage obtained by amplifying the first signal voltage Vsm (t) and the voltage obtained by removing the influence of the offset voltage from the voltage obtained by amplifying the second signal voltage. The difference can be taken out.
In the second embodiment, the influence of the offset voltage is removed after the voltage difference is amplified, whereas in the third embodiment, each of the two types of signal voltages is amplified and the influence of the offset voltage is detected from each of them. After removing, voltage difference is taken out. In any case, a voltage difference that is not affected by the offset voltage can be extracted.

C. Variations:
Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. For example, when the S / N ratio is prevented from lowering due to the return of a noise component in a frequency band higher than the Nyquist frequency (1/2 of the sampling frequency) generated during sample hold, the output of the chopper amplifier It is preferable to insert a low-pass filter that cuts off noise in a frequency band higher than the Nyquist frequency from the voltage. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in the present specification or the drawings can achieve a plurality of objects at the same time, and has technical utility by achieving one of the objects.

DESCRIPTION OF SYMBOLS 100, 100a ... Signal processing circuit 110 ... 1st sample hold circuit 120 ... Adder circuit 130 ... 2nd sample hold circuit 500 ... Chopper amplifier 500a ... Differential amplification type chopper amplifier 600 ... Low pass filter circuit

Claims (3)

A chopper amplifier that inputs a signal voltage and outputs a voltage in which an offset voltage whose polarity is inverted in a predetermined cycle is superimposed on a voltage obtained by amplifying the signal voltage;
A first sample and hold circuit that samples and holds the output voltage of the chopper amplifier at the predetermined period and outputs the sampled and held voltage;
An arithmetic circuit that outputs a voltage corresponding to an arithmetic result including a process of adding the output voltage of the chopper amplifier and the output voltage of the first sample and hold circuit;
A second sample-and-hold circuit that samples and holds the output voltage of the arithmetic circuit at the predetermined period and outputs the sampled and held voltage;
The timing at which the sign of the offset voltage superimposed on the output voltage of the chopper amplifier is inverted is the first timing, the timing at which the first sample and hold circuit samples and holds is the second timing, and the second sample and hold circuit performs sample and hold. A signal processing circuit characterized in that the third timing is set within a period from the first timing to the second timing when the timing is the third timing.   The chopper amplifier inputs two kinds of signal voltages and outputs a voltage in which an offset voltage whose polarity is inverted at a predetermined cycle is superimposed on a voltage obtained by amplifying a difference between the two kinds of signal voltages. 2. The signal processing circuit according to 1. A first signal voltage chopper amplifier that inputs a first signal voltage and outputs a voltage in which an offset voltage whose polarity is inverted in a predetermined cycle is superimposed on a voltage obtained by amplifying the first signal voltage;
  A first sample and hold circuit for a first signal voltage that samples and holds the output voltage of the chopper amplifier for the first signal voltage at the predetermined period and outputs the sampled and held voltage;
  A second signal voltage chopper amplifier that inputs a second signal voltage and outputs a voltage in which an offset voltage whose polarity is inverted in a predetermined cycle is superimposed on a voltage obtained by amplifying the second signal voltage;
  A first sample-and-hold circuit for a second signal voltage that samples and holds the output voltage of the chopper amplifier for the second signal voltage at the predetermined period and outputs the sampled and held voltage;
  A value obtained by adding an output voltage of the first signal voltage chopper amplifier and an output voltage of the first signal hold circuit for the first signal voltage, an output voltage of the chopper amplifier for the second signal voltage, and the second An arithmetic circuit for outputting a voltage corresponding to a difference from a value obtained by adding the output voltages of the first sample hold circuit for signal voltage;
  A second sample-and-hold circuit that samples and holds the output voltage of the arithmetic circuit at the predetermined period and outputs the sampled and held voltage;
  The timing at which the polarity of the offset voltage superimposed on the output voltage of the chopper amplifier for the first signal voltage and the chopper amplifier for the second signal voltage is inverted is a first timing, and the first sample hold circuit for the first signal voltage And the first sample hold circuit for the second signal voltage is set to the second timing, and the sample hold timing to the second sample hold circuit is set to the third timing. A signal processing circuit characterized in that the third timing is set within the period up to.

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