JP5293289B2 - Multi-core processor and control method thereof - Google Patents

Multi-core processor and control method thereof Download PDF

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JP5293289B2
JP5293289B2 JP2009057261A JP2009057261A JP5293289B2 JP 5293289 B2 JP5293289 B2 JP 5293289B2 JP 2009057261 A JP2009057261 A JP 2009057261A JP 2009057261 A JP2009057261 A JP 2009057261A JP 5293289 B2 JP5293289 B2 JP 5293289B2
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processing time
tasks
processor core
power consumption
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久典 藤沢
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富士通株式会社
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing
    • Y02D10/20Reducing energy consumption by means of multiprocessor or multiprocessing based techniques, other than acting upon the power supply
    • Y02D10/22Resource allocation
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing
    • Y02D10/20Reducing energy consumption by means of multiprocessor or multiprocessing based techniques, other than acting upon the power supply
    • Y02D10/24Scheduling
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing
    • Y02D10/30Reducing energy consumption in distributed systems
    • Y02D10/36Resource sharing

Description

  The present invention relates to a control method for reducing the power consumption of an multicore processor and an multicore processor.

In a multi-core processor having a plurality of processor cores, tasks are allocated to the respective processor cores so that the respective processor cores execute the tasks in parallel, so that high computing performance is realized. In order to reduce the power consumption of the multi-core processor, so-called dynamic voltage frequency control (DVFS) is performed in the multi-core processor.
Here, in a processor having a single processor core, the processing time required for a task may be longer than the time that can be processed by the task determined by the maximum performance of the processor core. Therefore, in a single processor core, DFVS is executed by reducing the frequency of the power supply voltage or operation clock supplied to the processor core and extending the actual task processing time according to the required processing time.

  On the other hand, in a multi-core processor, tasks are not assigned continuously to each processor core, but due to parallelism, depending on the status of other processor cores, the next task There is a waiting time until processing starts. Therefore, in the multi-core processor, the DFVS reduces the frequency of the power supply voltage or the operation clock supplied to the processor core in consideration of both the processing time required for the task and the waiting time until the task processing starts. It is executed by extending the actual task processing time (see Patent Document 1).

  That is, in general, DFVS pays attention to the relationship between one task assigned to the processor core of interest and the task assigned next, and the frequency of the power supply voltage or operation clock supplied to the processor core of interest. It is executed by controlling.

JP 2006-293768 A

  Focusing on a group of tasks, a multi-core processor designed to reduce power by providing a function to control the power supply voltage or operation clock frequency supplied to a plurality of processor cores that process the group of tasks in association with each other, Also provided is a control method for reducing the power consumption of a multi-core processor by controlling the power supply voltage supplied to a plurality of processor cores that process a group of tasks or the frequency of an operation clock in association with each other.

In order to solve the above problems, according to an aspect of the invention,
A plurality of processor cores that process a plurality of tasks in parallel, an identification number that identifies a related first task group for each task, a task processing time required for the processor core to process the task, and a first task group A register for storing an upper limit period for executing the tasks included in
From the tasks included in the first task group, the second task group consisting of a plurality of tasks that are processed in parallel and connected to the same task is extracted, and the longest of the task processing times of the plurality of tasks The task processing time is defined as the first processing time for processing the second task group, and the second task group occupying the upper limit period is executed according to the power consumption of the processor core that processes the second task group and the first processing time. A setting circuit for setting the second processing time;
A drive circuit that changes the frequency or power supply voltage of the operation clock supplied to the processor core that processes each task from the predetermined frequency or power supply voltage of the operation clock according to the ratio between the task processing time and the second processing time. A multi-core processor is provided.

  As a result, for the task group that requires a large amount of power consumption, the processing time for the upper limit period becomes longer, and the power consumption of the processor core that executes the task group is greatly reduced. There is an effect of increasing.

FIG. 1 is a diagram illustrating a multi-core processor 10 according to the first embodiment. FIG. 2 is a flowchart 20 for explaining a control method for reducing the power consumption of the multi-core processor 10. 3A, 3B, 3C, and 3D are diagrams for explaining a specific example of the operation op1. 4A and 4B are diagrams illustrating a specific example of the operation op2. 5A, FIG. 5B, FIG. 5C, FIG. 5D, and FIG. 5E show an example in which operation op2 is performed on a task group composed of tasks having a more complicated relationship. FIG. 6 is a diagram for explaining a specific example of the operation op4.

  The present invention includes the embodiments described below that have been modified by the design that can be conceived by those skilled in the art, and those in which the components shown in the embodiments have been recombined. Further, the present invention includes those in which the constituent elements are replaced with other constituent elements having the same operational effects, and are not limited to the following embodiments.

FIG. 1 is a diagram illustrating a multi-core processor 10 according to the first embodiment. The multi-core processor 10 of the first embodiment includes a scheduler 11, a reference task information memory 12, a task information memory 13, a frequency control circuit 14, a power supply voltage control circuit 15, and n processor cores 181 to 18n (n is 1). Up to the above integer), the bus 19 is configured.
The multi-core processor 10 is a processor that executes a plurality of tasks included in a task group in parallel.
The scheduler 11 assigns a task to each processor core 18n, calculates the processing time of the assigned task in each processor core 18n, and determines the power supply voltage and operation clock frequency supplied to each processor core according to the processing time. It is a circuit to determine.
The reference task information memory 12 includes a task ID number (identification number) that identifies a task group to which the reference task relates and a reference ID included in the task group and each processor core 18n in a predetermined standard operation. This is a memory for storing a restriction time for processing the reference task, a start time of the reference task, and an execution flag indicating whether or not the reference task is being executed.

The task information memory 13 includes a task ID (identification number) that identifies all tasks except the reference task, an ID (identification number) of a reference task to which the task relates, and an operation clock for the standard operation of each processor core 18n. A memory that stores a standard processing time for executing the task at a frequency and a power supply voltage.
The frequency control circuit 14 includes a clock generation circuit and supplies an operation clock to each processor core 18n. The frequency control circuit 14 receives information on the frequency of the operation clock of each processor core 18 n from the scheduler 11 via the bus 19. Note that the clock generation circuit may generate a plurality of clocks having different clock frequencies, and supply different operation clocks by switching them, or generate one clock and divide the clocks. An operation clock may be generated by making a round.

The power supply voltage control circuit 15 includes a power supply voltage generation circuit and supplies a power supply voltage to each processor core 18n. The power supply voltage control circuit 15 receives information on the power supply voltage of each processor core 18 n from the scheduler 11 via the bus 19.
The processor core 18n is a processor that executes each task assigned to the scheduler.
The bus 19 is used for transmitting signals between circuits constituting the multi-core processor 10.

FIG. 2 is a flowchart 20 for explaining a control method for reducing the power consumption of the multi-core processor 10.
In operation op1, the scheduler 11 extracts a task group for performing time allocation based on the task ID number of the reference task, and all tasks related to the task group are related to the task ID of the task and the task. It is specified by the ID of the reference task. Next, the scheduler 11 grasps the time order relationship between tasks by analyzing a program given to the multi-core processor 10. Here, the time order relationship includes not only the order relationship of the start times of the tasks, but also the relationship of whether or not the processing result of one task is used for the execution of the other task. The scheduler 11 also constructs the dependency graph between tasks shown in FIG. 3D from the time order relationship obtained from the analysis of the program.

3A, 3B, 3C, and 3D are diagrams for explaining a specific example of the operation op1. FIG. 3A shows a table indicating the reference task information of task E serving as a reference task. The reference task information includes a task ID number of the reference task E, a constraint time, a start time, and an execution flag. Then, the scheduler 11 extracts a task group based on the task ID number of the reference task E. FIG. 3B shows a table indicating task information of tasks. The task information includes task IDs of tasks A, B, C, and D, a reference task ID, a processing amount, and a standard processing time. Therefore, the scheduler 11 specifies a task related to the task group from the task ID and the reference task ID.
FIG. 3C is a diagram showing a time order relationship between tasks in a task group. The scheduler 11 starts the processing of the task D after the processing of the tasks A, B, and C and the reference task E starts from the given program, and uses the processing results of the tasks A, B, and C in the task D. Recognize that. Further, the scheduler 11 recognizes that the processing of the task F is performed after the processing of the task D is started, and the task F uses the results of the reference task E and the task D. Tasks A, B, C, D, and E are tasks related to this task group, and are tasks for which processing time is allocated. Task F is a task that follows this task group.
FIG. 3D is a diagram showing a dependency graph of task groups. The dependency graph is a graph in which a task is a node and a time order relationship between tasks is a branch. Further, a node at the final stage is a root, and a node that does not have a node connected to itself is a leaf. Then, tasks A, B, and C and reference task E are leaf nodes, and tasks D and F are root nodes. The scheduler 11 extracts the order relation between tasks in the task group from the analysis of the program and recognizes it as a dependency graph as shown in FIG. 3D.

Referring to FIG. 2, in operation op2, the scheduler 11 allocates processing time to each task. More specifically, operation op2 is performed as follows.
In operation op2-1, the scheduler 11 extracts tasks that are processed in parallel and are connected to the same task. Then, the power consumption Pk depending on the task processing time Tl is obtained for the processor core 18n that processes each task and the same task. Here, the power consumption Pk is given by the following equation.
Pk = P0 × Tl × (Lk / Tl / R0) q = Ak × Tl (1-q) ――――― (1) Equation Ak = P0 × (Lk / R0) q ――――― (2) Expression P0: Power consumption of the processor core 18n with respect to the standard operation of the processor core 18n R0: Maximum processing amount per unit time of the processor core 18n with respect to the standard operation of the processor core 18n Lk: Processing amount of the task q: DVFS is applied It is a characteristic coefficient determined by the characteristics of the processor core 18n, and is a value of about 1.5 to 2. Note that although P0 and R0 are common values in all the processor cores 18n, they may be different from each other. Absent. Further, P0 and R0 can be stored in the scheduler 11 in advance.
The reason why the power consumption Pk is expressed as a function of the processing time Tl will be described below. First, the power P per unit time is generally expressed as P∝f × V 2 from the frequency f and the power supply voltage V. Next, the delay time of the logic gate has a relationship between the power supply voltage V and Td∝V −2.5 to −3.5 . Therefore, V 2 ∝T −0.57 to −0.8 . On the other hand, f∝1 / Td. Therefore, P∝f is 1.57 to 1.8 . Further, the processing time T when a task with the load L is processed at the frequency f is T = L × f0 / R0 / f, assuming that the processor can process the load of R0 per unit time at the frequency f0. Therefore, f∝L / T / R0. Therefore, since the power consumption during the processing time T is P × T, Pk = P × T∝T × (L / T / R0) 1.57 to 1.8 .

Next, the extracted task is set as an integrated task, and the sum of the power consumption of each task is calculated as the power consumption of the integrated task. That is, it is as follows.
Total power of integrated task = ΣP0 × Ts × (Lk / Ts / R0) q = (Bs) × Ts (1-q) ―――――――― (3)
Bs = ΣAk = ΣP0 × (Lk / R0) q (4) where Ts is a processing time common to a plurality of processor cores 18n executing the integrated task.

In operation op2-2, the scheduler 11 sequentially extracts integrated tasks performed serially and makes them sequential tasks. It is assumed that there is no task performed in parallel and is not an integrated task of operation op2-1, but a task performed in series with the integrated task of operation op2-1 is also an integrated task of operation op2-2.
As a result, a plurality of integrated tasks are sequentially connected in series. If a sequential task is composed of m integrated masks, the power consumption CSn of the sequential task is as follows.
CSn = Bn1 * Tn1 (1-q) + Bn2 * Tn2 (1-q) +. . . . . + Bnm × Tnm (1−q) (5) where Bnm is a coefficient Bs in an expression representing the total power of the integrated task, and is a power coefficient. Tnm is a processing time common to the plurality of processor cores 18n that execute the integrated task.
Next, the scheduler 11 determines the ratio of the integrated task processing time so that the ratio of the power coefficient of each integrated task to the 1 / qth power matches the ratio of the processing time of each integrated task.
That is, Bn1 (1 / q) : Bn2 (1 / q) :. . . : Bnm (1 / q) = Tn1: Tn2:. . . : Tn1, Tn2,. . . , Determine the ratio of Tnm.
When the processing time for performing the entire sequential task is given as Tn, the processing time of each integrated task in Tn is Tn1 = Tn × Bn1 (1 / q) / (Bn1 (1 / q) + Bn2 (1 / q) + ... + Bnm (1 / q) ),. . . . , Tnm = Tn × Bnm (1 / q) / (Bn1 (1 / q) + B2 (1 / q) +... + Bnm (1 / q) )), and CSn is calculated from the equation (5):
CSn = Tn (1-q) * (Bn1 (1 / q) + Bn2 (1 / q) + ... + Bnm (1 / q) ) / (Bn1 (1 / q) + Bn2 (1 / q) +. + Bnm (1 / q) ) (1-q) = Tn (1-q) × (Bn1 (1 / q) + Bn2 (1 / q) + ... + Bnm (1 / q) ) q ―――― (6) Equation

In operation op2-3, the scheduler 11 incorporates all tasks in the task group except the reference task into the operation op2-1, the integrated task of operation op2-2, or the sequential task of operation op2-2. Here, when the above task is taken into the sequential task, the operation op2-2 or the operation op2-1 integrated task that is parallel to the sequential task of the operation op2-2 and connected to the same task, or the operation op2-2 sequential task. If there are any, they are newly integrated to form an integrated task of operation 2-3.
When calculating the integrated task of the above new operation op2-3, when the sequential task in parallel is set as the integrated task, the larger Ta among the processing times Ta and Tb of each sequential task is adopted. The power consumption CSm of the integrated task is
CSm = (Ba) × Ta (1-q)
Ba = (Ba1 (1 / q ) + Ba2 (1 / q) + ... + Bam (1 / q)) q + (Bb1 (1 / q) + Bb2 (1 / q) + ... + Bbs (1 / q ) ) Q ―――― (7) If there are multiple sequential tasks in parallel, the longest processing time is Ta, and (Bb1 (1 / q) + Bb2 ( 1 / q) + ... + Bbs (1 / q) ) The term of q is added by the number of sequential tasks.
On the other hand, when the integrated task and the sequential task are used as the integrated task of the new operation 2-3, the total power of the integrated task is (Bs) × Ts (1-q) , and the power consumption of the sequential task is CSn = Tn (1 -q) x (Bn1 (1 / q) + Bn2 (1 / q) + ... + Bnm (1 / q) ) If q , the power consumption CSm of the integrated task is the long processing time of Ts and Tn. As Ta,
CSm = (Bs) Ta (1-q) + Ta (1-q) * (Bn1 (1 / q) + Bn2 (1 / q) + ... + Bnm (1 / q) ) q
CSm = (Ba) × Ta (1-q)
Ba = (Bn1 (1 / q) + Bn2 (1 / q) +... + Bnm (1 / q) ) q + Bs-(8)
As described above, when the operation op2-3 is completed, a sequential task in which the integrated tasks of the operation op2-3 are sequentially connected is completed.

In operation op2-4, the scheduler 11 processes the integrated task so that the ratio of the power coefficient of the integrated task in each operation op2-3 to the 1 / qth power matches the ratio of the processing time of each integrated task. Determine the time ratio.
That is, B1 (1 / q) : B2 (1 / q):. . . : Bn (1 / q) = T1: T2:. . . : T1, T2,. . . , Tn ratio is determined. B1 to Bn in the above equation (9) are the same coefficients as Ba in the equation (7) or (8).
Next, the scheduler 11 assigns the constraint time (T criterion) of the reference task of this task group as the processing time of each integrated task at the ratio of the processing time of the integrated task.
That is, T reference × B1 (1 / q) / (B1 (1 / q) + B2 (1 / q) + ... + Bn (1 / q) ),. . . . , T reference × Bn (1 / q) / (B1 (1 / q) + B2 (1 / q) +... + Bn (1 / q) ) Reset the processing time. However, if the reset processing time is shorter than the standard processing time of the integration task, the standard processing time of the integration task that was shortened in advance is subtracted from the standard task constraint time, and the remaining constraint time is calculated. Allocate the remaining integration tasks with the ratio of the remaining integration task processing times.
However, when the difference between the standard processing time and the shortened processing time is small, it is possible to increase the power supply voltage of the processor core 18n or the frequency of the operation clock.
Next, the operation op2-1, the operation op2-2 integration task, and the operation op2-2 sequential task constituting the integration task of each operation op2-3 are assigned to the operation op2-3 integration task. The processing time Tm is further allocated to each of the tasks at a ratio of the 1 / qth power of the power coefficients of the tasks constituting them.

As a result, the power consumption CSm of each integrated task is as follows.
CSm = T standard (1-q) × Bm (1 / q) / (B1 (1 / q) + B2 (1 / q) + ... + Bm (1 / q) ) (1-q)
Further, the power consumption of the entire sequential task including m integrated masks is as follows.
CS = T criterion (1-q) × (B1 (1 / q) + B2 (1 / q) + ... + Bm (1 / q) ) / (B1 (1 / q) + B2 (1 / q) +. ( + Bm (1 / q) ) (1-q) = T reference (1-q) x (B1 (1 / q) + B2 (1 / q) + ... + Bm (1 / q) ) q- ( 10) Expression The constraint time of the reference task of the task group becomes longer than the processing time for each integrated task. Therefore, since q is about 1.5 to 2, since 1-q is a negative number, the T criterion (1-q) is reduced, so that the power consumption CS increases the processing time for each integrated task. Will decrease.

Further, as described above, in each integrated task, the processing time of the processor core 18n that executes the task is extended. This means that the processing amount of each integrated task is equal to the processing of the processor core 18n within the reference task constraint time. This means that the frequency of the operation clock supplied to the processor core 18n and the power supply voltage are lowered so as to match the amounts. Furthermore, extending the processing time of the processor core 18n in accordance with the power coefficient of each integrated task according to the power of 1 / q indicates that the power consumption reduction amount is increased as the processor core 18n has higher power consumption. .
Therefore, the power consumption of the multiprocessor core 10 that executes the task group can be greatly reduced.

4A and 4B are diagrams illustrating a specific example of the operation op2. FIG. 4A is a table showing the task ID, standard task ID, standard processing time, time distribution ratio, retime distribution ratio, and processing time of tasks A, B, C, and D related to the task group.
The processing amount of task A is 300M. The processing amount of task B and task C is 250M. The processing amount of task D is 100M. Accordingly, assuming that the maximum processing amount R0 per unit time for the standard operation of each processor core 18n is 1000M, the standard processing times of the tasks A, B, C, and D are 300ms, 250ms, 250ms, and 100ms, respectively. . It is assumed that the restriction time of the standard task E of the task group related to the tasks A, B, C, and D is 600 ms, and the processing time of the task F that follows this task group is 100 ms.

Here, assuming that the power consumption P0 of the processor core 18n with respect to the standard operation of the processor core 18n is 412 mW, the sum of the power coefficients (ABC) of the integrated task composed of the tasks A, B, and C is as follows. .
Sum of power coefficients (ABC) = 412 × (300/1000) 1.6 + 412 × (250/1000) 1.6 + 412 × (250/1000) 1.6 = 149
On the other hand, the power coefficient (D) of task D is
Power coefficient (D) = 412 × (300/1000) 1.6 = 10
Therefore, the ratio of the constraint time of the integrated task composed of tasks A, B, and C and the time distribution ratio of the constraint time of task D are as follows.
Ratio of constraint time of integrated task: Ratio of constraint time of task D = 149 1 / 1.6 : 10 1 / 1.6 = 22.8: 4.3 = 5.3: 1

  Here, since the constraint time of the reference task E of the task group is 600 ms, if 600 ms is allocated to the processing time of the integrated task and the task D at a ratio of 5.3: 1, 505 ms and 95 ms are obtained.

However, since the processor core 18n cannot process the processing amount of the task D at 95 ms, the processing time of the task D is reset to the minimum processing time of 100 ms that can process the task D. On the other hand, the processing time of the integrated task composed of tasks A, B, and C is set to 500 ms by subtracting the minimum processing time of 100 ms that can process task D from the constraint time of 600 ms of the reference task E. As a result, the re-time distribution ratio between the processing time of the integrated task composed of tasks A, B, and C and the processing time of task D is 5: 1.
FIG. 4B is a diagram showing the processing status of tasks A, B, and C after the processing time of the integrated task composed of tasks A, B, and C is allocated as described above. After the start of task E, task D is started 500 ms later. Tasks A, B, and C start simultaneously with task E, but the processing time is extended to 500 ms later.

5A, FIG. 5B, FIG. 5C, FIG. 5D, and FIG. 5E show an example in which operation op2 is performed on a task group composed of tasks having a more complicated relationship. FIG. 5A shows a dependency graph of tasks from task A to task I forming the same task group. According to the dependency graph of FIG. 5A, the reference task is task I. Task A, task B, and task C are performed in parallel and are connected to task D. Task D is a serial task with task A, task B, and task C, and is connected to task E. Task F is a task connected to task G. From task A to E, tasks F and G are performed in parallel, and task E and task G are connected to task H. Task H is a serial task from task A to task G, and is connected to task J together with reference task I.
Therefore, operation op2-1 is performed, and the scheduler 11 extracts tasks A, B, and C as integrated tasks A-C that are tasks processed in parallel and connected to the same task D.
FIG. 5B shows that integrated task A-C is formed as a result of operation op2-1.
Therefore, for the tasks A, B, and C, the power consumption of the processor core 18n that executes each task is obtained by the equations (1) and (2).
Next, the total power for executing the integrated task composed of tasks A, B, and C is obtained from the equations (3) and (4).
Next, operation op2-2 is performed. As a result, the scheduler 11 extracts the integrated tasks A-C, D, and E as sequential tasks. Task F and task G are extracted as sequential tasks.
In FIG. 5C, as a result of performing the operation op2-2, the integrated task A-C, the task D, and the task E form a sequential task A-E, and similarly, the tasks F, G also form a sequential task FG. By the way.
Therefore, first, the task D and task E are integrated tasks of the operation op2-2, and the power consumption CS1 of the sequential task AE including the tasks AC, D, and E is expressed as follows from the equation (4). Become.
CS1 = B11 × T11 (1-q) + B12 × T12 (1-q) + B13 × T13 (1-q)
B11 × T11 (1-q) is the total power of integrated task A-C, B12 × T12 (1-q) is the total power of task D, and B13 × T13 (1-q) is the total power of task E. is there. T11 is a processing time common to task A to task C, T12 is a processing time of task D, and T13 is a processing time of task E. B11, B12, and B13 are power coefficients of the respective tasks. Here, the processing time T1 of the entire sequential task A-E is T1 = T11 + T12 + T13.
Next, when T1 is reassigned in proportion to the power coefficient of each task to the 1 / qth power, from Equation (5) and Equation (6),
CS1 = T1 (1-q) (B11 (1 / q) + B12 (1 / q) + B13 (1 / q) ) q .
On the other hand, using task F and task G as an integrated task of operation op2-2, power consumption CS2 of sequential task FG composed of tasks F and G is as follows from equation (4).
CS2 = B21 × T21 (1-q) + B22 × T22 (1-q)
B21 × T21 (1-q) is the total power of the integrated task F, and B22 × T22 (1-q) is the total power of the task G. B21 and B22 are power coefficients of task F and task G, respectively. T21 is the processing time of task F, and T22 is the processing time of task D. Here, the processing time T2 of the entire sequential task FG is T2 = T21 + T22.
Similarly, when T2 is reassigned in proportion to the power coefficient of each task to the 1 / qth power, CS2 = T2 (1-q) (B21 (1 / q) + B22 from Expressions (5) and (6) (1 / q) ) q .
Next, operation op2-3 is performed. As a result, the scheduler 11 forms an integrated task of operation op2-3 from the sequential task AE composed of tasks AC, task D, and task E and the sequential task FG composed of tasks F and G. To do.
FIG. 5D shows that the scheduler 11 has formed the integrated task A-G from the sequential task AE and the sequential task FG as a result of performing the operation op2-3.
The total power of the integrated task A-G is as follows.
Total power of integrated task AG = CS1 + CS2 = T1 (1-q) (B11 (1 / q) + B12 (1 / q) + B13 (1 / q) ) q + T2 (1-q) (B21 (1 / q ) + B22 (1 / q) ) q ------------------ (11) Here, let T (AG) be the longer of T1 and T2. Then, the total power of the integrated task A-G is as follows.
Total power of integrated task A-G = T (A-G) (1-q) × B (A-G) ―――― (12) Formula B (A-G) = (B11 (1 / q) + B12 (1 / q) + B13 (1 / q) ) q + (B21 (1 / q) + B22 (1 / q) ) q
FIG. 5E shows that the scheduler 11 forms a sequential task A-H from the integrated task A-G and the integrated task H.
The power consumption CS (A-H) of the sequential task formed from tasks A to H is as follows.
CS (A−H) = T (A−G) (1-q) × B (A−G) + TH (1-q) × B (H) ―――― (13) Therefore, the reference task I The processing time is assigned to each integrated task so that the following formula is satisfied.
T (A−G) : T H = B (A−G) (1 / q) : B (H) (1 / q) ―――― (14) As a result, CS (A−H) is as follows. become that way.
CS (A−H) = T standard × (B (A−G) (1 / q) + B (H) (1 / q) ) q ―――― (15)

The operation op3 will be further described with reference to FIG. In operation op3, the scheduler 11 checks the execution status of the reference task. If it is being executed, the scheduler 11 sets a value obtained by subtracting the execution time from the restriction time of the reference task as a new restriction time. Next, the processing time of each integrated task determined in operation op2 is corrected based on the re-time allocation ratio with respect to the new constraint time.
In operation op4, the scheduler 11 calculates the load factor by dividing the standard processing time of each task constituting the integrated task by the processing time assigned to the integrated task.
Next, the frog scheduler 11 previously holds a table shown in FIG. 6B, which will be described later. Based on the table shown in FIG. 6B, the frequency and power of the operation clock supplied from the load factor to the processor core 18n that executes each task. Determine the voltage. Next, the scheduler 11 transmits the determined operation clock frequency and power supply voltage of each processor core 18 n to the frequency control circuit 14 and the power supply voltage control circuit 15. The frequency control circuit 14 and the power supply voltage control circuit 15 supply the operation clock having the frequency determined by the scheduler 11 and the power supply voltage having the determined voltage to each processor core 18n, and the operation of each processor core 18n. To control.

  FIG. 6 is a diagram for explaining a specific example of the operation op4 for the task group. FIG. 6A shows the standard processing time of tasks A, B, C, and D related to the task group shown in FIGS. 4A and 4B, the processing time allocated to the integration task, and the standard processing time and the allocation task. The table showing the load factor calculated | required from processing time is shown. The standard processing times for tasks A, B, C, and D are 300 ms, 250 ms, 250 ms, and 100 ms. On the other hand, the processing time allocated to the integrated task is 500 ms for tasks A, B, and C, and 100 ms for task D. As a result, the load factor of task A is 0.6, the load factor of task B is 0.5, the load factor of task C is 0.5, and the load factor of task D is 1.0.

  FIG. 6B is a table showing the frequency of the operation clock, the power supply voltage, and the power consumption with respect to the load factor of the processor core 18n. The load factor is described in increments of 0.1 from 1 to 0.2. The frequency of the operation clock is 1000 Mhz when a task with a load factor of 1.0 is executed. Hereinafter, every time the load factor decreases by 0.1, the frequency of the operation clock decreases by 100 Mhz. When the load factor decreases from 1.0 to 0.2, the power supply voltage is 1.2V, 1.2V, 1.15V, 1.1V, 1.05V, 1.0V, 0.95V, 0.85V, It decreases to 0.75V. The power consumption decreases to 412 mW, 412 mw, 303 mW, 242 mW, 190 mW, 144 mW, 104 mW, 63 mW, and 32 mW. The scheduler 11 stores the table of FIG. 5B in advance, and determines the frequency and power supply voltage of the operating clock of the processor core 18n that executes the task based on the calculated load factor for each task.

Furthermore, a specific example of the operation op4 for the task groups shown in FIGS. 5A to 5E will be described. The scheduler 11 determines T (A−G) and T H so that the expression (14) is satisfied and T reference = T (A−G) + T H, and the processing time for the integrated task A−G Allocate T (AG) . Next, the scheduler 11 assigns processing times T1 and T2 to the sequential tasks AE and sequential tasks FG so that T2 = T1 = T (AG) . Next, the scheduler 11 allocates processing times T21 and T22 so that T2 = T21 + T22 and T21: T22 = B21 (1 / q) : B22 (1 / q) . Next, the scheduler 11 has processing times T11, T12, T13 so that T1 = T11 + T12 + T13 and T11: T12: T13 = B11 (1 / q) : B12 (1 / q) : B13 (1 / q). Is allocated. That is, after a sequential task that is executed in parallel with the reference task I is formed, the processing time of each task is determined by going back to the integrated task that forms the sequential task.
Next, the scheduler 11 divides the standard processing time of the tasks A, B, and C by T11, calculates the load factor, and uses the table of FIG. 6B to determine the operation clock to be supplied to the processor core that executes the tasks A, B, and C. Determine the frequency and power supply voltage. Next, the load rates of tasks D and E are obtained by dividing the standard processing times of tasks D and E by T12 and T13. Next, the operation clock and power supply voltage supplied to the processor core that executes tasks D and E are obtained from the table of FIG. 6B. Next, the standard processing times of tasks F and G are divided by T21 and T22, and the load factors of tasks F and G are obtained. Next, from the table in FIG. 6B, the frequency and power supply voltage of the operation clock supplied to the processor core that executes the tasks F and G are obtained. Then, the standard processing time of the task H, divided by T H, determine the load factor of tasks H. Next, the frequency and power supply voltage of the operation clock supplied to the processor core executing the task H are obtained from the table of FIG. 6B.

From the above, the processor core of Example 1 is
A plurality of processor cores (processor core 18n) for processing a plurality of tasks in parallel;
For each task, an identification number that identifies the associated first task group (tasks A, B, C, D, E), and the task processing time required to process the task (standard of tasks A, B, C) Processing time), and registers (reference task information memory 12, task information memory 13) for storing an upper limit period (task E constraint time) for executing tasks included in the first task group,
Among the tasks included in the first task group, a second task group (task A, task A, B, C) that is processed in parallel and includes a plurality of tasks connected to the same task (task D). B, C) is extracted, and the longest task processing time among the task processing times of the plurality of tasks is defined as the first processing time (standard processing time of task A) for processing the second task group. A setting circuit for setting a second processing time (Tm in operation op2-4) of the second task group occupying the upper limit period according to the power consumption and the first processing time of the processor core that processes the two task groups;
Depending on the ratio between the first processing time and the second processing time (the load factor of the operation op4), the frequency of the operation clock supplied to the processor core that processes the second task group or the power supply voltage (the operation frequency of FIG. 5B, A drive circuit (scheduler 11) for reducing the power supply voltage);
Is a multi-core processor.
According to the multi-core processor, the processing time of the processor core that processes the second task group is extended according to the power consumption.
As a result, the second task group requiring a large amount of power consumption, the second processing time occupying during the upper limit period becomes long, and the power consumption of the processor core executing the second task group is greatly reduced. This has the effect of reducing power consumption.

The features of the present invention are described below.
(Appendix 1)
Multiple processor cores that process multiple tasks in parallel;
Task processing necessary for the processor core to process the task by receiving an identification number for identifying the associated first task group and a predetermined operating clock frequency or power supply voltage for each task. A register for storing time and an upper limit period for executing the task included in the first task group;
A second task group consisting of a plurality of tasks connected to the same task among the tasks included in the first task group is extracted, and the plurality of the tasks are Among the task processing times, the longest task processing time is defined as a first processing time for processing the second task group, and the power consumption of the processor core for processing the second task group and the first processing time are determined. A setting circuit for setting a second processing time for executing the second task group occupying during the upper limit period;
Depending on the ratio between the task processing time and the second processing time, the frequency or power supply voltage of the operation clock supplied to the processor core that processes each task is set to the predetermined frequency or power supply voltage of the operation clock. A drive circuit to be changed from
A multi-core processor comprising:
(Appendix 2)
The setting circuit further specifies, for the tasks included in the first task group, a serial task to be executed in series with respect to the tasks including the second task group, and the task processing time of the serial task And a third processing time for executing the serial task that occupies during the upper limit period according to the power consumption of the processor core that processes the serial task,
The drive circuit further sets a frequency or a power supply voltage of an operation clock supplied to the processor core that processes the serial task according to a ratio between the task processing time of the serial mask and the third processing time. The multi-core processor according to appendix 1, wherein the multi-core processor is lowered below a predetermined operating clock frequency or power supply voltage.
(Appendix 3)
The processor that processes the serial task, wherein A2 is the power consumption of the processor core that processes the second task group, T2 is the second processing time, and B2 is a proportional coefficient between A2 and T2 (1-q). When the power consumption of the core is A3, the task processing time of the serial task is T3, and the proportionality coefficient between A3 and T3 (1-q) is B3, the setting circuit is B2 (1 / q) : B3 ( 1 / q) = T2: The multi-core processor according to appendix 2, wherein T3 is set.
(Appendix 4)
Multiple processor cores that process multiple tasks in parallel;
Task processing necessary for the processor core to process the task by receiving an identification number for identifying the associated first task group and a predetermined operating clock frequency or power supply voltage for each task. A control method of the multi-core processor, comprising: a time and a register that stores an upper limit period for executing the task included in the first task group,
Extracting a second task group consisting of a plurality of the tasks connected to the same task among the tasks included in the first task group, the tasks being processed in parallel;
Among the task processing times of the plurality of tasks, the longest task processing time is defined as a first processing time for processing the second task group, and power consumption of the processor core for processing the second task group and Setting the second processing time for executing the second task group occupying during the upper limit period according to the first processing time;
Depending on the ratio between the task processing time and the second processing time, the frequency or power supply voltage of the operation clock supplied to the processor core that processes each task is set to the predetermined frequency or power supply voltage of the operation clock. The process of changing from
A control method for a multi-core processor, comprising:
(Appendix 5)
For the tasks included in the first task group, identifying a serial task that is executed in series with respect to the tasks included in the second task group;
Setting a third processing time to execute the serial task during the upper limit period according to the task processing time of the serial task and the power consumption of the processor core that processes the serial task;
Depending on the ratio of the task processing time and the third processing time of the serial mask, the frequency of the operation clock or the power supply voltage supplied to the processor core that processes the serial task is the frequency of the predetermined operation clock. Or a step of lowering the power supply voltage,
The control method of the multi-core processor according to appendix 4, further comprising:
(Appendix 6)
Multiple processor cores that process multiple tasks in parallel;
Task processing necessary for the processor core to process the task by receiving an identification number for identifying the associated first task group and a predetermined operating clock frequency or power supply voltage for each task. A control method of the multi-core processor, comprising: a time and a register that stores an upper limit period for executing the task included in the first task group,
Extracting a second task group consisting of a plurality of the tasks connected to the same task among the tasks included in the first task group, the tasks being processed in parallel;
Identifying a serial task to be executed in series with respect to the tasks included in the second task group, for the tasks included in the first task group;
The processor that processes the serial task, wherein A2 is the power consumption of the processor core that processes the second task group, T2 is the second processing time, and B2 is a proportional coefficient between A2 and T2 (1-q). When the power consumption of the core is A3, the task processing time of the series task is T3, and the proportionality coefficient between A2 and T2 (1-q) is B2, the setting circuit is B2 (1 / q) : B3 ( 1 / q) = T2: setting T3;
Depending on the ratio between the task processing time and the second processing time, the frequency or power supply voltage of the operation clock supplied to the processor core that processes each task is set to the predetermined frequency or power supply voltage of the operation clock. The frequency or power supply voltage of the operation clock supplied to the processor core that processes the serial task is determined in advance according to the ratio between the task processing time of the serial mask and the third processing time. Changing the operation clock frequency or power supply voltage,
A control method for a multi-core processor, comprising:

  According to the present invention, since the power consumption of the processor core is greatly reduced, it is possible to provide a multi-core processor with a large reduction in power consumption.

10 multi-core processor 11 scheduler 12 reference task information memory 13 task information memory 14 frequency control circuit 15 power supply voltage control circuit 19 bus 20 flowchart 181-18n processor core

Claims (2)

  1. Multiple processor cores that process multiple tasks in parallel;
    Task processing necessary for the processor core to process the task by receiving an identification number for identifying the associated first task group and a predetermined operating clock frequency or power supply voltage for each task. A register for storing time and an upper limit period for executing the task included in the first task group;
    A second task group consisting of a plurality of tasks connected to the same task among the tasks included in the first task group is extracted, and the plurality of the tasks are Among the task processing times, the longest task processing time is defined as a first processing time for processing the second task group, and the power consumption of the processor core for processing the second task group and the first processing time are determined. A second processing time for executing the second task group occupying the upper limit period is set, and the tasks included in the first task group are executed in series with the tasks including the second task group A serial task to be processed, and the serial task occupying the upper limit period according to the task processing time of the serial task and the power consumption of the processor core that processes the serial task. A setting circuit for setting the third processing time to perform a task,
    Depending on the ratio between the task processing time and the second processing time, the frequency or power supply voltage of the operating clock supplied to the processor core that processes each task is set to the predetermined operating clock of the processor core. The frequency or power supply voltage of the operation clock supplied to the processor core that processes the serial task is changed according to the ratio between the task processing time of the serial mask and the third processing time. A drive circuit for lowering the frequency of the predetermined operation clock or a power supply voltage ;
    The proportional coefficient is A, the proportional coefficient is B, the index representing the frequency dependence of the power consumption of the operation clock is q, the power consumption of the processor core is P, and the frequency of the operation clock supplied to the processor core Is F, the power consumption P is calculated by the formula A × F q + B ,
    The processor that processes the serial task , wherein A2 is the power consumption of the processor core that processes the second task group, T2 is the second processing time, and B2 is a proportional coefficient between A2 and T2 (1-q). The power consumption of the core is A3, the third processing time is T3, the number T3 (1-q) expressed using q in the formula A × F q + B, the A3 and the T3 (1-q) , When the proportionality factor and B3, the setting circuit, B2 (1 / q): B3 (1 / q) = T2: multicore processor, characterized in that you set the T3.
  2. Multiple processor cores that process multiple tasks in parallel;
    Task processing necessary for the processor core to process the task by receiving an identification number for identifying the associated first task group and a predetermined operating clock frequency or power supply voltage for each task. A control method of the multi-core processor, comprising: a time and a register that stores an upper limit period for executing the task included in the first task group,
    Extracting a second task group consisting of a plurality of the tasks connected to the same task among the tasks included in the first task group, the tasks being processed in parallel;
    Among the task processing times of the plurality of tasks, the longest task processing time is defined as a first processing time for processing the second task group, and power consumption of the processor core for processing the second task group and Setting the second processing time for executing the second task group occupying during the upper limit period according to the first processing time;
    Depending on the ratio between the task processing time and the second processing time, the frequency or power supply voltage of the operation clock supplied to the processor core that processes each task is set to the predetermined frequency or power supply voltage of the operation clock. The process of changing from
    Identifying a serial task to be executed in series with respect to the tasks included in the second task group, for the tasks included in the first task group;
    According to the task processing time of the serial task and the power consumption of the processor core that processes the serial task, a third processing time for executing the serial task during the upper limit period is set as the second task group. The power consumption of the processor core for processing is A2, the second processing time is T2, and A2 and T2 (1-q) Is proportional to B2, the power consumption of the processor core for processing the serial task is A3, the third processing time is T3, and the calculation formula A × F q Number T3 expressed using q in + B (1-q) , A3 and T3 (1-q) If the proportionality coefficient is B3, 2 (1 / q) : B3 (1 / q) = T2: a step of setting T3;
    Depending on the ratio between the task processing time of the serial mask and the third processing time, the frequency or power supply voltage of the operating clock supplied to the processor core that processes the serial task is set to the predetermined operating clock. Changing from frequency or power supply voltage;
    The proportional coefficient is A, the proportional coefficient is B, the index representing the frequency dependence of the power consumption of the operation clock is q, the power consumption of the processor core is P, and the frequency of the operation clock supplied to the processor core Is F, the power consumption P is calculated as A × F q A control method of a multi-core processor characterized by being calculated by + B.
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