JP5290526B2 - Switching power supply circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that abnormal noise occurs from a transformer at the time of shift from thinning oscillation to regular oscillation when thinning oscillation is performed at the time of a light load since shift between thinning oscillation and regular oscillation periodically occurs and the period becomes an audio range band. <P>SOLUTION: Since mask time MT is increased by increase time PT when thinning oscillation is started in a switching power supply, a periodical change in thinning oscillation and regular oscillation is suppressed. Abnormal noise hardly occurs from the transformer at the time of shift from thinning oscillation to regular oscillation. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

  The present invention relates to a switching power supply circuit, and more particularly to a switching power supply circuit having a function of suppressing switching loss when load power is reduced.

  Many types of electronic devices require a stable DC voltage, and for this reason, switching power supplies using a transformer are widely used.

  That is, the switching power supply receives a DC voltage rectified and smoothed from commercial AC on the primary side of the transformer, and is converted into an intermittent primary current by the switching element. Then, on the secondary side of the transformer, the secondary current is rectified and smoothed to a DC voltage lower than the commercial AC voltage. Thus, the switching power supply using a transformer can supply a stable low-voltage DC voltage while being electrically insulated from commercial AC.

  Here, if the switching element is forcibly turned on and off at any time, switching noise and switching loss increase. In order to solve such a problem, for example, the switching element is controlled to be turned on when capacitors are connected in parallel and the oscillating voltage generated at both ends of the capacitor is a minimum value.

  By the way, the switching power supply is designed so that the power conversion efficiency is maximized at the rated power consumption of the electronic device. For this reason, for example, when the electronic device has been in a standby state for a long time, the oscillation frequency of the transformer becomes high and the switching loss increases and the power conversion efficiency decreases when the load is light.

  FIG. 5: shows the flowchart for demonstrating the function which suppresses the switching loss at the time of light load about the switching power supply which concerns on a prior art. FIG. 6 shows waveform diagrams of the oscillating voltage Vds, the edge detection signal EG, the mask time MT, the trigger signal TG, and the source / drain signal Ids.

  First, the case of rated power consumption will be described.

  The vibration voltage detection circuit 141 detects the vibration voltage Vds of the capacitor connected in parallel with the switching element or a voltage equivalent thereto, and outputs it to the edge detection circuit 142. The edge detection circuit 142 outputs the edge detection signal EG to the trigger circuit 140 at the timing when the oscillating voltage Vds becomes the minimum value or when it is assumed that the oscillating voltage Vds becomes the minimum value. When the edge detection signal EG is input, the trigger circuit 140 outputs the trigger signal TG to the oscillator 126. When the trigger signal TG is input, the oscillator 126 outputs a narrow pulse to the set end S of the flip-flop 170.

  The flip-flop 170 is set to H when the input to the set end S falls. When H is input from the output terminal Q, the drive circuit 172 controls the switching element SW to be turned on so that the source / drain current Ids flows.

  When the source / drain current Ids becomes an overcurrent, the overcurrent detection circuit 132 or the error amplifier (not shown) outputs H to the reset terminal R of the flip-flop 170. At this time, the flip-flop 170 is set to L, and the drive circuit 172 turns off the switching element SW and stops the flow of the source / drain current Ids.

  Next, the light load will be described.

  When the light load detection circuit 150 detects a light load, the light load detection circuit 150 outputs H to the gate control circuit 144. The gate control circuit 144 receives this output and commands the gate circuit 140 for a mask time MT of a certain time. At this time, when the mask time MT is commanded, the gate circuit 140 thins out the trigger signal TG to eliminate the oscillation frequency.

  With this method, the switching power supply suppresses the oscillation frequency of the transformer at a light load, and the power conversion efficiency is improved.

Examples of related technical literatures include the following patent literatures.
JP-A-4-217865 JP 2001-245471 A JP 2001-268907 A

  However, when tooth loss oscillation is performed, there is a case where an unusual noise such as zy is generated from the transformer at the time of transition between tooth loss oscillation and normal oscillation. This is due to the fact that the transition between tooth loss oscillation and normal oscillation occurred periodically, and this cycle was in the audible frequency band.

In view of the above, the switching power supply circuit according to the present invention converts the current induced on the secondary side of the transformer into a DC voltage by rectifying and smoothing the switching element that sends current to the primary side of the transformer in response to the trigger signal. The trigger signal is thinned out so as not to be supplied to the switching element in a periodic mask time, and the mask time varies depending on whether the trigger signal is thinned , It increases when the trigger signal is thinned out .

  In the switching power supply according to the present invention, the periodical oscillation and the normal oscillation are prevented from periodically changing in a short period, and an abnormal noise such as zy is generated from the transformer at the time of the transition between the periodical oscillation and the normal oscillation. It becomes difficult.

  Hereinafter, embodiments of a switching power supply according to the present invention will be specifically described with reference to the drawings.

[Overall configuration of switching power supply]
FIG. 1 shows the overall configuration of a switching power supply circuit. In the switching power supply circuit, when the input DCin is input to the primary side of the transformer T and the switching element SW is on / off controlled by the control circuit 20, a primary current flows to the primary side of the transformer T. The secondary side of the transformer is electrically insulated from the primary side, and a secondary current corresponding to the primary current flows. The secondary current is rectified and smoothed to obtain a desired DC voltage DCout. The input DCin is a DC voltage rectified and smoothed from commercial AC.

  Hereinafter, the entire configuration of the switching power supply circuit will be described in detail. First, the primary side of the transformer T will be described with reference to each input terminal of the control circuit 20.

  The control circuit 20 includes an EG input terminal, a Vcc input terminal, a VFB input terminal, an Isen input terminal, a COMP input terminal, and an OUT output terminal.

  The EG input terminal is connected to a connection point between the coil L3 and the resistor R2 via the resistor R10. The control circuit 20 detects the falling edge of the voltage generated in the coil L3 based on the input of the EG input terminal, and sends a pulse signal from the OUT output terminal to the gate of the switching element SW so as to be synchronized with this edge. Output. Here, the voltage of the coil L1 and the voltage of the coil L3 are synchronized. For this reason, the switching element SW is controlled so as to be turned on at the timing when the vibration voltage of the capacitor Cres is assumed to be a minimum value or the vibration voltage becomes a minimum value, and an excessive current generation is prevented.

  The Vcc input terminal is connected to the input DCin through the resistor R1. Here, between the connection of the resistor R1 and the Vcc input terminal, the capacitors C1 and C2 are respectively connected to the ground. Further, at the connection point between the capacitors C1 and C2, it is connected to the ground via the diode D1, the resistor R2, and the primary coil L3. For this reason, the capacitors C1 and C2 are charged from the current supplied from the input DCin via the resistor R1 and the current supplied from the coil L3. Then, the control circuit 20 performs control so that the switching element SW is kept off during a period in which the voltage input to the Vcc input terminal is unstable.

  The VFB input terminal is connected to the ground via a resistor R9, and a voltage serving as a reference for determining whether the voltage input to the Vcc input terminal is rising is input.

  A voltage signal corresponding to the current flowing through the switching element SW is input to the Isen input terminal. That is, in the switching element SW, the capacitor Cres is connected in parallel between the source and the drain. Here, the capacitor Cres is charged when the switching element SW is turned off, and is discharged when the switching element SW is turned on. The capacitor Cres is connected to the ground via the current detection resistor Rsen, and a potential is input to the Isen input terminal based on the current flowing through the current detection resistor Rsen. In such a configuration, the control circuit 20 monitors whether or not an overcurrent flows through the switching element SW based on the voltage input to the Isen input terminal, and turns off the switching element SW when the overcurrent flows.

  The COMP input terminal is connected to the phototransistor PT of the photocoupler PC. Then, the control circuit 20 monitors whether a large voltage is generated on the secondary side of the transformer T based on the voltage input to the COMP input terminal, and turns off the switching element SW when the large voltage is generated.

  Subsequently, the secondary side of the transformer T will be described. The secondary side of the transformer T is electrically insulated from the secondary side of the transformer T. For this reason, a DC voltage can be stably output in a state electrically insulated from commercial AC.

  The transformer T has a secondary coil L2 having one end connected to the anode of the diode D2 and the other end connected to the cathode of the diode D2 via the capacitor C5. Thereby, only the secondary current obtained in the output side coil L2 passes through the diode D2 to charge the capacitor C5. And the capacitor | condenser C5 produces a DC voltage at both ends, and this is output as output DCout.

  The capacitor C5 has a voltage detection circuit 136 connected to both ends. The voltage detection circuit 136 is connected to the photodiode PD of the photocoupler PC, and the difference between the secondary voltage of the transformer T and the target voltage value is input to the COMP input terminal and compared by the control circuit 20.

[Internal configuration of control circuit]
Next, the internal configuration of the control circuit 20 will be specifically described with reference to FIG.

  An oscillation voltage Vds based on the drain voltage of the switching element SW is input to the edge detection circuit 42 from the input terminal EG. The edge detection circuit 42 detects the falling edge of the oscillating voltage Vds and outputs an edge detection signal EG. Further, when the edge detection signal EG is input, the oscillator 26 outputs the signal to the set terminal S of the flip-flop 70 and the gate control circuit 44. Here, at the rated power consumption, the gate circuit 40 outputs the edge detection signal EG as it is as the trigger signal TG of the oscillator 26. However, when the oscillation frequency of the oscillator 26 increases, the gate control circuit 44 determines that the light load state is in effect and instructs the gate circuit 40 to set the mask time MT. The gate circuit 40 does not output the trigger signal TG during the mask time MT even if the edge detection signal EG is input.

  The voltage Vcc is input to the positive input terminal of the comparison circuit 22 from the Vcc terminal. Here, the low voltage Vst is input to the negative input terminal of the comparison circuit 22. For this reason, the comparison circuit 22 outputs L while the voltage Vcc falls below the low voltage Vst, and when the voltage Vcc exceeds the low voltage Vst, it determines that the voltage Vcc has risen reliably and outputs H. The output of the comparison circuit 22 is input to the reference voltage circuit 34 and the inverting input terminal of the NOR circuit 4. The reference voltage circuit 34 inputs the reference voltage Va to the positive input terminal of the comparison circuit 30 while H is supplied from the comparison circuit 22.

  The voltage VFB is input to the negative input terminal of the comparison circuit 30 from the VFB terminal. Here, the voltage VFB is the same voltage as the ground voltage. Therefore, when the reference voltage circuit 34 rises, the comparison circuit 30 outputs the H because the positive input terminal becomes higher than the negative input terminal. The output of the comparison circuit 30 is connected to the cathode of a Zener diode ZD whose anode is connected to the ground, and the output of the comparison circuit 30 is set to a voltage Vs that is the breakdown voltage of the Zener diode ZD. The voltage Vs is input to the negative input terminal of the comparison circuit 32.

  The voltage Isen based on the drain current of the switching element SW is input to the positive input terminal of the comparison circuit 32 from the Isen terminal. Here, the voltage Vs and the voltage Isen are set so that the comparison circuit 32 outputs H when the current of the switching element SW becomes an overcurrent.

  The output from the photocoupler PC is connected to the output of the comparison circuit 30 from the COMP terminal. Here, in the photocoupler PC, when a large voltage is generated in the secondary coil L2, the phototransistor is turned on and outputs L. For this reason, when a large voltage is generated in the secondary coil L2, L is input to the negative input of the comparison circuit 32.

  That is, the comparison circuit 32 is supplied with a signal from the COMP terminal as a negative input and a signal from the Isen terminal as a positive input. Therefore, the higher the output voltage on the secondary side of the transformer T and the larger the current of the switching element SW, the higher the output of the comparison circuit 32 becomes. The output of the comparison circuit 32 is input to the reset terminal R of the flip-flop 70.

  The flip-flop 70 is set to H when the input to the set terminal S falls, and is set to L when the input to the reset terminal R rises. The output of the inverted Q output terminal of the flip-flop 70 is input to the NOR circuit 24.

  The drive circuit 72 changes the output of the NOR circuit 24 to an output with sufficient current capability and outputs it to the gate of the switching element SW.

[Operation of switching element]
With this configuration, the switching element SW operates as follows.

  First, until the voltage Vcc rises, L is output from the comparison circuit 22 and the output of the NOR circuit 24 is fixed to L, so that the switching element SW is turned off.

  On the other hand, when the voltage Vcc rises completely, H is output from the comparison circuit 22, which is inverted and L is input to the inverting input terminal of the NOR circuit 24.

  In this state, when a pulse is output from the oscillator 26 and its falling edge is input, the flip-flop 70 is set to L, whereby the output of the NOR circuit 24 becomes H. Due to the output H of the NOR circuit 24, H is supplied from the drive circuit 72 to the gate of the switching element SW, the switching element SW is turned on, and a current flows through the coil L1.

  Also, this current increases the voltage at the Isen terminal and decreases the voltage at the COMP terminal, and when the output of the comparator 32 rises, the flip-flop 70 is set to H and the output of the NOR circuit 24 becomes L, The switching element SW is turned off.

  Here, at a light load, since the current supplied to the coil L2 is reduced, the change of the current flowing to the coil L1 is accelerated, the switching of the switching element SW is accelerated, and the switching loss is increased.

  Therefore, when the frequency of the oscillator 26 becomes higher than a predetermined value, the gate control circuit 44 determines that the load is light, commands a mask time for closing the gate circuit 40, and prevents the edge detection signal from being input to the oscillator 26. To do.

  At this time, conventionally, since the mask time is a fixed time, a pulse output having an audible frequency band is generated at the output of the oscillator 26. For this reason, the transition between tooth loss oscillation and normal oscillation occurs periodically in the audible frequency band, and there is a case where an abnormal noise such as zy is generated from the transformer.

  In this regard, in the present invention, since the mask time is changed according to a predetermined rule, the occurrence of abnormal noise is suppressed. Hereinafter, the mask time change rule will be described in detail with reference to waveform diagrams.

[Change in mask time]
In the present invention, in order to prevent the generation of abnormal noise, the gate control circuit 44 operates so that the mask time changes at the time of transition between the tooth loss oscillation and the normal oscillation. In other words, when the trigger signal is input at the mask time and the missing tooth oscillation starts, the mask time is increased, and a state in which the missing tooth oscillation is easily forcibly continued is created. On the other hand, when the trigger signal is not input during the mask time and the shift from the tooth loss oscillation to the normal oscillation is performed, the mask time is controlled to return to the initial value.

  Hereinafter, the change in the mask time will be specifically described with reference to the waveform diagrams of the respective parts in FIGS. 1 and 2. In the following description, it is assumed that the light load state continues and the gate control circuit 44 continues to instruct the gate circuit 40 for the mask time.

  FIG. 3 shows the oscillating voltage Vds, the edge detection signal EG, the mask time MT, the trigger signal TG, and the source / drain current Ids at the time of transition from normal oscillation to tooth loss oscillation.

  When the vibration voltage Vds of the capacitor Cres reaches a minimum value, the edge detection circuit 42 outputs an edge detection signal EG at that timing.

  When the edge detection signal EG is input to the gate circuit 40 at the mask time MT, the edge detection signal EG is thinned out and the trigger signal TG is output from the gate circuit 40 to the oscillator 26. Then, the drain current Ids flows through the switching element SW according to the trigger signal TG.

  Here, in the present invention, when the edge detection signal EG is input within the mask time MT, the gate circuit 40 is instructed by the gate control circuit 44 to add the increase time PT to the mask time MT. As a result, the trigger detection signal TG input next is easily thinned out by the increase time PT, and is suppressed so as not to switch from the tooth loss oscillation to the normal oscillation in a short time.

  On the other hand, FIG. 4 shows the oscillating voltage Vds, the edge detection signal EG, the mask time MT, the trigger signal TG, and the source / drain current Ids at the time of transition from the tooth loss oscillation to the normal oscillation.

  In the present invention, the gate circuit 40 eliminates the increase time MT from the gate control circuit 44 when the edge detection signal EG is not input within the mask time MT in a state where the increase time is added to the mask time MT. Only the mask time MT is input. As a result, the possibility that the trigger detection signal TG is thinned out immediately after returning to the normal oscillation is reduced, and the normal oscillation is not switched to the toothless oscillation in a short time.

  As described above, in the present invention, when the edge detection signal EG is not detected within the mask time MT, the quasi-resonant circuit is operated at the mask time MT of the initial setting value. If it is detected, an increase time PT is added to the mask time MT, so that a situation in which oscillation is easily lost is surely created. For this reason, periodical oscillation and normal oscillation are prevented from periodically changing in a short period of time, and an audible noise from the transformer is less likely to occur at the time of transition between the missing oscillation and normal oscillation.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

  For example, in the above-described embodiment, the mask time MT is changed by adding the increase time PT at the time of tooth loss oscillation. However, the present invention is not limited to this. For example, two types of mask time MT are set, and control may be performed so as to be switched between tooth loss oscillation and normal oscillation.

  Further, in the above embodiment, when the tooth loss oscillation starts, the gate control circuit 44 increases the mask time MT to be commanded next. However, the present invention is not limited to this. For example, the mask time PT may be increased after commanding the mask time MT a predetermined number of times.

  In the above embodiment, the VFB terminal is provided. However, the present invention is not limited to this, and the same applies to a configuration in which the VFB terminal is not provided.

  In the above embodiment, the capacitor Cres is connected in parallel with the switching element SW. However, the present invention is not limited to this, and the capacitor Cres is similarly applied even if one end is connected to the connection point between the primary coil L1 and the switching element SW and the other end is connected to the ground.

1 shows an overall configuration of a switching power supply circuit according to the present invention. 1 shows a control circuit for a switching power supply according to the present invention. The wave form diagram of the switching power supply which concerns on this invention is shown. The wave form diagram of the switching power supply which concerns on this invention is shown. The flowchart of the switching power supply circuit which concerns on a prior art is shown. The wave form diagram of the switching power supply circuit which concerns on a prior art is shown.

Explanation of symbols

20 control circuit 22, 30, 32 comparison circuit 24 NOR circuit 26 oscillator 34 reference voltage circuit 40 gate circuit 42 edge detection circuit 44 gate control circuit 70 flip-flop 72 drive circuit SW switching element

Claims (4)

A switching element for passing a current to the primary side of the transformer in response to the trigger signal;
An output circuit that rectifies and smoothes the current induced on the secondary side of the transformer and converts the current into a DC voltage;
The trigger signal is thinned out so as not to be supplied to the switching element in a periodic mask time,
The switching power supply circuit according to claim 1, wherein the mask time varies depending on whether or not the trigger signal is thinned out, and increases when the trigger signal is thinned out . A switching element for passing a current to the primary side of the transformer in response to the trigger signal;
An output circuit that rectifies and smoothes the current induced on the secondary side of the transformer and converts the current into a DC voltage;
The trigger signal is thinned out so as not to be supplied to the switching element in a periodic mask time,
The switching power supply circuit according to claim 1, wherein the mask time changes depending on whether or not the trigger signal is thinned out, and decreases unless the trigger signal is thinned out . A switching element for passing a current to the primary side of the transformer in response to the trigger signal;
An output circuit that rectifies and smoothes the current induced on the secondary side of the transformer and converts the current into a DC voltage;
The trigger signal is thinned out so as not to be supplied to the switching element in a periodic mask time,
The switching power supply circuit according to claim 1, wherein the mask time varies depending on whether or not the trigger signal is thinned out, increases when the trigger signal is thinned out, and decreases when the trigger signal is not thinned out . A switching element for passing a current to the primary side of the transformer in response to the trigger signal;
An output circuit that rectifies and smoothes the current induced on the secondary side of the transformer and converts the current into a DC voltage;
The trigger signal is thinned out so as not to be supplied to the switching element in a periodic mask time,
The switching power supply circuit according to claim 1, wherein the mask time changes according to a degree of thinning out the trigger signal, and increases when the degree of thinning out the trigger signal increases, and decreases when the degree of thinning out the trigger signal decreases .