JP5288399B2 - Parameter extraction method and apparatus - Google Patents

Description

  The present invention relates to a parameter extraction method and apparatus for extracting parameters of an equivalent circuit model of a field effect transistor used in a power conversion circuit.

  The ratio of electric energy to the total energy consumption (electricity generation rate) is increasing year by year. Currently, the rate of electrification in Japan has reached 40% and is expected to increase further in the future. In order to effectively use limited resources, it is a major issue to improve the efficiency of a power conversion circuit that performs electric energy conversion and control technology. In addition, with the advent of the ubiquitous society, further miniaturization is desired in power conversion circuits used in information devices such as personal computers and mobile phones.

  Under such circumstances, field effect transistors (hereinafter referred to as FETs) used in power conversion circuits have become more important than ever. Since the FET is a unipolar element, it can operate at high speed, and the power conversion circuit can be expected to be downsized. As the types of FET, metal-oxide film-semiconductor field effect transistor (hereinafter referred to as MOSFET), metal-insulating film-semiconductor field effect transistor (hereinafter referred to as MISFET), metal-semiconductor field effect transistor (hereinafter referred to as MESFET), high Examples thereof include an electron mobility transistor (hereinafter referred to as HEMT) and an electrostatic induction transistor (hereinafter referred to as SIT).

  Among FETs used in power conversion circuits (hereinafter referred to as power FETs), the most commonly used at present is Si-MOSFETs using Si as a semiconductor material. However, since this conventional MOSFET has a problem of high on-resistance, the application range of the power FET is limited.

  In recent years, new element structures such as a super junction MOSFET that solve this problem have been developed, and the application range of power FETs has been expanded. Also, research on FETs using SiC, III-V nitride semiconductors, II-VI group oxide semiconductors, and wide band gap materials such as diamond, which have superior physical properties compared to conventionally used Si, has advanced. In the future, the application range of power FETs is expected to further widen.

  In order to fabricate a small and highly efficient power conversion circuit using these power FETs, the switching frequency, the input / output filter for waveform shaping, the heat sink for heat dissipation, and the like are used. It is necessary to design comprehensively in consideration of capacitance and parasitic inductance. In the prior art, an optimum design method is generally performed by repeating trial production and evaluation while relying on developer know-how. However, such a method requires a great deal of effort to develop a power conversion circuit. In addition, accurate evaluation by actual measurement of the power conversion circuit requires technology to accurately measure voltage and current waveforms, but the voltage and current measurement probes themselves affect the waveforms, and the rise time constant of the probes. In general, this is a difficult problem due to the fact that higher-speed waveforms cannot be measured.

  In order to solve such a problem and perform a quick optimum design, it is effective to use a circuit simulation technique. In producing a power conversion circuit, the number of prototypes can be reduced by predicting the result by circuit simulation in advance, so that a significant reduction in development period and development cost can be expected.

  In order to perform circuit simulation of the power conversion circuit, it is indispensable to represent the power FET by an equivalent circuit model. An equivalent circuit model is a circuit model that artificially represents the operating characteristics of an FET using parameters that can be computed by a computer. FIG. 1 shows an equivalent circuit model of a general power FET that has been widely used. This equivalent circuit model includes 4 gate-source capacitance (hereinafter Cgs), gate-drain capacitance (hereinafter Cgd), drain-source capacitance (hereinafter Cds), and channel current source (hereinafter Ich). It consists of two parameters.

  Equivalent circuit models are roughly classified into two types, that is, physical models and experimental models, depending on the description method of these parameters. The parameters in the physical model are described as equations based on the semiconductor physical properties and device dimensions. The feature of the physical model is that it can cope with changes in the dimensions of the device and variations in doping concentration. However, when the device structures are different, such as MOSFET, MISFET, MESFET, HEMT, and SIT, it is necessary to newly derive equations. In addition, it is difficult to completely reproduce the characteristics of an actual power FET using the physical properties and element dimensions of the semiconductor, and the error between the simulation and the actual measurement value is large. An example of the physical model is BSIM3v3, and Non-Patent Document 1 is an example of application of this to circuit simulation of power FETs.

  On the other hand, the parameters in the experimental model are described as an appropriate approximate expression or table based on the values extracted by actual measurement. The feature of the experimental model is high versatility that can be applied to all kinds of FETs such as MOSFET, MISFET, MESFET, HEMT, and SIT as long as they are unipolar elements. In addition, since the actual measurement values are used as they are, the simulation accuracy is high and it is suitable for analog circuit simulation. Therefore, the experimental model is used in an analog high-frequency circuit such as a monolithic microwave integrated circuit using a GaAs FET, and an example is the Root model described in Non-Patent Document 2. However, the conventional parameter extraction method in the high-frequency experimental model needs to be performed by using S parameter measurement or the like in order to reproduce the direct current characteristic, the high frequency characteristic, and the noise characteristic. Requires know-how.

  Therefore, a parameter extraction method using an impedance measuring instrument is generally used as a conventional technique for extracting parameters such as Cgs, Cgd, and Cds in an experimental model of a power FET as a simpler technique. Non-patent document 3 describes a parameter extraction method using an impedance measuring instrument. As an example, FIG. 2 shows a schematic diagram of a Cgd parameter extraction apparatus using an impedance measuring instrument. First, an arbitrary gate-source voltage (hereinafter referred to as Vgs) and a drain-source voltage (hereinafter referred to as Vds) are applied to the power FET 1 to be extracted by the voltage source 3 and the voltage source 4. Cgd can be extracted by generating a minute high-frequency voltage from the impedance measuring instrument 2 and measuring the current response thereto.

  Also, the Cgs and Cds extraction device according to the prior art using an impedance measuring device differs from the Cgd extraction device in FIG. 2 in the configuration of the impedance measuring device, the high frequency cutoff reactor, and the DC cutoff capacitor. The basic extraction method is the same as the above Cgd extraction method.

Currently, most power FET data sheets on the market describe model parameters extracted by the prior art using this impedance measuring instrument. However, the circuit simulation method using the equivalent circuit model created using the parameters measured by the parameter extraction method according to the prior art has a large error from the actual measurement value.
Takao Nano et al., “Modeling and parameter extraction techniques for high voltage devices with BSIM3v3”, IEICE Technical Report Integrated Circuits Vol. 98 No. 352 p. 79-86, 1998 Hiroshi Kondo, “Development of HP Root Model: Proposal for Standard Problems”, Proceedings of the IEICE General Conference Electronics No. 1 p. 487, 1996 IEEJ Electrical Standards Committee Standard No. 2406, "MOS field effect power transistor", 2004

  As described above, in the equivalent circuit model of the power FET in the prior art, the accuracy of the model or the complexity of the parameter extraction method is a problem. An object of the present invention is to solve the above-mentioned problem by extracting high-accuracy parameters by a relatively simple method with respect to an equivalent circuit model belonging to an experimental model in a power FET, and obtaining an equivalent circuit obtained thereby. An object is to provide a circuit simulation technique using a circuit model.

  The parameter extraction method and apparatus of the present invention extract parameters of an equivalent circuit model of a field effect transistor used in a power conversion circuit. The equivalent circuit model includes parameters including a gate-source capacitance Cgs, a gate-drain capacitance Cgd, a drain-source capacitance Cds, and a channel current source Ich. An inductive load, a commutation diode, and a pulse voltage generator are connected to the field effect transistor to switch the field effect transistor, and the gate-source voltage Vgs, drain-source voltage Vds, drain The gate-source capacitance Cgs, the gate-drain capacitance Cgd, and the channel current source Ich are extracted from the switching waveform of the current Id and the output voltage Vgcc of the pulse voltage generator.

  Here, the switching waveform includes a gate-source voltage Vgs, a drain-source voltage Vds, a drain current Id, and a pulse during a period in which the field-effect transistor transitions from an on state to an off state or from an off state to an on state. It is a waveform of the output voltage Vgcc of a voltage generator.

  The gate-source capacitance Cgs, the gate-drain capacitance Cgd, and the channel current source Ich are extracted as follows using the switching waveform in the period of transition from the on state to the off state. First, the time t1 when the gate-source voltage Vgs stops decreasing and the drain-source voltage Vds starts increasing, the time t2 when the gate-source voltage Vgs and drain current Id start decreasing, and the gate-source voltage Vgs A time t3 when the output voltage Vgcc of the pulse voltage generator is reached, a period 1 from time t1 to t2, and a period 2 from time t2 to t3. The gate-source capacitance Cgs is extracted using the fact that the rate of decrease of the gate-source voltage Vgs in period 2 is regulated by the rate at which Cgs is charged and discharged by the gate current. The gate-drain capacitance Cgd is extracted by utilizing the fact that the rising speed of the drain-source voltage Vds in period 1 is regulated by the speed at which Cgd is charged and discharged by the gate current. The channel current source Ich is extracted as the value of the measured drain current Id at an arbitrary gate-source voltage Vgs and drain-source voltage Vds.

  Similarly, the gate-source capacitance Cgs, the gate-drain capacitance Cgd, and the channel current source Ich are extracted as follows using the switching waveform during the transition from the off state to the on state. The time t4 when the pulse voltage is output from the pulse voltage generator, the time t5 when the rise of the gate-source voltage Vgs stops and the drop of the drain-source voltage Vds starts, and the rise of the gate-source voltage Vgs starts and drain- Time t6 when the drop of the source voltage Vds stops, time 3 from time t4 to time t5, and time period 4 from time t5 to time t6. The gate-source capacitance Cgs is extracted using the fact that the rising speed of the gate-source voltage Vgs in period 3 is regulated by the speed at which Cgs is charged and discharged by the gate current. The gate-drain capacitance Cgd is extracted using the fact that the rate of decrease of the drain-source voltage Vds in period 4 is regulated by the rate at which Cgd is charged and discharged by the gate current. The channel current source Ich is extracted as the value of the measured drain current Id at an arbitrary gate-source voltage Vgs and drain-source voltage Vds.

ここで、Ｖｇｃｃはゲートに接続したパルス電圧発生器の出力電圧、Ｖｇｓはゲート−ソース間電圧、ｄＶｇｓ／ｄｔは単位時間当たりのＶｇｓの変化量、ｄＶｄｓ／ｄｔは単位時間当たりのＶｄｓの変化量、Ｒａは前記パルス電圧発生器とゲートの間に挿入した抵抗値、Ｃａはゲート−ソース間寄生容量、及びＣｂはゲート−ドレイン間寄生容量である。 The gate-source capacitance Cgs and the gate-drain capacitance Cgd are extracted based on the following equation (1).

Here, Vgcc is the output voltage of the pulse voltage generator connected to the gate, Vgs is the gate-source voltage, dVgs / dt is the amount of change in Vgs per unit time, and dVds / dt is the amount of change in Vds per unit time. , Ra is a resistance value inserted between the pulse voltage generator and the gate, Ca is a gate-source parasitic capacitance, and Cb is a gate-drain parasitic capacitance.

The gate-source capacitance Cgs and the gate-drain capacitance Cgd are extracted based on the following equation (2).

The gate-source capacitance Cgs is extracted based on the following equation (3).

The gate-drain capacitance Cgd is extracted based on the following equation (4).

  The parameter extraction method in the equivalent circuit model of the power FET according to the present invention has a feature that it is relatively simple and can obtain a highly accurate parameter, and by using the equivalent circuit model obtained thereby. An advantageous effect that a highly accurate circuit simulation can be performed is obtained.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a basic configuration of an equivalent circuit model of an FET generally used in the prior art. The equivalent circuit model of the power FET in the present invention also uses the configuration of the equivalent circuit model shown in FIG. There are four types of parameters in this equivalent circuit model: Cgs, Cgd, Cds, and Ich.

  A parameter extraction method for these parameters according to the present invention will be described. FIG. 3 is a schematic diagram of a parameter extraction apparatus according to the present invention. The FET for power 1 is an extraction target, and the inductive load 11 is an inductive load in switching. By generating a pulse voltage from the pulse voltage generator 13, the power FET 1 is switched from the on state to the off state, or from the off state to the on state.

  The parameter extraction according to the present invention can be performed using any switching waveform from the on state to the off state or from the off state to the on state. Here, a parameter extraction method using a switching waveform during a period of transition from an on state to an off state will be described. First, by adjusting the output voltage of the pulse voltage generator 13, a voltage higher than the threshold voltage is applied to the power FET 1 to turn it on. Then, an arbitrary load current IL is passed through the inductive load 11. Then, the pulse voltage generator 13 generates a pulse voltage equal to or lower than the threshold voltage, thereby switching the power FET 1 from the on state to the off state. As a result, the current path of the load current IL flowing through the power FET 1 is commutated to the commutation diode 14. By measuring the switching waveforms of Vgs, Vds, Id and the output voltage Vgcc of the pulse voltage generator 13 in the power FET 1 at this time by the voltmeter 17, the voltmeter 18, the ammeter 19, and the voltmeter 16, respectively. A switching waveform in the inductive load shown in FIG. 4 is obtained.

  Here, the switching waveform shown in FIG. 4 can be divided into a period 1 from time t1 to t2 and a period 2 from time t2 to t3. However, t1, t2, and t3 are the time when the gate-source voltage Vgs stops decreasing and the drain-source voltage Vds starts increasing, the gate-source voltage Vgs and the drain current Id start decreasing, And the time when the gate-source voltage Vgs reaches the output voltage from the pulse voltage generator connected to the gate.

  However, if the variable resistor 15 is too small, a surge voltage is generated in the Vds waveform due to resonance between the parasitic inductance of the measuring device and the output capacitance of the power FET 1, so that the accuracy of parameter extraction according to the present invention is reduced. To do. In such a case, the occurrence of resonance can be suppressed by adjusting the resistance value of the variable resistor 15. The value of the variable resistor 15 necessary for suppressing the occurrence of resonance varies depending on the characteristics of the power FET 1 to be extracted.

ここで、Ｖｇｃｃは電圧計１６により測定したパルス電圧発生器１３の出力電圧、Ｖｇｓは電圧計１７で測定したゲート−ソース間電圧、ｄＶｇｓ／ｄｔは電圧計１７で測定した単位時間当たりのＶｇｓの変化量、ｄＶｄｓ／ｄｔは電圧計１８で測定した単位時間当たりのＶｄｓの変化量、Ｒａは可変抵抗１５の抵抗値、Ｃａはパラメータ抽出装置の持つゲート−ソース間寄生容量２０の値、及びＣｂはパラメータ抽出装置の持つゲート−ドレイン間寄生容量２１の値である。上記（５）式における、左辺はゲート電流、及び右辺はＣｇｓ、Ｃｇｄ、Ｃａ、及びＣｂを流れる変位電流を表す。 According to the present invention, by using the switching waveform in the inductive load obtained as described above, the values of Cgs and Cgd can be extracted by the following method. First, in the switching period 1 and the period 2, the following relational expression is established, which is the basis for extracting Cgs and Cgd in the present invention.

Here, Vgcc is the output voltage of the pulse voltage generator 13 measured by the voltmeter 16, Vgs is the gate-source voltage measured by the voltmeter 17, and dVgs / dt is the Vgs per unit time measured by the voltmeter 17. The amount of change, dVds / dt is the amount of change in Vds per unit time measured by the voltmeter 18, Ra is the resistance value of the variable resistor 15, Ca is the value of the gate-source parasitic capacitance 20 of the parameter extraction device, and Cb Is the value of the gate-drain parasitic capacitance 21 of the parameter extraction device. In the above equation (5), the left side represents the gate current, and the right side represents the displacement current flowing through Cgs, Cgd, Ca, and Cb.

ここで、上記（６）における、Ｃｇｓに比べてＣｇｄが十分小さいという仮定は、一般的な電力用ＦＥＴにおいて成り立つ。 In the above equation (5), Ra, Ca, and Cb are known values unique to the extraction device, and therefore there are two unknowns, Cgs and Cgd. Therefore, by assuming either Cgs or Cgd, the other value can be extracted by the above equation (5). Here, as a more specific example, an extraction method when it is assumed that Cgd is sufficiently smaller than Cgs will be described. When it is assumed that Cgd is sufficiently smaller than Cgs, the above equation (5) is simplified as follows.

Here, the assumption that Cgd is sufficiently smaller than Cgs in (6) above holds true for a general power FET.

上記（７）式における、右辺第二項、右辺第三項、及び右辺第四項は、それぞれ期間２におけるＶｄｓの変化、装置のゲート−ソース間寄生容量２０、及び装置のゲート−ドレイン間寄生容量２１の影響を表す、補正項である。 Using the above equation (6), the value of Cgs is extracted from the switching waveform of period 2 in FIG. 4 by the following method. In period 2, the value of Vds is substantially constant, and the rate of decrease in the gate-source voltage Vgs is regulated by the rate at which Cgs is charged and discharged by the gate current. Therefore, Cgs can be extracted with high accuracy from the switching waveform in period 2 by the following equation obtained by modifying the above equation (6).

In the above equation (7), the second term on the right side, the third term on the right side, and the fourth term on the right side are the change in Vds, the gate-source parasitic capacitance 20 of the device, and the gate-drain parasitic of the device, respectively. This is a correction term representing the influence of the capacity 21.

  The value of Cgd included in the second term on the right side in the above equation (7) is, for example, a value extracted by the conventional technique using the impedance measuring device described with reference to FIG. 2, or the following equation (9) or ( The value extracted by equation (10) may be used.

上記（８）式によるＣｇｓの抽出は、上記（７）式に比べて、抽出精度は低下するが、Ｃｇｄが未知の条件においても、Ｃｇｓを抽出できる利点を持つ。 Further, when the influence of the second term on the right side is small, Cgs can be extracted by the following formula simplified by ignoring the second term on the right side in the above equation (7).

Extraction of Cgs by the above equation (8) has an advantage that it can extract Cgs even under a condition where Cgd is unknown, although the extraction accuracy is lower than that of the above equation (7).

上記（９）式における、右辺第二項、及び右辺第三項は、それぞれ期間１におけるＶｇｓの変化、及び装置のゲート−ドレイン間寄生容量２１の影響を表す、補正項である。 Next, the value of Cgd is extracted from the switching waveform of period 1 in FIG. 4 by the following method. In the period 1, the value of Vgs is substantially constant, and the rising speed of the drain-source voltage Vds is regulated by the speed at which Cgd is charged and discharged by the gate current. Therefore, Cgd can be extracted from the switching waveform in period 1 with high accuracy by the following equation obtained by modifying the above equation (6).

In the above equation (9), the second term on the right side and the third term on the right side are correction terms representing the change in Vgs in period 1 and the influence of the gate-drain parasitic capacitance 21 of the device, respectively.

  The value of Cgs included in the second term on the right side in the above equation (9) includes, for example, Cgs extracted by a conventional technique using an impedance measuring instrument, or Cgs extracted by the above equation (7) or (8). A value may be used.

上記（１０）式によるＣｇｄの抽出は、上記（９）式に比べて、抽出精度は低下するが、Ｃｇｓが未知の条件においても、Ｃｇｄを抽出できる利点を持つ。 Further, when the influence of the second term on the right side is small, Cgd can be extracted by the following formula simplified by ignoring the second term on the right side in the above formula (9).

Extraction of Cgd by the above equation (10) has an advantage that it can extract Cgd even under conditions where Cgs is unknown, although the extraction accuracy is lower than that of the above equation (9).

  Next, the value of Ich is extracted from the switching waveform shown in FIG. 4 by the following method. First, a switching waveform as shown in FIG. 4 is measured while gradually changing the value of the load current IL flowing through the inductive load 11. By plotting the relationship between Vgs and Vds in the switching waveform thus obtained, a graph as shown in FIG. 5 is obtained. By setting the value of the drain current Id measured by the ammeter 19 at each Vgs and Vds to be Ich, the value of Ich at any Vgs and Vds can be extracted.

  As described above, Cgs, Cgd, and Ich can be extracted from the switching waveform in the inductive load according to the present invention. The Cds extraction method in the present invention uses the conventional extraction method using an impedance measuring instrument.

  Further, the present invention has been described above using the switching waveform in the period in which the power FET shifts from the on state to the off state. Similarly, the parameter extraction according to the present invention can be performed by using the switching waveform in the period in which the power FET shifts from the off state to the on state.

  FIG. 6 is a schematic diagram of switching waveforms obtained by the parameter extraction device shown in FIG. 3 during a period in which the power FET 1 shifts from the off state to the on state. Here, the switching waveform shown in FIG. 6 includes a time t4 when the pulse voltage is output from the pulse voltage generator 13, a time t5 when the rise of the gate-source voltage Vgs stops and the drop of the drain-source voltage Vds starts. In addition, the period 3 from time t4 to t5 and the period 4 from time t5 to t6 are divided by setting the time t6 when the rise of the gate-source voltage Vgs starts and the decrease of the drain-source voltage Vds stops.

  The parameter extraction method according to the present invention using the switching waveform from the off state to the on state is the above-described method using the switching waveform from the on state to the off state. Can be executed by replacing period 3 with period 3.

  Here, the advantages of the parameter extraction method using the switching waveform due to the induced back load in the present invention will be described. The advantage of the parameter extraction method according to the present invention is that the parameter extraction of the parameter can be performed with high accuracy compared to the parameter extraction method using the impedance measuring instrument as the prior art. The reason why the extraction accuracy is improved is that an inductive load is used. By using the inductive load, parameter extraction of parameters can be performed in a state close to the operating conditions of the power FET in the actual power conversion circuit, and the extraction accuracy can be improved. That is, actual power conversion circuits often have inductive loads. For example, when an AC motor is driven using an inverter circuit which is a kind of power conversion circuit, an electromagnet in the AC motor becomes an inductive load. In addition, in a DC-DC converter which is a kind of power conversion circuit, an inductance used for an output stage low-pass filter becomes an inductive load.

  As described above, by using the inductive load, it is possible to extract the parameters of the parameters in a state close to the actual operating condition. By using the equivalent circuit model of the power FET obtained in this way, it is possible to perform a circuit simulation that can reproduce an actual waveform with high accuracy.

  In the following, as an embodiment of the present invention, an actual measurement value and a circuit simulation result in a power conversion circuit using a Si-MOSFET which is a kind of power FET are compared. First, Si-MOSFET parameter extraction was performed using the parameter extraction apparatus shown in FIG. The voltage source 12 in the parameter extracting device was set to 100V. The variable resistor 15 was 1.2 kΩ.

  FIG. 7 is an example of a switching waveform in the transition period from the on-state to the off-state in the Si-MOSFET, measured using the parameter extracting device shown in FIG. From this switching waveform, Cgs, Cgd, and Ich were extracted using the parameter extraction method according to the present invention described with reference to FIG. Cds was extracted by a method using an impedance measuring instrument which is a conventional technique. An equivalent circuit model having the configuration shown in FIG. 1 is created from Cgs, Cgd, Cds, and Ich obtained as described above, and this is used as an equivalent circuit model according to the present invention.

  For comparison, the extraction of Cgs and Cgd is extracted by a method using an impedance measuring device as a conventional technique, and the equivalent circuit model according to the present invention is replaced with Cgs and Cgd. Equivalent circuit model.

  A comparison of Cgd extracted by the present invention and the prior art is shown in FIG. Thus, the Cgd values extracted by the present invention and the prior art were different.

  The circuit simulation result using the equivalent circuit model created by the present invention and the prior art was compared with the actual measurement value in the power conversion circuit. Here, a step-down chopper, which is a kind of DC-DC converter, is used as the power conversion circuit. FIG. 9 shows a schematic diagram of a general step-down chopper. In the step-down chopper used in this experiment, the input voltage was 40 V, the output current was 4 A, and the gate resistance was 81Ω.

  FIG. 10 is a comparison of the actual measurement value of the turn-off waveform in the step-down chopper and the circuit simulation result according to the prior art. It can be seen that the rise of Vds in the circuit simulation result is faster than the actually measured value and the error is large.

  On the other hand, FIG. 11 is a comparison of actual measurement values and circuit simulation results according to the present invention. The measured value and the circuit simulation result almost overlap each other, and it can be seen that a good agreement is obtained as compared with the conventional technique shown in FIG.

  As described above, by using the present invention, circuit simulation in an actual power conversion circuit can be performed with high accuracy.

  In the following, as an example of the present invention, an actual measurement value and a circuit simulation result in a power conversion circuit using GaN-HMET which is a kind of power FET are compared. GaN is a wide band gap semiconductor called III-V nitride semiconductor.

  First, GaN-HEMT parameter extraction was performed using the parameter extraction apparatus shown in FIG. The voltage source 12 in the parameter extracting device was set to 45V. The variable resistor 15 was 9.8 kΩ. Cgs, Cgd, and Ich were extracted from the switching waveform measured using the parameter extraction apparatus of FIG. 3 by using the parameter extraction method according to the present invention described with reference to FIG. Cds was extracted by a method using an impedance measuring instrument which is a conventional technique. An equivalent circuit model having the configuration shown in FIG. 1 is created from Cgs, Cgd, Cds, and Ich obtained as described above, and this is used as an equivalent circuit model according to the present invention.

  For comparison, the extraction of Cgs and Cgd is extracted by a method using an impedance measuring device as a conventional technique, and the equivalent circuit model according to the present invention is replaced with Cgs and Cgd. Equivalent circuit model.

  A comparison of Cgd extracted by the present invention and the prior art is shown in FIG. Thus, the Cgd values extracted by the present invention and the prior art were different. Compared with the extraction result in the Si-MOSFET shown in FIG. 8, the magnitude relationship of Cgd extracted by the present invention and the prior art was reversed.

  The circuit simulation result using the equivalent circuit model created by the present invention and the prior art was compared with the actual measurement value in the power conversion circuit. Here, a step-down chopper is used as the power conversion circuit. The input voltage of the step-down chopper was 40 V, and the gate resistance and output current values were changed.

  FIG. 13 is a comparison of measured values, circuit simulation results according to the present invention, and circuit simulation results according to the prior art in switching loss when the gate resistance of the step-down chopper is 320Ω and the output current is changed. However, the switching loss in this specification is defined as the time integral of the multiplication of the Vds and Id waveforms at the turn-on and turn-off of the power FET. As can be seen from FIG. 13, the circuit simulation result according to the prior art has a large error from the actual measurement value, and the maximum error is 24%. On the other hand, the circuit simulation result according to the present invention has good consistency with the actually measured value, and the maximum error is as small as 6%.

  FIG. 14 shows the result of comparing the actual measurement value of switching loss and the circuit simulation result according to the present invention with greatly changing the gate resistance. Even when the gate resistance is changed, it can be seen that the circuit simulation result according to the present invention is in good agreement with the actually measured value. Moreover, even if the value of the output current is changed to 4A, 2A, and 1A, good agreement with the actually measured value is obtained. The maximum error of the circuit simulation result according to the present invention with respect to the actually measured value was as small as 6%.

  As described above, by using the present invention, circuit simulation in an actual power conversion circuit can be performed with high accuracy.

  In the present specification, the present invention has been described using the basic configuration of the equivalent circuit model of the power FET composed of Cgs, Cgd, Cds, and Ich shown in FIG. In addition to this basic configuration, the internal circuit is associated with the gate electrode, the internal resistance associated with the drain electrode, the internal resistance associated with the source electrode, and the gate electrode. The present invention can also be applied to the configuration of an equivalent circuit model to which parameters such as internal inductance, internal inductance associated with the drain electrode, and internal inductance associated with the source electrode are added.

  In this embodiment, the parameter extraction result and the circuit simulation result using Si-MOSFET and GaN-HEMT as the power FET are shown. However, the present invention can be applied to all other power FETs. It is. For example, the present invention can also be applied to power FETs such as MISFET, MESFET, and SIT, which have an element structure different from the MOSFET and HEMT introduced this time. In addition to Si and GaN, the present invention can also be applied to power FETs using semiconductor materials such as SiC compound semiconductors, III-V group nitride semiconductors, II-VI group oxide semiconductors, and diamonds. I can do it.

  In the present specification, the present invention has been described using an n-channel type power FET in which electrons carry current. However, the present invention also applies to a p-channel type power FET in which holes carry current. A parameter extraction method based on a switching waveform using a certain inductive load can be applied. When the present invention is applied to a p-channel power FET, the gate-source voltage Vgs rises with respect to the switching waveform in the n-channel power FET described with reference to FIGS. , And the descent relationship is reversed.

  In this embodiment, the step-down chopper is used as the power conversion circuit. However, the present invention can be applied to circuit simulation in all power conversion circuits using power FETs.

Schematic diagram of equivalent circuit model of power FET Schematic diagram of Cgd extraction device using impedance measuring device according to the prior art Schematic diagram of parameter extraction apparatus according to the present invention Schematic diagram of switching waveforms during the transition from on to off state used for parameter extraction Schematic diagram of switching waveforms used for Ich extraction Schematic diagram of switching waveform during transition from OFF state to ON state used for parameter extraction Measurement result of switching waveform used for parameter extraction in Si-MOSFET Extraction results of Cgd according to the prior art and the present invention in Si-MOSFET Schematic diagram of step-down chopper Measured value of turn-off waveform in step-down chopper using Si-MOSFET and circuit simulation result by conventional technology Measured value of turn-off waveform in step-down chopper using Si-MOSFET, and circuit simulation result according to the present invention Extraction results of Cgd according to the prior art and the present invention in GaN-HEMT Measured values and circuit simulation results of switching loss when the output current is changed in a step-down chopper using a GaN-HEMT Measured values and circuit simulation results of switching loss when the gate resistance is changed in a step-down chopper using GaN-HEMT

Explanation of symbols

1 Power FET to be extracted
2 Impedance measuring device 3 Voltage source 4 Voltage source 5 Voltmeter 6 Voltmeter 7 Ammeter 8 High frequency cutoff reactor 9 High frequency cutoff reactor 10 DC cutoff capacitor 11 Inductive load 12 Voltage source 13 Pulse voltage generator 14 Commutation diode DESCRIPTION OF SYMBOLS 15 Variable resistance 16 Voltmeter 17 Voltmeter 18 Voltmeter 19 Ammeter 20 Parasitic capacitance between gate-sources 21 Parasitic capacitance between gate-drains 22 Power FET
23 commutation diode 24 gate circuit 25 gate resistor 26 output capacitor 27 output inductor 28 input capacitor

Claims (14)

In a parameter extraction method for extracting parameters of an equivalent circuit model of a field effect transistor used in a power conversion circuit,
The equivalent circuit model is composed of parameters including a gate-source capacitance Cgs, a gate-drain capacitance Cgd, a drain-source capacitance Cds, and a channel current source Ich.
The equivalent circuit model includes a circuit including a drain-source capacitance Cds between a drain electrode and a source electrode of a field effect transistor, a gate-drain capacitance Cgd and a gate-source capacitance Cgs connected in series. A circuit in which a gate electrode of a field effect transistor is provided in between and a circuit formed by a channel current source Ich are connected in parallel,
A circuit side in which a circuit in which an inductive load and a commutation diode are connected in parallel to one end of a voltage source is connected in parallel to the drain electrode of the field effect transistor that is the target of the equivalent circuit model. One end of the voltage source, the other end of the voltage source is connected to the source electrode of the field effect transistor, a gate resistor and a pulse voltage generator are connected in series to the gate electrode of the field effect transistor, In a circuit in which the other end of the pulse voltage generator is connected to the source electrode of the field effect transistor,
Te state smell predetermined voltage to the field effect transistor by the pulse voltage generator was applied to on or off,
The field effect transistor from off to on state by applying a predetermined pulse voltage generated by the pulse voltage generator, or when switched from OFF ON state,
Changes in the gate-source voltage Vgs, the drain-source voltage Vds, the drain current Id, and the output voltage Vgcc of the pulse voltage generator during the transition from the ON state to the OFF state or from the OFF state to the ON state. A parameter extracting method, wherein the gate-source capacitance Cgs, the gate-drain capacitance Cgd, and the channel current source Ich are extracted on the basis of the represented switching waveform. The switching waveforms are the waveforms of the gate-source voltage Vgs, the drain-source voltage Vds, the drain current Id, and the output voltage Vgcc of the pulse voltage generator during the period in which the field effect transistor transitions from the on state to the off state. And
The time t1 at which the gate-source voltage Vgs starts to drop and the drain-source voltage Vds starts to rise and the gate-source voltage Vgs and the drain current Id start to drop starts at the time when the pulse voltage application starts. A time t3 when the source-to-source voltage Vgs reaches the output voltage Vgcc of the pulse voltage generator, a period 1 from time t1 to t2, and a period 2 from time t2 to t3.
The gate-source capacitance Cgs is extracted using the fact that the rate of decrease of the gate-source voltage Vgs in period 2 is regulated by the rate at which Cgs is charged / discharged by the gate current,
The gate-drain capacitance Cgd is extracted by utilizing the fact that the rate of rise of the drain-source voltage Vds in period 1 is regulated by the rate at which Cgd is charged and discharged by the gate current,
The channel current source Ich is a numerical value of the gate-source voltage Vgs and the drain-source voltage Vds at each time of the switching waveform obtained by gradually changing the value of the load current IL flowing through the inductive load 11. Is extracted as the value of the drain current Id measured at the time at an arbitrary gate-source voltage Vgs and drain-source voltage Vds on the graph with X and Y coordinates .
The parameter extracting method according to claim 1, comprising: The switching waveforms are the waveforms of the gate-source voltage Vgs, the drain-source voltage Vds, the drain current Id, and the output voltage Vgcc of the pulse voltage generator during the period in which the field effect transistor transitions from the off state to the on state. And
The time t4 when the pulse voltage is output from the pulse voltage generator, the time t5 when the rise of the gate-source voltage Vgs stops and the drop of the drain-source voltage Vds starts, and the rise of the gate-source voltage Vgs starts and drain- As time t6 when the drop of the source-to-source voltage Vds stops, and from time t4 to t5 as period 3 and from time t5 to t6 as period 4,
The gate-source capacitance Cgs is extracted using the fact that the rising speed of the gate-source voltage Vgs in period 3 is regulated by the speed at which Cgs is charged and discharged by the gate current,
The gate-drain capacitance Cgd is extracted using the fact that the rate of decrease of the drain-source voltage Vds in period 4 is regulated by the rate at which Cgd is charged / discharged by the gate current,
The channel current source Ich is a numerical value of the gate-source voltage Vgs and the drain-source voltage Vds at each time of the switching waveform obtained by gradually changing the value of the load current IL flowing through the inductive load 11. Is extracted as the value of the drain current Id measured at the time at an arbitrary gate-source voltage Vgs and drain-source voltage Vds on the graph with X and Y coordinates .
The parameter extracting method according to claim 1, comprising: 4. The parameter extracting method according to claim 2, wherein the gate-source capacitance Cgs and the gate-drain capacitance Cgd are extracted from the following equation (1).

Here, Vgcc is the output voltage of the pulse voltage generator connected to the gate, Vgs is the gate-source voltage, dVgs / dt is the amount of change in Vgs per unit time, and dVds / dt is the amount of change in Vds per unit time. , Ra is a resistance value inserted between the pulse voltage generator and the gate, Ca is a gate-source parasitic capacitance, and Cb is a gate-drain parasitic capacitance. 4. The parameter extracting method according to claim 2, wherein the gate-source capacitance Cgs and the gate-drain capacitance Cgd are extracted from the following equation (2).

Here, Vgcc is the output voltage of the pulse voltage generator connected to the gate, Vgs is the gate-source voltage, dVgs / dt is the amount of change in Vgs per unit time, and dVds / dt is the amount of change in Vds per unit time. , Ra is a resistance value inserted between the pulse voltage generator and the gate, Ca is a gate-source parasitic capacitance, and Cb is a gate-drain parasitic capacitance. 4. The parameter extracting method according to claim 2, wherein the gate-source capacitance Cgs is extracted from the following equation (3).

Here, Vgcc is the output voltage of the pulse voltage generator connected to the gate, Vgs is the gate-source voltage, dVgs / dt is the amount of change in Vgs per unit time, and Ra is between the pulse voltage generator and the gate. The inserted resistance value, Ca is a gate-source parasitic capacitance, and Cb is a gate-drain parasitic capacitance. 4. The parameter extracting method according to claim 2, wherein the gate-drain capacitance Cgd is extracted from the following equation (4).

Here, Vgcc is the output voltage of the pulse voltage generator connected to the gate, Vgs is the gate-source voltage, dVds / dt is the amount of change in Vds per unit time, and Ra is between the pulse voltage generator and the gate. The inserted resistance value and Cb are the gate-drain parasitic capacitance. In a parameter extraction device for extracting parameters of an equivalent circuit model of a field effect transistor used in a power conversion circuit,
The equivalent circuit model is composed of parameters including a gate-source capacitance Cgs, a gate-drain capacitance Cgd, a drain-source capacitance Cds, and a channel current source Ich.
The equivalent circuit model includes a circuit including a drain-source capacitance Cds between a drain electrode and a source electrode of a field effect transistor, a gate-drain capacitance Cgd and a gate-source capacitance Cgs connected in series. A circuit in which a gate electrode of a field effect transistor is provided in between and a circuit formed by a channel current source Ich are connected in parallel,
A circuit side in which a circuit in which an inductive load and a commutation diode are connected in parallel to one end of a voltage source is connected in parallel to the drain electrode of the field effect transistor that is the target of the equivalent circuit model. One end of the voltage source, the other end of the voltage source is connected to the source electrode of the field effect transistor, a gate resistor and a pulse voltage generator are connected in series to the gate electrode of the field effect transistor, In a circuit in which the other end of the pulse voltage generator is connected to the source electrode of the field effect transistor,
Te state smell predetermined voltage to the field effect transistor by the pulse voltage generator was applied to on or off,
The field effect transistor from off to on state by applying a predetermined pulse voltage generated by the pulse voltage generator, or when switched from OFF ON state,
Changes in the gate-source voltage Vgs, the drain-source voltage Vds, the drain current Id, and the output voltage Vgcc of the pulse voltage generator during the transition from the ON state to the OFF state or from the OFF state to the ON state. 3. A parameter extracting apparatus that extracts the gate-source capacitance Cgs, the gate-drain capacitance Cgd, and the channel current source Ich based on a switching waveform that is expressed . The switching waveforms are the waveforms of the gate-source voltage Vgs, the drain-source voltage Vds, the drain current Id, and the output voltage Vgcc of the pulse voltage generator during the period in which the field effect transistor transitions from the on state to the off state. And
The time t1 at which the gate-source voltage Vgs starts to drop and the drain-source voltage Vds starts to rise and the gate-source voltage Vgs and the drain current Id start to drop starts at the time when the pulse voltage application starts. A time t3 when the source-to-source voltage Vgs reaches the output voltage Vgcc of the pulse voltage generator, a period 1 from time t1 to t2, and a period 2 from time t2 to t3.
The gate-source capacitance Cgs is extracted using the fact that the rate of decrease of the gate-source voltage Vgs in period 2 is regulated by the rate at which Cgs is charged / discharged by the gate current,
The gate-drain capacitance Cgd is extracted by utilizing the fact that the rate of rise of the drain-source voltage Vds in period 1 is regulated by the rate at which Cgd is charged and discharged by the gate current,
The channel current source Ich is a numerical value of the gate-source voltage Vgs and the drain-source voltage Vds at each time of the switching waveform obtained by gradually changing the value of the load current IL flowing through the inductive load 11. Is extracted as the value of the drain current Id measured at the time at an arbitrary gate-source voltage Vgs and drain-source voltage Vds on the graph with X and Y coordinates .
The parameter extracting device according to claim 8, comprising: The switching waveforms are the waveforms of the gate-source voltage Vgs, the drain-source voltage Vds, the drain current Id, and the output voltage Vgcc of the pulse voltage generator during the period in which the field effect transistor transitions from the off state to the on state. And
The time t4 when the pulse voltage is output from the pulse voltage generator, the time t5 when the rise of the gate-source voltage Vgs stops and the drop of the drain-source voltage Vds starts, and the rise of the gate-source voltage Vgs starts and drain- As time t6 when the drop of the source-to-source voltage Vds stops, and from time t4 to t5 as period 3 and from time t5 to t6 as period 4,
The gate-source capacitance Cgs is extracted using the fact that the rising speed of the gate-source voltage Vgs in period 3 is regulated by the speed at which Cgs is charged and discharged by the gate current,
The gate-drain capacitance Cgd is extracted using the fact that the rate of decrease of the drain-source voltage Vds in period 4 is regulated by the rate at which Cgd is charged / discharged by the gate current,
The channel current source Ich is a numerical value of the gate-source voltage Vgs and the drain-source voltage Vds at each time of the switching waveform obtained by gradually changing the value of the load current IL flowing through the inductive load 11. Is extracted as the value of the drain current Id measured at the time at an arbitrary gate-source voltage Vgs and drain-source voltage Vds on the graph with X and Y coordinates .
The parameter extracting device according to claim 8, comprising: 11. The parameter extracting device according to claim 9, wherein the gate-source capacitance Cgs and the gate-drain capacitance Cgd are extracted from the following equation (1):

Here, Vgcc is the output voltage of the pulse voltage generator connected to the gate, Vgs is the gate-source voltage, dVgs / dt is the amount of change in Vgs per unit time, and dVds / dt is the amount of change in Vds per unit time. , Ra is a resistance value inserted between the pulse voltage generator and the gate, Ca is a gate-source parasitic capacitance, and Cb is a gate-drain parasitic capacitance. 11. The parameter extraction device according to claim 9, wherein the gate-source capacitance Cgs and the gate-drain capacitance Cgd are extracted from the following equation (2):

Here, Vgcc is the output voltage of the pulse voltage generator connected to the gate, Vgs is the gate-source voltage, dVgs / dt is the amount of change in Vgs per unit time, and dVds / dt is the amount of change in Vds per unit time. , Ra is a resistance value inserted between the pulse voltage generator and the gate, Ca is a gate-source parasitic capacitance, and Cb is a gate-drain parasitic capacitance. The parameter extracting device according to claim 9 or 10, wherein the gate-source capacitance Cgs is extracted from the following equation (3).

Here, Vgcc is the output voltage of the pulse voltage generator connected to the gate, Vgs is the gate-source voltage, dVgs / dt is the amount of change in Vgs per unit time, and Ra is between the pulse voltage generator and the gate. The inserted resistance value, Ca is a gate-source parasitic capacitance, and Cb is a gate-drain parasitic capacitance. The parameter extracting device according to claim 9 or 10, wherein the gate-drain capacitance Cgd is extracted from the following equation (4).

Here, Vgcc is the output voltage of the pulse voltage generator connected to the gate, Vgs is the gate-source voltage, dVds / dt is the amount of change in Vds per unit time, and Ra is between the pulse voltage generator and the gate. The inserted resistance value and Cb are the gate-drain parasitic capacitance.

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