JP5278511B2 - Network connection device, switching circuit device, and address learning processing method - Google Patents

Description

  The present technology relates to a technology related to address learning in a network connection device such as a switch.

  Conventionally, in a layer 2 (L2) switch, address learning for registering a source address (SA) in FDB (Forwarding DataBase) has been performed by switch hardware. For example, as shown in FIG. 1, a switch LSI (Large Scale Integrated circuit), which is switch hardware, includes a port, an FDB, and a management unit. Then, the FDB is searched by the source address (SA) of the packet received at the port (step (1001)), and the SA search result is notified to the management unit (step (1002)). If the SA is not registered in the FDB, the management unit registers the SA in the FDB (step (1003)). However, the management unit included in such a switch LSI can only perform simple SA registration, and cannot deal with a case where filtering by advanced processing such as authentication is necessary. Examples of cases where filtering by advanced processing is necessary include, for example, a case where the VLAN ID of the received packet is different from the VLAN ID of the received packet, and a plurality of different VLAN IDs when registering the SA of the received packet. There are cases where you want to register entries, and cases where you perform address translation for ports in different domains.

  There are the following techniques for performing address learning using such hardware. That is, the transfer processing time required for the packet is obtained from the packet length and the actual execution time of the transfer destination determination process is measured. According to the time difference between the transfer processing required time and the measured transfer destination determination process. It is determined whether or not to perform additional processing such as MAC address learning. According to this, as compared with the case where additional processing such as MAC address learning is always performed, packet discard is reduced, and an inexpensive system with good cost performance can be configured. Furthermore, it is possible to efficiently perform address learning without performing only learning for a specific address.

JP 2006-295550 A

  As described above, address learning using only hardware cannot support various address learning. Therefore, even if software-based address learning is introduced, not all problems are simply solved.

  Accordingly, an object of the present technology is to enable appropriate address learning by software in a network connection device such as a switch.

  The network connection device performs a predetermined learning process for a specific address in response to a request from the switch unit that outputs a packet received from the first port to the second port among a plurality of ports. And a processor that executes a management program. The switch unit described above is an entry including an address of a device connected to the port, learning data indicating whether the processor has learned the address, and an identifier of the port to which the device is connected. Is stored in the table. When the switch unit does not register the source address of the specific device included in the packet received from the specific port in the table, learning data indicating that the source address and the source address are being learned When the second packet including the source address of the specific device is received from the specific port, the entry including the ID and the identifier of the specific port is registered in the table, and the processor is requested to learn the source address. If an entry including the transmission source address of a specific device and learning data indicating that learning is in progress has already been registered in the table, the processor is not requested to learn the transmission source address. Further, when a request for changing learning data of a specific entry in the table to learned is received from the processor, the learning data of the specific entry in the table is set to learned.

  It becomes possible to appropriately perform address learning by software in the network connection device.

FIG. 1 is a diagram for explaining the prior art. FIG. 2 is a diagram illustrating a technology that is a premise of the embodiment of the present technology. FIG. 3 is a functional block diagram of the L2 switch according to the present embodiment. FIG. 4 is a diagram illustrating a configuration example of the FDB. FIG. 5 is a diagram for explaining a queue structure according to the present embodiment. FIG. 6 is a diagram showing a main processing flow of the present embodiment. FIG. 7A is a diagram illustrating a processing flow of SA processing. FIG. 7B is a diagram illustrating a state of an FDB or the like for explaining the SA processing. FIG. 8 is a diagram illustrating the states of the head pointer storage unit and the tail pointer storage unit for explaining the SA processing. FIG. 9 is a diagram illustrating a state of an FDB or the like for explaining the SA processing. FIG. 10 is a diagram illustrating the states of the head pointer storage unit and the tail pointer storage unit for explaining the SA processing. FIG. 11 is a diagram illustrating a processing flow of interrupt generation processing. FIG. 12 is a diagram showing a processing flow of internal resource access processing from the processor. FIG. 13 is a diagram showing a processing flow of address registration interrupt processing. FIG. 14 is a diagram showing a processing flow of address registration interrupt processing. FIG. 15 is a diagram illustrating a state of an FDB or the like for explaining address registration interrupt processing. FIG. 16 is a diagram illustrating the states of the head pointer storage unit and the tail pointer storage unit for explaining the address registration interrupt processing. FIG. 17 is a diagram illustrating a state of an FDB or the like for explaining address registration interrupt processing. FIG. 18 is a diagram illustrating the states of the head pointer storage unit and the tail pointer storage unit for explaining the address registration interrupt processing. FIG. 19 is a diagram showing a processing flow of DA processing.

[Assumptions of the embodiment of the present technology]
As described in the background art, the address learning using only the hardware in the L2 switch cannot cope with an advanced and flexible address learning pattern such as MAC VLAN authentication that switches learning and changes learning contents. Therefore, a configuration is conceivable in which a switch management processor is introduced separately from the switch LSI, and a management program for executing various address learning is executed by the switch management processor.

  An example of such a case is shown in FIG. In the example of FIG. 2, the switch LSI has a plurality of ports, an FDB, and a management unit. The switch LSI is connected to the switch management processor via a communication path (bus or network), and the switch management processor executes an operating system (OS) and a management program on the OS. In such a configuration, the FDB is searched by the source address (SA) of the packet received at the port (step (1101)), and the SA search result is notified to the management unit (step (1102)). If the SA is not registered in the FDB, the management unit issues a learning request interrupt to the processor (step (1103)).

  Thereafter, information such as SA is transferred from the management unit of the switch LSI to the management program executed by the switch management processor, or the contents of the FDB are transferred via the switch management processor and the management unit in response to a request from the management program. Or Using the data thus transferred, address learning is performed by the management program, and as a result, a request instructing whether to register or discard the SA in the FDB is output from the switch management processor to the management unit of the switch LSI ( Step (1104)). Then, in response to a request from the switch management processor, the switch LSI management unit registers the SA in the FDB or discards the SA (step (1105)).

  In address learning using such a management program, the latency in steps (1102) to (1105) is large, and the learning throughput is low. If packets containing SAs that are not registered in the FDB continue, learning will not be in time and learning will be lost. In order to cope with this, it is necessary to mask or queue subsequent SA search results. However, when masking, naturally, a new learning request is discarded during masking, so that a miss occurs, and when simply queuing, learning requests for the same SA are continuously added to the queue. Things can happen. In this case, a resource including a band between the switch LSI and the switch management processor is wasted, resulting in a problem that throughput is further reduced.

  As described above, address learning cannot be performed properly simply by causing the switch management processor to execute a management program for performing address learning separately from the switch LSI.

  In this embodiment, a configuration that solves such a specific problem is introduced.

[Specific contents of this embodiment]
FIG. 3 shows a configuration example of the L2 switch 100 in the present embodiment. The L2 switch 100 includes a switch LSI 110 and a switch management processor 120 connected to the switch LSI 110 via a communication path 131 and an interrupt signal line 132. The switch LSI 110 includes a port unit (ports 1 to 3 in FIG. 3) connected to a terminal device or the like (terminals 101 to 103 in FIG. 3), an FDB 111 connected to the port unit, and a management unit connected to the FDB 111. 112 and a tag storage unit 113 connected to the management unit 112 and functioning as a queue for managing the order of address learning. As will be described below, the FDB 111 and the tag storage unit 113 may be integrated as shown by a dotted line in FIG. In addition, a learning state flag 1111 indicating whether or not address learning is being performed is newly added to the FDB 111 as described below. The management unit 112 includes a head pointer storage unit 1121 that stores a head pointer that functions as a queue for managing the order of address learning together with the tag storage unit 113 and a tail pointer storage unit 1122 that stores a tail pointer. Further, the switch management processor 120 executes a management program 121 on the OS.

  FIG. 4 shows a data configuration example of the FDB 111. As shown in FIG. 4, in association with the MAC address that is the search key, output port information in which the identifier of the port to which the device with the MAC address is connected is registered, and whether or not the MAC address is being learned A learning state flag 1111 indicating whether it is already registered is registered. Each row of such a table is hereinafter referred to as an entry, and its storage location is hereinafter referred to as an index.

  By using such an FDB 111, it is possible to filter overlapping address learning requests as described below. When a new SA is received, a new entry is registered in the FDB 111 and the learning state flag 1111 is set to “learning”. When an entry update request is received from the switch management processor 120 as a result of address learning by the management program 121, the learning state flag 1111 is changed to “learned”, and packet transfer based on the entry is started. On the other hand, when an entry deletion request is received from the switch management processor 120, the corresponding entry is deleted.

  Specifically, when a packet (= MAC frame) is received from the port unit, an SA search is performed on the FDB 111 with the SA (= source MAC address) of the packet. At this time, if there is no corresponding entry in the FDB 111, a new entry whose learning state flag 1111 indicates “learning” is added to the FDB 111, and address learning is performed. On the other hand, if there is a corresponding entry and the learning state flag 1111 is “learning”, it is not necessary to perform any more address learning, so the address learning request is suppressed. As a result, overlapping address learning can be filtered to improve the address learning throughput. On the other hand, if the learning state flag 1111 is “learned”, address learning is not particularly required, and processing is performed as usual.

  When a packet is received from the port unit, DA search is performed on the FDB 111 even with the transmission destination address (DA: Destination address. = Transmission destination MAC address) of the packet. At this time, if there is no corresponding entry, the packet is broadcast to all ports. If there is a corresponding entry and the learning state flag 1111 is “learning”, the packet is broadcast to all the ports in the same state as when there is no corresponding entry. In other words, each device connected to each port is caused to determine whether the packet is addressed to itself. On the other hand, if the corresponding entry exists and the learning state flag 1111 is “learned”, the packet is transferred to the corresponding port as usual.

Next, a queue for managing the order of address learning will be described with reference to FIG. In the tag storage unit 113, pointers for corresponding entries in the FDB 111 are stored. This pointer points to the entry for the SA that should perform address learning by registering next. In the example of FIG. 5, the pointer of the index of the entry of Next0 has a index Next1 entry for SA should be carried out address learning by the next register. The pointer of the entry of the index Next1 becomes the index Next2 of the entry for the SA for which address learning is to be performed by further registering next. The pointer of the entry of the index Next2 is NULL because there is no SA for which address learning is to be performed next. Although not explicitly shown in FIG. 5, the pointer for the entry whose learning state flag 1111 is “learned” is not used (that is, treated as Don't care).

  Further, the management unit 112 holds a head pointer (Next0 in FIG. 5) that points to the entry of the FDB 111 that should first perform address learning, and finally a tail pointer that points to the entry of the FDB 111 that should perform address learning. (Next2 in FIG. 5) is held.

  In this way, the learning entry in the FDB 111 is managed in a queue structure, and the access of the switch management processor 120 is made efficient. That is, access from the switch management processor 120 is limited to the first entry being learned in the queue structure, so that the overhead for access is reduced and the processing performance is improved.

  Since the size of the FDB 111 is the upper limit for the number of addresses that can be learned originally (that is, the number of learned entries + the number of entries being learned ≦ the total number of FDB entries), a tag (pointer area) is provided in association with each entry in the FDB 111. Efficient. Further, if the tag storage unit 113 is provided in the FDB 111, the free area of the FDB 111 can be used more efficiently.

  Next, an outline of the operation of the L2 switch 100 according to the present embodiment shown in FIG. 3 will be described. For example, when the terminal 101 is connected to the port 1 and the port 1 receives a packet of the transmission source address SA (MAC address = A1) from the terminal 101, the FDB 111 is searched with this SA (MAC address = A1) (step ( 1)). Then, the SA search result is notified to the management unit 112 (step (2)). If the SA search result indicates that the SA is not registered in the FDB 111, the management unit 112 adds an entry for the SA to the FDB 111 (step (3)). The learning status flag 1111 of the additional entry is “learning”. In addition, the head pointer storage unit 1121 and the tail pointer storage unit 1122 and the tag storage unit 113 in the management unit 112 perform necessary processing for registering additional entries in the queue.

  Further, when the queue size becomes 1 or more, the management unit 112 interrupts the switch management processor 120 via the interrupt signal line 132 (step (4)). The management program 121 of the switch management processor 120 that has received the interrupt accesses the management unit 112 of the switch LSI 110 to identify the head entry of the queue and acquire data of the head entry of the queue via the communication path 131, A predetermined process for learning is performed (step (5)). As a result of the predetermined address learning by the management program 121 of the switch management processor 120, if the SA of the first entry in the queue may be registered, an entry update request is issued. The data is output to the management unit 112 of the switch management processor 120 (step (6)).

  If the request from the switch management processor 120 is an entry update request, the management unit 112 changes the learning state flag 1111 of the corresponding entry to “learned”, and if the request is an entry deletion request, deletes the corresponding entry in the FDB 111. (Step (7)).

  For steps (5) to (7), the switch management processor 120 repeats the process until the queue becomes empty.

  By performing such processing, address learning can be performed without waste and without omission.

  Details of the processing of the L2 switch 100 will be described below with reference to FIGS. First, for example, a packet is received from any of the terminals 101 to 103 at any of the ports 1 to 3 (FIG. 6: step S1). Then, SA processing by SA of the received packet is performed (step S3). This process will be described in detail below. Also, DA processing by DA of the received packet is performed (step S5). The DA process is a process for determining how to transfer a received packet, and will be described in detail below. Such processing is performed every time a packet is received.

  Next, SA processing will be described with reference to FIG. 7A. First, the FDB 111 is searched with the SA of the received packet (step S11). Since this step corresponds to step (1) in FIG. 3, it is indicated by “* (1)” in FIG. 7A.

  Then, it is determined whether the SA of the received packet is unregistered in the FDB 111 (step S13). This step corresponds to step (2) in FIG. If the SA is already registered in the FDB 111, address learning for the SA is not performed regardless of whether the learning state flag 1111 of the SA entry is “learning” or “learned” (step S25). If “learning”, duplicate address learning is avoided, and if “learned”, originally learning is unnecessary, so nothing is done in this way (displayed as a dotted line block in FIG. 7). Return to.

  On the other hand, if the SA of the received packet is not registered in the FDB 111, the management unit 112 in the FDB 111 has a new entry (MAC address = SA, learning state flag 1111 = during learning, pointer to the corresponding entry in the tag storage unit 113) = NULL) is added to the index = New1 (step S15). This step corresponds to step (3) in FIG. Further, the FDB 111 is in a state as shown in FIG. 7B.

  Then, the management unit 112 determines whether the end pointer is NULL (step S17). The fact that the tail pointer is NULL means that there is no entry for address learning in the queue, and the new entry added this time becomes the head entry. If the tail pointer is NULL, the management unit 112 sets the index (New1) of the additional entry as the head pointer (step S19). Then, control goes to a step S23. On the other hand, if the end pointer is not NULL, a new entry must be set at the end because there is already an entry that is being learned. Therefore, the index (New1) of the additional entry is set in the pointer field of the entry pointed to by the end pointer (that is, the corresponding field in the tag storage unit 113) (step S21). As a result, the additional entry can be registered at the end of the queue. Then, control goes to a step S23.

  In step S23, the management unit 112 sets the index (New1) of the additional entry in the end pointer (step S23). Then, the process returns to the original process.

  When steps S19 and S23 are executed, the index New1 is registered in the head pointer storage unit 1121 and the tail pointer storage unit 1122, as shown in FIG. On the other hand, when steps S21 and S23 are executed, as shown in FIG. 9, in the FDB 111, the pointer field (the corresponding field in the tag storage unit 113) for the entry that has been the last entry and the index is New0. Then, the index New1 of the entry added this time is registered. Also, as shown in FIG. 10, the head pointer storage unit 1121 stores the index Head 0 of the head entry, and the tail pointer storage unit 1122 registers the index New 1 of the entry added this time.

  As described above, when a packet including an unregistered SA is received, a new entry is registered in the FDB 111 and the new entry is set at the end of the queue.

  Next, processing of the management unit 112 that monitors the tail pointer storage unit 1122 will be described with reference to FIG. The management unit 112 monitors the tail pointer storage unit 1122 and determines whether the tail pointer is NULL (FIG. 11: step S31). If NULL, there is no address to learn, so wait until the tail pointer is registered. On the other hand, if the tail pointer is registered, the management unit 112 asserts an address registration request interrupt to the switch management processor 120 (step S33). This step corresponds to step (4) in FIG. Then, the process returns to step S31.

  When the tail pointer is set in this manner, an address registration request interrupt is asserted to the switch management processor 120, and address learning is started.

  In addition, the management unit 112 performs the following processing in response to a request from the switch management processor 120. Specifically, the management unit 112 determines whether any processing request has been received from the switch management processor 120 (FIG. 12: step S41), and waits until it is received if not received. On the other hand, when any processing request is received from the switch management processor 120, it is determined whether it is an access request to the pointer in the management unit 112 (specifically, the start pointer or the end pointer) (step S43). If it is an access request (read / write) to the pointer in the management unit 112, the management unit 112 accesses the pointer of the request destination and outputs the result to the switch management processor 120 (step S45). This step is a part of step (5) in FIG. 3, for example. Then, the process returns to step S41.

  On the other hand, if it is not an access request to the management unit pointer, the management unit 112 determines whether it is an access request to the FDB 111 (step S47). If it is an access request to the FDB 111, the management unit 112 accesses the FDB 111 according to the request, and outputs the result to the switch management processor 120 (step S49). For example, the contents of the entry may be read out and output to the switch management processor 120 in response to a request to read out the contents of the entry, the learning state flag 1111 of the entry may be changed in response to the request, Or delete it. This step is part of step (7) in FIG. After step S49, the process returns to step S41. If the access request is not for the FDB 111, the process returns to step S41.

  The management unit 112 also operates as an interface with the switch management processor 120 in this way.

  Next, processing of the management program 121 of the switch management processor 120 will be described with reference to FIGS. First, the switch management processor 120 receives an address registration interrupt from the switch LSI 110 via the interrupt signal line 132 (step S51). This step corresponds to step (4) in FIG. Then, the management program 121 executed by the switch management processor 120 instructs the management unit 112 of the switch LSI 110 to acquire the start pointer, and acquires the start pointer from the management unit 112 of the switch LSI 110 (step S53). This step corresponds to step (5) in FIG. 3 and is related to step S45 in FIG. Then, it is determined whether the head pointer is NULL (step S55). This step is effective when the process is completed and returned from the subsequent process. That is, it is naturally not NULL at first. If the head pointer is NULL, the process ends.

  If the head pointer is not NULL, the management program 121 instructs the management unit 112 to acquire the entry (for example, index “Head1”) pointed to by the head pointer, and the data of the entry pointed to by the head pointer from the management unit 112 of the switch LSI 110 Is acquired (step S57). Here, the pointer stored in the corresponding field of the tag storage unit 113 is also acquired at the same time. This step corresponds to part of step (5) in FIG. 3 and relates to step S49 in FIG. For example, as shown in FIG. 15, for the entry of index “Head 1”, the MAC address is SB, the output port information is port 2, the learning state flag 1111 is being learned, and the pointer of the corresponding field in the tag storage unit 113 Is New2.

  After that, the management program 121 makes the pointer field value (the value of the corresponding field in the tag storage unit 113) of the acquired entry (for example, the entry whose index is “Head1”) with respect to the head pointer storage unit 1121, “New2” in the above example. ) Is set to the management unit 112 of the switch LSI 110 (step S59). As a result, the top entry is replaced with the next entry. As illustrated in FIG. 16, “New2” is registered in the head pointer storage unit 1121. However, if the pointer field value of the acquired entry is “NULL” as in the entry of the index “New2” in FIG. 15, it is instructed to set “NULL”. This step corresponds to part of step (5) in FIG. 3 and relates to step S43 in FIG. Then, the processing shifts to the processing in FIG.

  Shifting to the description of the process of FIG. 14, a predetermined determination process (that is, an address learning process) is performed using the contents of the acquired entry (step S61). For example, it is determined whether or not the combination matches a specific address and VLAN, and registration is rejected if applicable. In addition, there are various variations such as obtaining information on IP packets as well as entries in the FDB 111 and determining whether to register. However, such processing itself is not the main point of the present embodiment but is conventionally known processing, and thus will not be described further.

  Then, the management program 121 determines whether or not to register the determination result SA in step S61 (“SB” in the example of FIG. 15) (step S63). When registering the SA, the management program 121 registers the acquired entry (index “Head1”). An entry update request is output to the management unit 112 of the switch LSI 110 so as to change the learning state flag 1111 of (entry) to learned (step S65). This step corresponds to step (7) in FIG. 3 and relates to step S49 in FIG. Then, the process proceeds to step S69. If such processing is performed, the FDB 111 and the like change from the state of FIG. 15 to the state of FIG.

  On the other hand, if the SA is not registered, the management program 121 outputs an entry deletion request to the management unit 112 of the switch LSI 110 so as to delete the acquired entry (entry of index “Head1”) (step S67). This step corresponds to step (7) in FIG. Then, the process proceeds to step S69.

  In step S69, the management program 121 determines whether the head pointer is NULL. In step S59, determination is made based on whether or not the management unit 112 of the switch LSI 110 is instructed to set NULL as the head pointer. If the head pointer is not NULL, the process returns to step S51 in FIG.

  On the other hand, if the head pointer is NULL, the management program 121 instructs the management unit 112 of the switch LSI 110 to set NULL to the tail pointer (step S71). As a result, a state in which there is no entry for address learning in the queue of the switch LSI 110 is determined. That is, as shown in FIG. 16, NULL is registered in both the start pointer storage unit 1121 and the end pointer storage unit 1122 in the management unit 112. This step is related to step S45 of FIG. Then, the process returns to step S51 in FIG.

  By performing such processing, address learning is appropriately performed from the head entry of the queue of the switch LSI 110. Furthermore, the queue is appropriately updated, and if it exists, address learning is performed for entries to be learned in order.

  Next, the DA process will be described with reference to FIG. First, the FDB 111 is searched with the DA of the received packet (step S81). Then, it is determined whether the DA is unregistered in the FDB 111 (step S83). If the DA is not registered in the FDB 111, it means that it is not known to which port the device related to the DA is connected, so the packet is transferred to all ports except the port that received the packet (step S89). Then, the process returns to the original process.

  On the other hand, if the DA has already been registered in the FDB 111, the learning state flag 1111 is set in this embodiment, so this is confirmed. If the learning state flag 1111 indicates that learning is in progress, whether or not to register this address has not yet been determined, and there may be a device that processes this packet at another port. Therefore, the process proceeds to step S89, and the packet is transferred to all ports except the port that received the packet.

  On the other hand, when the learning state flag 1111 indicates that learning has been completed, the packet is output to the output port included in the entry (step S87). Since the corresponding entry may be used if it has been learned, the packet is output in this way. Then, the process returns to the original process.

  By performing the above processing, if the DA is not learned and registered in the FDB 111, it is determined whether the packet should be transferred to all ports and received by devices connected to those ports. It is supposed to let you.

  As described above, by appropriately managing the learning state flag 1111, it is possible to efficiently filter overlapping address learning, and when the processing speed of the switch management processor 120 is slow by appropriately managing the queue. Also, missed address learning requests are eliminated. That is, with the minimum addition of the learning state flag 1111 and the tag storage unit 113, the efficiency of address learning can be improved, and there is no loss of information. As a result, even if the switch management processor 120 performs advanced address learning, the performance impact caused by the address learning can be suppressed to a very small value.

  Although the embodiment of the present technology has been described above, the present technology is not limited to this. For example, the functional block diagram shown in FIG. 3 is an example, and in some cases, the switch LSI 110 and the switch management processor 120 may be integrated. Even in such a case, the present embodiment operates.

  As for the processing flow, as long as the processing result does not change, the processing order may be changed or may be executed in parallel.

  The present embodiment can be summarized as follows.

  The network connection device according to the first aspect of the present technology includes: a switch unit that outputs a packet received from the first port among the plurality of ports to the second port; and a specific unit in response to a request from the switch unit And a processor that executes a management program that performs a predetermined learning process on the address. The switch unit described above includes an entry including the address of the device connected to the port, learning data indicating whether the processor has learned the address, and the identifier of the port to which the device is connected. It has a table to store. When the switch unit does not register the source address of the specific device included in the packet received from the specific port in the table, learning data indicating that the source address and the source address are being learned When the second packet including the source address of the specific device is received from the specific port, the entry including the ID and the identifier of the specific port is registered in the table, and the processor is requested to learn the source address. If an entry including the transmission source address of a specific device and learning data indicating that learning is in progress has already been registered in the table, the processor is not requested to learn the transmission source address. Further, when a request for changing learning data of a specific entry in the table to learned is received from the processor, the learning data of the specific entry is set to learned in the table.

  Thus, by managing the learning data in the table as described above, it becomes possible to appropriately filter the overlapping address learning, and the efficient address learning can be performed by the processor.

  Note that the switch unit and the processor described above may be different hardware modules. In such a case, the configuration as described above is particularly effective due to latency problems.

  In addition, when the above-described switch unit receives a second packet including a specific destination address from a specific port, the specific destination address and learning data indicating that learning is being performed are stored in the table. If the entry to be included is already registered, the second packet may be output to a plurality of ports excluding a specific port. In this way, during learning, since it is uncertain whether the transmission destination address can be really registered, the device connected to each port by broadcasting a packet is a corresponding device. Or not.

  Furthermore, a mechanism for managing the learning order of entries indicating that learning data is being learned in the table described above may be further provided. By maintaining such a configuration, even when the processing speed of the processor is low, it becomes possible to learn addresses without missing them in the correct order.

  In the mechanism described above, a pointer field is provided for each entry, and a pointer to the entry to be learned next is associated with the entry indicating that the learning data is being learned in the pointer field. May be registered. Further, a pointer to the entry to be learned first and a pointer to the entry to be learned last may be separately held. In this way, the mechanism described above can be realized with a simple configuration, and the table also functions as a request queue for address learning. The pointer field may be integrated with the table described above, or may be held in a different memory or recording area. In the case of being integrated, the processing is simpler and the memory utilization efficiency is higher.

  When such a pointer field or the like is used, the above-described switch unit, when a pointer to the last entry to be learned has already been registered, The address of the entry newly registered in the table may be registered in the pointer field, and the address of the entry newly registered in the table may be registered as a pointer to the entry to be learned last. Then, after requesting the processor to learn the transmission source address, in response to the request for the head pointer from the processor, the address of the head entry indicated by the pointer to the entry to be learned first is output to the processor. In response to the first entry acquisition request specifying the first entry address from the first entry, the first entry data and the address stored in the pointer field associated with the first entry are read from the table and output to the processor. Further, in response to an address setting request stored in the pointer field associated with the first entry from the processor, the address included in the address setting request is registered as a pointer to the entry to be learned first. It may be. In this way, the learning order is appropriately managed.

  In addition, the switching circuit device for a network connection device according to the second aspect of the present technology performs a predetermined learning process on a device address connected to a certain port among the plurality of ports and a specific address. It has a table for storing an entry including learning data indicating whether or not a processor executing the management program has learned a specific address, an identifier of a port to which the device is connected, and a management unit. . When the transmission source address of the specific device included in the packet received from the specific port is not registered in the table, the management unit learns the transmission source address and the transmission source address. And an entry including a specific port identifier are registered in the table, and the processor is requested to learn the source address. In addition, when a second packet including a transmission source address of a specific device is received from a specific port, an entry including the transmission source address of the specific device and learning data indicating that learning is in progress is registered in the table. If it has already been completed, the processor is not requested to learn the source address. Further, when a request for changing learning data of a specific entry in the table to learned is received from the processor, the learning data of the specific entry is set to learned in the table.

  The following supplementary notes are further disclosed with respect to the embodiments including the above examples.

(Appendix 1)
A switch unit for outputting a packet received from the first port among the plurality of ports to the second port;
A processor that executes a management program that performs a predetermined learning process for a specific address in response to a request from the switch unit;
Have
The switch part is
A table storing an entry including an address of a device connected to the port, learning data indicating whether or not the processor has learned the address, and an identifier of the port to which the device is connected And
When a source address of a specific device included in a packet received from a specific port is not registered in the table, learning data indicating that the source address and the source address are being learned, and the specific address Registering an entry including a port identifier in the table and requesting the processor to learn the source address;
When the second packet including the transmission source address of the specific device is received from the specific port, the table includes an entry including the transmission source address of the specific device and learning data indicating that learning is being performed. If registered, do not request the processor to learn the source address,
A network connection device that sets the learning data of the specific entry in the table as learned when a request for changing the learning data of the specific entry in the table to learned is received from the processor.

(Appendix 2)
The switch part is
When a second packet including a specific destination address is received from the specific port, an entry including the specific destination address and learning data indicating learning is registered in the table. The network connection device according to claim 1, wherein the second packet is output to the plurality of ports excluding the specific port.

(Appendix 3)
The network connection device according to appendix 1 or 2, further comprising a mechanism for managing a learning order of entries indicating that the learning data is being learned in the table.

(Appendix 4)
In the mechanism,
A pointer field is provided for each entry,
In the pointer field, a pointer to an entry to be learned next is registered in association with an entry indicating that the learning data is being learned,
The network connection device according to claim 3, further comprising a pointer to the entry to be learned first and a pointer to the entry to be learned last.

(Appendix 5)
A switch unit that outputs a packet received from the first port among the plurality of ports to the second port, and a management program that executes a predetermined learning process for a specific address in response to a request from the switch unit An address learning processing method executed by a network connection device having a processor
A specific port is stored in a table storing an entry including an address of a device connected to the port, learning data indicating whether the processor has learned the address, and an identifier of the port to which the device is connected. If the transmission source address of a specific device included in the packet received from is not registered, the transmission source address, learning data indicating that the transmission source address is being learned, and an identifier of the specific port are included. A requesting step of registering an entry in the table and requesting the processor to learn the source address;
When the second packet including the transmission source address of the specific device is received from the specific port, the table includes an entry including the transmission source address of the specific device and learning data indicating that learning is being performed. If registered, suppressing the request for learning the source address to the processor; and
When receiving a request to change the learning data of a specific entry in the table to learned from the processor, setting the learning data of the specific entry to learned in the table;
Address learning processing method.

(Appendix 6)
In the switch part,
A pointer field is provided for each entry,
In the pointer field, a pointer to an entry to be learned next is registered in association with an entry indicating that the learning data is being learned.
Furthermore, a pointer to the entry to be learned first and a pointer to the entry to be learned last are separately held,
In the request step,
If a pointer to the last entry to be learned has already been registered, the address of the entry newly registered in the table in the request step is stored in the pointer field for the last entry to be learned. Register,
Registering the address of the entry newly registered in the table in the requesting step as a pointer to the entry to be learned last;
Outputting the address of the head entry indicated by the pointer to the entry to be learned first to the processor in response to a request for the head pointer from the processor after the requesting step;
In response to a first entry acquisition request specifying the first entry address from the processor, the first entry data and the address stored in the pointer field associated with the first entry are read from the table. Outputting to the processor;
In response to an address setting request stored in the pointer field associated with the head entry from the processor, an address included in the address setting request is used as a pointer to the entry to be learned first. Registering, and
The address learning processing method according to claim 5, further comprising:

(Appendix 7)
An address of a device connected to a certain port among a plurality of ports, and learning data indicating whether or not a processor that executes a management program for performing a predetermined learning process for a specific address has learned the specific address; A table storing an entry including an identifier of a port to which the device is connected;
And a management department,
The management unit
When a source address of a specific device included in a packet received from a specific port is not registered in the table, learning data indicating that the source address and the source address are being learned, and the specific address Registering an entry including a port identifier in the table and requesting the processor to learn the source address;
When the second packet including the transmission source address of the specific device is received from the specific port, the table includes an entry including the transmission source address of the specific device and learning data indicating that learning is being performed. If registered, do not request the processor to learn the source address,
When the request to change the learning data of a specific entry in the table to learned is received from the processor, the learning data of the specific entry is set to learned in the table.
Switching circuit device for network connection devices.

100 L2 switch 110 Switch LSI
120 switch management processor 111 FDB 112 management unit 113 tag storage unit 1111 learning state flag 1121 head pointer storage unit 1122 tail pointer storage unit 121 management program

Claims (8)

In a network connection device comprising a switch and a processor,
The switch is
Multiple ports each receiving packets ,
A source address of a packet received from any one of the plurality of ports, registration processing information indicating whether the processor is determining whether to register the source address, and the packet are received A storage unit that stores an identifier for identifying the port in association with each other;
Determining whether a source address included in a packet received via any one of the plurality of ports is stored in the storage unit;
If the transmission source address included in the received packet is not stored in the storage unit, the transmission source address included in the received packet, registration processing information indicating that address registration processing is being performed, and the packet Are stored in the storage unit in the order in which the packets are received,
A request for determining whether or not to register the transmission source address first stored in the storage unit is transmitted to the processor;
In response to a request of the determination processing, when receiving a request to change the registration processing information from said processor registered, and a management unit for changing the registration process information corresponding to the source address registered,
The processor is
If a request determination process of registering whether the source address from the switch, if it is registered in the transmission source address, a request to change the registration process information corresponding to the source address registered, A network connection device that transmits to the switch. The network connection device further includes
Have a mechanism for managing the registration order of the transmission source address registration processing information indicating that the registration process in the storage unit is associated,
Oite to the mechanism,
A pointer field is provided for each source address,
In the pointer field, a pointer of a transmission source address to be registered next is registered in association with a transmission source address whose corresponding registration processing information is being registered,
Further, a pointer to the source address to be registered first and a pointer to the source address to be registered last are separately held.
The network connection device according to claim 1. The management unit
When the transmission source address included in the received packet is stored in the storage unit and the registration processing information corresponding to the transmission source address is information indicating that the address registration processing is being performed, the transmission is sent to the processor. 3. The network connection device according to claim 1, wherein a request for determining whether or not to register an original address is not transmitted. The processor is
When a request for determining whether or not to register a transmission source address is received from the switch, if registration of the transmission source address cannot be performed, a deletion request for deleting registration processing information corresponding to the transmission source address is transmitted to the switch. And
The management unit
4. The network connection device according to claim 1, wherein when the deletion request is received from the processor, registration processing information corresponding to the transmission source address is deleted from the storage unit. 5. . In a switching circuit device connected to a processor,
Multiple ports each receiving packets ,
A storage unit that stores a source address of a received packet, registration processing information indicating a registration status of the source address by the processor, and an identifier of a port that has received the packet;
When the transmission source address included in the packet received via any one of the plurality of ports is not stored in the storage unit, the transmission source address included in the received packet and address registration processing The registration processing information indicating that the packet is in correspondence with the identifier of the port that has received the packet, and stores it in the storage unit in the order of packet reception,
Sending a processing request for determining whether or not to register a transmission source address first stored in the storage unit to the processor,
When receiving a request to change the registration process information registered from the processor receiving the determination process request, and a management unit for changing the registration process information corresponding to the source address of the determination process request target to the registered Have
A switching circuit device. The switching circuit further includes:
Have a means for managing the registration order of the transmission source address registration processing information indicating that the registration process in the storage unit is associated,
The means include
A pointer field is provided for each source address,
In the pointer field, a pointer of a transmission source address to be registered next is registered in association with a transmission source address whose corresponding registration processing information is being registered,
Further, a pointer to the source address to be registered first and a pointer to the source address to be registered last are separately held.
The switching circuit device according to claim 5. The management unit
When the transmission source address included in the received packet is stored in the storage unit, and the registration processing information corresponding to the transmission source address indicates that the address registration processing is being performed, the processor is notified of the transmission source address. The switching circuit device according to claim 5 or 6, wherein a request for registration permission determination processing is not transmitted. The management unit
The registration processing information corresponding to the source address related to the deletion request is deleted from the storage unit when a registration processing information deletion request is received from the processor. One switching circuit device.

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