JP5272555B2 - FM transmitter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the occurrence of carrier leak by avoiding deviation (DC offset) in the center of an amplitude level between differential signals (P, N), which occurs when an IQ signals are processed with differential signals in an FM transmitter. <P>SOLUTION: A calibration circuit is provided for correcting the DC offset, between differential signals Ip, In of an I signal and between differential signals Qp, Qn of a Q signal, which occur in D-A converters 2a, 2b and low-pass filters 3a, 3b. The circuit includes: a comparator 10c for comparing voltages of the differential signals Ip, In/Qp, Qn of the I/Q signal outputted from the low-pass filters 2a, 2b; and first and second calibration DACs 10a, 10b and a logic circuit 11 for applying correction voltages P, N to the low-pass filters 2a, 2b so as to decrease a voltage difference between the differential signals Ip, In/Qp, Qn outputted from the low-pass filters 2a, 2b in accordance with the comparison result of the comparator 10c. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  TECHNICAL FIELD The present invention relates to an FM transmitter that is provided in an FM transceiver having an FM (Frequency Modulation) tuner function and an FM transmitter function, an FM transceiver having an AM tuner function, etc., and that converts an audio stereo signal or the like into an FM signal and transmits the FM signal. Is.

  In an FM transmitter that converts an audio stereo signal into an FM signal and transmits the signal, a direct modulation method and IQ (In-phase / Quadrature) modulation are used as methods for performing modulation by digital signal processing when the audio stereo signal is converted into an FM signal. The system is mainly used.

  As a feature, the direct modulation method has a simple circuit configuration, but overmodulation is likely to occur. The IQ modulation method has advantages and disadvantages that the modulation control is simple but the circuit configuration is complicated.

  In the case of an FM transmitter using an IQ modulation method, the audio stereo signal is converted into digital data by anti-aliasing filter processing (AAF) and AD converter (ADC) for each L / R signal, and filtered by a DSP (Digital Signal Processor) circuit. After being processed and signal processed, it is output as an IQ signal.

  The IQ signal is converted to an analog signal by a DA converter (DAC), and harmonic components generated by the DAC are excluded by an LPF (Low Pass Filter) and mixed with a carrier wave by a multiplier (MIXER). The power amplifier (PA) outputs RF (Radio Frequency).

  In the case of the IQ modulation method, when a variation caused by a process or a difference caused by a layout occurs between IQ signals, a noise component called carrier leak occurs.

  When this carrier leak occurs, in the case of an FM transmitter, the audio characteristic is deteriorated and the adjacent channel is adversely affected.

  The cause of the layout can be suppressed at the design stage, but the variation due to the process is difficult to suppress. Therefore, it is necessary to study a correction technique for reducing carrier leakage.

  Further, the cause of the carrier leak includes a phase error between IQ signals, a gain error, and a DC offset error.

  In the case of high-frequency bands used for digital communications, etc., technology is used to detect and correct deviations after quadrature modulation using a detection circuit or level detection circuit. However, this technology also requires a large processing circuit for processing. It is not easy.

  Compared to the high frequency band used in such digital communication, the frequency band used in the FM transmitter is as low as 76 MHz to 108 MHz, and the cause of the carrier leak is from the phase error and gain error between IQ signals. However, the DC offset error is dominant.

  Further, when an IQ signal is processed with a differential signal, a deviation (DC offset) may occur at the center of the amplitude level of the differential signal (P, N), which also causes carrier leakage. Since the difference between the differential signals is greatly affected by variations caused by the process in the manufacturing process, the influence on the occurrence of carrier leak is also large.

  The techniques related to the FM transmitter are disclosed in, for example, Patent Documents 1 and 2, and the techniques for suppressing and adjusting the carrier leak are described in Patent Documents 3 to 8 and the like, and the offset of the IQ signal is patented. Each of them is disclosed in Document 9 and the like.

JP 2007-096694 A JP 2007-088657 A JP 2007-267345 A JP 2006-041631 A JP 2001-007869 A Japanese Patent Laid-Open No. 08-032464 Japanese Patent Application Laid-Open No. 07-05891 Japanese Patent Laid-Open No. 06-237281 JP 2007-235463 A

  The problem to be solved is that the conventional technique cannot avoid the deviation (DC offset) of the center of the amplitude level of the differential signal (P, N) that occurs when the IQ signal is processed with the differential signal. Is a point.

  The object of the present invention is to solve these problems of the prior art, and incorporates a circuit for correcting a DC offset between differential signals when processing IQ signals with differential signals, thereby reducing the occurrence of carrier leakage. Is to realize.

In order to achieve the above object, the invention of claim 1 converts an I signal output from a digital signal processing circuit that IQ-modulates an input audio stereo signal and converts it into an FM signal to convert it to an analog signal. A first D / A converter that outputs differential signals Ip and In, and a second D / A converter that converts the Q signal output from the digital signal processing circuit into an analog signal and outputs differential signals Qp and Qn of the Q signal. The D / A converter, the first low-pass filter for removing harmonic components generated by the digital / analog conversion of the first D / A converter, and the digital / analog conversion of the second D / A converter. An FM transmitter comprising at least a second low-pass filter for removing generated harmonic components,
The DC offset between the differential signals Ip and In of the I signal and the differential signals Qp and Qn of the Q signal generated in the first and second DA converters and the first and second low-pass filters. A calibration circuit for correcting the DC offset between
The calibration circuit includes a first comparator for comparing voltages of the differential signals Ip and In of the I signal output from the first low-pass filter, and the Q signal output from the second low-pass filter. The I signal output from the first and second low-pass filters according to the comparison result of the second comparator for comparing the voltages of the differential signals Qp and Qn and the first and second comparators. Control means for correcting each of the first and second low-pass filters so that the voltage difference between the differential signals Ip and In and the voltage difference between the differential signals Qp and Qn of the Q signal are reduced. And
The first comparator includes means for outputting either a high level (1) or a low level (0) signal according to the voltage difference between the differential signals Ip and In of the I signal,
The second comparator comprises means for outputting either a high level (1) or a low level (0) signal according to the voltage difference between the differential signals Qp and Qn of the Q signal,
The control means includes
Generates two analog signals P and N that are monotonously increased / decreased relatively according to the input n-bit string (n ≧ 2) digital signal and have the same voltage when the intermediate digital code (10...) Is input. A first converter that outputs to the first low-pass filter;
At the start of startup, the intermediate digital code is input to the first converter, and the analog signals P and N having the same voltage are output from the first converter to the first low-pass filter. Using the output (high level “1” or low level “0”) of the first comparator according to the differential signals Ip and In from the first low-pass filter, the differential from the first low-pass filter An operation of generating a digital code for reducing the voltage difference between the signals Ip and In and inputting the digital code to the first converter is repeated n times, and the digital code generated at the nth time is used as the differential signal of the I signal. A first controller that inputs a DC offset correction value between Ip and In to the first converter;
Two analog signals P and N that are monotonously increased / decreased relatively according to the input digital code of the n-bit string and have the same voltage when the intermediate digital code is input are generated in the second low-pass filter. When the start-up is started, the intermediate digital code is input to the second converter, and the analog signal P having the same voltage is supplied from the second converter to the second low-pass filter. N is output, and the output of the second comparator (high level “1” or low level “0”) corresponding to the differential signals Qp and Qn from the second low-pass filter is used thereafter. 2 generates a digital code for reducing the voltage difference between the differential signals Ip and In from the two low-pass filters and inputs the digital code to the second converter. That operates the repeated n times, the digital code generated on the n-th and and a second controller to be input to the second converter as a differential signal Qp, DC offset correction value between Qn of the Q signal It is characterized by.

  According to the present invention, in the FM transmitter equipped with the calibration circuit configured as described in (1) above, the DC offset between the differential signals generated in the DAC and the LPF due to process variations in the manufacturing process is reduced. Correction can be made and carrier leakage can be reduced. Further, in the calibration circuit having the configuration (2), even if a DC offset occurs in the comparator, the calibration is performed by replacing the comparator input, and the average value is obtained to cancel the DC offset in the comparator. It is possible to obtain the obtained value. Further, in the FM transmitter equipped with the calibration circuit having the configuration (3), the DC offset adjustment can be automatically performed during the power-on sequence, so that the differential generated between the DAC and the LPF due to process variations. It is possible to automatically correct the DC offset between signals. In the FM transmitter equipped with the calibration circuit having the configuration (4), the calibration operation for adjusting the DC offset can be arbitrarily executed from the host. It is possible to statistically process the calibration results and adopt the optimum value as the calibration value.

  The best mode for carrying out the present invention will be described below with reference to the drawings. FIG. 1 is a block circuit diagram showing a configuration example of an FM transmit according to the present invention, FIG. 2 is a block circuit diagram showing a configuration example of a calibration circuit in FIG. 1, and FIG. 3 is a calibration in FIG. 4 is a timing chart showing an example of the operation of the circuit, FIG. 4 is an explanatory diagram showing an example of the output voltage from the calibration circuit in FIG. 2, and FIG. 5 obtains the optimum value of the calibration set in the calibration circuit in FIG. FIG. 6 is a block circuit diagram showing a configuration example of a general FM transmit.

  First, a general configuration of an FM transmitter that employs an IQ modulation method will be described with reference to FIG.

  The audio stereo signal Lin / Rin is sent to a digital signal processing circuit (shown in the figure) via anti-aliasing filters (shown as “AAF” in the figure) 64a and 64b and AD converters (shown as “ADC” in the figure) 65a and 65b. (Indicated as “DSP”) 61.

  In the DSP 61, the input audio signal is subjected to filter processing (LPF, HPF, etc.) and signal processing (gain control, pre-emphasis processing, etc.), and then converted into a stereo composite signal together with the pilot signal in the STREO GEN 61a. In IQMOD 61b, the signal is converted into an FM signal by IQ modulation and output.

  The converted IQ signal output from the DSP 61 is converted to an analog signal by a DA converter (described as “DAC” in the figure) 62a and 62b, and the differential output voltage from the DA converters 62a and 62b is: High-frequency components generated by the DA converters 62a and 62b are cut by the low-pass filters (described as “LPF” in the figure) 63a and 63b.

  The differential output voltages of the DA converters 62a and 62b whose harmonic components have been cut by the low-pass filters 63a and 63b are combined with a carrier wave generated by a local oscillator 66 (described as “LOSC” in the figure) 66 and a multiplier (see FIG. In the multiplier 67, the IQ signal and the carrier wave are mixed together, and an RF output (“RFout” in the figure) is output by a power amplifier (indicated as “PA” in the figure) 68. (Describe)

  The DSP 61 can perform processing according to the setting in the REGISTER 69 from the host via the HOST I / F.

  Next, the FM transmitter using the calibration circuit for DC offset adjustment of this example will be described with reference to FIG.

  The difference between the FM transmitter of this example shown in FIG. 1 and the FM transmitter shown in FIG. 6 is the calibration for correcting the deviation between the differential signals (P, N) occurring in the LPFs 63a and 63b in FIG. And a logic circuit (described as “CALCTRL” in the figure) 11 for controlling the LPF calibration circuit 10 is added.

  That is, in the FM transmitter in FIG. 1 as well, the audio stereo signal Lin / Rin includes anti-aliasing filters (described as “AAF”) 4a and 4b and AD converters (described as “ADC”) 5a and 5b. Is input to the digital signal processing circuit 1 (described as “DSP” in the figure) 1.

  In the digital signal processing circuit 1, the input audio signal is subjected to filter processing (LPF, HPF, etc.) and signal processing (gain control, pre-emphasis processing, etc.), and then the stereo composite signal together with the pilot signal in the STREEO GEN 1 a. Further, the signal is converted into an FM signal (I signal, Q signal) by IQ modulation in IQMOD 1b and output.

  The converted I signal and Q signal output from the digital signal processing circuit 1 are converted into analog signals by DA converters (described as “DAC” in the drawing) 2a and 2b, respectively, and differential signals Ip and In And are output as differential signals Qp and Qn, and then input to low-pass filters (described as “LPF” in the figure) 3a and 3b.

  In the low-pass filters 3a and 3b, harmonic components generated in the DA converters 2a and 2b are cut from the input differential signals Ip and In and the differential signals Qp and Qn.

  The differential signals Ip and In and the differential signals Qp and Qn of the DA converters 2a and 2b whose harmonic components are cut by the low-pass filters 3a and 3b are generated by a local oscillator 6 (described as “LOSC” in the figure). Along with the carrier wave thus obtained, it is input to a multiplier (denoted as “MIXER” in the figure) 7.

  In this multiplier 7, the input differential signals Ip, In and differential signals Qp, Qn and a carrier are mixed together, and an RF output (“PA” in the figure) 8 is output by a power amplifier (described as “PA” in the figure). RFout ”). The digital signal processing circuit 1 can perform processing according to data set in the REGISTER 9 via a HOST I / F from a host (not shown).

  In this example, a calibration circuit is further provided. As shown in the FM transmitter of FIG. 1, this calibration circuit includes a logic circuit (described as “CALCTRL” in the figure) 11 provided in the digital signal processing circuit 1 and an LPF calibration provided outside the digital signal processing circuit 1. Circuit 10 (described as “LPFCAL” in the figure).

  Based on the control from the logic circuit 11, the LPF calibration circuit 10 detects the deviation between the differential signals Ip and In output from the low-pass filters 3a and 3b and the deviation between the differential signals Qp and Qn. Perform the corrective action.

  The internal configuration of the LPF calibration circuit 10 will be described with reference to FIG. The LPF calibration circuit 10 shown in FIG. 2 is provided with two calibration DACs (described as “CALDAC” in the figure) 10 a and 10 b and one comparator (described as “CALCMP” in the figure) 10 c. Further, a switching circuit including two AND circuits, one converter circuit, and a plurality of switches is provided.

  With such a configuration, the LPF calibration circuit 10 of the present example has the DC offset between the differential signals Ip and In of the I signal generated in the matching process of the DA converters 2a and 2b and the low-pass filters 3a and 3b. , Q is operated to correct the DC offset between the differential signals Qp and Qn.

  That is, the LPF calibration circuit 10 compares the differential signals Ip and In of the I signal output from the low-pass filter 3a and the differential signals Qp and Qn of the Q signal output from the low-pass filter 3b by the comparator 10c. The I signal differential signals Ip and In and the Q signal differential signals Qp and Qn output from the low pass filters 3a and 3b, respectively, according to the comparison result (CAL_CMPO) of the comparator 10c. Each of the low-pass filters 3a and 3b is corrected by the calibration DACs 10a and 10b so that each has the same voltage.

  Specifically, the comparison result of the comparator 10c is input to the logic circuit 11 in FIG. 1, and the logic circuit 11 generates digital codes CAL_I and CAL_Q according to the comparison result (CAL_CMPO) of the comparator 10c, Output to each of the calibration DACs 10a and 10b.

  The calibration DAC 10a outputs, to the low-pass filter 3a, voltages (P, N) for increasing or decreasing the differential signals Ip and In in the low-pass filter 3a according to the input digital code CAL_I. The application DAC 10b outputs voltages (P, N) for increasing or decreasing the differential signals Qp and Qn in the low-pass filter 3b to the low-pass filter 3b in accordance with the input digital code CAL_Q.

  In the low-pass filters 3a and 3b to which the outputs (P, N) from the calibration DACs 10a and 10b are input, the differential signals Ip and In of the I signal are respectively corresponding to the inputs (P and N). And the differential signals Qp and Qn of the Q signal each increase or decrease, the result is reflected in the comparison result in the comparator 10c, and by repeating this operation, the differential signal of the I signal in the low-pass filters 3a and 3b Each of Ip and In and each of the differential signals Qp and Qn of the Q signal are brought close to the same voltage.

  Here, each of the calibration DACs 10a and 10b in the LPF calibration circuit 10 of this example shown in FIG. 2 has a constant voltage by the digital codes “CAL_I” and “CAL_Q” output from the logic circuit 11 in FIG. (P, N) is output and is always operating.

  Further, for example, when the signal “CAL_EN” output from the logic circuit 11 is “1”, the LPF calibration circuit 10 enters the DC offset adjustment mode, and the comparator 10 c also operates.

  In this example, the comparator 10c is used by sharing time with the I signal / Q signal. However, the comparator 10c may be individually used for each of the I signal / Q signal.

  Further, in order to make it possible to grasp the occurrence of a DC offset in the comparator 10c and the gray zone due to signal noise, the input signal to the comparator can be replaced by the CAL_POL signal output from the logic circuit 11.

  In the DC offset adjustment mode, the DA converters 2a and 2b are in a normal operation state, and output voltages of the differential signals (differential signals Ip and In of the I signal and differential signals of the Q signal). Qp, Qn) must be fixed with a digital code that is expected to be the same.

  The DC offset adjustment calibration operation of the LPF calibration circuit 10 having such a configuration will be described with reference to FIG.

  3, signals other than the output CAL_CMPO of the comparator 10c are generated in the logic unit 11 in the digital signal processing circuit 1 in FIG.

  In this example, the calibration DACs 10a and 10b are 6 bits for both I / Q in the following description. However, the present invention is not limited to this (6 bits), and the resolution required for correction is used. The number of bits may be selected accordingly.

  First, the calibration of the LPF calibration circuit 10 is started by setting the CAL_EN signal to “1 (high level)”. The D-A converters 2a and 2b are kept in a normal operation state, but the values of the differential signals output to both the I signal and the Q signal are the same voltage for the input data to the DA converters 2a and 2b. Secure to.

  CAL_CLK outputs 13 clocks, and the calibration DACs 10a and 10b and the comparator 10c operate with this clock.

  First, in the state of CAL_IQSEL = 1 (high level), calibration from the I side is selected and executed as follows.

  When the digital code of CAL_I [5: 0] = 100000 (binary) is applied to the calibration DACs 10a and 10b at the first falling edge of CAL_CLK, the output CAL_CMPO of the comparator 10c is output at the rising edge of CAL_CLK. Therefore, the result is taken into CAL_I [5] at the next falling edge of CAL_CLK, and CAL_I [4: 0] = 10000 (binary) is output.

  If this process is performed six times, CAL_I [5: 0] to be given to the calibration DACs 10a and 10b when the P and N inputs to the comparator 10c by the binary search are equal can be obtained.

  Thereafter, the logic circuit 11 sets CAL_IQSEL = 0, and similarly performs calibration (CAL_Q [5: 0]) on the Q side, that is, the low-pass filter 3b.

  If CAL_Q [5: 0] is obtained in the same manner, the logic circuit 11 sets CAL_CLK = 1, and then fixes and stops the clock. Thereafter, the calibration operation is stopped by setting CAL_EN = 0.

  The digital codes CAL_I [5: 0] and CAL_Q [5: 0] obtained by the DC offset adjustment calibration operation remain in the held state, and the calibration DACs 10a and 10b are output at a constant voltage. At this time, the differential outputs Ip, In and Qp, Qn from the low-pass filters 3a, 3b in FIG. 2 have substantially the same voltage.

  Hereinafter, this operation will be described more specifically. First, in the calibration operation in this example, “CAL_I / Q [5: 0]” is changed in six stages from “100000” to “*** 1” and input to the calibration DACs 10a and 10b. The change in the output of the comparator 10c with respect to the values from “100000” to “**** 1” will be described.

  The output from the comparator 10c, that is, either “high level (= 1)” or “low level (= 0)” is input to each “*” portion in “****** 1”. In FIG. 3, if the value I [5] of the output (CAL_CMPO) of the comparator 10c is “0”, the second CAL_I [5: 0] input to the calibration DAC 10a is “010000”. In this way, the output CAL_CMPO from the comparator 10 c is directly reflected on the inputs of the calibration DACs 10 a and 10 b via the logic circuit 11.

  In this example, the calibration DACs 10a and 10b have 64 input values of 6 bits from “100,000” to “*** 1”, and their outputs are matched to the inputs (0 to 63). As shown in FIG. 4, it changes so that it may line up linearly. In FIG. 4, each of the 64 output values is represented by a straight line. When the intermediate digital code input “CAL_I [5: 0] = [100000 (decimal 32)]”, the differential signal I, P has the same voltage.

  As shown in FIG. 4, the outputs of the calibration DACs 10a and 10b are monotonically increasing on the P side of the differential signals I and Q and monotonically decreasing on the N side, depending on the input digital code. As the digital code becomes larger, the P side and the N side relatively monotonically increase and decrease monotonously.

  In FIG. 3, the signal “* reflecting the output signal (* = 1 or 0) from the comparator 10c corresponding to the sixth input signal“ CAL_I / Q [5: 0] ”(= ****** 1). “***” (for example, a value such as “010001” or “100010”) is a correction value, and is a final input value to the calibration DACs 10a and 10b.

  The operation until the final correction value “****” is specified will be described using a specific example. Here, for ease of explanation, the outputs of the DA converters 2a and 2b in FIG. 2 are P1 and N1, the outputs of the calibration DACs 10a and 10b are P2 and N2, and the outputs of the low-pass filters 3a and 3b are P3. And N3. The comparator 10c outputs “high level (= 1)” when “N3> P3”.

  First, when an intermediate digital code “100000 (decimal 32)” is input to the calibration DACs 10a and 10b, the output P2 of the calibration DACs 10a and 10b becomes N2, as shown in FIG.

  The outputs P2 and N2 are added to the outputs P1 and N1 from the DA converters 2a and 2b to become P3 and N3.

  If P1> N1 (P1 is about 0.33 V), P3> N3 because P2 = N2, and as a result, the output CAL_CMPO of the comparator 10c becomes “0 (low level)”. This value (0) is taken into CAL_I [5] in the logic circuit 11, and then the digital code (“* 10000” in FIG. 3) given to the calibration DACs 10a and 10b becomes “010000”.

  In the case of the digital code “010000”, P2 <N2 (N2 is about 1V is large). In this case, P3 <N3, the output CAL_CMPO of the comparator 10c this time becomes “1 (high level)”, and this value (1) is taken into the next digital code CAL_I [4] in the logic circuit 11, As a result, the digital code given to the calibration DACs 10a and 10b next becomes “011000”.

  In this case, P2 <N2 (N2 is about 0.4 V is large), and again P3 <N3. As a result, the output CAL_CMPO of the comparator 10c is “1”, and this value is the following in the logic circuit 11: The digital code CAL_I [3] is taken in, and as a result, the digital code given to the calibration DACs 10a and 10b next becomes “011100”.

  When “011100” is given as the digital code to the calibration DACs 10a and 10b, P2 <N2 (N2 is about 0.2V is large), and this time, P3> N3, and the output CAL_CMPO of the comparator 10c is “0”. This value is taken into the next digital code CAL_I [2] in the logic circuit 11, and as a result, the digital code given to the calibration DACs 10a and 10b next becomes “011010”.

  When “011010” is given to the calibration DACs 10a and 10b, P2 <N2 (N2 is about 0.3V is large), P3> N3, and the output CAL_CMPO of the comparator 10c is “0”. The value is taken into the next digital code CAL_I [1] in the logic circuit 11, and as a result, the digital code given to the calibration DACs 10a and 10b next becomes “011001”.

  When this digital code “011001” is applied to the calibration DACs 10a and 10b, P2 <N2 (N2 is about 0.35V is large), and as a result, P3 <N3, and the output CAL_CMPO of the comparator 10c is “1”. This value (“1”) is taken into the digital code CAL_I [0] in the logic circuit 11, and the code finally given to the calibration DACs 10a and 10b is “011001”.

  In this explanation, a deviation of 0.02 V remains, but this time because it is processed with 6 bits, and if the resolution is a problem, it can be dealt with by increasing the number of bits so that the above processing can be repeated.

  However, the above-described example is a case where there is no DC offset in the comparator 10c. If there is a DC offset in the comparator 10c, the above-described calibration result is obtained by the DC offset in the comparator 10c. The value deviates from the optimum value.

  In order to cope with such a case, the input to the comparator 10c is switched by the CAL_POL from the logic circuit 11, and an average with the result is obtained to obtain an optimum value.

  In other words, the logic circuit 11 inverts CAL_POL from “0” to “1” and switches the switch, thereby inverting the output CAL_CMPO of the comparator 10c, and the input signal CAL_I [5 to the calibrator DACs 10a and 10b. : 0] and CAL_Q [5: 0].

  Then, by switching CAL_POL between “0” and “1” and taking the average of the results obtained by switching the input to the comparator 10c, it is possible to obtain an optimal correction value.

  Specifically, first, calibration results CAL_I0 and CAL_Q0 are obtained with CAL_POL = 0, and then calibration results CAL_I1 and CAL_Q1 are obtained with CAL_POL = 1.

  If there is no difference between CAL_I0 and CAL_I1 and CAL_Q0 and CAL_Q1, there is no offset in the comparator 10c. If there is a difference, the average value of each is used as the optimum calibration result (correction value). To do.

  This processing may be performed automatically by hardware, or the calibration results CAL_I and CAL_Q are output to an external host, recorded, and read again from the external host, and CAL_I and CAL_Q are given from the external host. Thus, it is possible to set CAL_I and CAL_Q from the external host without performing calibration at the next startup. Further, by executing calibration twice with CAL_POL = 0 and 1 under the control of the host side, it is possible to obtain the optimum value by obtaining the average in software.

  FIG. 5 shows a method for specifying the optimum value (average value) of calibration when considering the case where a DC offset occurs in the comparator 10c.

  Further, with such a configuration, it is possible to employ a highly accurate calibration result such as an average value or a maximum value after N times as necessary.

  As described above with reference to FIGS. 1 to 5, the FM transmitter of this example includes a digital signal processing circuit (DSP) 1 that employs an IQ modulation method when converting an audio stereo signal into an FM signal, DA converters (DACs) 2a and 2b that convert the I signal and Q signal generated by the digital signal processing circuit 1 into analog signals and output them differentially, and digital-to-analog conversion in the DA converters 2a and 2b The differential signal Ip of the I signal is composed of low-pass filters (LPF) 3a and 3b for removing harmonic components generated at the time, and further generated in the DA converters 2a and 2b and the low-pass filters 3a and 3b. Calibration circuit (LPF key) for correcting the DC offset between In and In and the DC offset between the Q differential signals Qp and Qn. The rebirth circuit 10 and the logic circuit 11) are built in, and in the FM transmitter equipped with this calibration circuit, the DA converters 2a and 2b and the low-pass due to process (manufacturing process) variations are provided. The DC offset between the differential signals generated by the filters 3a and 3b can be corrected, and carrier leak can be reduced.

  In the calibration circuit of this example, the comparator 10c that compares the voltage of the differential signals Ip and In of the I signal output from the low-pass filter 3a and the voltage of the differential signals Qp and Qn of the Q signal, and the low-pass filter As the comparator 10c that compares the voltage of the differential signals Ip and In of the I signal output from 3b and the voltage of the differential signals Qp and Qn of the Q signal, the same comparator is commonly used by switching the switch. Further, according to the comparison result of the comparator 10c, the voltage difference between the I signal differential signals Ip and In and the Q signal differential signals Qp and Qn output from the low pass filters 3a and 3b, respectively. As a control means for correcting each of the low-pass filters 3a and 3b so that the voltage difference is reduced, a logic circuit is used. It has a configuration in which a 11.

  The logic circuit 11 causes the calibration DAC 10a to output the differential signals Ip and In of the I signal output from the low-pass filter 3a to the low-pass filter 3a according to the comparison result regarding the low-pass filter 3a of the comparator 10c. In order to reduce the voltage difference, a voltage for increasing / decreasing each of the differential signals Ip and In of the I signal output from the low-pass filter 3a is input, and the low-pass filter 3b of the comparator 10c is input by the calibration DAC 10b. Q signal output from the low-pass filter 3b so that the voltage difference between the differential signals Qp and Qn of the Q signal output from the low-pass filter 3b decreases with respect to the low-pass filter 3b. Differential signals Qp and Qn Inputting the voltage to increase or decrease the voltage.

  The calibration DACs 10a and 10b relatively monotonously increase / decrease in accordance with the n-bit string (n ≧ 2) digital code input from the logic circuit 11, and are the same when the intermediate digital code (10...) Is input. Two analog signals P and N as voltages are generated and output to the low-pass filters 3a and 3b.

  The comparator 10c generates either a high level (1) or low level (0) signal according to the voltage difference between the differential signals Ip and In of the I signal, and similarly, the differential signal of the Q signal. Either a high level (1) signal or a low level (0) signal is generated according to the voltage difference between Qp and Qn and output to the logic circuit 11.

  The logic circuit 11 inputs an intermediate digital code to the calibration DACs 10a and 10b at the start of startup, and outputs analog signals P and N of the same voltage from the calibration DACs 10a and 10b to the low-pass filters 3a and 3b. Thereafter, by using the output (high level “1” or low level “0”) of the comparator 10 c according to the differential signals Ip, In, Qp, Qn from the low-pass filters 3 a, 3 b, the low-pass filters 3 a, An operation of generating a digital code for reducing the voltage difference between the differential signals Ip, In, Qp, and Qn from 3b and inputting the digital code to the calibration DACs 10a and 10b is repeated n times, and generated for the nth time. The digital code is a DC offset correction value between the differential signals Ip and In of the I signal, the Q signal Doshingo Qp, DAC 10A for each calibration as DC offset correction value between Qn, input to 10b.

  For example, the logic circuit 11 moves the position of “1” in the intermediate digital code (10...) From the most significant bit to the lower order bit one lower, and is the previous bit position of the moved “1”. A digital code (* 1...) In which the result * (* = 1 or 0) of the comparator 10c is substituted for the most significant bit is generated, and thereafter, the position of “1” in the previous digital code is sequentially subordinated. , And a digital code is generated by substituting the result * of the previous comparator 10c into the previous bit position of the moved "1".

  Further, the logic circuit 11 can switch the connection between the comparator 10c and the low-pass filters 3a and 3b by inputting a high level (1) or low level (0) CAL_IQSEL signal to the switch circuit.

  Further, the logic circuit 11 inputs the high level (1) or low level (0) CAL_POL signal to the switch circuit, thereby inputting the differential signal Ip of the I signal from the low-pass filter 3a input to the comparator 10c. Each switching of In or switching of the differential signals Qp and Qn of the Q signal from the low-pass filter 3b can be performed. In this way, the differential signal Ip and the differential signal In output from the low-pass filter 3a are switched and input to the comparator 10c, and the differential signal Qp and the differential signal Qn output from the low-pass filter 3b are switched and compared. 10c, an average value of the DC offset correction value obtained before switching and the DC offset correction value obtained after switching is obtained, and this average DC offset correction value is inputted to the calibration DACs 10a and 10b. .

  In addition, the calibration circuit of this example can be operated to start / stop according to the instruction information by inputting the instruction information from the outside, and the differential signals Ip, In of the I signal by the calibration circuit. And the correction values of the differential signals Qp and Qn of the Q signal are output to and stored in an external storage device, so that the calibration instruction for starting the calibration circuit and the differential signal Ip of the I signal are externally stored. , In and the correction value of the Q differential signal Qp, Qn are input, the calibration circuit is activated, and the DC offset between the I signal differential signal Ip, In using the correction value and Q The correction operation of the DC offset between the differential signals Qp and Qn of the signal can be started.

  As described above, the calibration circuit of the present example includes two DACs (calibration DACs 10a, 10a, 10b) that have two voltage outputs that monotonously increase and decrease monotonically according to the digital code and that have the same voltage output in the intermediate code. 10b) and a comparator (comparator 10c) for comparing the differential outputs (P, N) of the LPF, and the input of this comparator (comparator 10c) can be switched. Even if a DC offset occurs in the (comparator 10c), a value obtained by canceling the DC offset in the comparator (comparator 10c) by performing calibration by replacing the input of the comparator (comparator 10c) and obtaining an average value thereof Can be obtained.

  In addition, the calibration operation of this example is automatically executed during the power-on sequence, and the calibration result is directly reflected as a correction value. Therefore, in the FM transmitter of this example, the DC offset adjustment is automatically performed during the power-on sequence. The DC offset between the differential signals generated by the DA converters 2a and 2b and the low-pass filters 3a and 3b due to process variations can be automatically corrected.

  In addition, it is possible to control whether the calibration function of this example is enabled / disabled from an external host via the HOST I / F and REGISTER 9, and the calibration result can be changed to HOST I / F. It is possible to output and record to the host via the REGISTER 9 and to give this calibration value from the host side. As described above, in the FM transmitter of this example, the calibration operation for adjusting the DC offset can be arbitrarily executed from the host. Therefore, the calibration result obtained by the plurality of executions is statistically processed. Thus, an optimum value can be adopted as the calibration value.

  In addition, this invention is not limited to the example demonstrated using FIGS. 1-5, In the range which does not deviate from the summary, various changes are possible. For example, in this example, one comparator 10c is configured to be commonly used by switching the connection to each of the low-pass filters 3a and 3b with a switch circuit. However, two comparators 10c are prepared and the low-pass filter 3a is prepared. , 3b may be used individually.

  In this example, the logic circuit is built in the DSP 1. However, the logic circuit may be provided outside the DSP 1. Also, although the digital code input to the calibration DAC is 6 digits, it may be increased or decreased according to the required accuracy.

It is a block circuit diagram which shows the structural example of FM transmission concerning this invention. FIG. 2 is a block circuit diagram illustrating a configuration example of a calibration circuit in FIG. 1. FIG. 3 is a timing chart illustrating an operation example of the calibration circuit in FIG. 2. It is explanatory drawing which shows the example of an output voltage from the calibration circuit in FIG. FIG. 3 is an explanatory diagram illustrating an example of data used when obtaining an optimum value of calibration set in the calibration circuit in FIG. 2. It is a block circuit diagram which shows the structural example of a general FM transmit.

Explanation of symbols

  1: Digital signal processing circuit (DSP), 1a: STREO GEN, 1b: IQMOD, 2a, 2b: DA converter (DAC), 3a, 3b: low-pass filter (LPF), 4a, 4b: anti-aliasing filter (AAF) 5a, 5b: AD converter (ADC), 6: local oscillator (LOSC), 7: multiplier (MIXER), 8: power amplifier (PA), 9: REGISTER, 10: LPF calibration circuit (LPFCCAL) 10a, 10b: Calibration DAC (CALDAC), 10c: Comparator (CALCMP), 11: Logic circuit (CALCTRL), 61: Digital signal processing circuit (DSP), 61a: STREO GEN, 61b: IQMOD, 62a, 62b : DA converter (DAC ), 63a, 63b: low-pass filter (LPF), 64a, 64b: anti-aliasing filter (AAF), 65a, 65b: AD converter (ADC), 66: local oscillator (LOSC), 67: multiplier (MIXER), 68: Power amplifier (PA), 69: REGISTER, HOST I / F: Host, Lin / Rin: Audio stereo signal, RFout: RF output.

Claims (3)

A first D− that converts the I signal output from the digital signal processing circuit that performs IQ modulation on the input audio stereo signal to convert it to an FM signal, and outputs differential signals Ip and In of the I signal. An A converter, a second DA converter that converts the Q signal output from the digital signal processing circuit into an analog signal and outputs differential signals Qp and Qn of the Q signal, and the first DA A first low-pass filter for removing harmonic components generated by digital-analog conversion of the converter, and a second low-pass filter for removing harmonic components generated by digital-analog conversion of the second DA converter An FM transmitter having at least
The DC offset between the differential signals Ip and In of the I signal and the differential signals Qp and Qn of the Q signal generated in the first and second DA converters and the first and second low-pass filters. A calibration circuit for correcting the DC offset between
The calibration circuit includes a first comparator for comparing voltages of the differential signals Ip and In of the I signal output from the first low-pass filter, and the Q signal output from the second low-pass filter. The I signal output from the first and second low-pass filters according to the comparison result of the second comparator for comparing the voltages of the differential signals Qp and Qn and the first and second comparators. Control means for correcting each of the first and second low-pass filters so that the voltage difference between the differential signals Ip and In and the voltage difference between the differential signals Qp and Qn of the Q signal are reduced. And
The first comparator includes means for outputting either a high level (1) or a low level (0) signal according to the voltage difference between the differential signals Ip and In of the I signal,
The second comparator comprises means for outputting either a high level (1) or a low level (0) signal according to the voltage difference between the differential signals Qp and Qn of the Q signal,
The control means includes
Generates two analog signals P and N that are monotonously increased / decreased relatively according to the input n-bit string (n ≧ 2) digital signal and have the same voltage when the intermediate digital code (10...) Is input. A first converter that outputs to the first low-pass filter;
At the start of startup, the intermediate digital code is input to the first converter, and the analog signals P and N having the same voltage are output from the first converter to the first low-pass filter. Using the output (high level “1” or low level “0”) of the first comparator according to the differential signals Ip and In from the first low-pass filter, the differential from the first low-pass filter An operation of generating a digital code for reducing the voltage difference between the signals Ip and In and inputting the digital code to the first converter is repeated n times, and the digital code generated at the nth time is used as the differential signal of the I signal. A first controller that inputs a DC offset correction value between Ip and In to the first converter;
Two analog signals P and N that are monotonously increased / decreased relatively according to the input digital code of the n-bit string and have the same voltage when the intermediate digital code is input are generated in the second low-pass filter. A second converter for outputting;
At the start of startup, the intermediate digital code is input to the second converter, and analog signals P and N having the same voltage are output from the second converter to the second low-pass filter. Using the output (high level “1” or low level “0”) of the second comparator according to the differential signals Qp and Qn from the second low-pass filter, the differential from the second low-pass filter is used. An operation of generating a digital code for reducing the voltage difference between the signals Ip and In and inputting the digital code to the second converter is repeated n times, and the digital code generated at the nth time is used as the differential signal of the Q signal. An FM transmitter comprising: a second controller that inputs a DC offset correction value between Qp and Qn to the second converter. The first and second comparators consist of one comparator,
First switching means for switching connection between the one comparator and the first and second low-pass filters;
Switching between the differential signals Ip and In of the I signal from the first low-pass filter, or the differential signal Qp of the Q signal from the second low-pass filter, which is input to the one comparator. , Qn, a second switching means for switching each of them,
First DC offset correction value obtained by the first and second controllers before switching by the second switching means, and obtained by the first and second controllers after switching by the second switching means. And a third controller for obtaining an average value of the second DC offset correction value and inputting the obtained average DC offset correction value to the first and second converters. The FM transmitter according to claim 1. It comprises a digital signal processing circuit for filtering input audio signals and converting them into FM signals, and the first, second and third controllers are provided in the digital signal processing circuit. The FM transmitter according to claim 2.

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