JP5269286B2 - Photodetection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a light detection circuit coping with a change in illuminance in the light detection circuit for converting a photocurrent to a frequency according to the level of the photocurrent. <P>SOLUTION: The light detection circuit 1 comprises a first integral circuit IG1 connected to a photodiode PD; a first comparator COMP1 to which the output of the first integral circuit IG1 is inputted; a reset signal generation means 30 for resetting the first integral circuit IG1 according to the output of the first comparator COMP1; and an all reset terminal 100 to which an all reset signal is inputted, where the first integral circuit COMP1 is reset when the switching frequency of the level of signals outputted from the first comparator COMP1 is lower than a prescribed value. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

  The present invention relates to a photodetection circuit.

As described in Patent Document 1, the inventor of the present application converts the charge generated in the photodiode into a voltage via an integration circuit, and then inputs the voltage to a comparator to thereby change the frequency according to the magnitude of the photocurrent. Has been proposed.
JP 2004-325409 A

  However, there is room for improvement in the above-described photodetection circuit, and in particular, in the case of detection in the case of low illuminance, the period during which charge is accumulated in the integration circuit becomes long, so the output signal frequency becomes very low, and the measurement time I found a problem that the credibility of whether or not the signal is low. That is, the comparator output does not change if the charge is not accumulated up to a specified amount even after a long time has passed.

  The present invention has been made in view of such a problem, and an object of the present invention is to provide a photodetection circuit that can cope with a change in illuminance in a photodetection circuit that converts the frequency of a photocurrent.

In order to solve the above-described problem, a photodetection circuit according to the present invention includes a first integration circuit connected to one end of a photodiode, a first comparator to which an output of the first integration circuit is input, and the photodiode A second integration circuit connected to one end; a second comparator to which an output of the second integration circuit is input; and the first and second integrations complementarily in accordance with the outputs of the first and second comparators When the frequency of switching the signal level output from the first comparator and the signal level output from the first comparator is lower than a predetermined value, an all reset signal is generated from the illuminance determination circuit that generates the all reset signal. by the input, the first and provided simultaneously with all reset terminal for resetting the second integrating circuit, the frequency of switching of the signal level output from the first comparator is the predetermined value or less In this case, the frequency at which the signal level is switched is output to measure the repetition frequency of the pulse. When the frequency is lower than the predetermined value, the all reset signal is supplied to the all reset terminal. And a pulse width measurement is performed by outputting a period until the signal level output from the first comparator is switched with a reset timing of the all reset signal as a reference time. To do. The photodetection circuit according to the present invention further includes an output control switch interposed between the reset signal generating means and the output terminal of the photodetection circuit and disconnected by the input of the all reset signal to the all reset terminal. It is characterized by providing.

  When the voltage generated according to the amount of charge accumulated in the first integration circuit exceeds the threshold value of the first comparator, the output of the first comparator is switched. That is, the higher the photocurrent intensity, the shorter the output of the comparator, and when the output of the comparator is switched, the reset signal generating means resets the integrating circuit and starts accumulating charge again. In this way, the photocurrent generated in the photodiode is converted to a frequency corresponding to the magnitude of the photocurrent.

  If the signal level switching frequency output from the first comparator is measured by an externally connected circuit, etc., and this is lower than a predetermined value, for example, if it can be determined that it has become daytime to night, all Input an all reset signal to the reset terminal. The input of the all reset signal means that a signal having a level at which the integration circuit is reset is input.

In the case of low illuminance, since an all reset signal is input, the first and second integration circuits are reset at the same time, and charge accumulation is started using this reset timing as a reference time. That is, since the measurement start time is known, if the period from the time until the output of the first comparator is switched is measured, the measurement can be performed with high reliability even in the case of low illuminance. In other words, when the illuminance decreases and the repetition frequency becomes abnormally low, the measurement is switched from the measurement of the pulse repetition frequency to the measurement of the pulse width.

  The photodetection circuit of the present invention includes a second integration circuit connected to one end of the photodiode, and a second comparator to which an output of the second integration circuit is input. The first and second integrating circuits are reset complementarily according to the output of the second comparator.

  In this case, since the first and second integration circuits are complementarily reset, one of the integration circuits can accumulate charge even in the reset period.

  The all reset terminal is connected to the output line of the reset signal generating means so that the first and second integration circuits are reset simultaneously when the all reset signal is input to the all reset terminal. To do.

  That is, normally, the first and second integration circuits are complementarily reset, but the all reset signal is interposed in the output line of the reset signal generating means, and both the integration circuits are reset simultaneously. The reliability of measurement can be improved.

  The photodetection circuit further includes an output control switch interposed between the reset signal generating means and the output terminal of the photodetection circuit. When an all reset signal is input to the all reset terminal, the output control switch is The all reset terminal and the output control switch are connected so as to be disconnected.

  By providing the output control switch, it is possible to connect a plurality of outputs of the photodetection circuit to one input terminal of a control IC such as a microcomputer. Turn off all output control switches of multiple connected photodetection circuits (set all photodetection circuits connected to the same input terminal to all reset state), or turn on only one output control switch. By controlling, it is possible to read each of the outputs of the present photodetection circuit connected by a plurality of such connections with a control IC such as a microcomputer.

  According to this photodetection circuit, the photodetection circuit that converts the photocurrent into a frequency corresponding to the magnitude of the photocurrent can cope with an illuminance change.

  Hereinafter, the photodetector circuit according to the embodiment will be described. In addition, the same code | symbol shall be used for the same element and the overlapping description is abbreviate | omitted.

  FIG. 1 is a circuit diagram of a photodetection circuit.

  The photodetection circuit 1 includes an integration circuit IG1 connected to the cathode of the photodiode PD.

  The integration circuit IG1 includes a capacitor Cf1 interposed between the output terminal and the inverting input terminal of the operational amplifier OP1, a switch SW10 capable of short-circuiting both ends of the capacitor Cf1, and a gate for connecting / disconnecting an input signal to the operational amplifier OP1. And a switch SW11. A reference potential Vr1 is applied to the non-inverting input terminal of the operational amplifier OP1.

  A signal Q is applied to the gate switch SW11 of the integrating circuit IG1, and when Q is at the H level, the gate switch SW11 is turned on. The short-circuit switch SW10 is supplied with a signal QB (Q bar) complementary to the signal Q. When QB is at the H level, the switch SW10 is turned on.

When resetting the integration circuit IG1, the signal QB is set to H level to turn on the short-circuit switch SW10. To start charge accumulation, the signal Q is set to H level to turn on the gate switch SW11 and the short-circuit switch. SW10 is opened (QB = L level).
An integrating circuit IG1 connected to the cathode of the photodiode PD is provided.

  The photodetection circuit 1 further includes an integration circuit IG2 connected to the cathode of the photodiode PD. The integration circuit IG2 operates complementarily to the integration circuit IG1. That is, during the period in which the integration circuit IG1 is accumulating charge, the integration circuit IG2 is in a reset state, and when the integration circuit IG1 is reset, the integration circuit IG2 is accumulating charge. That is, even during the reset period of one integration circuit, the other integration circuit can accumulate charges, so that the photocurrent can be linearly converted to a frequency according to the magnitude of the photocurrent up to a high frequency. .

  In other words, in the photodetection circuit 1, since the first and second integration circuits IG1 and IG2 are complementarily reset, one of the integration circuits can accumulate charge even in the reset period.

  Normally, the first and second integration circuits IG1 and IG2 are complementarily reset. However, an all reset signal RESET described later is input to the output line of the RS flip-flop 30, and both integration circuits IG1. , IG2 is reset at the same time to improve the reliability of measurement at low illumination. That is, when an all reset signal is input to the all reset terminal 100, the all reset terminal 100 outputs the output lines (NAND2, NAND3) of the RS flip-flop 30 so that the first and second integration circuits IG1, IG2 are reset simultaneously. )It is connected to the.

  The integrating circuit IG2 includes a capacitor Cf2 interposed between the output terminal and the inverting input terminal of the operational amplifier OP2, a switch SW20 capable of short-circuiting both ends of the capacitor Cf2, and a gate for connecting / disconnecting an input signal to the operational amplifier OP2. And a switch SW21. A reference potential Vr1 is applied to the non-inverting input terminal of the operational amplifier OP2.

  When the signal Q is given to the gate switch SW11 of one integration circuit IG1, the signal QB is given to the gate switch SW21 of the other integration circuit IG2. When QB is at the H level, the gate switch SW21 is turned on. The short-circuit switch SW20 is given a signal Q complementary to the signal QB. When Q is at the H level, the switch SW20 is turned on.

  When resetting the integration circuit IG2, the short-circuit switch SW20 is turned on by setting the signal Q to the H level, and when the charge accumulation is started, the gate switch SW21 is turned on by setting the signal QB to the H level. SW20 is opened (Q = L level).

  The photodetection circuit 1 includes a comparator COMP1 to which the output of the integration circuit IG1 is input, and an RS flip-flop 30 that resets the integration circuit IG1 according to the output of the comparator COMP1 (reset signal generation means: input is S terminal) The photocurrent generated in the photodiode PD is converted into a frequency corresponding to the magnitude of the photocurrent.

  When the voltage OUT1 generated according to the amount of charge accumulated in the integrating circuit IG1 exceeds the threshold value Vr2 of the comparator COMP1, the output of the comparator COMP1 is switched from the H level to the L level.

  The photodetection circuit 1 includes a comparator COMP2 to which the output of the other integration circuit IG2 is input, and an RS flip-flop 30 (reset signal generation means: input) that resets the integration circuit IG2 in accordance with the output of the comparator COMP2. R terminal)), and converts the photocurrent generated in the photodiode PD into a frequency corresponding to the magnitude of the photocurrent.

  When the voltage OUT2 generated according to the amount of charge accumulated in the integration circuit IG2 exceeds the threshold value Vr2 of the comparator COMP2, the output of the comparator COMP2 is switched from the H level to the L level.

  That is, the higher the photocurrent intensity, the shorter the comparator output, and when the comparator output is switched, the output (Q, QB) from the RS flip-flop 30 alternately resets the integrating circuit IG1 or IG2 and again. , Start accumulating charge. In this way, the photocurrent generated in the photodiode PD is converted into a frequency corresponding to the magnitude of the photocurrent.

  The RS flip-flop is formed by connecting two NAND circuits (NAND4 and NAND5). In the case of a negative logic input (when the input is 0), the input terminal S = 1, and the input terminal R = 0, The output Q ′ = 0 and the output QB ′ = 1. When the input terminal S = 0 and the input terminal R = 1, the output Q ′ = 1 and the output QB ′ = 0. When the input terminal S = 1 and the input terminal R = 1, the outputs Q ′ and QB ′ are unchanged. The H level is 1 and the L level is 0.

  At the subsequent stage of the RS flip-flop 30, an integration circuit and NAND circuits (NAND2 and NAND3) for measuring timing all reset are connected, and outputs of these circuits are signals Q and QB, respectively, for the integration circuits IG1 and IG2. Input to the switch.

  When an all reset signal ALL RESET (hereinafter referred to as a RESET signal) is input from the all reset terminal 100, an inverted RESET signal (RESET bar) is generated through the inverter I1. The inverted reset signal is input to the output control switch SW1. When the RESET signal is at H level, the inverted reset signal is at L level. At this time, the output control switch SW1 is turned off, and the output of the NAND circuit (NAND1) becomes H level. Since the output of NAND1 passes through the inverter I2, the potential of this line X becomes L level. When the line X is at the L level, the all-reset NAND circuits (NAND2, NAND3) are supplied with the H level signal, the signal Q = QB = H level, and both the integration circuits IG1, IG2 are reset. . In the normal control state, of course, the values of Q and QB are different.

  When the H level RESET signal is input, the H level RESET signal is input to the switch SW2 via the inverters I1 and I3, the S terminal of the SR flip-flop 30 is connected to the ground, and becomes the L level. SR flip-flop 30 is also reset. When the input RESET signal becomes L level, the photodetection circuit output OUTPUT always starts from the same output value (L level).

  The circuit 1 is provided to prevent circuit instability due to Q = QB = L level. That is, when Q = QB = L level, the NAND 6 becomes L level. , X line is set to L level, and Q = QB = H level is operated.

  The output of the RS flip-flop 30 is output to the outside through the inverter I4, NAND circuit (NAND7), inverter I5, and output control switch SW1. Since one of the NANDs 7 normally receives an H level signal, it does not substantially function until the RESET signal becomes H level.

  A transistor TR1 is interposed between the photodiode PD and the integrating circuit IG1 (IG2). A resistance element TR2 is interposed between the transistor TR1 and the photodiode PD. An operational amplifier OP10 is connected to the transistor TR1.

  The operational amplifier OP10 has an output terminal connected to the control terminal (gate) of the N-channel transistor TR1, an inverting input terminal (first input terminal) connected to the node J between the resistance element TR2 and the transistor TR1, and It has a non-inverting input terminal (second input terminal) that is short-circuited to the anode of the photodiode PD.

  Although the photodiode PD has a parasitic capacitance Cd, the output voltage OUT1 (OUT2) in the integration circuit IG1 (IG2) is originally affected by the parasitic capacitance Cd. In the photodetector circuit 1 of the present embodiment, the transistor TR1 is interposed between the photodiode PD and the integrating circuit IG1 (IG2), so that the output voltage OUT1 (OUT2) of the integrating circuit IG1 (IG2) is the parasitic capacitance Cd. It is almost unaffected.

  The output terminal of the operational amplifier OP10 is connected to the control terminal (gate, base) of the transistor TR1, and feedback control is performed on the potential of the node J on the resistance element side of the transistor TR1. This potential is controlled so that the bias voltage of the photodiode PD becomes a zero bias voltage.

  The anode potential of the photodiode PD and the non-inverting input terminal of the operational amplifier OP10 are short-circuited to the ground potential, and the potential of the inverting input terminal of the operational amplifier OP10 is equal to the potential of the non-inverting input terminal of the transistor TR1. Since the control terminal potential is controlled, a zero bias is applied to the photodiode PD.

  The resistance element TR2 is configured by an N-channel transistor. The transistor TR1 and the resistance element TR2 are cascode-connected. The control terminal of the transistor constituting the resistance element TR2 is fixed at a constant potential. This constant potential is composed of a control terminal of the resistance element TR2, a transistor TR3 connected to the control terminal, and a current source IS connected to the transistor TR3. The current source IS can also be configured inside the operational amplifier OP10.

  Between the transistor TR1 and the integration circuit IG1 (IG2), a limiter circuit LM for limiting the current I flowing through the photodiode PD is provided. In this case, since the current input to the integration circuit IG1 (IG2) is limited, the integration circuit IG1 (IG2) can be protected. The limiter circuit LM is controlled by a resistor R10 interposed between the transistor TR1 and the integrating circuit IG1, an operational amplifier OP11 having an inverting / non-inverting input terminal connected between both ends of the resistor R10, and an output of the operational amplifier OP11. A current source IS2, and the current source IS2 is connected to the transistor TR1.

  When the current flowing through the resistor R10 increases and the potential difference generated between the resistors R10 increases, the current is supplied from the current source IS2 so that the current flowing through the resistor R10 decreases.

  FIG. 2 is a timing chart for explaining the operation of the circuit.

  When the all reset signal is at the L level, when light enters the photodiode PD, the photocurrent I flows through the photodiode PD, and when the signal Q is at the H level, accumulation of charge is started in the capacitor Cf1 of the one integration circuit IG1, The output voltage OUT1 rises linearly (a).

  When the output voltage OUT1 exceeds the reference voltage Vr2 of the comparator COMP1, the output of the comparator COMP1 that has been at the H level is inverted and switched to the L level. That is, the L level is input to the S terminal of the negative flip-flop SR flip-flop 30 (b).

  Then, the output of the SR flip-flop 30 is switched, Q becomes L level and QB becomes H level. That is, the capacitor Cf1 of the integration circuit IG1 is short-circuited, reset is performed, and the output voltage OUT1 becomes L level. Therefore, the input voltage to the S terminal returns from the L level to the H level.

  At this time, in the other integration circuit IG2, since Q = L level and QB = H level, charge accumulation is started and the output voltage OUT2 rises linearly (c). When the output voltage OUT2 exceeds the reference voltage Vr2 of the comparator COMP2, the output of the comparator COMP2 is inverted from the H level to the L level, an L level signal is input to the R terminal, and the output of the RS flip-flop 30 is Switch (d). Thereafter, the operation is the same as the operation of the path on the integration circuit IG1 side.

  When the all reset signal is at the H level, the SR flip-flop 30 and the integrating circuits IG1 and IG2 are simultaneously reset, and a photometric operation is newly started (e).

  The all reset signal (H level) is input when the illuminance of light incident on the photodiode PD is low. That is, referring to FIG. 1 again, the photodetection circuit 1 includes an illuminance determination circuit LJ.

  The illuminance determination circuit LJ takes in the pulse signal output from the output terminal OUTPUT, measures the number of pulses within a unit time of the pulse signal, and determines that the illuminance is low when the measured number of pulses is equal to or less than a predetermined value. Then, an H level all reset signal is output to the all reset terminal 100. The illuminance determination circuit LJ is a microcomputer having a ROM in which a program is stored.

  FIG. 3 is a flowchart showing a reset signal generation procedure in the illuminance determination circuit LJ.

First, the signal from the output terminal OUTPUT is measured for X seconds, and the number of pulses in this period is measured. The number of pulses in period X is N (S1). Next, it is determined whether or not the measured pulse number N is greater than or equal to a predetermined value N ₀ , that is, whether or not it is “bright”. When the determination result is Yes, since the frequency measurement of the photocurrent is sufficient for reliability, the measurement result is output to the external device (S5). If the determination result is No, that is, if the surrounding is “dark”, an all reset signal (H level) is output (S3).

  At this time, the output terminal OUTPUT is disconnected from the RS flip-flop 30. That is, the output control switch SW1 is turned off.

By providing the output control switch SW1 , it is possible to connect a plurality of outputs of the photodetection circuit to one input terminal of a control IC such as a microcomputer. Turn off all output control switches of multiple connected photodetection circuits (set all photodetection circuits connected to the same input terminal to all reset state), or turn on only one output control switch. By controlling, it is possible to read each of the outputs of the present photodetection circuit connected by a plurality of such connections with a control IC such as a microcomputer.

  From the falling time of the all reset signal, the output control switch SW1 is turned on and measurement is started. Thereafter, a period from when the all reset signal falls to when the output signal level of the output terminal OUTPUT is switched is measured (S4). This period is proportional to the intensity of light incident on the photodiode PD. Since the photocurrent accumulation period measurement in the dark is sufficient for reliability, the measurement result is output to the external device (S5).

  FIG. 4 is a graph (both logarithm) showing the relationship between illuminance and photometric time.

  As described above, even if the all reset signal is not forcibly input, the accumulation period can be measured if the next integration circuit reset period is reached, but in this case, it is necessary to wait until the next reset period. Don't be.

  When the reset is performed under the condition where the illuminance is low, the photometry time becomes shorter as the illuminance becomes higher, and becomes a constant value when the illuminance becomes higher than a specified value (solid line Reset). Even when reset is not performed, the photometry time becomes shorter as the illuminance increases (dotted line Non-Reset). However, when the reset is not performed, the photometry time becomes longer than when the reset is performed.

  As described above, the photodetector circuit 1 includes the first integration circuit IG1 connected to one end of the photodiode PD, the first comparator COMP1 to which the output of the first integration circuit IG1 is input, and the first When the frequency of switching of the signal level output from the first comparator COMP1 and the RS flip-flop 30 that resets the first integrating circuit IG1 according to the output of the comparator COMP1 is lower than a predetermined value (S2: No ), An all reset terminal 100 to which an all reset signal (H level) for resetting the first integrating circuit IG1 is input.

  When the frequency of switching of the signal level output from the first comparator COMP1 is measured by a circuit connected to the outside, and when this is lower than a predetermined value, for example, when it can be determined that it has become daytime to night, An all reset signal is input to the all reset terminal 100. The all reset signal is a signal at a level at which the integration circuit is reset. In the above example, the all reset signal is an H level signal.

  In the case of low illuminance, an all reset signal is input, so the first integration circuit IG1 is reset, and charge accumulation starts using this reset timing (falling time of the all reset signal in the above example) as a reference time. Is done. That is, since the measurement start time is known, if the period from the time until the output of the first comparator COMP1 is switched is measured, the measurement can be performed with high reliability even in the case of low illuminance. In other words, when the illuminance decreases and the repetition frequency becomes abnormally low, the measurement is switched from the measurement of the pulse repetition frequency to the measurement of the pulse width.

  The present invention can be used for a photodetection circuit.

It is a circuit diagram of a photodetection circuit. It is a timing chart for explaining circuit operation. It is a flowchart which shows the generation | occurrence | production procedure of a reset signal. It is a graph which shows the relationship between illumination intensity and photometry time.

Explanation of symbols

IG1, IG2 ... integration circuit, PD ... photodiode, TR1 ... transistor, TR2 ... resistance element.

Claims (2)

In the light detection circuit,
A first integrating circuit connected to one end of the photodiode;
A first comparator to which an output of the first integrating circuit is input;
A second integrating circuit connected to one end of the photodiode;
A second comparator to which the output of the second integration circuit is input;
Reset signal generating means for resetting the first and second integrating circuits in a complementary manner in accordance with the outputs of the first and second comparators;
When the switching frequency of the signal level output from the first comparator is lower than a predetermined value, an all reset signal is input from an illuminance determination circuit that generates an all reset signal. An all reset terminal for simultaneously resetting the second integrating circuit;
With
When the switching frequency of the signal level output from the first comparator is equal to or higher than the predetermined value, the frequency of switching the signal level is output, thereby measuring the repetition frequency of the pulse,
When the frequency is lower than the predetermined value, the all reset signal is input to the all reset terminal, and the signal level output from the first comparator with a reset timing of the all reset signal as a reference time By outputting the period until switching, pulse width measurement is performed.
An optical detection circuit characterized by that.   2. The output control switch according to claim 1, further comprising an output control switch interposed between the reset signal generating means and the output terminal of the photodetection circuit and disconnected by the input of the all reset signal to the all reset terminal. Light detection circuit.

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