JP5268865B2 - Integrated circuit for image processing and image processing apparatus - Google Patents

Description

  The present invention relates to an image processing integrated circuit capable of executing a plurality of image processing and an image processing apparatus using the same.

  Conventionally, image processing apparatuses such as scanners, printers, digital copiers, and multi-functional peripherals use dedicated image processing integrated circuits (ASICs) to execute image processing at high speed. Such image processing devices have different image processing contents, for example, the amount of image data to be processed, depending on the product specifications. There was a need to design. However, the development cost and design cost of the integrated circuit are extremely expensive and take a long time to develop, which increases the development cost of the image processing apparatus and prolongs the development lead time.

  Therefore, for example, when the image processing content is changed by executing image processing using a plurality of general-purpose image processing units such as DSP (Digital Signal Processor), the number of general-purpose image processing units is increased or decreased. A technique is known in which the system is made to have versatility and flexibility by adjusting (see, for example, Patent Document 1).

JP 2005-323159 A

  However, when a plurality of general-purpose image processing units are used as described above, the image processing unit is not optimized for the target image processing as compared with a dedicated image processing integrated circuit made by optimizing the desired image processing content. For this reason, there is a disadvantage that the processing is wasted and it is difficult to obtain performance, or the circuit scale is increased including unnecessary circuits, resulting in a higher cost than the dedicated image processing integrated circuit.

  An object of the present invention is to provide an image processing integrated circuit that can easily cope with a change in image processing contents without re-developing and designing an element, and an image processing apparatus using the same.

An integrated circuit for image processing according to the present invention includes:
An image data acquisition unit for acquiring image data from the outside;
A first image processing unit that performs first image processing on image data to be processed;
A second image processing unit 1 and a second image processing unit 2 that perform second image processing different from the first image processing on the image data to be processed;
A first memory including at least a first memory 1 and a first memory 2 used for the first image processing by the first image processing unit;
A second memory 1 used for the second image processing by the second image processing unit 1;
A second memory 2 used for the second image processing by the second image processing unit 2;
A setting accepting unit that accepts a mode setting instruction for a normal mode for executing the first image processing and an extended mode for not executing the first image processing;
When a mode setting instruction for instructing the normal mode is received by the setting reception unit, the image data acquired by the image data acquisition unit is supplied to the first image processing unit as image data to be processed, and the first In a normal mode in which the data subjected to the first image processing by one image processing unit is supplied to at least one of the second image processing unit 1 and the second image processing unit 2 as image data to be processed. When the mode setting instruction for setting and instructing the extended mode is received by the setting receiving unit, the image data acquired by the image data acquiring unit is used as the second image processing unit 1 and the second image processing unit 2. And the first memory 1 is integrated with the second memory 1 by the second image processing unit 1. Let used to image processing, the first memory 2, and the second memory 2 and a control unit for setting the enhanced mode that makes use in the second image processing by integrally the second image processing section 2 is one It is configured to be integrated into one element.

  According to this configuration, when the mode setting instruction for instructing the normal mode is received by the setting receiving unit, the image data acquired by the image data acquiring unit is supplied to the first image processing unit as image data to be processed. The Then, the data subjected to the first image processing by the first image processing unit using the first memory is supplied as image data to be processed to at least one of the second image processing units, and the second image The second image processing is executed using the second memory by at least one of the processing units.

Then, when changing the image processing content, the image data acquired by the image data acquiring unit is input to at least one of the second image processing units by inputting a mode setting instruction for the extended mode to the setting receiving unit. And at least a part of the first memory is used for the second image processing by the at least one second image processing unit together with the second memory, so that the memory capacity usable in the second image processing is increased. Will be increased. As described above, even when the memory capacity required for the second image processing is increased due to the change of the image processing content, the memory capacity usable in the second image processing is increased in the expansion mode. Therefore, it becomes easy to execute the second image processing corresponding to the change of the image processing content without re-developing and designing the image processing integrated circuit.
According to this configuration, in the expansion mode, the first memory is used by being distributed to the plurality of second image processing units, and the memory capacity usable in the plurality of second image processing units is increased. Even if the memory capacity required for the second image processing is increased due to the change in the processing content, a plurality of image processing contents can be changed in accordance with the change in the image processing content without re-development and design of the integrated circuit for image processing. It is easy to execute the second image processing. In this case, since the image processing integrated circuit can execute a plurality of image processing even in the expansion mode, there is an effect that the image processing integrated circuit can be used when the image processing content is changed. Increase.

The second image processing unit 1 and the second image processing unit 2 are
Different image processing is sequentially executed as the second image processing,
The controller is
In the extended mode, the image data acquired by the image data acquisition unit is sent to a processing unit that executes image processing first among the two processing units of the second image processing unit 1 and the second image processing unit 2. It is preferable to supply .

  According to this configuration, in the extended mode, the image data acquired by the image data acquisition unit is sequentially subjected to different image processing by the plurality of second image processing units. Therefore, it is suitable for an application that requires a plurality of types of image processing on image data.

The image data acquisition unit, the first image processing unit, the second image processing unit 1, the second image processing unit 2, and a switching unit that switches a connection relationship between the first memories.
The controller is
When a mode setting instruction for instructing the normal mode is received by the setting receiving unit, the switching unit performs the image data acquisition unit, the first image processing unit, and the first image processing unit and the second image. By connecting at least one of the processing unit 1 and the second image processing unit 2 and connecting the first memory to the first image processing unit so as to be accessible, the normal mode is set.
When the setting accepting unit accepts a mode setting instruction for instructing the extended mode, the switching unit accepts at least one of the image data acquiring unit, the second image processing unit 1 and the second image processing unit 2. And the first memory 1 is connected to the second memory 1 so as to be accessible from the second image processing unit 1, and the first memory 2 is accessible from the second image processing unit 2. It is preferable to set the expansion mode by connecting to the second memory 2 .

  According to this configuration, when the mode setting instruction for instructing the normal mode is received by the setting receiving unit, the control unit is configured to switch the image data acquisition unit, the first image processing unit, and the first image processing unit by the switching unit. By connecting at least one of the second image processing units, the image data acquired by the image data acquiring unit is supplied to the first image processing unit as image data to be processed, and the first image processing unit Thus, the data subjected to the first image processing is supplied as image data to be processed to at least one of the second image processing units. At this time, the control unit causes the switching unit to connect the first memory to the first image processing unit so that the first memory can be accessed, so that the first image processing unit executes the first image processing using the first memory. Is possible.

  When the mode accepting instruction for instructing the extended mode is accepted by the setting accepting unit, the control unit causes the switching unit to connect the image data obtaining unit and at least one of the at least one second image processing unit. Thus, the image data acquired by the image data acquisition unit is supplied to at least one of the second image processing units. At this time, since the control unit causes the switching unit to connect the first memory to at least one second image processing unit, the second image processing unit uses the first and second memories to perform the second operation. It is possible to execute the image processing.

  The first image processing is preferably shading processing.

  According to this configuration, the shading process is first performed on the image data acquired by the image data acquisition unit in the normal mode, and the shading process is not executed in the extended mode.

  Further, it is preferable that the second image processing includes error diffusion.

  According to this configuration, the second image processing unit executes error diffusion using the second memory in the normal mode, and executes error diffusion using at least a part of the first memory together with the second memory in the extended mode. Therefore, the memory capacity that can be used for error diffusion can be increased in the extended mode.

  The second image processing preferably includes compression processing.

  According to this configuration, the second image processing unit executes the compression process using the second memory in the normal mode, and executes the compression process using at least a part of the first memory together with the second memory in the extended mode. Therefore, the memory capacity that can be used for the compression processing can be increased in the expansion mode.

  In addition, an image processing apparatus according to the present invention acquires the above-described image processing integrated circuit, a document image acquisition unit that acquires image data representing an image of a document, and transmits the image data to the image data acquisition unit, and the setting reception unit. And a mode setting unit for setting a mode setting instruction for instructing the normal mode.

  According to this configuration, the image processing integrated circuit is set to the normal mode. Then, the first image processing and the second image processing are performed on the image data acquired by the document image acquisition unit by the image processing integrated circuit.

  In addition, an image processing apparatus according to the present invention provides an image processing integrated circuit, a document image acquisition unit that acquires image data representing an image of a document, and image data acquired by the document image acquisition unit. An external image processing unit that performs third image processing and transmits the image data to the image data acquisition unit, and a mode setting unit that sets a mode setting instruction to instruct the extension mode to the setting reception unit.

  According to this configuration, the image processing integrated circuit is set to the expansion mode. Then, the third image processing is performed on the image data acquired by the document image acquisition unit by the external image processing unit, and the image processing integration is performed on the image data on which the third image processing is performed. A second image process is performed by the circuit. At this time, in the extended mode, the memory capacity that can be used by the second image processing unit for the second image processing is increased as compared with the normal mode. 2 image processing can be performed.

  When the image processing integrated circuit and the image processing apparatus having such a configuration change the image processing content, the image data acquisition unit inputs the mode setting instruction of the extended mode to the setting reception unit. The acquired image data is supplied to at least one of the second image processing units, and the first memory is used together with the second memory for the second image processing by the at least one second image processing unit. The memory capacity that can be used in the second image processing is increased. As described above, even when the memory capacity required for the second image processing is increased due to the change of the image processing content, the memory capacity usable in the second image processing is increased in the expansion mode. Therefore, it becomes easy to execute the second image processing corresponding to the change of the image processing content without re-developing and designing the image processing integrated circuit.

1 is a side view schematically illustrating an internal configuration of a multifunction peripheral that is an example of an image processing apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating an example of an electrical configuration of the multifunction machine illustrated in FIG. 1. It is a block diagram which shows an example of a structure of the image process part shown in FIG. It is a block diagram which shows an example of a structure of the image process part shown in FIG.

  Embodiments according to the present invention will be described below with reference to the drawings. In addition, the structure which attached | subjected the same code | symbol in each figure shows that it is the same structure, The description is abbreviate | omitted. FIG. 1 is a side view schematically showing an internal configuration of a multifunction peripheral as an example of an image processing apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating an example of an electrical configuration of the multifunction machine 1 illustrated in FIG.

  Note that the image processing apparatus is not limited to a multifunction peripheral, and may be, for example, a copying machine, a printer, a facsimile machine, a scanner apparatus, or the like.

  The multifunction device 1 has functions such as a copy function, a printer function, a scanner function, and a facsimile function. The multi-function device 1 includes a main body 2, a stack tray 3 disposed on the left side of the main body 2, a document reading unit 5 (document image acquisition unit) disposed on the top of the main body 2, and a document The document feeding unit 6 disposed above the reading unit 5 and the apparatus control unit 100 disposed inside the main body unit 2 are provided. In addition, a substantially rectangular operation panel 47 is provided at the front portion of the multifunction machine 1.

  The document reading unit 5 includes a scanner unit 51 including a CCD (Charge Coupled Device) 512, an exposure lamp 511, and the like, and a document table 52 and a document reading slit 53 made of a transparent member such as glass. The scanner unit 51 is configured to be movable by a drive unit (not shown). When reading a document placed on the document table 52, the scanner unit 51 is moved along the document surface at a position facing the document table 52, and the document image is scanned. The image data acquired while scanning is output to an image processing unit 8 described later.

  Further, when reading the document fed by the document feeding unit 6, the document reading unit 5 is moved to a position facing the document reading slit 53, and the document by the document feeding unit 6 is passed through the document reading slit 53. The image of the document is acquired in synchronization with the transport operation, and the image data is output to the image processing unit 8 described later.

  The document feeding unit 6 includes a document placing unit 61 for placing a document, a document discharge unit 62 for discharging a document whose image has been read, and a document placed on the document placing unit 61. A document transport mechanism 63 including a paper feed roller (not shown), a transport roller (not shown) and the like for feeding the paper one by one to a position facing the document reading slit 53 and discharging it to the document discharge section 62 is provided. The document conveyance mechanism 63 further includes a sheet reversing mechanism (not shown) that reverses the document and reversely conveys the document to a position facing the document reading slit 53, and scans both sides of the document through the document reading slit 53. 51 can be read.

  The document feeding unit 6 is provided so as to be rotatable with respect to the main body unit 2 so that the front side thereof can move upward. By moving the front side of the document feeder 6 upward to open the upper surface of the document table 52, the user can place a read document, such as a book in a spread state, on the upper surface of the document table 52. ing.

  The main body 2 includes a plurality of paper feed cassettes 461, a paper feed roller 462 that feeds the recording paper from the paper feed cassette 461 one by one and conveys the recording paper to the recording unit 40, and the recording paper carried out of the paper feed cassette 461. And a recording unit 40 for forming an image.

  The recording unit 40 forms a toner image on the optical unit 42, the photoconductive drum 43, and the photoconductive drum 43 that outputs a laser beam or the like based on the image data acquired by the scanner unit 51 and exposes the photoconductive drum 43. An image forming unit 412 including a developing unit 44 and a transfer unit 41 that transfers the toner image on the photosensitive drum 43 to the recording paper, and the recording paper to which the toner image has been transferred are heated to fix the toner image on the recording paper. A fixing unit 45 and a paper transport unit 411 that is provided in a paper transport path in the recording unit 40 and includes transport rollers 463, 464, and the like that transport the recording paper to the stack tray 3 or the discharge tray 48.

  Referring to FIG. 2, the multi-function device 1 further includes an image processing unit 8, an image memory 140, a facsimile communication unit 170 (original image acquisition unit), a network I / F unit 210 (original image acquisition unit), a parallel I / F. An F unit 181 (original image acquisition unit), a serial I / F unit 182 (original image acquisition unit), and an HDD (Hard Disk Drive) 150 are provided, and the operations of these units are controlled by the apparatus control unit 100.

  The image processing unit 8 converts an analog image signal output from the scanner unit 51 into a digital image when the document is read by the scanner unit 51, performs image processing for improving image quality, and then converts the image into a compressed image. This compressed image is stored in the image memory 140. The apparatus control unit 100 stores the compressed image stored in the image memory 140 in the HDD 150 as data constituting a file to be document managed.

  At the time of printout, image data (compressed image) stored in the image memory 140 is expanded by, for example, the image processing unit 8, and further an exposure control signal for performing exposure by the optical unit 42, for example, a laser emitted from the exposure apparatus It is converted into an exposure control signal for controlling the light beam. The recording unit 40 prints out based on this control signal.

  The device control unit 100 controls the operation of the entire device. For example, a CPU (Central Processing Unit) that executes predetermined arithmetic processing, a ROM (Read Only Memory) that stores a predetermined control program, and data A RAM (Random Access Memory) that is temporarily stored and peripheral circuits thereof are configured. By executing a control program stored in the ROM, a scanner controller 101, a facsimile controller 102, a printer controller 103, It functions as a copy controller 104 and a network controller 105.

  The scanner controller 101 controls the operation of each unit necessary for the operation of the scanner unit. For example, the scanner controller 101 causes the document reading unit 5 to read an image of a document to acquire image data, causes the image processing unit 8 to perform image processing on the image data, and stores the image data in the image memory 140 or the HDD 150. Thus, the multifunction device 1 is caused to function as a scanner device.

  The copy controller 104 generates an exposure control signal in the image processing unit 8 based on the image data stored in the image memory 140 or the HDD 150 by the same processing as the scanner controller 101, and transmits the exposure control signal to the recording unit 40, so that the image on the sheet is printed. Let the formation take place. Thus, the multifunction device 1 is caused to function as a copying apparatus.

  The facsimile controller 102 controls the operation of each unit necessary for the facsimile operation, and controls the facsimile communication unit 170 that adjusts data necessary for facsimile communication. The facsimile communication unit 170 is provided with an NCU (Network Control Unit) that controls connection of a telephone line with a destination facsimile that is a data transmission / reception partner.

  The facsimile communication unit 170 is an example of a document image acquisition unit. The facsimile communication unit 170 receives image data representing an image of a document transmitted from a partner facsimile via a telephone line, and outputs the image data to the image processing unit 8.

  The printer controller 103 performs operation control of each unit necessary for printer operation. The printer controller 103 includes a parallel I / F unit 181 that is connected to an external device by parallel transmission that transmits several bits at a time using a plurality of signal lines, and one bit at a time using a single signal line. A serial I / F unit 182 connected to an external device by serial transmission for sending data is connected.

  Each of the parallel I / F unit 181 and the serial I / F unit 182 is an example of a document image acquisition unit, receives image data representing an image of a document from an external device, and outputs the image data to the image processing unit 8.

  The network controller 105 controls transmission / reception of data to / from an external device on the network connected via the network I / F unit 210, for example, a PC (personal computer) or a site (server) on the Internet. It is. The network I / F unit 210 is an example of a document image acquisition unit, receives image data representing an image of a document from an external device connected to the network, and outputs the image data to the image processing unit 8.

  FIG. 3 is a block diagram showing an example of the configuration of the image processing unit 8 shown in FIG. The image processing unit 8 shown in FIG. 3 includes an image processing integrated circuit 80 and an AFE (analog front end) circuit 81 according to an embodiment of the present invention.

  The AFE circuit 81 samples the image signal output from the CCD 512 for each pixel, converts it to a digital value, and outputs it to the image processing integrated circuit 80 as image data for each line.

  The image processing integrated circuit 80 includes, for example, a shading circuit 801 (first image processing unit), an error diffusion circuit 802 (second image processing unit), a compression circuit 803 (second image processing unit), a control unit 804, and a line memory. 811 (first memory), line memory 812 (second memory), line memory 813 (second memory), switching units 821, 822, 823, 824, 825, image input terminal 826 (image data acquisition unit), image output A terminal 827 and a mode setting terminal 828 (setting receiving unit) are ASICs (Application Specific Integrated Circuits) integrated on one chip.

  The image input terminal 826 is connected to the AFE circuit 81 and accepts input of image data output from the AFE circuit 81. The image input terminal 826 is connected to the shading circuit 801 via the switching unit 821, and the shading circuit 801 is connected to the error diffusion circuit 802 via the switching unit 822. The error diffusion circuit 802 is connected to the compression circuit 803, and the compression circuit 803 is connected to the image output terminal 827.

  The image output terminal 827 is connected to the image memory 140, and the image data output from the compression circuit 803 is stored in the image memory 140.

  In FIG. 3, a circuit that reads out and decompresses compressed image data from the image memory 140 and generates an exposure control signal is omitted.

  A line memory 812 is connected to the error diffusion circuit 802, and a line memory 813 is connected to the compression circuit 803. In addition, a line memory 811 is connected to the shading circuit 801 via a switching unit 823.

  The line memory 811 includes a memory block A and a memory block B that can be independently accessed. The memory block A is connected to the line memory 812 via the switching unit 824, and the memory block B is connected to the line memory 813 via the switching unit 825.

  The line memories 811, 812, and 813 are RAMs configured to store image data for one line, for example. The first and second memories are not necessarily limited to line memories, and may be memories used for the first and second image processing, respectively.

  The line memory 811 is divided into two blocks, a memory block A and a memory block B, and each block can be accessed as an independent memory. The line memory 812 is connected to the error diffusion circuit 802 to be accessible, and the line memory 813 is connected to the compression circuit 803 to be accessible.

  The shading circuit 801 is an image processing circuit that reduces density unevenness of image data in the main scanning direction by performing shading correction on the image data read by the document reading unit 5 for each line.

  The document reading unit 5 causes the CCD 512 to read the image of the document line by line in the main scanning direction. The image data acquired by the CCD 512 includes, for example, the light distribution characteristics of the exposure lamp 511 and each pixel of the CCD 512. Due to characteristic variation or the like, there is a case where the density of pixels arranged in the main scanning direction varies, resulting in density unevenness.

  Thus, for example, each pixel necessary for causing the CCD 512 to read an image of a white reference plate having a uniform density and adjusting the density value of each pixel in the obtained image data for one line to the reference white density. These correction values (coefficients) are calculated in advance and stored in advance in a storage unit such as the image memory 140 as a shading correction value.

  Then, the shading circuit 801 converts, for example, the shading correction value of each pixel stored in the image memory 140 into the density value of each pixel in one line of image data input from the AFE circuit 81 to the image input terminal 826. Shading correction is performed by multiplying each. The image data for one line after shading correction obtained in this way is stored in the line memory 811.

  Then, the shading circuit 801 outputs the image data after shading correction stored in the line memory 811 to the error diffusion circuit 802 via the switching unit 822 in response to a control signal from the control unit 804, for example.

  As described above, since the shading correction is performed for each line, the line memory 811 needs to have a capacity capable of storing image data for at least one line. For example, the line memory 811 is configured to store a plurality of lines. May be.

  The error diffusion circuit 802 is an image processing circuit that performs image processing by the error diffusion method on the image data that has been subjected to the shading correction by the shading circuit 801. An electrophotographic image forming apparatus and an ink jet image forming apparatus cannot freely change the density of one dot according to the density value of a pixel. For example, halftones such as gray until the color changes from white to black are expressed by the black and white dot density per area of the image, and the image is recognized as if it is an image with a smooth change.

  As described above, the error diffusion method is an image process for converting image data in which each pixel has multi-tone density values into image data in which halftones are expressed by binarized data indicating the presence or absence of dots. is there. Specifically, in the error diffusion method, the difference (binarization error) between the density before conversion of the target pixel and the pixel density after binarization is distributed to the image signal of the pixel to be binarized thereafter. Thus, when viewed in a wide range, the average gradation of the binary image is brought close to the gradation of the multi-valued image.

  Then, the error diffusion circuit 802 performs image processing by such an error diffusion method on either the image data subjected to the shading process in the shading circuit 801 or the image data received by the image input terminal 826. This is executed using the line memory 812.

  Then, in the previous process of the error diffusion circuit 802, image processing is executed for each line. Therefore, in order to accept the image data executed in the previous process, the line memory 812 has image data for at least one line. For example, it may be configured to have a storage capacity for a plurality of lines.

  The compression circuit 803 compresses the image data that has been subjected to the error diffusion processing by the error diffusion circuit 802 in a compression format such as JPEG (Joint Photographic Expert Group) or MMR (Modified Modified Read). Is stored in the image memory 140 connected to the. The compression circuit 803 executes the compression process using the line memory 813.

  Then, in the error diffusion circuit 802, which is a pre-process of the compression circuit 803, image processing is executed in units of one line (or a plurality of lines) using the line memory 812 having a capacity for one line (or a plurality of lines). Therefore, in order to accept the image data executed in the previous process, the line memory 813 needs to have a capacity capable of storing image data for one line (or a plurality of lines).

  The switching units 821, 822, 823, 824, and 825 are switching circuits that switch the connection relationship among the image input terminal 826, the shading circuit 801, the error diffusion circuit 802, and the line memories 811 812, and 813. In FIG. 3, the switching units 821, 822, 823, 824, and 825 are conceptually described with graphic symbols of switching elements for easy understanding, but the switching units 821, 822, 823, 824, and 825 are illustrated. For example, a multiplexer, a selector circuit, or the like can be used.

  Alternatively, as the switching units 823, 824, and 825, for example, an access control circuit that controls access to the line memory 811 (memory block A, memory block B) is used, for example, the line memory 811 (memory block A, memory block B). By functionally changing the image processing circuit that can access the line memory 811 (memory block A, memory block B) functionally by means such as changing the address where the memory is arranged, the line memory 811 (memory block A, memory block B) and the connection relationship between the shading circuit 801, the error diffusion circuit 802 (line memory 812), and the compression circuit 803 (line memory 813) may be switched.

  In the following description, for example, the switching units 821, 822, 823, 824, and 825 are represented as expressions including concepts such as switching of data input / output paths by a multiplexer, a selector circuit, and the like, and switching of accessibility by access control. , Switched or connected (accessible), disconnected (not accessible).

  The switching unit 821 connects the image input terminal 826 and the shading circuit 801 in accordance with a control signal from the control unit 804 and supplies the image data received by the image input terminal 826 to the shading circuit 801. The terminal 826 and the shading circuit 801 are disconnected to switch whether the image input terminal 826 and the switching unit 822 are connected.

  The switching unit 822 connects the shading circuit 801 and the error diffusion circuit 802 in accordance with a control signal from the control unit 804 and supplies the image data output from the shading circuit 801 to the error diffusion circuit 802 or the switching unit. 821 and the error diffusion circuit 802 are connected to switch whether image data obtained from the image input terminal 826 via the switching units 821 and 822 is supplied to the error diffusion circuit 802.

  The switching unit 823 connects or disconnects the line memory 811 in which the memory block A and the memory block B are connected to the shading circuit 801 in accordance with a control signal from the control unit 804.

  The switching unit 824 connects or disconnects the line memory 812 and the memory block A in accordance with a control signal from the control unit 804. The memory block A connected to the line memory 812 can be accessed from the error diffusion circuit 802 as an integral line memory connected to the line memory 812.

  The switching unit 825 connects or disconnects the line memory 813 and the memory block B in accordance with a control signal from the control unit 804. The memory block B connected to the line memory 813 can be accessed from the compression circuit 803 as an integral line memory connected to the line memory 813.

  The control unit 804 controls the operation of the switching units 821, 822, 823, 824, and 825 according to the instruction signal received by the mode setting terminal 828. Specifically, when the mode setting terminal 828 is set to a low level, for example, as a mode setting instruction for instructing the normal mode, the control unit 804 sets the image input terminal 826 and the shading circuit 801 by the switching unit 821 as the normal mode. The switching unit 822 connects the shading circuit 801 and the error diffusion circuit 802, the switching unit 823 connects the line memory 811 to the shading circuit 801, and the switching units 824 and 825 connect the line memory 812 and line memory. 813 is separated from memory block A and memory block B.

  In the image processing unit 8 shown in FIG. 3, the mode setting terminal 828 is connected to the circuit ground via the wiring 82 and is set to the low level. In this case, the wiring 82 corresponds to an example of a mode setting unit that instructs the normal mode.

  As a result, the control unit 804 sets the normal mode. FIG. 3 shows a state in which the switching units 821, 822, 823, 824, and 825 are set to the normal mode.

  As described above, in the image processing integrated circuit 80 set to the normal mode, the shading circuit 801 uses the line memory 811 to perform the shading process on the image data input from the AFE circuit 81 to the image input terminal 826. Since the error diffusion circuit 802 performs error diffusion processing using the line memory 812 and the compression circuit 803 performs compression processing using the line memory 813, a plurality of image processing such as shading, error diffusion, and compression are optimized. It can be executed by a dedicated circuit.

  Therefore, it is easy to improve the performance compared to the case where a plurality of general-purpose image processing units are used as in the background art, and the possibility of increasing the circuit scale including unnecessary circuits can be reduced. Easy.

  Incidentally, as described above, the line memories 811, 812, and 813 of the image processing integrated circuit 80 need to have a storage capacity for at least one line. For example, in an image processing apparatus that is designed to read a document image of A4 size or smaller, the line memories 811, 812, and 813 may have a storage capacity for one line in the A4 size. Accordingly, the line memories 811, 812, and 813 have a storage capacity for one line in the A4 size (or storage capacity for a plurality of lines in the A4 size), for example.

  Then, if the image processing integrated circuit 80 is used in an image processing apparatus that is designed to read an A3 size document image that is larger than the A4 size, for example, the storage capacity of the line memories 811 812, and 813 will be insufficient. . Conventionally, in such a case, it is necessary to newly design and manufacture an integrated circuit for image processing. Even when it is desired to change the processing content of the shading circuit 801, it is necessary to newly design and manufacture the image processing integrated circuit.

  However, even in such a case, the image processing integrated circuit 80 shown in FIG. 3 can cope with switching the mode setting without newly designing and manufacturing the image processing integrated circuit. It is.

  FIG. 4 is a block diagram showing an example of the configuration of the image processing unit 8a in the case where the image processing integrated circuit 80 is used in an image processing apparatus having a specification for reading a document image having a large size such as an A3 size document image. Such an image processing apparatus can be realized by using, for example, the image processing unit 8a shown in FIG. 4 instead of the image processing unit 8 shown in FIG. 3 as the image processing unit 8 shown in FIG.

  The image processing unit 8a illustrated in FIG. 4 includes an image processing integrated circuit 80, an AFE circuit 81, and an image processing circuit 83 (external image processing unit). The mode setting terminal 828 of the image processing integrated circuit 80 is connected to the circuit power supply via the wiring 82a, and the mode setting terminal 828 is set to the high level.

  The AFE circuit 81 illustrated in FIG. 4 outputs, for example, image data indicating an image for each line of A3 size to the image processing circuit 83.

  The image processing circuit 83 is configured using, for example, an FPGA (Field Programmable Gate Array), and includes a shading circuit 831 and a line memory 832 connected to be accessible from the shading circuit 831. The line memory 832 has a larger storage capacity than the line memory 811, and has a storage capacity for one line of, for example, A3 size.

  The shading circuit 831 uses the line memory 832 to execute shading processing on the image data output from the AFE circuit 81, for example, for each line of A3 size. The shading process performed by the shading circuit 831 may be the same as the shading circuit 801 or may be performed by a method different from the shading circuit 801.

  Further, the image processing circuit 83 may include an image processing circuit that performs image processing different from shading instead of the shading circuit 831. In this way, the image processing integrated circuit 80 can be provided with an arbitrary image processing circuit in place of the shading circuit 831 by setting the expansion mode, so that the image processing integrated circuit 80 is designed. It is easy to change the image processing content of the image processing unit 8a without changing.

  The image processing unit 8a configured as described above first outputs, for example, image data for one line of A3 size from the AFE circuit 81, and the shading circuit 831 performs shading on the image data. At this time, since the line memory 832 has a larger storage capacity than the line memory 811, it is possible to perform shading on image data having a document size larger than that of the image processing unit 8.

  In the image processing integrated circuit 80, the mode setting terminal 828 is connected to the circuit power supply via the wiring 82a and is set to the high level. In this case, the wiring 82a corresponds to an example of a mode setting unit that instructs an expansion mode.

  For example, when the mode setting terminal 828 is set to a high level as a mode setting instruction for instructing the expansion mode, the control unit 804 connects the image input terminal 826 and the switching unit 822 with the switching unit 821 as the expansion mode. 822 connects the switching unit 821 (image input terminal 826) and the error diffusion circuit 802, the switching unit 823 disconnects the line memory 811 from the shading circuit 801, and the switching unit 824 connects the line memory 812 and the memory block A. And the line memory 813 and the memory block B are connected by the switching unit 825.

  As a result, the control unit 804 sets the extended mode. FIG. 4 shows a state in which the switching units 821, 822, 823, 824, and 825 are set to the expansion mode.

  As described above, in the image processing integrated circuit 80 set to the extended mode, the error diffusion circuit 802 is connected to the line memory 812, the memory block A, and the image data input from the image processing circuit 83 to the image input terminal 826. An error diffusion process is performed using a line memory comprising: In this case, the capacity of the line memory that can be used by the error diffusion circuit 802 is the combined capacity of the line memory 812 and the memory block A. Therefore, even for image data larger than that in the normal mode, for example, A3 size image data A diffusion process can be performed.

  Next, the compression circuit 803 applies compression processing to the image data subjected to error diffusion by the error diffusion circuit 802 using a line memory including the line memory 813 and the memory block B, and then stores it in the image memory 140. Let In this case, the capacity of the line memory that can be used by the compression circuit 803 is the combined capacity of the line memory 813 and the memory block B. Therefore, even image data larger than that in the normal mode, for example, A3 size image data is compressed. Can be applied.

  In the image processing unit 8a, the image processing circuit 83 does not need to perform a plurality of image processings unlike the image processing integrated circuit 80, so that the circuit scale can be made smaller than that of the image processing integrated circuit 80. For example, an FPGA is used. It is easy to configure. Since the FPGA can freely program the circuit, the FPGA does not require a period and cost required for newly designing and manufacturing a dedicated integrated circuit such as an ASIC.

  The image processing integrated circuit 80 can increase the storage capacity of the line memory that can be used by the error diffusion circuit 802 and the compression circuit 803 by switching from the normal mode to the expansion mode. Even when it is necessary to increase the storage capacity of the line memory in order to use the integrated circuit 80 for different models of the image processing apparatus, a newly designed integrated circuit for image processing with an increased storage capacity of the line memory, The period and cost required for manufacturing are unnecessary.

  Further, the image processing integrated circuit 80 switches to the expansion mode, thereby disconnecting the shading circuit 801 that is an image processing circuit that performs image processing first, and external image processing such as the image processing circuit 83 provided outside. The image data processed by the image processing unit can be image-processed by the second and subsequent image processing circuits, for example, the error diffusion circuit 802 and the compression circuit 803, so that an image processing integrated circuit is not newly designed and manufactured. It is easy to change the image processing performed first.

  In addition, although the example which uses the shading circuit 801 was shown as a 1st image process part which performs an image process initially, a 1st image process part is not restricted to what performs a shading, It performs other image processes. There may be. Moreover, although the example provided with the error diffusion circuit 802 and the compression circuit 803 was shown as a 2nd image process part, the 2nd image process part may be one and may be three or more. Further, the processing content of the second image processing unit is not limited to error diffusion or compression processing.

  Further, although an example in which a plurality of second image processing units are connected in series to sequentially form an image has been shown, a plurality of second image processing units are connected in parallel, and the switching unit 822 causes the shading circuit 801 or the image input terminal 826 to be connected. The image data output from any of the above may be distributed and supplied to each second image processing unit.

  Further, instead of the output data of the AFE circuit 81 in FIGS. 3 and 4, image data acquired by the facsimile communication unit 170, the parallel I / F unit 181, the serial I / F unit 182, and the network I / F unit 210. May be used.

  Further, the image data output from the image output terminal 827 is not necessarily limited to the example output to the image memory 140, and may be configured such that image processing is performed by another image processing circuit, for example.

DESCRIPTION OF SYMBOLS 1 Multifunctional device 2 Main body part 5 Original reading part 8, 8a Image processing part 40 Recording part 42 Optical unit 43 Photosensitive drum 51 Scanner part 52 Original stand 53 Original reading slit 80 Integrated circuit for image processing 81 AFE circuit 82, 82a Wiring 83 Image processing circuit 100 Device control unit 140 Image memory 170 Facsimile communication unit 181 Parallel I / F unit 182 Serial I / F unit 210 Network I / F unit 412 Image forming unit 511 Exposure lamp 512 CCD
801 Shading circuit 802 Error diffusion circuit 803 Compression circuit 804 Control unit 811, 812, 813 Line memory 811a First memory block 811b Second memory block 821, 822, 823, 824, 825 switching unit 826 Image input terminal 827 Image output terminal 828 Mode setting terminal 831 Shading circuit 832 Line memory

Claims (8)

An image data acquisition unit for acquiring image data from the outside;
A first image processing unit that performs first image processing on image data to be processed;
A second image processing unit 1 and a second image processing unit 2 that perform second image processing different from the first image processing on the image data to be processed ;
A first memory including at least a first memory 1 and a first memory 2 used for the first image processing by the first image processing unit;
A second memory 1 used for the second image processing by the second image processing unit 1 ;
A second memory 2 used for the second image processing by the second image processing unit 2;
A setting accepting unit that accepts a mode setting instruction for a normal mode for executing the first image processing and an extended mode for not executing the first image processing;
When a mode setting instruction for instructing the normal mode is received by the setting reception unit, the image data acquired by the image data acquisition unit is supplied to the first image processing unit as image data to be processed, and the first In a normal mode in which the data subjected to the first image processing by one image processing unit is supplied to at least one of the second image processing unit 1 and the second image processing unit 2 as image data to be processed. When the mode setting instruction for setting and instructing the extended mode is received by the setting receiving unit, the image data acquired by the image data acquiring unit is used as the second image processing unit 1 and the second image processing unit 2. is supplied to at least one of, and the first memory 1, the second memory 1 integrally with the second by the second image processing unit 1 Let used to image processing, the first memory 2, and the second memory 2 and a control unit for setting the integrally said that let used in the second image processing section the by 2 second image processing enhanced mode An integrated circuit for image processing, characterized in that the integrated circuit is integrated in one element. The second image processing unit 1 and the second image processing unit 2 are:
Different image processing is sequentially executed as the second image processing,
The controller is
In the extended mode, the image data acquired by the image data acquisition unit is sent to a processing unit that executes image processing first among the two processing units of the second image processing unit 1 and the second image processing unit 2. The integrated circuit for image processing according to claim 1 , wherein the integrated circuit is supplied. The image data acquisition unit, the first image processing unit, the second image processing unit 1, the second image processing unit 2, and a switching unit for switching a connection relationship between the first memories,
The controller is
When a mode setting instruction for instructing the normal mode is received by the setting receiving unit, the switching unit performs the image data acquisition unit, the first image processing unit, and the first image processing unit and the second image. By connecting at least one of the processing unit 1 and the second image processing unit 2 and connecting the first memory to the first image processing unit so as to be accessible, the normal mode is set.
When the setting accepting unit accepts a mode setting instruction for instructing the extended mode, the switching unit accepts at least one of the image data acquiring unit, the second image processing unit 1 and the second image processing unit 2. And the first memory 1 is connected to the second memory 1 so as to be accessible from the second image processing unit 1 , and the first memory 2 is accessible from the second image processing unit 2. image processing integrated circuit according to claim 1 or 2 by Rukoto is connected to the second memory 2, and performs setting of the extended mode. The integrated circuit for image processing according to any one of claims 1 to 3 , wherein the first image processing is shading processing. The second image processing, image processing integrated circuit according to any one of claims 1-4, characterized in that it comprises an error diffusion. The second image processing, image processing integrated circuit according to any one of claims 1 to 5, characterized in that it comprises a compression process. An integrated circuit for image processing according to any one of claims 1 to 6 ,
A document image acquisition unit that acquires image data representing an image of a document and transmits the image data to the image data acquisition unit;
An image processing apparatus comprising: a mode setting unit that sets a mode setting instruction for instructing the normal mode to the setting reception unit. An integrated circuit for image processing according to any one of claims 1 to 6 ,
A document image acquisition unit that acquires image data representing an image of the document;
An external image processing unit that performs third image processing on the image data acquired by the document image acquisition unit and transmits the image data to the image data acquisition unit;
An image processing apparatus comprising: a mode setting unit that sets a mode setting instruction that instructs the extended mode to the setting reception unit.

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