JP5264465B2 - Nonvolatile memory device and addressing method of nonvolatile memory device - Google Patents

Description

  The present invention is non-volatile in conformity with the JEDEC (Joint Electron Device Engineering Council) DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) standard (JESD79-4; Low Power Double Data Rate (LPDDR) SDRAM Specification). The present invention relates to a technology for accessing a memory device.

In the case of a memory device having a storage capacity of 1 Gbit (16 Mbits × 16 I / O × 4 banks), 24-bit data is required for address designation within one input / output I / O. In the standard for DDR SDRAM, an address is specified by data input in a time division manner (hereinafter, data for address specification is referred to as “address data”). 14-bit data is used for specifying the row address, and 10-bit data is used for specifying the column address. That is, 14-bit data of the active command ACT and 10-bit data of the read command RD are used as address data. A row address is designated by the active command ACT, and the designated row address is activated. A column address is designated by the read command RD, and the designated column address is activated.
Even when the memory device is a non-volatile memory device, it is possible to specify an address in accordance with the JEDEC DDR SDRAM standard.

  In a nonvolatile memory device that reads data by a current sensing method, a precharge is performed from a cascode current source on a data bus to a bit line BL before an active command ACT is input and a word line WL is activated. The bit line BL and the data bus are connected by a Y-pass gate switch. The Y-pass gate switch is controlled to be turned on / off by a column decoder. The column decoder uses an internal boosted voltage. The internal boosted voltage is also used in the Y-pass gate switch. Since the Y-pass gate switch is boosted by the internal boost voltage, the resistance in the path from the cascode current source on the data bus to the memory sector can be reduced.

Precharging is performed on the bit line BL of the memory sector to be accessed. Specifically, when the address data is input after the power is turned on, the Y-pass gate switch for selecting the bit line BL of the vertical block designated by the address data is turned on. When the Y-pass gate switch is turned on, only the bit line BL is charged. Bit lines BL other than the bit line BL selected by the address data are not precharged. Therefore, charge loss can be reduced and current consumption can be reduced.
An internal boosted voltage is applied to the word line WL via the power supply signal line VWL. Therefore, charge is consumed by charging / discharging of the internal boosted voltage due to the wiring capacity of the power supply signal line VWL and the word line WL. The power supply signal line VWL is a plurality of signal lines and is selected according to the address data.

According to the JEDEC standard, 14-bit address data is input at the time of the active command ACT, and then 10-bit address data is input at the time of the read command RD. With the address data for 14 bits input first, the number of bits is small to specify the address to be accessed. Therefore, in some cases, a bit line or a word line that may be selected is selected from the time of the active command ACT and a high voltage is applied, and when the address is determined at the time of the read command, the unselected bit Sometimes the access time is forced to be shortened by discharging lines and word lines.
In this case, the internal boosted voltage must be applied to the originally unselected bit line or word line, and current is wasted.

Patent Document 1 discloses an invention for reducing power consumption in address designation in an SDRAM. In Patent Document 1, the address input buffer is activated after all the address data is input, and the address input buffer is deactivated after a predetermined period, thereby shortening the time for activating the address input buffer as much as possible. Low power consumption is achieved.
JP 2008-34098 A

  The present invention provides a non-volatile memory device and a method thereof that can perform addressing with lower power consumption than the prior art, while complying with the JEDEC SDRAM standard, based on a concept different from Patent Document 1. Let it be an issue.

  The non-volatile memory device of the present invention that solves the above problems includes a plurality of memory cells that can store data each of which can take two or more values, a plurality of word lines for accessing each memory cell, and each A plurality of bit lines for accessing a memory cell, and one of the plurality of word lines and a predetermined number of bit lines are activated to activate the word line and the bit line; The memory cell connected to the external device can be accessed from an external device, and the first address data and the second address data sequentially input from the outside, and a number corresponding to a part of the first address data. After selecting a word line from the plurality of word lines, according to a part of the second address data, from the word line selected according to a part of the first address data A row decoder for selecting and activating a word line, and a number of bit lines equal to or greater than the predetermined number of bit lines according to the remaining portion of the first address data, and then a remaining portion of the second address data. And a column decoder for selecting and activating the predetermined number of bit lines from the bit lines selected according to the remaining portion of the first address data. From an external device, it becomes possible to access the memory cells connected to the activated word line and the activated bit line.

  The non-volatile memory device of the present invention selects the number of word lines and bit lines according to the first address data inputted first, and then uses the second address data inputted next to the first address data. One word line and a predetermined number of bit lines are selected from the selected word lines and bit lines. For example, in the JEDEC DDR SDRAM standard, a bit line is selected in addition to a word line by an active command ACT that was conventionally used only for selecting a word line. Thereby, the consumption of the internal boosted voltage for selecting the bit line can be reduced as compared with the prior art.

When reading data from a memory cell by current sensing, the nonvolatile memory device of the present invention includes, for example, a sense amplifier for sensing a current flowing through the activated bit line, and a sense amplifier. A Y-pass gate switch that is connected via a data bus and that connects the activated bit line and the data bus according to an instruction from the column decoder may further be provided.
For example, the number of the sense amplifiers corresponding to the number of the predetermined number of bit lines is provided. With such a configuration, it is possible to sense current flowing in the same number of bit lines as the sense amplifier among the predetermined number of bit lines at a time. Such a configuration is effective for burst reading.

  The nonvolatile memory device of the present invention may further include, for example, a word line selection unit that is connected to the plurality of word lines and activates the one word line in accordance with an instruction from the row decoder. . When a plurality of memory sectors are provided, one word line selection unit is provided for each of the plurality of memory sectors. Each word line selection unit is activated only by being connected to the word line to be activated according to an instruction from the row decoder. As a result, the word line selection unit that is not related to the activation of the word line is not activated and power consumption is reduced.

  The addressing method of the nonvolatile memory device of the present invention is as follows. That is, it has a plurality of memory cells capable of storing data each of which can take a binary state or more, a plurality of word lines for accessing each memory cell, and a plurality of bit lines for accessing each memory cell. When one of the plurality of word lines and one of the plurality of bit lines are activated, the activated word line and the memory cell connected to the bit line are externally connected. A memory sector that is accessible from the device; a row decoder that activates one word line specified by first address data and second address data sequentially input from the outside; and the first address data and the first address data This is a method executed by a non-volatile memory device including a column decoder that activates one bit line specified by two address data. First, the row decoder selects a number of word lines corresponding to a part of the first address data from the plurality of word lines, and the column decoder determines the number of word lines according to the remaining portion of the first address data. A number of bit lines equal to or greater than the predetermined number of bit lines are selected from a plurality of bit lines. Next, the row decoder selects the one word line from the word lines selected according to a part of the first address data according to a part of the second address data, and the column decoder However, according to the remaining portion of the second address data, the predetermined number of bit lines are selected from the bit lines selected according to the remaining portion of the first address data.

  According to the present invention as described above, the bit line selection is performed in order to prioritize the selection of the bit line by the first address data input first among the first address data and the second address data sequentially input. Therefore, the consumption of the internal boosted voltage can be reduced as compared with the prior art.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
<Configuration>
FIG. 1 is a configuration diagram of the nonvolatile memory device 1 of the present embodiment.
The nonvolatile memory device 1 includes four banks 10. The nonvolatile memory device 1 is accessed by a memory controller (not shown). Data is written to or read from the nonvolatile memory device 1 by access from the memory controller. The four banks 10 are individually activated or deactivated according to data input from the memory controller. Each bank 10 in the nonvolatile memory device 1 has the same configuration.

FIG. 2 shows a configuration diagram of the bank 10.
One bank 10 includes 16 vertical blocks 12. One vertical block 12 is connected to one input / output I / O 11. The input / output I / O 11 is activated or deactivated together with the connected vertical block 12. Address data such as an active command ACT and a read command RD input from the memory controller is input to the input / output I / O 11. The input / output I / O 11 activates or deactivates a predetermined memory cell in the vertical block 12 according to the address data.

FIG. 3 shows a configuration diagram of the vertical block 12. The vertical block 12 includes a memory cell array and peripheral circuits.
The memory cell array includes 16 memory sectors 13. For this purpose, one bank 10 has 256 memory sectors 13. Each memory sector 13 is provided along 2048 global bit lines GBL.
One memory sector 13 has 512 word lines WL and 2048 local bit lines LBL. The local bit line LBL has a one-to-one correspondence with the global bit line GBL, and is connected to the corresponding global bit line GBL via a sector selection switch (not shown). The memory sector 13 is provided with a plurality of memory cells (not shown) capable of storing data that can take two or more values, and the memory cell to be accessed is selected by the word line WL and the local bit line LBL. It has become.

  The peripheral circuit includes a Y-pass gate switch 14, a column decoder 15, a sense amplifier 16, a word line selection unit 17, a row decoder 18, a sector decoder 19, and a boosting power source 20. One word line selector 17 and one sector decoder 19 are provided for each memory sector 13.

  The Y-pass gate switch 14 is connected to the column decoder 15. The column decoder 15 controls the Y-pass gate switch 14 based on the address data, and inputs the Y pass gate boost voltage VPPIq output from the boost power supply 20 to the Y-pass gate switch 14. When the Y-pass gate boost voltage VPPIq is input via the column decoder 15, the Y-pass gate switch 14 connects the global bit line GBL corresponding to the column address specified by the address data and the data bus DB. One of the 2048 global bit lines GBL is connected to the sense amplifier 16 via the data bus DB.

  One sense amplifier 16 may be provided, but a plurality of sense amplifiers may be provided. For example, when burst reading is performed, if the burst length is “8” and the specification is 16 I / O, if 128 sense amplifiers 16 are provided, data can be read in one access. When there are a plurality of sense amplifiers 16, a plurality of data buses DB are prepared, and each sense amplifier 16 is connected to a different data bus DB. The sense amplifier 16 senses a current flowing through the global bit line GBL when reading data from the memory cell. For this purpose, a cascode current source is provided on the data bus DB or in the sense amplifier 16. Data obtained as a result of current sensing by the sense amplifier 16 is output from the nonvolatile memory device 1 to the memory controller as data read from the memory cell.

The word line selection unit 17 activates the word line WL corresponding to the row address specified by the address data. FIG. 4 is a configuration diagram of the word line selection unit 17. The word line selection unit 17 includes a main X decoder 171 and a sub X decoder 172. One word line selection unit 17 includes 32 main X decoders 171, and one main X decoder 171 includes 16 sub X decoders 172. Each of the slave X decoders 172 is connected to a word line WL. For this reason, 512 word lines WL can be controlled by one word line selection unit 17. An X decoder boost voltage VPXGq is applied to the word line selection unit 17 from the boost power supply 20, and the word line WL corresponding to the address data is thereby activated.
The word line selector 17 is connected to the row decoder 18 by 16 power supply signal lines VWL. Each word line WL is connected to any one of the power supply signal lines VWL. That is, the 16 power supply signal lines VWL are connected to each of the 32 main X decoders 171 built in each of the 16 word line selection units 17. The 16 slave X decoders 172 and the 16 power supply signal lines VWL of each main decoder 171 have a one-to-one correspondence, and the power supply signal line VWL is a word line WL connected to the corresponding slave X decoder 172. Connected to. The word line boosted voltage VPXVq is applied to the activated word line WL from the connected power supply signal line VWL. When the word line boost voltage VPXVq is input from the boost power supply 20, the row decoder 18 activates the power signal line VWL according to the address data.

  When the Y-pass gate switch boost voltage VPPIq is input, the sector decoder 19 turns on the sector selection switch in the memory sector 13. As a result, the global bit line GBL and the local bit line LBL in the memory sector 13 are connected. The sector decoder 19 activates the corresponding memory sector 13.

  The boost power supply 20 generates an internal boost voltage used in the nonvolatile memory device 1 and supplies it to the column decoder 15, the word line selector 17, the row decoder 18, and the sector decoder 19.

  Since the vertical block 12 having such a configuration has 512 × 16 = 8192 word lines WL and 2048 global bit lines GBL, 16 Mbit addresses can be specified. For this purpose, one vertical block 12 has a storage capacity of 16 Mbits. Since the storage capacity of one vertical block 12 is 16M bits, the storage capacity of one bank 10 is 256M bits, and the storage capacity of the nonvolatile memory device 1 is 1G bits.

  In such a non-volatile memory device 1, an address is designated by the process shown in the process flowchart of FIG.

First, the bank 10 is selected from the nonvolatile memory device 1 based on data sent from the memory controller (step S10). The selected bank 10 is activated. Next, a desired memory cell is selected from the activated bank 10 by address data.
Of the address data, the address data of the active command ACT is 14 bits, and the address data of the read command RD is 10 bits. The active command ACT and the read command RD are input in a time division manner. First, an active command ACT is input to the nonvolatile memory device 1, and then a read command RD is input.

  A predetermined number of vertical blocks 12 are selected from the 16 vertical blocks 12 included in the bank 10 activated in step S10 in accordance with the active command ACT. Further, a predetermined number of memory sectors 13 are selected from the 16 memory sectors 13 included in the selected vertical block 12. Further, a predetermined number of word lines WL and global bit lines GBL are selected from the selected memory sector 13 in accordance with the active command ACT (step S20). The selected memory sector 13, word line WL, and global bit line GBL are activated.

  Next, one is selected from each of the vertical block 12 and the memory sector 13 activated in step S20 according to the read command RD. Except for each selected vertical block 12 and memory sector 13, the other vertical blocks 12 and memory sectors 13 are deactivated. In response to the read command RD, one word line WL and a predetermined number of global bit lines GBL are selected from the word lines WL and global bit lines GBL activated in step S20 (step S30). Except for the selected word line WL and global bit line GBL, the other word lines WL and global bit lines GBL are deactivated. In the case of burst reading, the number of selected global bit lines GBL is determined according to the burst length.

In this way, one memory sector 13 is selected from the vertical block 12 based on the address data, and one word line WL connected to the memory cell to be accessed from the selected memory sector 13 and a predetermined number of memory sectors 13 are selected. Global bit line GBL is selected. Since the 14-bit data of the active command ACT selects the bit line in addition to the word line WL, the consumption of the internal boost voltage can be reduced as compared with the conventional case.
Hereinafter, how the memory cell is selected in step S20 and step S30 will be described in detail.

<Example 1>
Selection by active command ACT (step S20):
In the first embodiment, the word line WL and the global bit line GBL are selected as follows according to the address data for 14 bits of the active command ACT.
First, four vertical blocks 12 are selected from the 16 vertical blocks 12 and activated according to 2-bit address data of the active command ACT.

  Next, for each of the activated four vertical blocks 12, one is selected from the 16 memory sectors 13 by the address data for 4 bits. For example, the sector decoder 19 selects one memory sector 13 by the address data for 4 bits of the active command ACT. The selected memory sector 13 is activated, and the local bit line LBL and the global bit line GBL are connected by a built-in sector selection switch.

Next, 32 word lines WL are selected from 512 word lines WL for the memory sector 13 activated in each of the activated four vertical blocks 12. Address data for 4 bits is used to select the word line WL. The selection of the word line WL is performed, for example, when the row decoder 18 selects one of the 16 power supply signal lines VWL based on the address data for 4 bits of the active command ACT. The row decoder 18 applies the word line boost voltage VPXVq to the selected power supply signal line VWL. One memory sector 13 has 32 main X decoders 171, and one main X decoder 171 is connected to 16 word lines WL via a sub X decoder 172. By selecting one power supply signal line VWL, one word line WL is selected in each main X decoder 171, so that 32 word lines are selected in each memory sector 13.
Further, 128 global bit lines are selected from 2048 global bit lines GBL for the memory sector 13 activated in each of the activated four vertical blocks 12. Four bits of address data are used to select the global bit line GBL. The selection of 128 global bit lines GBL is performed by the Y-pass gate switch 14. The Y-pass gate switch 14 connects the selected global bit line GBL to the sense amplifier 16 via the data bus according to the instruction of the column decoder 15 by the address data for 4 bits of the active command ACT. The selected word line WL, global bit line GBL, and local bit line LBL are activated.

Selection by read command RD (step S30):
Next to the 14-bit address data of the active command ACT, the address is continuously designated by the 10-bit address data of the read command RD.
First, one vertical block 12 is selected from the four vertical blocks 12 activated by the active command ACT by the address data of 2 bits of the read command RD. The four vertical blocks 12 activated by the active command ACT are deactivated leaving one selected vertical block 12.

Next, one word line WL is selected from one memory sector 13 selected by an act command ACT in one selected vertical block 12. That is, one word line WL is selected from the 32 word lines WL selected by the active command ACT by the address data for 5 bits of the read command RD. For example, one main X decoder 171 is selected by the row decoder 18. As a result, only the word line WL connected to the main X decoder 171 is selected.
In this way, data is read from the memory cells connected to the activated one word line WL and 128 local bit lines LBL, and 16-bit address data corresponding to 3 bits of the read command RD. Data is selected and burst output to the input / output I / O 11.
As described above, by selecting one word line WL and 128 global bit lines GBL, address designation and data burst output are performed.

As described above, one power supply signal line VWL and 128 global bit lines GBL are selected in each of the four vertical blocks 12 by the active command ACT. Therefore, the consumption of the internal boosted voltage generated by the boost power supply 20 is smaller than when only the word line WL is selected by the active command ACT as in the prior art.
In the first embodiment, in the address selection by the active command ACT, the current consumption by the power supply signal line VWL is 300 uA × 4 = 1200 uA, the current consumption by the Y pass gate boost voltage VPPIq used for selection of the global bit line GBL and the local bit line LBL. Is 60 uA × 4 = 240 uA, the address selection by the read command RD causes the current consumption by the word line selection boost voltage VPXGq in the main X decoder 171 to be 200 uA, and the current consumption of the boost power supply 20 is 1.64 mA in total.
In the address selection method similar to the conventional DRAM, since one word line WL is selected by the active command ACT, the current consumed by the power supply signal line VWL is 300 uA × 1 = 300 uA. However, since the global bit line GBL is not selected, a large amount of current is consumed. As an example, the current consumption is at least 4.3 mA due to the address selection by the active command ACT.

<Example 2>
Selection by active command ACT (step S20):
In the second embodiment, the word line WL and the global bit line GBL are selected as follows according to the address data for 14 bits of the active command ACT.
First, two vertical blocks 12 are selected from the 16 vertical blocks 12 by the address data for 3 bits of the active command ACT and activated.

  Next, for each of the activated two vertical blocks 12, one of 16 memory sectors 13 is selected by address data for 4 bits. For example, the sector decoder 19 selects one memory sector 13 by the address data of the 4-bit active command ACT. The selected memory sector 13 is activated, and the local bit line LBL and the global bit line GBL are connected by a built-in sector selection switch.

Next, 64 word lines WL are selected from 512 word lines WL for the memory sector 13 activated in each of the activated two vertical blocks 12. Address data for 3 bits is used to select the word line WL. The selection of the word line WL is performed, for example, when the row decoder 18 selects two of the 16 power supply signal lines VWL based on 3-bit address data of the active command ACT. The row decoder 18 applies the word line boost voltage VPXVq to the selected power supply signal line VWL.
In addition, for the memory sector 13 activated in each of the activated two vertical blocks 12, 128 global bit lines are selected from 2048 global bit lines GBL. Four bits of address data are used to select the global bit line GBL. The selection of 128 global bit lines GBL is performed by the Y-pass gate switch 14. The Y-pass gate switch 14 connects the selected global bit line GBL to the sense amplifier 16 via the data bus according to the instruction of the column decoder 15 by the address data for 4 bits of the active command ACT. The selected word line WL, global bit line GBL, and local bit line LBL are activated.

Selection by read command RD (step S30):
Next to the 14-bit address data of the active command ACT, the address is continuously designated by the 10-bit address data of the read command RD.
First, one vertical block 12 is selected from the two vertical blocks 12 activated by the active command ACT by the address data for one bit of the read command RD. The two vertical blocks 12 activated by the active command ACT are inactivated while leaving one selected vertical block 12.

Next, one word line WL is selected from one memory sector 13 selected by an act command ACT in one selected vertical block 12. That is, one word line WL is selected from the 64 word lines WL selected by the active command ACT by the address data for 6 bits of the read command RD.
In this way, data is read from the memory cells connected to the activated one word line WL and 128 local bit lines LBL, and 16-bit address data corresponding to 3 bits of the read command RD. Data is selected and burst output to the input / output I / O 11.

As described above, two power supply signal lines VWL and 128 global bit lines GBL are selected in each of the two vertical blocks 12 by the active command ACT. Therefore, the consumption of the internal boosted voltage generated by the boost power supply 20 is smaller than when only the word line WL is selected by the active command ACT as in the prior art.
In the second embodiment, in the address selection by the active command ACT, the current consumption by the power supply signal line VWL is 300 uA × 4 = 1200 uA, the current consumption by the Y pass gate boost voltage VPPIq used for the selection of the global bit line GBL and the local bit line LBL. Is 60 uA × 2 = 120 uA, and the address selection by the read command RD causes the current consumption by the word line selection boost voltage VPXGq in the main X decoder 171 to be 200 uA, and the current consumption of the boost power supply 20 is 1.52 mA in total.

<Example 3>
Selection by active command ACT (step S20):
In the third embodiment, the word line WL and the global bit line GBL are selected as follows according to the address data for 14 bits of the active command ACT.
First, one vertical block 12 is selected from the 16 vertical blocks 12 by the address data for 4 bits of the active command ACT.

  Next, one activated vertical block 12 is selected from 16 memory sectors 13 by 4-bit address data. For example, the sector decoder 19 selects one memory sector 13 by the address data for 4 bits of the active command ACT. The selected memory sector 13 is activated, and the local bit line LBL and the global bit line GBL are connected by a built-in sector selection switch.

Next, for one activated memory sector 13, 128 word lines WL are selected from 512 word lines WL. Two bits of address data are used to select the word line WL. The selection of the word line WL is performed, for example, when the row decoder 18 selects four from the 16 power supply signal lines VWL by the address data for 2 bits of the active command ACT. The row decoder 18 applies the word line boost voltage VPXVq to the selected power supply signal line VWL.
In addition, for one activated memory sector 13, 128 global bit lines are selected from 2048 global bit lines GBL. Four bits of address data are used to select the global bit line GBL. The selection of 128 global bit lines GBL is performed by the Y-pass gate switch 14. The Y-pass gate switch 14 connects the selected global bit line GBL to the sense amplifier 16 via the data bus according to the instruction of the column decoder 15 by the address data for 4 bits of the active command ACT. The selected word line WL, global bit line GBL, and local bit line LBL are activated.

Selection by read command RD (step S30):
Next to the 14-bit address data of the active command ACT, the address is continuously designated by the 10-bit address data of the read command RD.
First, one word line WL is selected from one memory sector 13 of one vertical block 12 activated by the active command ACT. That is, one word line WL is selected from the 128 word lines WL selected by the active command ACT by the address data of 7 bits of the read command RD.
In this way, data is read from the memory cells connected to the activated one word line WL and 128 local bit lines LBL, and 16-bit address data corresponding to 3 bits of the read command RD. Data is selected and burst output to the input / output I / O 11.

As described above, four power supply signal lines VWL and 128 global bit lines GBL are selected by one vertical block 12 by the active command ACT. Therefore, the consumption of the internal boosted voltage generated by the boost power supply 20 is smaller than when only the word line WL is selected by the active command ACT as in the prior art.
In the third embodiment, in the address selection by the active command ACT, the current consumption by the power supply signal line VWL is 300 uA × 4 = 1200 uA, the current consumption by the Y pass gate boost voltage VPPIq used for the selection of the global bit line GBL and the local bit line LBL. Is 60uA × 1 = 60uA, and the address selection by the read command RD causes the current consumption by the word line selection boost voltage VPXGq in the main X decoder 171 to be 200uA, and the current consumption of the boost power supply 20 is 1.46mA in total.

  In the data output of the first to third embodiments, all 128 global bit lines GBL are sensed immediately after the read command RD is input. When the burst length is “8”, 128 bits of data can be continuously read 8 times at 16 I / O. As a result, high-speed data reading is realized while realizing low current consumption.

It is a block diagram of the non-volatile memory device of this embodiment. It is a block diagram of a bank. It is a block diagram of a vertical block. It is a block diagram of a word line selection part. 6 is a processing flowchart of address designation in the nonvolatile memory device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Non-volatile memory device, 10 ... Bank, 11 ... Input / output I / O, 12 ... Vertical block, 13 ... Memory sector, 14 ... Y-pass gate switch, 15 ... Column decoder, 16 ... Sense amplifier, 17 ... Word Line selection unit, 171 ... main X decoder, 172 ... slave X decoder, 18 ... row decoder, 19 ... sector decoder, 20 ... boosting power supply

Claims (6)

A plurality of memory cells each capable of storing data that can take two or more states, a plurality of word lines for accessing each memory cell, and a plurality of bit lines for accessing each memory cell; When one of the plurality of word lines and a predetermined number of bit lines are activated, the activated word line and the memory cell connected to the bit line can be accessed from an external device. Sectors,
The first address data and the second address data sequentially input from the outside are used to select the number of word lines corresponding to a part of the first address data from the plurality of word lines, and then the second address data A row decoder that selects and activates the one word line from word lines selected according to a part of the first address data according to a part of the first address data;
After selecting the number of bit lines equal to or greater than the predetermined number of bit lines according to the remaining portion of the first address data, select according to the remaining portion of the first address data according to the remaining portion of the second address data. A column decoder that selects and activates the predetermined number of bit lines from the bit lines;
Non-volatile memory device. A sense amplifier for sensing a current flowing in the activated bit line;
A Y-pass gate switch connected to the sense amplifier via a data bus and connecting the activated bit line and the data bus according to an instruction from the column decoder; Yes,
The nonvolatile memory device according to claim 1. The number of the sense amplifiers is provided according to the number of the predetermined number of bit lines, and the current flowing through the same number of bit lines as the sense amplifier among the predetermined number of bit lines can be sensed at a time.
The nonvolatile memory device according to claim 2. A word line selection unit that is connected to the plurality of word lines and that activates the one word line according to an instruction from the row decoder;
The non-volatile memory device according to claim 1. A plurality of the memory sectors are provided,
One word line selection unit is provided for each of the plurality of memory sectors, and only the one connected to the word line to be activated is activated by an instruction from the row decoder.
The nonvolatile memory device according to claim 4. A plurality of memory cells each capable of storing data that can take two or more states, a plurality of word lines for accessing each memory cell, and a plurality of bit lines for accessing each memory cell; When one of the plurality of word lines and a predetermined number of bit lines are activated, the activated word line and the memory cell connected to the bit line can be accessed from an external device. A sector, a row decoder for activating one word line specified by first address data and second address data sequentially input from the outside, and specified by the first address data and the second address data A method implemented by a non-volatile memory device comprising: a column decoder for activating the predetermined number of bit lines;
The row decoder selects a number of word lines corresponding to a part of the first address data from the plurality of word lines, and the column decoder selects the plurality of word lines according to the remainder of the first address data. Selecting a number of bit lines equal to or greater than the predetermined number of bit lines
The row decoder selects the one word line from the word lines selected according to a part of the first address data according to a part of the second address data, and the column decoder Selecting the predetermined number of bit lines from the bit lines selected according to the remaining portion of the first address data in accordance with the remaining portion of the second address data;
Non-volatile memory device addressing method.

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