JP5263251B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having an error correction function.

  In recent years, the required memory capacity of semiconductor memory devices such as DRAM (Dynamic Random Access Memory) mounted on information equipment has been rapidly increasing. This increase in memory capacity has been dealt with by progress in miniaturization technology, but as the miniaturization technology progresses, the reliability of memory cells decreases. In order to prevent this, an extra storage area (redundant area) is provided in the memory cell array, and a defective memory cell in the redundant area is selected instead of a defective memory cell in the normal memory cell array area. There was redundant technology to remedy. Although this technology can prevent a decrease in the reliability of the product itself, in recent years, a memory cell that requires a refresh operation such as a DRAM causes a failure after product shipment due to a sudden change in retention time. There was a problem.

  As one of countermeasures against defects due to such a sudden change in the retention period, an ECC (Error Checking and Correcting) function is installed. When a 1-bit correctable ECC that is generally used is used, even if there is a 1-bit error in the read data, it can be corrected using the ECC. In addition, there is a method of using the ECC function to take over the remedy for defects by the redundancy technique. That is, when the error in the ECC code (for example, a Hamming code) is 1 bit, the redundant area is not used, and error correction is performed by reading in a 1-bit error state every time.

  By doing this, single bit failure to a certain extent (two or more failures are not generated by one read operation, but one read operation is caused by BL (bit line) short / break). In this case, it is not necessary to use a redundant area. As a result, since there are too many defective bits that cannot be remedied in a predetermined redundant area, a chip that has been discarded as a defective chip can be made a non-defective chip, which can contribute to an improvement in yield.

  However, if there are too many single bit defects that have been taken over by the ECC function to repair the defective bits by the redundancy technique, the probability that the defective bits can be saved due to a sudden change in the holding time will be low. What is important here is to determine how many can be used when shipping as a product, and to determine if the ECC function can replace the defective bits with redundancy technology and test it. Is that you can.

  For this purpose, a counter that can count the number of times that error correction has been performed and a register that can set the upper limit of the number of error corrections are arranged, and a comparison circuit is used to compare the value of the counter and the register and output the comparison result. This function is required.

A semiconductor memory device having the above functions is disclosed in, for example, Patent Documents 1, 2, and 3, and has the following configuration.
FIG. 9 is a diagram showing a configuration of a conventional semiconductor memory device.

  A conventional semiconductor memory device 20 includes a data bit unit 21 for storing data bits, a parity bit unit 22 for storing parity bits, data bits and parity bits among data stored in a memory cell array of a memory core (not shown). An error correction circuit 23 that performs error correction with reference, a parity calculation circuit 24 that generates a parity bit by calculation based on a Hamming code, for example, according to input data, a counter 25 that counts the number of error corrections, and error correction It has a register 26 for storing the upper limit value of the number of times, a comparison circuit 27 for comparing the counted error correction number and the upper limit value of the error correction stored in the register 26, an output circuit 28 and an input circuit 29.

  In this conventional semiconductor memory device 20, the error correction circuit 23 performs 1-bit error detection and error correction with reference to, for example, 64 data bits and 7 parity bits. Error detection is performed by inverting the detected defective bit, and the result is output via the output circuit 28. The counter 25 counts the number of error corrections when a count start signal is input during the test. Then, the comparison circuit 27 compares the error correction count with the upper limit value of the error correction count previously stored in the register 26, and determines whether or not the error correction count exceeds a predetermined upper limit value. When the upper limit is exceeded, the output circuit 28 outputs an alarm.

JP 49-60450 (p3, Fig. 2) JP-A-1-94599 (p4, p5, FIG. 1) Japanese Patent Laid-Open No. 6-131884 (paragraph numbers [0006] to [0008], FIG. 1)

  However, in the conventional semiconductor memory device, depending on the test pattern, the data at the same address may be accessed a plurality of times. However, there is a problem that the defective bit is counted a plurality of times.

  According to one aspect of the invention, in a semiconductor memory device having an error correction function for correcting a defective bit, whether error correction has been performed for each data bit and parity bit necessary to construct a code capable of correcting 1-bit error. There is provided a semiconductor memory device including an error correction storage unit for storing error correction information on whether or not.

  According to the disclosed semiconductor memory device, when the number of error corrections is counted, an error at the same address is corrected a plurality of times depending on the test pattern, and the problem that the accurate error correction number cannot be grasped can be solved.

1 is a diagram showing a configuration of a semiconductor memory device according to a first embodiment. It is a figure which shows the structure of the semiconductor memory device of 2nd Embodiment. It is a figure which shows the structure of the semiconductor memory device of 3rd Embodiment. It is a figure which shows the structure of the semiconductor memory device of 4th Embodiment. It is a timing chart which shows the mode of writing of the error correction information to the error correction storage bit. It is a figure which shows the memory | storage state of a memory core after writing of the error correction information to an error correction storage bit. 5 is a timing chart showing how error correction storage bits are read and counted. It is a figure which shows the structure of the semiconductor memory device of 5th Embodiment. It is a figure which shows the structure of the conventional semiconductor memory device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram showing a configuration of the semiconductor memory device according to the first embodiment.
The semiconductor memory device 10a according to the first embodiment includes a data bit unit 11 that stores data bits, a parity bit unit 12 that stores parity bits, and an error correction circuit that performs error correction with reference to the data bits and the parity bits. 13, a parity calculation circuit 14 that generates a parity bit by calculation based on a Hamming code, for example, according to input data, a counter 15a that counts the number of error corrections, and a register 16a that sets an upper limit value of the number of error corrections The comparator 17 compares the counted number of error corrections with the upper limit of the number of error corrections stored in the register 16a, and includes an output circuit 18 and an input circuit 19.

  The data bit unit 11 and the parity bit unit 12 are configured by a memory cell array of a memory core (not shown). The memory cell array is configured in units of 4 bits or 8 bits, for example, in which 4 or 8 memory cells are selected by one column selection line.

A sense amplifier, a write amplifier, a column decoder for designating an address, a row decoder, and the like are not shown.
In the semiconductor memory device 10a of the first embodiment, the register 16a for storing the upper limit value of the number of error corrections is different from the conventional one, and an upper limit value setting signal (hereinafter referred to as the first embodiment) is input from the outside. The upper limit value is changed according to the external upper limit value capturing signal). The setting upper limit value is taken into the register 16a via a data input / output pin (not shown), for example, when the external upper limit value taking signal becomes a high level during the test. This upper limit value is an upper limit value that can be used to repair defective bits by the redundancy technique by the ECC function.

Hereinafter, the operation of the semiconductor memory device 10a will be described.
At the time of data writing, data input from a data input / output pin (not shown) is stored at a specified address of the data bit unit 11 via the input circuit 19. At this time, a parity bit is generated by a calculation based on an ECC code (for example, a Hamming code) in accordance with input data in the parity calculation circuit 14 and stored in a predetermined address of the parity bit unit 12.

  For example, when an ECC code for 1-bit error correction is constructed, 4-bit parity bits are generated for 8-bit data bits, 5-bit parity bits for 64-bit data bits, 64-bit data A 7-bit parity bit is generated for each bit, and an 8-bit parity bit is generated for the 128-bit data bits and stored in the parity bit unit 12.

  On the other hand, at the time of data reading, for example, 64-bit data bits and 7-bit parity bits for constructing an ECC code are read from the addresses specified in the data bit part 11 and the parity bit part 12 in one reading. At this time, the error correction circuit 13 refers to the data bit and the parity bit to perform 1-bit error detection and error correction, and when a defective bit is detected, the error correction circuit 13 inverts the bit to correct the corrected data. Output.

Next, the operation during the test will be described.
At the time of the test, the address is incremented or decremented according to a predetermined test pattern, and the data at all addresses in the data bit part 11 and the parity bit part 12 are accessed. The error correction circuit 13 performs 1-bit error detection and error correction with reference to, for example, 64-bit data bits for constructing the ECC code and 7-bit parity bits corresponding thereto. The counter 15a starts counting the number of error corrections when the count start signal input from the external pin at the time of the test becomes a high level. At this time, the count value output from the counter and the upper limit value of the number of error corrections stored in the register 16a are input to the comparison circuit 17 and compared. The comparison result in the comparison circuit 17 is output via the output circuit 18. If the count value in the counter 15a does not satisfy the upper limit value set in the register 16a, the counter 15a continues to count the number of error corrections as it is. When the predetermined test pattern is completed, for example, the count start signal input to the counter 15a becomes a low level, and the count of the number of error corrections is stopped. When the upper limit value is reached during the test, the output circuit 18 outputs an alarm, for example, and the counter 15a stops counting.

  By the way, the upper limit value is an upper limit that can be used to repair defective bits by the redundancy technique using the ECC function. If the upper limit value is too small, a large number of redundant areas are required depending on the number of error corrections. On the other hand, if the upper limit value is too large, the probability of saving a defective bit due to a sudden change in holding time when the number of error corrections is large is reduced. Therefore, in the semiconductor memory device 10a of the first embodiment, the upper limit value set in the register 16a can be adjusted during the test. Specifically, after the count of the number of error corrections is completed, the input external upper limit value capture signal is set to a high level, for example, and the setting upper limit value is captured to the register 16a from a data input / output pin (not shown), and a new upper limit is set. Set as a value.

  For example, after counting the number of error corrections, the upper limit value is changed according to the presence or absence of an alarm, and the approximate number of error corrections is detected depending on whether the presence or absence of an alarm changes. The upper limit is set by estimating the amount of defects due to sudden fluctuations. As a result, the upper limit value can be set according to the number of error corrections during the test.

Next, a semiconductor memory device according to a second embodiment will be described.
FIG. 2 is a diagram illustrating a configuration of the semiconductor memory device according to the second embodiment.
The same components as those of the semiconductor memory device 10a of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  In the semiconductor memory device 10b of the second embodiment, the register 16b for setting the upper limit value is different from the semiconductor memory device 10a of the first embodiment, and an upper limit value setting signal (in the second embodiment, from the outside). , A count value storage signal) is input (when the count value is stored at a high level), the count result of the error correction count in the counter 15a is set as the upper limit value of the error correction count.

  Hereinafter, an operation of the semiconductor memory device 10b according to the second embodiment will be described. Since operations at the time of reading and writing are the same as those of the semiconductor memory device 10a of the first embodiment, description thereof is omitted.

  At the time of the test, after the number of error corrections by the counter 15a is counted, for example, the count value storage signal is set to the high level and the count result is stored in the register 16b. Then, after a predetermined time after performing the stress test, the test is performed again with the same test pattern as the previous time, and the previous count result set in the register 16b by the comparison circuit 17 and the current count result output from the counter 15a are obtained. Compare. If the current counting result is greater than the previous one, for example, an alarm is output from the output circuit 18 and the deterioration with time can be grasped.

  Instead of fetching the upper limit value from the outside when the count value storage signal is at a high level by inputting the count value storage signal to the register 16a of the semiconductor memory device 10a of the first embodiment. The count value of the counter 15a may be stored in the register 16a.

Next, a semiconductor memory device according to a third embodiment will be described.
FIG. 3 is a diagram illustrating the configuration of the semiconductor memory device according to the third embodiment.
The same components as those of the semiconductor memory device 10a according to the first or second embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  In the semiconductor memory device 10c of the third embodiment, the register 16c differs from the semiconductor memory device 10a of the first embodiment in that an upper limit value setting signal (in the third embodiment, the upper limit value increment / When a decrement signal is input (when it becomes high level), the upper limit value is incremented or decremented in synchronization with the clock signal.

  The operation of the semiconductor memory device 10c according to the third embodiment will be described below. Since operations at the time of reading and writing are the same as those of the semiconductor memory device 10a of the first and second embodiments, description thereof is omitted.

  During the test, after the error correction count is counted by the counter 15a, for example, when the upper limit value increment / decrement signal is set to the high level, the register 16c increments or decrements the upper limit value stored in advance in synchronization with the clock signal. And each time, it compares with the count result of the number of times of error correction. For example, when an alarm has not occurred, if the upper limit value is decremented, a certain value becomes smaller than the count result of the number of error corrections, and an alarm is generated. On the other hand, when an alarm is generated, if the upper limit value is incremented, the alarm does not occur because a certain value exceeds the count result of the number of error corrections. That is, the details of the number of error corrections can be grasped from the signal from the comparison circuit 17.

  Incidentally, after counting the number of error corrections by the counter 15a to the register 16a of the semiconductor memory device 10a of the first embodiment, the above upper limit increment / decrement signal is input, and the details of the number of error corrections are described. You may make it understandable.

Next, a semiconductor memory device according to a fourth embodiment will be described.
FIG. 4 is a diagram showing a configuration of the semiconductor memory device according to the fourth embodiment.
The same components as those of the semiconductor memory device 10a of the first to third embodiments are denoted by the same reference numerals, and description thereof is omitted.

  The semiconductor memory device 10d according to the fourth embodiment has a function of preventing defective bits from being counted a plurality of times when a test is performed using a test pattern in which data at the same address may be accessed a plurality of times. Have In order to realize such a function, the semiconductor memory device 10d performs error correction for each data bit and parity bit necessary for constructing an ECC code (for example, a Hamming code) capable of correcting 1-bit error. It has an error correction storage bit 12a for storing error correction information on whether or not. When the count start signal is input, the counter 15b counts the number of times that error correction has been performed based on the error correction information stored in the error correction storage bit 12a.

  Usually, the memory cell array is configured in units of 4 bits or 8 bits. That is, four or eight memory cells are selected by one column selection line. For example, in the case of an 8-bit configuration, when a Hamming code is constructed with 7 parity bits for 64 data bits, 7 bits are sufficient to store the parity bits, so there is a surplus of 1 bit. By assigning this 1 bit to the error correction storage bit 12a, this function can be realized without increasing the memory cell array.

The operation of the semiconductor memory device 10d according to the fourth embodiment will be described below.
Since operations at the time of reading and writing are the same as those of the semiconductor memory device 10a of the first to third embodiments, description thereof will be omitted.

  During the test, first, the semiconductor memory device 10d accesses data at all addresses in the memory cell array, and the error correction circuit 13 performs 1-bit error detection and error correction.

FIG. 5 is a timing chart showing how error correction information is written to the error correction storage bits.
Here, the row address Add (0) is first selected, and for example, 64 data bits and 7 parity bits are read from the memory core (Core), and the error correction circuit 13 detects and corrects the error. The result is written in the error correction storage bit 12a of the memory core as error correction information. For example, “1” is stored when error correction is performed, and “0” is stored when error correction is not performed. By performing the above processing on all row addresses Add (1), Add (2),..., Add (m−1), Add (m), data at all addresses is accessed, and error correction is performed. Information is written to the error correction storage bit 12a.

FIG. 6 is a diagram illustrating a storage state of the memory core after writing the error correction information to the error correction storage bit.
For every 64 data bits and 7 parity bits required to construct an ECC code that can correct a 1-bit error, the error correction storage bit is “1”, and no error correction is performed. In the case of “0”, “0” is stored.

Next, the operation when counting the number of error corrections will be described.
FIG. 7 is a timing chart showing how the error correction storage bits are read and counted.

  For example, when a count start signal is input to the counter 15b, all row addresses Add (0) to Add (m) are sequentially selected and read. As a result, the data of the error correction storage bit 12a is read inside the memory core (not shown). The counter 15b counts up only when the data stored in the error correction storage bit 12a is “1” indicating that error correction has been performed. FIG. 7 shows that the number of errors as a result of counting is 5807 (16 AF in hexadecimal). The counting result is output via the output circuit 18.

  In a normal test pattern, access to the data of all addresses is repeated a plurality of times. Therefore, if the number of error corrections is directly counted by the counter 15b, the same address is counted a plurality of times. For this reason, there is a problem that the exact number of error corrections cannot be grasped. However, since the semiconductor memory device 10d of the fourth embodiment uses the error correction storage bit 12a, even if the error at the same address is corrected a plurality of times, the error correction storage bit is overwritten with “1”. Therefore, the exact number of error corrections can be counted by counting this number at the end.

Next, a semiconductor memory device according to a fifth embodiment will be described.
FIG. 8 is a diagram showing a configuration of the semiconductor memory device according to the fifth embodiment.
The same components as those of the semiconductor memory device 10a of the first to fourth embodiments are denoted by the same reference numerals, and description thereof is omitted.

  The semiconductor memory device 10e of the fifth embodiment is compared with the semiconductor memory device 10d of the fourth embodiment in comparison with the upper limit value setting register 16a shown in the semiconductor memory device 10a of the first embodiment. The circuit 17 is added.

According to such a configuration, the upper limit value set in the register 16a can be arbitrarily set in accordance with the accurate error correction count result.
It should be noted that when the count value storage signal is at a high level by further inputting the count value storage signal as shown in FIG. 2 to the semiconductor memory device 10e of the fifth embodiment, it is for external setting. Instead of the upper limit value, the count result of the counter 15a may be stored in the register 16a. Thereby, deterioration with time can be grasped more accurately.

DESCRIPTION OF SYMBOLS 10a Semiconductor memory device 11 Data bit part 12 Parity bit part 13 Error correction circuit 14 Parity operation circuit 15a Counter 16a Register 17 Comparison circuit 18 Output circuit 19 Input circuit

Claims (1)

In a semiconductor memory device having an error correction function for correcting a defective bit,
An error correction storage unit for storing error correction information indicating whether or not error correction has been performed for each data bit and parity bit necessary for constructing a code capable of correcting 1-bit error;
When correcting the data bit of the same address multiple times, an error correction circuit that overwrites the error correction information associated with the data bit with the same value;
A counter that refers to the error correction information and counts the number of values indicating that error correction has been performed;
A semiconductor memory device comprising:

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