JP5258342B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP5258342B2
JP5258342B2 JP2008081631A JP2008081631A JP5258342B2 JP 5258342 B2 JP5258342 B2 JP 5258342B2 JP 2008081631 A JP2008081631 A JP 2008081631A JP 2008081631 A JP2008081631 A JP 2008081631A JP 5258342 B2 JP5258342 B2 JP 5258342B2
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power supply
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芳雄 藤井
芳嗣 杉本
大児 彌永
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New Japan Radio Co Ltd
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Description

本発明は、複数チャネルの信号を同様に個々に処理する際に、クロストークの防止を図った半導体装置およびその製造方法に関するものである。   The present invention relates to a semiconductor device in which crosstalk is prevented when a plurality of channels of signals are individually processed, and a method for manufacturing the same.

例えば、複数のセンサで得られた信号を収集して個々に処理する際に、それらの信号を同一特性の増幅回路等の処理回路に入力して処理することが行われる。このとき、処理回路には、１チップに複数チャネル分が搭載された半導体装置が使用される。この半導体装置には、共通の半導体基板上に各処理回路が形成され、各々の処理回路用に共通の電源端子および個別の入出力端子が設けられている。   For example, when signals obtained by a plurality of sensors are collected and individually processed, the signals are input to a processing circuit such as an amplifier circuit having the same characteristics and processed. At this time, a semiconductor device in which a plurality of channels are mounted on one chip is used for the processing circuit. In this semiconductor device, each processing circuit is formed on a common semiconductor substrate, and a common power supply terminal and individual input / output terminals are provided for each processing circuit.

ところが、このように１チップに複数の処理回路を搭載して複数チャネルの信号を処理する場合は、そのチャネル間でクロストークが発生し易く、各センサで得た信号に対して正確な信号処理を加えることができない。   However, when a plurality of processing circuits are mounted on a single chip to process signals of a plurality of channels in this way, crosstalk is likely to occur between the channels, and accurate signal processing is performed on the signals obtained by each sensor. Cannot be added.

そこで、従来では、例えば特許文献１に記載のように、半導体集積回路のあるチャネル用の端子群と別のチャネル用の端子群との間に、空き端子を配置して、この空き端子を接地に接続したり、あるいはオープンにして、チャネル間のクロストークの防止を図る技術が提案されている。
特開平５６−８１９６２号公報 Therefore, conventionally, as described in Patent Document 1, for example, an empty terminal is arranged between a terminal group for one channel of a semiconductor integrated circuit and a terminal group for another channel, and the empty terminal is grounded. A technique for preventing crosstalk between channels by connecting to or opening the network has been proposed.
Japanese Patent Laid-Open No. 56-81962

ところが、特許文献１に記載の技術では、あるチャネル用の端子群と別のチャネル用の端子群との間での相互干渉は回避できても、複数の処理回路が搭載される半導体集積回路の基板が共通であるので、その基板を経由してチャネル間でクロストークが発生し、処理信号に歪が発生する。   However, in the technique described in Patent Document 1, even if mutual interference between a terminal group for one channel and a terminal group for another channel can be avoided, a semiconductor integrated circuit on which a plurality of processing circuits are mounted is used. Since the substrate is common, crosstalk occurs between the channels via the substrate, and the processing signal is distorted.

本発明の目的は、複数チャネルの信号を処理する際に、クロストークを完全に防止して信号歪が発生しないようにした半導体装置およびその製造方法を提供することである。   An object of the present invention is to provide a semiconductor device and a method of manufacturing the same that completely prevent crosstalk and prevent signal distortion when processing signals of a plurality of channels.

上記目的を達成するために、請求項１にかかる発明の半導体装置は、第１および第２の入力端子、第１および第２の出力端子、正電源端子、並びに負電源端子を備えた端子部と、ダイアイランド部とを有する無酸素銅材質のリードフレームと、入力電極、出力電極、正電源電極、および負電源電極を有し、同一半導体基板から個片化された同一特性の少なくとも２個の半導体チップとを備え、該２個の半導体チップは、前記リードフレームの前記ダイアイランド部に相互に絶縁されて搭載され、前記第１の入力端子と前記第１の半導体チップ上の前記入力電極とを接続する第１の接続手段、前記第１の出力端子と前記第１の半導体チップ上の前記出力電極とを接続する第２の接続手段、前記正電源端子と前記第１の半導体チップ上の前記正電源電極とを接続する第３の接続手段、前記負電源端子と前記第１の半導体チップ上の前記負電源電極とを接続する第４の接続手段、前記第２の入力端子と前記第２の半導体チップ上の前記入力電極とを接続する第５の接続手段、前記第２の出力端子と前記第２の半導体チップ上の前記出力電極とを接続する第６の接続手段、前記正電源端子と前記第２の半導体チップ上の前記正電源電極とを接続する第７の接続手段、前記負電源端子と前記第２の半導体チップ上の前記負電源電極とを接続する第８の接続手段が、クロスすることなく互いに離間配置され、前記第１乃至第８の接続手段は、前記第１の入力端子と前記第２の入力端子にそれぞれ同一信号を入力したとき、前記第１の出力端子と前記第２の出力端子からそれぞれ出力する信号が同一となり、且つ前記第１の入力端子に入力した信号が前記第２の出力端子から出力せず、前記第２の入力端子に入力した信号が前記第１の出力端子から出力しないように、それぞれ長さを調整することでインピーダンス調整されている、
ことを特徴とする。
請求項２にかかる発明は、請求項１に記載の半導体装置において、前記第１および第２の半導体チップの前記入力電極、前記出力電極、前記正電源電極、および前記負電源電極がミラー対称となるように前記第１および第２の半導体チップを互いに離間して配置し、前記第１乃至第８の接続手段の長さを調整することで前記インピーダンス調整を行ったことを特徴とする。
請求項３にかかる発明は、請求項１又は２に記載の半導体装置において、前記第１および第２の半導体チップは、半導体基板の結晶方位が同一であることを特徴とする。
請求項４にかかる発明の半導体装置の製造方法は、正電源電極と負電源電極の間に電源電圧が印加されることにより入力電極から入力した信号を処理して出力電極から出力する回路パターンを半導体基板上に複数形成し、該回路パターンを個片化して同一特性の少なくとも第１および第２の半導体チップを用意する工程と、第１および第２の入力端子、第１および第２の出力端子、正電源端子、並びに負電源端子を備えた端子部と、ダイアイランド部とを有する無酸素銅材質のリードフレームを用意する工程と、前記第１および第２の半導体チップを相互に絶縁して前記リードフレームの前記ダイアイランド部に搭載する工程と、前記第１の入力端子と前記第１の半導体チップ上の前記入力電極とを接続する第１の接続手段、前記第１の出力端子と前記第１の半導体チップ上の前記出力電極とを接続する第２の接続手段、前記正電源端子と前記第１の半導体チップ上の前記正電源電極とを接続する第３の接続手段、前記負電源端子と前記第１の半導体チップ上の前記負電源電極とを接続する第４の接続手段、前記第２の入力端子と前記第２の半導体チップ上の前記入力電極とを接続する第５の接続手段、前記第２の出力端子と前記第２の半導体チップ上の前記出力電極とを接続する第６の接続手段、前記正電源端子と前記第２の半導体チップ上の前記正電源電極とを接続する第７の接続手段、前記負電源端子と前記第２の半導体チップ上の前記負電源電極とを接続する第８の接続手段を、前記第１の入力端子と前記第２の入力端子にそれぞれ同一信号を入力したとき、前記第１の出力端子と前記第２の出力端子からそれぞれ出力する信号が同一となるように、且つ前記第１の入力端子に入力した信号が前記第２の出力端子から出力せず、前記第２の入力端子に入力した信号が前記第２の出力端子から出力しないように、それぞれ長さを調整することでインピーダンス調整して、クロスすることなく相互に離間して配置する工程と、前記第１および第２の半導体チップを１つのパッケージ内に封止する工程と、を備えることを特徴とする。 In order to achieve the above object, a semiconductor device according to a first aspect of the present invention includes a first and a second input terminal, a first and a second output terminal, a positive power supply terminal, and a terminal portion including a negative power supply terminal. And an oxygen-free copper lead frame having a die island portion, an input electrode, an output electrode, a positive power supply electrode, and a negative power supply electrode, and at least two of the same characteristics separated from the same semiconductor substrate The two semiconductor chips are mounted on the die island portion of the lead frame so as to be insulated from each other, and the first input terminal and the input electrode on the first semiconductor chip are mounted. First connection means for connecting the first output terminal and the second connection means for connecting the output electrode on the first semiconductor chip, the positive power supply terminal and the first semiconductor chip The positive power of Third connecting means for connecting an electrode, fourth connecting means for connecting the negative power supply terminal and the negative power supply electrode on the first semiconductor chip, the second input terminal and the second semiconductor Fifth connection means for connecting the input electrode on the chip, sixth connection means for connecting the second output terminal and the output electrode on the second semiconductor chip, the positive power supply terminal and the Seventh connection means for connecting the positive power supply electrode on the second semiconductor chip, and eighth connection means for connecting the negative power supply terminal and the negative power supply electrode on the second semiconductor chip are crossed. They are spaced from each other without connecting means of the first to eighth, when inputting the respectively identical signal to said first input terminal second input terminal, the said first output terminal a The signals output from the two output terminals are the same. Next, and the input signal is not outputted from the second output terminal to the first input terminal, as signal input to the second input terminal is not output from the first output terminal, respectively length The impedance is adjusted by adjusting the thickness,
It is characterized by that.
The invention according to claim 2 is the semiconductor device according to claim 1, wherein the input electrode, the output electrode, the positive power supply electrode, and the negative power supply electrode of the first and second semiconductor chips are mirror-symmetric. The first and second semiconductor chips are arranged so as to be spaced apart from each other, and the impedance adjustment is performed by adjusting the lengths of the first to eighth connection means.
According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the first and second semiconductor chips have the same crystal orientation of the semiconductor substrate.
According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a circuit pattern for processing a signal input from an input electrode by applying a power supply voltage between a positive power supply electrode and a negative power supply electrode, Forming a plurality of semiconductor patterns on a semiconductor substrate and preparing at least first and second semiconductor chips having the same characteristics by dividing the circuit pattern into pieces; first and second input terminals; and first and second outputs Preparing a lead frame made of oxygen-free copper material having a terminal portion having a terminal, a positive power supply terminal and a negative power supply terminal, and a die island portion; and isolating the first and second semiconductor chips from each other. Mounting on the die island portion of the lead frame, first connection means for connecting the first input terminal and the input electrode on the first semiconductor chip, and the first output Second connection means for connecting a child and the output electrode on the first semiconductor chip; third connection means for connecting the positive power supply terminal and the positive power supply electrode on the first semiconductor chip; Fourth connection means for connecting the negative power supply terminal and the negative power supply electrode on the first semiconductor chip, and a second connection means for connecting the second input terminal and the input electrode on the second semiconductor chip. 5 connection means, sixth connection means for connecting the second output terminal and the output electrode on the second semiconductor chip, the positive power supply terminal and the positive power supply electrode on the second semiconductor chip A seventh connection means for connecting the negative power supply terminal and an eighth connection means for connecting the negative power supply electrode on the second semiconductor chip, the first input terminal and the second input When the same signal is input to each terminal, the first output So that the signals output from the terminal and the second output terminal are the same, and the signal input to the first input terminal is not output from the second output terminal, and the signal is input to the second input terminal. Adjusting the impedance by adjusting the lengths so that the input signal is not output from the second output terminal, and arranging the signals apart from each other without crossing; and the first and second And a step of sealing the semiconductor chip in one package.

本発明によれば、個々の半導体チップが同一特性であり、それらが同一の半導体基板から個片化されたものであり、且つ各接続手段がインピーダンス調整されているので、それらの半導体チップに同一信号を入力したとき、高い精度で同一の処理が実行され、同一の出力信号が出力する。また、各々の半導体チップは、相互に絶縁されているので、各半導体チップ間で信号が相互に影響し合うことはなく、高いセパレーション特性を実現できる。よって、クロストークを大幅に減少させることができ、歪特性を改善できる。   According to the present invention, since the individual semiconductor chips have the same characteristics, they are separated from the same semiconductor substrate, and the impedance of each connection means is adjusted, so that they are the same as those semiconductor chips. When a signal is input, the same processing is executed with high accuracy and the same output signal is output. Further, since the semiconductor chips are insulated from each other, signals do not affect each other between the semiconductor chips, and high separation characteristics can be realized. Therefore, crosstalk can be greatly reduced, and distortion characteristics can be improved.

図１は本発明の半導体装置の内部の構成図である。１０はリードフレームであり、銅の純度が９９．９９％以上で酸素濃度が１０ｐｐｍ以下の無酸素銅を材質とするフレームである。このリードフレーム１０は、端子部１１とダイアイランド部１２を備え、端子部１１には端子１１１〜１１８が形成され、ダイアイランド部１２に２個の演算増幅器２０Ａ，２０Ｂが搭載される。   FIG. 1 is an internal configuration diagram of a semiconductor device of the present invention. A lead frame 10 is a frame made of oxygen-free copper having a copper purity of 99.99% or more and an oxygen concentration of 10 ppm or less. The lead frame 10 includes a terminal portion 11 and a die island portion 12. Terminals 111 to 118 are formed on the terminal portion 11, and two operational amplifiers 20 </ b> A and 20 </ b> B are mounted on the die island portion 12.

この２個の演算増幅器２０Ａ，２０Ｂは、結晶方位が揃ったウエハに同一の演算増幅器を複数形成し、これを個片化したものの中から２個を抽出したものであり、その特性は高い精度で同一となっている。   The two operational amplifiers 20A and 20B are obtained by forming a plurality of identical operational amplifiers on a wafer having the same crystal orientation and extracting two pieces from the same, and their characteristics are highly accurate. Are the same.

演算増幅器２０Ａには、正電源電極２１Ａ、出力電極２２Ａ、反転入力電極２３Ａ、非反転入力電極２４Ａ、負電源電極２５Ａがそれぞれ外縁部に沿って反時計回りで設けられ、また、演算増幅器２０Ｂには、正電源電極２１Ｂ、出力電極２２Ｂ、反転入力電極２３Ｂ、非反転入力電極２４Ｂ、負電源電極２５Ｂがそれぞれ外縁部に沿って時計回りで設けられている。   The operational amplifier 20A is provided with a positive power supply electrode 21A, an output electrode 22A, an inverting input electrode 23A, a non-inverting input electrode 24A, and a negative power supply electrode 25A in the counterclockwise direction along the outer edge portion. The positive power supply electrode 21B, the output electrode 22B, the inverting input electrode 23B, the non-inverting input electrode 24B, and the negative power supply electrode 25B are provided clockwise along the outer edge portion.

演算増幅器２０Ａ、２０Ｂは、電極２１Ａ〜２５Ａと電極２１Ｂ〜２５Ｂがミラー対称となるように、ダイアイランド部１２上に、互いに分離して、且つ相互に接触しない絶縁性接着剤によって、搭載される。   The operational amplifiers 20A and 20B are mounted on the die island portion 12 by an insulating adhesive that is separated from each other and does not contact each other so that the electrodes 21A to 25A and the electrodes 21B to 25B are mirror-symmetrical. .

各電極２１Ａ〜２５Ａはそれぞれ金線や銅線等のワイヤ３１Ａ〜３５Ａでリードフレーム１０の端子部１１の端子１１１〜１１５に、また、各電極２１Ｂ〜２５Ｂはそれぞれ金線や銅線等のワイヤ３１Ｂ〜３５Ｂで同端子部１１の端子１１１，１１６〜１１８に、接続される。このとき、電極２１Ａ〜２５Ａと電極２１Ｂ〜２５Ｂはミラー対称であり、且つ外縁部に沿って設けられているので、各ワイヤ３１Ａ〜３５Ａ、ワイヤ３１Ｂ〜３５Ｂは端子１１１１〜１１８に対してクロスすることなく、接続される。   The electrodes 21A to 25A are wires 31A to 35A such as gold wires and copper wires, respectively, and the terminals 111 to 115 of the terminal portion 11 of the lead frame 10, and the electrodes 21B to 25B are wires such as gold wires and copper wires, respectively. 31B to 35B are connected to the terminals 111 and 116 to 118 of the terminal portion 11. At this time, since the electrodes 21A to 25A and the electrodes 21B to 25B are mirror symmetric and are provided along the outer edge, the wires 31A to 35A and the wires 31B to 35B cross the terminals 1111 to 118. Without being connected.

演算増幅器２０Ａは、端子１１３と１１４に入力する信号を処理して端子１１２に出力し、演算増幅器２０Ｂは、端子１１７と１１８に入力する信号を処理して端子１１６に出力する。そして、それら演算増幅器２０Ａ，２０Ｂに入力する信号が同じときは、その信号処理は同じ内容となる。また、このとき、端子１１２から出力する信号と端子１１６から出力する信号が同一となるように、各ワイヤ３１Ａ〜３５Ａ，３１Ｂ〜３５Ｂのインピーダンスが調整されている。この調整は、ワイヤの長さを調節することにより行われる。   The operational amplifier 20A processes signals input to the terminals 113 and 114 and outputs the processed signals to the terminal 112, and the operational amplifier 20B processes signals input to the terminals 117 and 118 and outputs the processed signals to the terminal 116. When the signals input to the operational amplifiers 20A and 20B are the same, the signal processing is the same. At this time, the impedances of the wires 31A to 35A and 31B to 35B are adjusted so that the signal output from the terminal 112 and the signal output from the terminal 116 are the same. This adjustment is performed by adjusting the length of the wire.

図２は図１の二点鎖線で囲んだ部分をモールド４０でパッケージ化した半導体装置の等価回路図である。Ｒ１Ａ，Ｒ２Ａは演算増幅器２０Ａの電源ラインとなるワイヤ３１Ａ，３５Ａの抵抗、Ｒ１Ｂ，Ｒ２Ｂは演算増幅器２０Ｂの電源ラインとなるワイヤ３１Ｂ，３５Ｂの抵抗、Ｒ３は端子１１１の抵抗、Ｒ４は端子１１５の抵抗である。   FIG. 2 is an equivalent circuit diagram of a semiconductor device in which a portion surrounded by a two-dot chain line in FIG. R1A and R2A are resistances of wires 31A and 35A serving as power supply lines of the operational amplifier 20A, R1B and R2B are resistances of wires 31B and 35B serving as power supply lines of the operational amplifier 20B, R3 is resistance of the terminal 111, and R4 is resistance of the terminal 115. Resistance.

ここで、演算増幅器２０Ａが動作するときは、抵抗Ｒ１Ａ，Ｒ２Ａ，Ｒ３，Ｒ４を動作電流が流れ、演算増幅器２０Ｂが動作するときは、抵抗Ｒ１Ｂ，Ｒ２Ｂ，Ｒ３，Ｒ４を動作電流が流れる。このように、抵抗Ｒ３，Ｒ４には演算増幅器２０Ａ、２０Ｂの動作電流が共通に流れるので、ここでの電圧降下は相手方の演算増幅器への供給電圧に影響を与える。この影響は、抵抗Ｒ３，Ｒ４の値が大きいほど大きくなる。   Here, when the operational amplifier 20A operates, an operating current flows through the resistors R1A, R2A, R3, and R4. When the operational amplifier 20B operates, an operating current flows through the resistors R1B, R2B, R3, and R4. As described above, since the operating currents of the operational amplifiers 20A and 20B flow in the resistors R3 and R4 in common, the voltage drop here affects the supply voltage to the other operational amplifier. This influence increases as the values of the resistors R3 and R4 increase.

この点について、本実施例では、リードフレーム１０に前記したような無酸素銅の材質を使用するので、その抵抗Ｒ３、Ｒ４の値を大幅に小さくでき、演算増幅器２０Ａ，２０Ｂの動作電流が相互の動作に与える影響を小さくできる。これは、電源ラインのワイヤの抵抗Ｒ１ＡとＲ１Ｂの値の相違、抵抗Ｒ２ＡとＲ２Ｂの値の相違が大きい（長さの差が大きい）ときに、特に有効である。   In this regard, in this embodiment, since the lead frame 10 is made of the oxygen-free copper material as described above, the values of the resistors R3 and R4 can be greatly reduced, and the operational currents of the operational amplifiers 20A and 20B are mutually reduced. The influence on the operation of can be reduced. This is particularly effective when the difference between the resistances R1A and R1B of the power line wire and the difference between the resistances R2A and R2B are large (the difference in length is large).

以上のように、本実施例の半導体装置は、演算増幅器２０Ａ，２０Ｂが同一回路構成であり、且つそれらの半導体基板が結晶方位を同一とする基板であり、且つ各ワイヤ３１Ａ〜３５Ａ，３１Ｂ〜３５Ｂのインピーダンスが調整されているので、それらの演算増幅器２０Ａ，２０Ｂに同一信号を入力したとき高い精度で同一の処理が実行され、同一の出力信号が出力する。   As described above, in the semiconductor device of this embodiment, the operational amplifiers 20A and 20B have the same circuit configuration, the semiconductor substrates are substrates having the same crystal orientation, and the wires 31A to 35A and 31B to Since the impedance of 35B is adjusted, when the same signal is input to these operational amplifiers 20A and 20B, the same processing is executed with high accuracy and the same output signal is output.

このとき、演算増幅器２０Ａ，２０Ｂは、ダイアイランド部１２に分離して、絶縁性接着剤により搭載され、且つ信号や電源用のワイヤがクロスすることなく相互に離間しているので、演算増幅器２０Ａで処理される信号と演算増幅器２０Ｂで処理される信号とは、相互に影響し合うことはなく高いセパレーション特性を実現できる。特に、リードフレーム１０のインピーダンスが小さくなるので、演算増幅器２０Ａ，２０Ｂの動作電流が電源に流れる際、電源用の端子１１１，１１５における電圧降下が少なく、演算増幅器２０Ａ，２０Ｂの一方の動作電流が他方に与える影響が極めて小さくなる。よって、クロストークを大幅に減少させることができ、歪特性を改善できる。   At this time, the operational amplifiers 20A and 20B are separated into the die island portion 12 and mounted with an insulating adhesive, and the signal and power wires are separated from each other without crossing, so the operational amplifier 20A The signal processed in step 1 and the signal processed in the operational amplifier 20B do not affect each other and can achieve high separation characteristics. In particular, since the impedance of the lead frame 10 is reduced, when the operating current of the operational amplifiers 20A and 20B flows to the power supply, the voltage drop at the power supply terminals 111 and 115 is small, and the operating current of one of the operational amplifiers 20A and 20B is reduced. The effect on the other is extremely small. Therefore, crosstalk can be greatly reduced, and distortion characteristics can be improved.

図３は別の実施例の半導体装置の内部の構成図である。本実施例では、ダイアイランド部を、演算増幅器２０Ａ用と演算増幅器２０Ｂ用のダイアイランド部１２Ａ，１２Ｂに完全に分離している。演算増幅器２０Ａ，２０Ｂをダイアイランド部に搭載するとき、絶縁性接着剤を使用することにより、それら演算増幅器２０Ａ，２０Ｂをダイアイランド部に対して絶縁することができるが、その絶縁性接着剤の塗布厚が不十分なときは、演算増幅器２０Ａ，２０Ｂの半導体基板とダイアイランド部との間の容量が大きくなり、演算増幅器２０Ａ，２０Ｂがダイアイランド部を経由して容量結合される場合がある。この点につき、本実施例では分離したダイアイランド部１２Ａ，１２Ｂに演算増幅器２０Ａ，２０Ｂを搭載するので、絶縁性接着剤の塗布厚のバラツキの影響を回避し、演算増幅器２０Ａ，２０Ｂのセパレーションを充分に確保することができる。   FIG. 3 is an internal configuration diagram of a semiconductor device according to another embodiment. In the present embodiment, the die island portion is completely separated into die island portions 12A and 12B for the operational amplifier 20A and the operational amplifier 20B. When the operational amplifiers 20A and 20B are mounted on the die island part, the operational amplifiers 20A and 20B can be insulated from the die island part by using an insulating adhesive. When the coating thickness is insufficient, the capacitance between the semiconductor substrates of the operational amplifiers 20A and 20B and the die island portion increases, and the operational amplifiers 20A and 20B may be capacitively coupled via the die island portion. . In this embodiment, since the operational amplifiers 20A and 20B are mounted on the separated die island portions 12A and 12B in this embodiment, the influence of variations in the coating thickness of the insulating adhesive is avoided, and the operational amplifiers 20A and 20B are separated. It can be secured sufficiently.

なお、以上の実施例では、演算増幅器２０Ａ，２０Ｂを使用した場合について説明したが、本発明は信号処理を行う半導体チップであれば、演算増幅器に限られるものではない。また、上記実施例では、モールド４０内に２個の演算増幅器２０Ａ，２０Ｂが搭載される場合について説明したが、３個以上の半導体チップを同様の構成で搭載することができることは勿論である。   In the above embodiment, the case where the operational amplifiers 20A and 20B are used has been described. However, the present invention is not limited to the operational amplifier as long as it is a semiconductor chip that performs signal processing. In the above embodiment, the case where two operational amplifiers 20A and 20B are mounted in the mold 40 has been described, but it is needless to say that three or more semiconductor chips can be mounted in the same configuration.

本発明の実施例の半導体装置の内部の構成図である。It is an internal block diagram of the semiconductor device of the Example of this invention. 図１の半導体装置の等価回路図である。FIG. 2 is an equivalent circuit diagram of the semiconductor device of FIG. 1. 本発明の別の実施例の半導体装置の内部の構成図である。It is an internal block diagram of the semiconductor device of another Example of this invention.

符号の説明Explanation of symbols

１０：リードフレーム、１１：端子部、１２，１２Ａ，１２Ｂ：ダイアイランド部、１１１〜１１８：端子
２０Ａ，２０Ｂ：演算増幅器、２１Ａ〜２５Ａ、２１Ｂ〜２５Ｂ：電極
３１Ａ〜３５Ａ，３１Ｂ〜３５Ｂ：ワイヤ
４０：モールド 10: lead frame, 11: terminal portion, 12, 12A, 12B: die island portion, 111-118: terminal 20A, 20B: operational amplifier, 21A-25A, 21B-25B: electrode 31A-35A, 31B-35B: wire 40: Mold

Claims (4)

第１および第２の入力端子、第１および第２の出力端子、正電源端子、並びに負電源端子を備えた端子部と、ダイアイランド部とを有する無酸素銅材質のリードフレームと、
入力電極、出力電極、正電源電極、および負電源電極を有し、同一半導体基板から個片化された同一特性の少なくとも２個の半導体チップとを備え、
該２個の半導体チップは、前記リードフレームの前記ダイアイランド部に相互に絶縁されて搭載され、
前記第１の入力端子と前記第１の半導体チップ上の前記入力電極とを接続する第１の接続手段、前記第１の出力端子と前記第１の半導体チップ上の前記出力電極とを接続する第２の接続手段、前記正電源端子と前記第１の半導体チップ上の前記正電源電極とを接続する第３の接続手段、前記負電源端子と前記第１の半導体チップ上の前記負電源電極とを接続する第４の接続手段、前記第２の入力端子と前記第２の半導体チップ上の前記入力電極とを接続する第５の接続手段、前記第２の出力端子と前記第２の半導体チップ上の前記出力電極とを接続する第６の接続手段、前記正電源端子と前記第２の半導体チップ上の前記正電源電極とを接続する第７の接続手段、前記負電源端子と前記第２の半導体チップ上の前記負電源電極とを接続する第８の接続手段が、クロスすることなく互いに離間配置され、
前記第１乃至第８の接続手段は、前記第１の入力端子と前記第２の入力端子にそれぞれ同一信号を入力したとき、前記第１の出力端子と前記第２の出力端子からそれぞれ出力する信号が同一となり、且つ前記第１の入力端子に入力した信号が前記第２の出力端子から出力せず、前記第２の入力端子に入力した信号が前記第１の出力端子から出力しないように、それぞれ長さを調整することでインピーダンス調整されている、
ことを特徴とする半導体装置。 A lead frame made of oxygen-free copper having first and second input terminals, first and second output terminals, a positive power supply terminal, a terminal portion having a negative power supply terminal, and a die island portion;
An input electrode, an output electrode, a positive power supply electrode, and a negative power supply electrode, and comprising at least two semiconductor chips having the same characteristics separated from the same semiconductor substrate,
The two semiconductor chips are mounted insulated from each other on the die island portion of the lead frame,
First connection means for connecting the first input terminal and the input electrode on the first semiconductor chip, and connecting the first output terminal and the output electrode on the first semiconductor chip. Second connection means, third connection means for connecting the positive power supply terminal and the positive power supply electrode on the first semiconductor chip, the negative power supply terminal and the negative power supply electrode on the first semiconductor chip A fourth connecting means for connecting the second input terminal to the input electrode on the second semiconductor chip; a second connecting terminal for connecting the second output terminal to the second semiconductor; Sixth connection means for connecting the output electrode on the chip, seventh connection means for connecting the positive power supply terminal and the positive power supply electrode on the second semiconductor chip, the negative power supply terminal and the first Connecting the negative power supply electrode on the second semiconductor chip. Connection means being spaced from each other without cross,
The first to eighth connection means output from the first output terminal and the second output terminal, respectively, when the same signal is input to the first input terminal and the second input terminal, respectively. The signal is the same, and the signal input to the first input terminal is not output from the second output terminal, and the signal input to the second input terminal is not output from the first output terminal. , Impedance is adjusted by adjusting the length ,
A semiconductor device. 請求項１に記載の半導体装置において、
前記第１および第２の半導体チップの前記入力電極、前記出力電極、前記正電源電極、および前記負電源電極がミラー対称となるように前記第１および第２の半導体チップを互いに離間して配置し、前記第１乃至第８の接続手段の長さを調整することで前記インピーダンス調整を行ったことを特徴とする半導体装置。 The semiconductor device according to claim 1,
The first and second semiconductor chips are spaced apart from each other so that the input electrode, the output electrode, the positive power supply electrode, and the negative power supply electrode of the first and second semiconductor chips are mirror-symmetrical. The impedance adjustment is performed by adjusting the lengths of the first to eighth connection means. 請求項１又は２に記載の半導体装置において、
前記第１および第２の半導体チップは、半導体基板の結晶方位が同一であることを特徴とする半導体装置。 The semiconductor device according to claim 1 or 2,
The semiconductor device characterized in that the first and second semiconductor chips have the same crystal orientation of the semiconductor substrate. 正電源電極と負電源電極の間に電源電圧が印加されることにより入力電極から入力した信号を処理して出力電極から出力する回路パターンを半導体基板上に複数形成し、該回路パターンを個片化して同一特性の少なくとも第１および第２の半導体チップを用意する工程と、
第１および第２の入力端子、第１および第２の出力端子、正電源端子、並びに負電源端子を備えた端子部と、ダイアイランド部とを有する無酸素銅材質のリードフレームを用意する工程と、
前記第１および第２の半導体チップを相互に絶縁して前記リードフレームの前記ダイアイランド部に搭載する工程と、
前記第１の入力端子と前記第１の半導体チップ上の前記入力電極とを接続する第１の接続手段、前記第１の出力端子と前記第１の半導体チップ上の前記出力電極とを接続する第２の接続手段、前記正電源端子と前記第１の半導体チップ上の前記正電源電極とを接続する第３の接続手段、前記負電源端子と前記第１の半導体チップ上の前記負電源電極とを接続する第４の接続手段、前記第２の入力端子と前記第２の半導体チップ上の前記入力電極とを接続する第５の接続手段、前記第２の出力端子と前記第２の半導体チップ上の前記出力電極とを接続する第６の接続手段、前記正電源端子と前記第２の半導体チップ上の前記正電源電極とを接続する第７の接続手段、前記負電源端子と前記第２の半導体チップ上の前記負電源電極とを接続する第８の接続手段を、前記第１の入力端子と前記第２の入力端子にそれぞれ同一信号を入力したとき、前記第１の出力端子と前記第２の出力端子からそれぞれ出力する信号が同一となるように、且つ前記第１の入力端子に入力した信号が前記第２の出力端子から出力せず、前記第２の入力端子に入力した信号が前記第２の出力端子から出力しないように、それぞれ長さを調整することでインピーダンス調整して、クロスすることなく相互に離間して配置する工程と、
前記第１および第２の半導体チップを１つのパッケージ内に封止する工程と、
を備えることを特徴とする半導体装置の製造方法。 A plurality of circuit patterns are formed on the semiconductor substrate by processing a signal input from the input electrode by applying a power supply voltage between the positive power supply electrode and the negative power supply electrode, and outputting the circuit pattern from the output electrode. Preparing at least first and second semiconductor chips having the same characteristics,
A step of preparing a lead frame made of oxygen-free copper having first and second input terminals, first and second output terminals, a positive power supply terminal, a terminal portion having a negative power supply terminal, and a die island portion When,
A step of insulating the first and second semiconductor chips from each other and mounting them on the die island portion of the lead frame;
First connection means for connecting the first input terminal and the input electrode on the first semiconductor chip, and connecting the first output terminal and the output electrode on the first semiconductor chip. Second connection means, third connection means for connecting the positive power supply terminal and the positive power supply electrode on the first semiconductor chip, the negative power supply terminal and the negative power supply electrode on the first semiconductor chip A fourth connecting means for connecting the second input terminal to the input electrode on the second semiconductor chip; a second connecting terminal for connecting the second output terminal to the second semiconductor; Sixth connection means for connecting the output electrode on the chip, seventh connection means for connecting the positive power supply terminal and the positive power supply electrode on the second semiconductor chip, the negative power supply terminal and the first Connecting the negative power supply electrode on the second semiconductor chip. When the same signal is input to the first input terminal and the second input terminal, respectively, the signals output from the first output terminal and the second output terminal are the same. on, and the input signal is not outputted from the second output terminal to the first input terminal, as signal input to the second input terminal is not output from the second output terminal, respectively length Adjusting the impedance by adjusting the thickness and arranging them apart from each other without crossing ; and
Sealing the first and second semiconductor chips in one package;
A method for manufacturing a semiconductor device, comprising:
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