JP5256534B2 - Method for copying data between memory cells of semiconductor memory - Google Patents

Description

  The present invention relates to a technique for copying data between memory cells of a semiconductor memory.

SRAM (Static Random) in recent years
In the memory such as Access Memory), CMOS process technology mounted on SoC advances, processing dimensions (scaling size) of integrated circuits are reduced, higher chip density and lower chip cost are realized, and memory capacity increases. ing. Such reduction of the scaling size expands the variation in threshold voltage of the transistors constituting the memory cell such as SRAM, reduces the noise margin of reading and writing in the memory cell, destabilizes the memory cell operation, The bit error rate (BER) is increased.

  In view of the above situation, the present inventors can dynamically change the bit reliability of the memory cell according to the application and the memory situation, ensure the stability of the operation, reduce the power consumption and increase the reliability. For the purpose of providing a memory capable of realizing the characterization, a mode in which 1 bit is composed of one memory cell (1 bit / 1 cell mode, hereinafter referred to as “normal mode”) and 1 bit in n ( The mode (1 bit / n cell mode, hereinafter referred to as “high-reliability mode”) configured by linking two or more memory cells can be dynamically switched from the normal mode to the high-reliability mode. By switching to, a new semiconductor that increases the operation stability of 1 bit, increases the cell current of the read operation (speeds up the read operation), and can self-repair bit errors It has already proposed a memory (see Patent Document 1).

  One embodiment of such a proposed semiconductor memory is cross-coupled as shown in FIG. 1, in which each output is connected to a path leading to each of a pair of bit lines arranged corresponding to a column of memory cells. In a memory cell comprising a pair of inverters, a pair of switch portions provided between the bit line and the output of the inverter, and one word line whose conduction can be controlled, two adjacent A pair of P-type MOS transistors and one mode control line capable of controlling the P-type MOS transistors to be conductive are added between data holding nodes of two memory cells.

Here, the circuit operation of the memory cell of FIG. 1 will be briefly described.
A memory cell (MC01) shown in FIG. 1 includes a P-type MOS transistor (M00) and an N-type MOS transistor (M02) connected in series between a power supply potential VVDDA and a ground potential VGNDA, and a power supply potential VVDDA and a ground potential VGNDA. A latch circuit composed of a P-type MOS transistor (M01) and an N-type MOS transistor (M03) connected in series is formed. The memory cell (MC01) itself is a general 6-transistor memory cell.
Similarly, in memory cell (MC10), P-type MOS transistor (M10) and N-type MOS transistor (M12) connected in series between power supply potential VVDDB and ground potential VGNDB, and between power supply potential VVDDB and ground potential VGNDB. A latch circuit including a P-type MOS transistor (M11) and an N-type MOS transistor (M13) connected in series to each other is formed. The memory cell (MC10) itself is a memory cell having a general 6-transistor configuration.

  In the memory cell (MC01), the gate terminals of the P-type MOS transistor (M00) and the N-type MOS transistor (M02) are both connected to the node (N01) of the P-type MOS transistor (M01) and the N-type MOS transistor (M03). Has been. The gate terminals of the P-type MOS transistor (M01) and the N-type MOS transistor (M03) are both connected to the node (N00) of the P-type MOS transistor (M00) and the N-type MOS transistor (M02). Since the transistors M00 to M03 are thus cross-coupled, the P-type MOS transistors (M00, M01) operate as load transistors, and the N-type MOS transistors (M02, M03) operate as drive transistors. The same applies to the memory cell (MC10).

The memory cell (MC01) includes a switch portion of N-type MOS transistors (M04, M05) connected between the complementary bit lines (BL, / BL) and the nodes (N00, N01). The gate terminals of the N-type MOS transistors (M04, M05) are both connected to a common word line (WLA), and the gate potential of the N-type MOS transistors (M04, M05) is controlled by the word line (WLA). . That is, in the memory cell (MC01), the P-type MOS transistors (M00, M01) are used as load transistors, the N-type MOS transistors (M02, M03) are driven transistors, and the N-type MOS transistors (M04, M05) are used. It operates as a switch unit.
The memory cell (MC10) also includes a switch unit of N-type MOS transistors (M14, M15) connected between the complementary bit lines (BL, / BL) and the nodes (N10, N11). The gate terminals of the N-type MOS transistors (M14, M15) are both connected to a common word line (WLA), and the gate potential of the N-type MOS transistors (M14, M15) is controlled by the word line (WLA). .

  A pair of P-type MOS transistors (M20, M21) serving as a mode control switch unit are provided between the data holding nodes (between N00 and N10, between N01 and N11) of the memory cells (MC01, MC10). One mode control line (/ CTRL) for controlling the conduction of the P-type MOS transistors (M20, M21) is provided.

  In the memory cell having the circuit configuration as described above, 1-bit data is stored in the memory cell (MC01) and 1-bit data is stored in the two memory cells, the memory cell (MC01) and the memory cell (MC10). The mode control line (/ CTRL) can be used properly. The memory cell having the above circuit configuration has two modes: a mode in which 1 bit is constituted by one memory cell (normal mode) and a mode in which 1 bit is constituted by connecting two memory cells (high reliability mode). Therefore, the bit reliability of the memory cell can be dynamically changed according to the application and the memory condition, and the operation stability is ensured to realize low power consumption and high reliability. By switching from the normal mode to the high reliability mode, it is possible to increase the operation stability of 1 bit, increase the cell current of the read operation (speed up the read operation), and perform self-repair of bit errors.

  The operation modes such as the normal mode and the high reliability mode can be dynamically changed for each memory cell block as shown in FIG. When switching from the normal mode to the high reliability mode, it is necessary to store the same data in the paired memory cells (MC01, MC10). For this reason, in the memory cell block whose mode is switched from the normal mode to the high reliability mode, it is necessary to copy data between all the memory cells in the block.

PCT / JP2009 / 50086

  As described above, in the proposed semiconductor memory, it is necessary to store the same data in the paired memory cells when shifting from the normal mode to the high reliability mode. However, the method of writing data to all the memory cells in the memory block has a problem that a long cycle time is required.

  In view of the above situation, the present invention provides a high-speed transition from the normal mode to the high-reliability mode in the proposed semiconductor memory capable of dynamically changing the bit reliability QoB (Quality of Bit) of the memory cell. An object of the present invention is to provide a batch data copy method between memory cells that can be operated at a low voltage.

In order to achieve the above object, a data copy method between memory cells according to a first aspect of the present invention is such that each output is connected to a path leading to each of a pair of bit lines arranged corresponding to a column of memory cells. 1 composed of a pair of cross-coupled inverters, a pair of switch units provided between the bit line and the output of the inverter, and one word line for controlling conduction of the switch units 1 bit memory comprising: a bit memory cell; a mode control switch unit between data holding nodes of adjacent memory cells; and one mode control line for controlling conduction of the mode control switch unit. A mode consisting of cells (1 bit / 1 cell mode; normal mode) and a mode consisting of n memory cells (where n is 2 or more) (1 bit) / N cell mode (high reliability mode) can be dynamically switched using a mode control line from a 1 bit / 1 cell mode (normal mode) to a 1 bit / n cell mode (high reliability mode). When the mode is switched, the holding data is transferred from the copy source memory cell (copy source cell) to the copy destination memory cell (copy destination cell).
1-1) setting a pair of bit lines to a high level, a word line state of a copy destination cell to a high level, and setting a ground line of the copy destination cell to a power supply potential;
1-2) setting the state of the word line of the copy destination cell to low level;
1-3) controlling the mode control line to turn on the mode control switch unit;
1-4) returning the ground line of the copy destination cell to the ground potential;
Consists of

  According to the above steps 1-1) to 1-4), in the memory cell block to be switched from the normal mode to the high reliability mode, batch data copy between the memory cells can be performed at high speed in a short cycle, and at low voltage operation. Yes.

According to a second aspect of the present invention, there is provided a data copy method between memory cells, in which each output is connected to a path leading to each of a pair of bit lines arranged corresponding to a column of memory cells. A 1-bit memory cell comprising a pair of inverters, a pair of switch units provided between the bit line and the output of the inverter, and one word line for controlling conduction of the switch units; A mode control switch unit between data holding nodes of adjacent memory cells, and one mode control line for controlling conduction of the mode control switch unit, each bit being composed of one memory cell Mode (1 bit / 1 cell mode; normal mode) and a mode in which 1 bit consists of n (n is 2 or more) memory cells (1 bit / n cell mode; high In the semiconductor memory that can be dynamically switched using the mode control line, the mode is switched from the 1-bit / 1-cell mode (normal mode) to the 1-bit / n-cell mode (high reliability mode). A method of transferring held data from a copy source memory cell (copy source cell) to a copy destination memory cell (copy destination cell),
2-1) setting the state of the pair of bit lines to low level, setting the state of the word line of the copy destination cell to high level, and setting the power line of the copy destination cell to the ground potential;
2-2) setting the state of the word line of the copy destination cell to low level;
2-3) controlling the mode control line to turn on the mode control switch;
2-4) returning the power supply line of the copy destination cell to the power supply potential;
Consists of

  According to the above steps 2-1) to 2-4), in the memory cell block to be switched from the normal mode to the high reliability mode, batch data copy between the memory cells can be performed at high speed in a short cycle, and at low voltage operation. Yes. Further, the data copy method between the memory cells of the second aspect is compared with the data copy method between the memory cells of the first aspect until immediately before the mode control switch unit in the step 2-3) becomes conductive. Since the internal state of the copy destination cell becomes more unstable, that is, all the data held in the copy destination cell is at a low level, the bit error rate (BER) of data copy can be reduced.

Here, when the mode control switch unit is configured by a P-type MOS transistor, it is preferable to use the data copy method between memory cells according to the second aspect of controlling the power supply line of the copy destination cell.
When the mode control switch unit is composed of P-type MOS transistors, the second aspect of controlling the power supply line of the copy destination cell is more data copy than the first aspect of controlling the ground line of the copy destination cell. This is because the bit error rate (BER) can be further reduced, and it is possible to operate at a lower operating voltage.

The mode control switch section is preferably composed of an N-type MOS transistor.
When the mode control switch is composed of an N-type MOS transistor, both the first viewpoint for controlling the ground line of the copy destination cell and the second viewpoint for controlling the power supply line of the copy destination cell are both data copy bits. This is because the error rate (BER) can be further reduced and the operation can be performed at a lower operating voltage.

  According to the batch data copy method between memory cells of the present invention, the transition time from the normal mode to the high reliability mode is significantly shortened in the proposed semiconductor memory capable of dynamically changing the bit reliability QoB of the memory cells. In addition, the operation lower limit voltage can be lower than that of one memory cell (6-transistor configuration).

Circuit diagram of memory cell of proposed semiconductor memory capable of dynamically changing bit reliability QoB of memory cell Conceptual diagram of the memory cell block of the proposed semiconductor memory Circuit configuration diagram of memory cell of Embodiments 1 and 2 Explanatory drawing (1st step) of the circuit state for every step in the data copy method of Example 1 Explanatory drawing (2nd step) of the circuit state for every step in the data copy method of Example 1 Explanatory drawing of the circuit state for every step in the data copy method of Example 1 (3rd step) Explanatory drawing (4th step) of the circuit state for every step in the data copy method of Example 1 Waveform diagram of data held in memory cell in first to fourth steps of embodiment 1 Explanatory drawing (1st step) of the circuit state for every step in the data copy method of Example 2 Explanatory drawing (2nd step) of the circuit state for every step in the data copy method of Example 2 Explanatory drawing (3rd step) of the circuit state for every step in the data copy method of Example 2 Explanatory drawing of the circuit state for every step in the data copy method of Example 2 (4th step) Waveform diagram of data held in memory cell in first to fourth steps of embodiment 2 Circuit configuration diagram of memory cell of Examples 3 and 4 Explanatory drawing (1st step) of the circuit state for every step in the data copy method of Example 3 Explanatory drawing (2nd step) of the circuit state for every step in the data copy method of Example 3 Explanatory drawing (3rd step) of the circuit state for every step in the data copy method of Example 3 Explanatory drawing of the circuit state for every step in the data copy method of Example 3 (4th step) Waveform diagram of data held in memory cell in first to fourth steps of embodiment 3 Explanatory drawing (1st step) of the circuit state for every step in the data copy method of Example 4 Explanatory drawing (2nd step) of the circuit state for every step in the data copy method of Example 4 Explanatory drawing (3rd step) of the circuit state for every step in the data copy method of Example 4 Explanatory drawing of the circuit state for every step in the data copy method of Example 4 (4th step) Waveform diagram of data held in memory cell in first to fourth steps of embodiment 4 Graph of operating voltage and bit error rate during data copying in Examples 1 to 4

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The scope of the present invention is not limited to the following examples and illustrated examples, and various changes and modifications can be made.

FIG. 3 is a circuit configuration diagram of memory cells of the first embodiment and a second embodiment described later.
In the first embodiment, a pair of P-type MOS transistors (M20, M21) are provided as a mode control switch unit between the data holding nodes of a pair of 1-bit memory cells (MC01, MC10) composed of 6 transistors. In a semiconductor memory provided with one mode control line (/ CTRL) for controlling the conduction of a P-type MOS transistor, two bits from a mode (normal mode) in which one bit is composed of one memory cell A method of batch data copying between memory cells that makes a high-speed transition to a mode (high-reliability mode) constituted by the memory cells will be described below.

4A to 4D are explanatory diagrams of circuit states for each step in the batch data copying method between memory cells according to the first embodiment. 4A to 4D, the data held in the node (m0, m1) of the memory cell (MC01) is copied to the memory cell (MC10), and the node (m0, m1) of the memory cell (MC01) is copied. And the data held in the nodes (n0, n1) of the memory cell (MC10) are the same.
In the normal mode, one bit is composed of one memory cell (MC01). In the bit information of the memory cell (MC01), the node m0 is “H” and the node m1 is “L”.
When shifting from the normal mode to the high-reliability mode, one bit is composed of two memory cells (MC01, MC10). That is, when shifting from the normal mode to the high reliability mode, the data held in the node (m0, m1) of the memory cell (MC01) and the data held in the node (n0, n1) of the memory cell (MC10) should be the same. The data held in the memory cell (MC01) needs to be copied to the memory cell (MC10).

  As data copy methods, there are two methods for controlling the ground line (VVGDB) and the power supply line (VVDDB) of the memory cell (MC10) of the copy destination. In the first embodiment, a data copy procedure will be described as a method for controlling the ground line (VGNDB).

  First, as shown in FIG. 4A, the state of the pair of bit lines (BL, / BL) is set to the high level ("H"), and the word line (WLB) of the copy destination memory cell (MC10). The state is set to the high level (“H”), and the ground line (VGNDB) of the copy destination memory cell (MC10) is set to the power supply potential (“VDD”) (first step).

  Next, as shown in FIG. 4B, the state of the word line (WLB) of the copy destination memory cell (MC10) is set to the low level (“L”) (second step).

  Next, as shown in FIG. 4C, the conduction control of the P-type MOS transistors (M20, M21) connecting the copy source memory cell (MC01) and the copy destination memory cell (MC10) is performed. The mode control line (/ CTRL) is set to the low level (“L”), the P-type MOS transistors (M20, M21) are turned on, and the data held in the nodes (m0, m1) of the copy source memory cell (MC01) is stored. Data is transferred to the copy destination memory cell (MC10) (third step).

Finally, as shown in FIG. 4-4, the ground line (VGNDB) of the copy destination memory cell (MC10) is again returned to the ground potential (“GND”) state (fourth step).
This completes the process of copying the data held in the memory cell (MC01) to the memory cell (MC10).

FIG. 5 shows waveforms of data held in the memory cells in the first to fourth steps of the first embodiment. The upper waveform shows the signal waveform of the word line (WLB), the mode control line (CTRL), and the ground line (VGNDB) of the copy destination memory cell. The middle waveform shows the waveform of the data held in the nodes (m0, m1) of the copy source memory cell (MC01). The lower waveform shows the signal waveform of the data held in the node (n0, n1) of the copy destination memory cell (MC10) on the data rewrite side by copying.
As shown in FIG. 5, the node (n0, n1) of the copy destination memory cell (MC10) is held at the timing when the mode control line (CTRL) becomes low level (“L”) in the third step. Data has been rewritten.

By using the data copy method between the memory cells of the first embodiment, it becomes possible to copy all the data in the memory cell block sharing the ground line (VGND) in several cycles, and from the normal mode to the high reliability mode. It becomes possible to greatly shorten the transition time to.
Further, as will be described later, the bit error rate (BER) during the copy operation in the data copy method between the memory cells of the first embodiment is 0.5 (V) or less, and the conventional memory cell having a 6-transistor configuration Compared with the copy operation, the operation lower limit voltage can be further improved.

Next, in the second embodiment, as in the first embodiment, a pair of P-types as a mode control switch unit is provided between data holding nodes of a pair of 1-bit memory cells (MC01, MC10) including six transistors. In a semiconductor memory provided with MOS transistors (M20, M21) and one mode control line (/ CTRL) for controlling the conduction of the P-type MOS transistor, a mode in which one bit is composed of one memory cell A method of batch data copying between memory cells that makes a high-speed transition from a (normal mode) to a mode (high reliability mode) in which one bit is composed of two memory cells will be described below.
The first embodiment is a method for controlling the ground line (VGNDB), whereas the second embodiment performs data copying by a method for controlling the power supply line (VVDDB).

  First, as shown in FIG. 6A, the state of the pair of bit lines (BL, / BL) is set to the low level (“L”) and the word line (WLB) of the copy destination memory cell (MC10). The state is set to the high level (“H”), and the power supply line (VVDDB) of the copy destination memory cell (MC10) is set to the ground potential (“GND”) (first step).

  Next, as shown in FIG. 6B, the state of the word line (WLB) of the copy destination memory cell (MC10) is set to the low level (“L”) (second step).

  Next, as shown in FIG. 6C, the conduction control of the P-type MOS transistors (M20, M21) connecting the copy source memory cell (MC01) and the copy destination memory cell (MC10) is performed. The mode control line (/ CTRL) is set to the low level (“L”), the P-type MOS transistors (M20, M21) are turned on, and the data held in the nodes (m0, m1) of the copy source memory cell (MC01) is stored. Data is transferred to the copy destination memory cell (MC10) (third step).

Finally, as shown in FIG. 6-4, the power supply line (VVDDB) of the copy destination memory cell (MC10) is returned to the power supply potential (“VDD”) state (fourth step).
This completes the process of copying the data held in the nodes (m0, m1) of the memory cell (MC01) to the memory cell (MC10).

FIG. 7 shows waveforms of data held in the memory cells in the first step to the fourth step of the second embodiment. The upper waveform shows the signal waveform of the word line (WLB), the mode control line (CTRL), and the power supply line (VVDDB) of the copy destination memory cell. The middle waveform shows the waveform of the data held in the nodes (m0, m1) of the copy source memory cell (MC01). The lower waveform shows the signal waveform of the data held in the node (n0, n1) of the copy destination memory cell (MC10) on the data rewrite side by copying.
As shown in FIG. 7, in the third step, the node (n0, n1) of the copy destination memory cell (MC10) is held at the timing when the mode control line (CTRL) becomes low level (“L”). Data has been rewritten.
Further, as shown in FIG. 7, until immediately before the timing when the mode control line (CTRL) becomes low level (“L”), the internal state of the copy destination memory cell becomes more unstable, that is, the copy destination memory. Since all the data held in the cell is at a low level, the bit error rate (BER) of data copy can be reduced.

By using the data copy method between the memory cells of the second embodiment, it becomes possible to copy all the data in the memory cell block sharing the power supply line (VVDD) in several cycles, from the normal mode to the high reliability mode. It becomes possible to greatly shorten the transition time to.
Further, as will be described later, the bit error rate (BER) during the copy operation in the data copy method between the memory cells of the second embodiment is 0.5 (V) or less, and the conventional memory cell having a 6-transistor configuration Compared with the copy operation, the operation lower limit voltage can be further improved.

Next, FIG. 8 is a circuit configuration diagram of the memory cell of the third embodiment and a fourth embodiment described later.
In the third embodiment, a pair of N-type MOS transistors (M20, M21) are provided as a mode control switch unit between the data holding nodes of a pair of 1-bit memory cells (MC01, MC10) composed of 6 transistors. In a semiconductor memory provided with one mode control line for controlling conduction of an N-type MOS transistor, a mode in which one bit is composed of one memory cell (normal mode) and a memory in which one bit is two A batch data copy method between memory cells that shifts to a configured mode (high reliability mode) at high speed will be described below.

9A to 9D are explanatory diagrams of circuit states for each step in the batch data copy method between memory cells according to the third embodiment. 9A to 9D, data held in the memory cell (MC01) node (m0, m1) is copied to the memory cell (MC10), and the data stored in the node (m0, m1) of the memory cell (MC01) is copied. Assume that the retained data and the retained data of the node (n0, n1) of the memory cell (MC10) are the same.
In the normal mode, one bit is composed of one memory cell (MC01). Bit information of the memory cell (MC01) is retained data of the node (m0, m1).
When shifting from the normal mode to the high-reliability mode, one bit is composed of two memory cells (MC01, MC10). That is, when shifting from the normal mode to the high-reliability mode, the memory cell (MC0) holds data (m0, m1) and the memory cell (MC10) hold data (n0, n1) to be the same. The data held in the node (m0, m1) of MC01) needs to be copied to the memory cell (MC10).

  As data copy methods, there are two methods for controlling the ground line (VVGDB) and the power supply line (VVDDB) of the memory cell (MC10) of the copy destination. In the third embodiment, a data copy procedure will be described as a method for controlling the ground line (VVGDB).

  First, as shown in FIG. 9A, the state of the pair of bit lines (BL, / BL) is set to the high level (“H”), and the word line (WLB) of the copy destination memory cell (MC10). The state is set to the high level (“H”), and the ground line (VGNDB) of the copy destination memory cell (MC10) is set to the power supply potential (“VDD”) (first step).

  Next, as shown in FIG. 9B, the state of the word line (WLB) of the copy destination memory cell (MC10) is set to the low level (“L”) (second step).

  Next, as shown in FIG. 9C, the conduction control of the N-type MOS transistors (M20, M21) connecting the copy source memory cell (MC01) and the copy destination memory cell (MC10) is performed. The mode control line (CTRL) is set to a high level (“H”), the N-type MOS transistors (M20, M21) are turned on, and the data (m0, m1) held in the copy source memory cell (MC01) is transferred to the copy destination. Data is transferred to the memory cell (MC10) (third step).

Finally, as shown in FIG. 9-4, the ground line (VGNDB) of the copy destination memory cell (MC10) is again returned to the ground potential (“GND”) state (fourth step).
This completes the process of copying the data (m0, m1) held in the memory cell (MC01) to the memory cell (MC10).

FIG. 10 shows waveforms of data held in the memory cells in the first step to the fourth step of the third embodiment. The upper waveform shows the signal waveform of the word line (WLB), the mode control line (CTRL), and the ground line (VGNDB) of the copy destination memory cell. The middle waveform shows the waveform of the data held in the nodes (m0, m1) of the copy source memory cell (MC01). The lower waveform shows the signal waveform of the data held in the node (n0, n1) of the copy destination memory cell (MC10) on the data rewrite side by copying.
As shown in FIG. 10, in the third step, the node (n0, n1) of the copy destination memory cell (MC10) is held at the timing when the mode control line (CTRL) becomes high level (“H”). Data has been rewritten.

By using the data copy method between the memory cells of the third embodiment, it becomes possible to copy all the data in the memory cell block sharing the ground line (VGND) in several cycles, from the normal mode to the high reliability mode. It becomes possible to greatly shorten the transition time to.
Further, as will be described later, the bit error rate (BER) during the copy operation in the data copy method between the memory cells of the third embodiment is 0.5 (V) or less, and the conventional memory cell having a 6-transistor configuration Compared with the copy operation, the operation lower limit voltage can be further improved.

Next, in the fourth embodiment, as in the third embodiment, a pair of N-types as a mode control switch unit is provided between data holding nodes of a pair of 1-bit memory cells (MC01, MC10) composed of six transistors. In a semiconductor memory provided with MOS transistors (M20, M21) and one mode control line (CTRL) for controlling the conduction of the N-type MOS transistor, a mode in which one bit is composed of one memory cell ( A batch data copy method between memory cells that shifts from a normal mode) to a mode (high reliability mode) in which one bit is composed of two memory cells will be described below.
The third embodiment is a method for controlling the ground line (VGNDB), whereas the fourth embodiment performs data copying by a method for controlling the power supply line (VVDDB).

  First, as shown in FIG. 11A, the state of the pair of bit lines (BL, / BL) is set to the low level (“L”), and the word line (WLB) of the copy destination memory cell (MC10). The state is set to the high level (“H”), and the power supply line (VVDDB) of the copy destination memory cell (MC10) is set to the ground potential (“GND”) (first step).

  Next, as shown in FIG. 11B, the state of the word line (WLB) of the copy destination memory cell (MC10) is set to the low level (“L”) (second step).

  Next, as shown in FIG. 11C, the conduction control of the N-type MOS transistors (M20, M21) connecting the copy source memory cell (MC01) and the copy destination memory cell (MC10) is performed. The mode control line (CTRL) is set to high level (“H”), the N-type MOS transistors (M20, M21) are turned on, and the data held in the nodes (m0, m1) of the copy source memory cell (MC01) is copied. Data is transferred to the previous memory cell (MC10) (third step).

Finally, as shown in FIG. 11-4, the power supply line (VVDDB) of the copy destination memory cell (MC10) is again returned to the power supply potential (“VDD”) state (fourth step).
This completes the process of copying the data held in the nodes (m0, m1) of the memory cell (MC01) to the memory cell (MC10).

FIG. 12 shows waveforms of data held in the memory cells in the first to fourth steps of the fourth embodiment. The upper waveform shows the signal waveform of the word line (WLB), the mode control line (CTRL), and the power supply line (VVDDB) of the copy destination memory cell. The middle waveform shows the waveform of the data held in the nodes (m0, m1) of the copy source memory cell (MC01). The lower waveform shows the signal waveform of the data held in the node (n0, n1) of the copy destination memory cell (MC10) on the data rewrite side by copying.
As shown in FIG. 12, in the third step, the node (n0, n1) of the copy destination memory cell (MC10) is held at the timing when the mode control line (CTRL) becomes high level (“H”). Data has been rewritten.
Also, as shown in FIG. 12, until the timing immediately before the mode control line (CTRL) becomes high level (“H”), the internal state of the copy destination memory cell becomes more unstable, that is, the copy destination memory. Since all the data held in the cell is at a low level, the bit error rate (BER) of data copy can be reduced.

By using the data copy method between the memory cells of the fourth embodiment, it becomes possible to copy all the data in the memory cell block sharing the power supply line (VVDD) in several cycles, from the normal mode to the high reliability mode. It becomes possible to greatly shorten the transition time to.
As will be described later, the bit error rate (BER) during the copy operation in the data copy method between memory cells of the fourth embodiment is 0.5 (V) or less. Compared with the copy operation, the operation lower limit voltage can be further improved.

FIG. 13 shows a graph of operating voltage and bit error rate during data copying in Examples 1 to 4. The horizontal axis is the operating voltage, and the vertical axis is the bit error rate (BER). The bit error rate (BER) at the time of the copy operation in the data copy method between the memory cells of Examples 1 to 4 is 0.5 (V) or less, which is compared with the copy operation of the conventional memory cell having a 6-transistor configuration. Thus, the operating lower limit voltage can be further improved.
More specifically, in the case of a conventional memory cell having a 6-transistor structure, the bit error rate (BER) of the data copy operation is 1. The operation lower limit voltage at E- ⁴ is 0.61 (V). On the other hand, the bit error rates (BER) of the data copy operations of the first to fourth embodiments are all 0.5 (V) or less.

  In particular, when the mode control switch unit is composed of P-type MOS transistors, the power supply line of the copy destination memory cell is controlled rather than the data copy method of the first embodiment that controls the ground line of the copy destination memory cell. It can be seen that the data copy method of Example 2 has a lower bit error rate (BER) and a lower operation lower limit voltage.

  In the case of the data copy method according to the third and fourth embodiments in which the mode control switch unit is configured by an N-type MOS transistor, the first and second embodiments in which the mode control switch unit is configured by a P-type MOS transistor. It can be seen that the bit error rate (BER) is lower and the operation lower limit voltage is smaller than the data copy method.

  The present invention is useful for an SRAM used for a cache memory of a computer or the like.

MC01, MC10 memory cell

Claims (6)

Provided between a pair of cross-coupled inverters, each output connected to a path leading to each of a pair of bit lines arranged corresponding to a column of memory cells, and the output of the bit line and the inverter A 1-bit memory cell comprising a pair of switch units and one word line for controlling conduction of the switch units;
A mode control switch unit between data holding nodes of adjacent memory cells, and one mode control line for controlling conduction of the mode control switch unit,
A mode in which 1 bit is composed of one memory cell (1 bit / 1 cell mode) and a mode in which 1 bit is composed of n (n is 2 or more) memory cells connected (1 bit / n In a semiconductor memory that can be dynamically switched using a mode control line,
When the mode is switched from the 1 bit / 1 cell mode to the 1 bit / n cell mode, the held data is transferred from the copy source memory cell (copy source cell) to the copy destination memory cell (copy destination cell). A method,
1-1) setting a pair of bit lines to a high level, setting a word line of the copy destination cell to a high level, and setting a ground line of the copy destination cell to a power supply potential;
1-2) setting the state of the word line of the copy destination cell to low level;
1-3) controlling the mode control line to turn on the mode control switch unit;
1-4) returning the ground line of the copy destination cell to the ground potential;
A method for copying data between memory cells. Provided between a pair of cross-coupled inverters, each output connected to a path leading to each of a pair of bit lines arranged corresponding to a column of memory cells, and the output of the bit line and the inverter A 1-bit memory cell comprising a pair of switch units and one word line for controlling conduction of the switch units;
A mode control switch unit between data holding nodes of adjacent memory cells, and one mode control line for controlling conduction of the mode control switch unit,
A mode in which 1 bit is composed of one memory cell (1 bit / 1 cell mode) and a mode in which 1 bit is composed of n (n is 2 or more) memory cells connected (1 bit / n In a semiconductor memory that can be dynamically switched using a mode control line,
When the mode is switched from the 1 bit / 1 cell mode to the 1 bit / n cell mode, the held data is transferred from the copy source memory cell (copy source cell) to the copy destination memory cell (copy destination cell). A method,
2-1) setting a pair of bit lines to a low level, setting a word line of the copy destination cell to a high level, and setting a power supply line of the copy destination cell to a ground potential;
2-2) setting the state of the word line of the copy destination cell to a low level;
2-3) controlling the mode control line to turn on the mode control switch unit;
2-4) returning the power supply line of the copy destination cell to the power supply voltage;
A method for copying data between memory cells. Provided between a pair of cross-coupled inverters, each output connected to a path leading to each of a pair of bit lines arranged corresponding to a column of memory cells, and the output of the bit line and the inverter A 1-bit memory cell comprising a pair of switch units and one word line for controlling conduction of the switch units;
A mode control switch unit between data holding nodes of adjacent memory cells, and one mode control line for controlling conduction of the mode control switch unit,
A mode in which 1 bit is constituted by one memory cell (1 bit / 1 cell mode) and a mode in which 1 bit is constituted by connecting two memory cells (1 bit / 2 cell mode) In a semiconductor memory that can be switched dynamically using a mode control line,
When the mode is switched from the 1 bit / 1 cell mode to the 1 bit / 2 cell mode, the holding data is transferred from the copy source memory cell (copy source cell) to the copy destination memory cell (copy destination cell). A method,
1-1) setting a pair of bit lines to a high level, setting a word line of the copy destination cell to a high level, and setting a ground line of the copy destination cell to a power supply potential;
1-2) setting the state of the word line of the copy destination cell to low level;
1-3) controlling the mode control line to turn on the mode control switch unit;
1-4) returning the ground line of the copy destination cell to the ground potential;
A method for copying data between memory cells. Provided between a pair of cross-coupled inverters, each output connected to a path leading to each of a pair of bit lines arranged corresponding to a column of memory cells, and the output of the bit line and the inverter A 1-bit memory cell comprising a pair of switch units and one word line for controlling conduction of the switch units;
A mode control switch unit between data holding nodes of adjacent memory cells, and one mode control line for controlling conduction of the mode control switch unit,
A mode in which 1 bit is constituted by one memory cell (1 bit / 1 cell mode) and a mode in which 1 bit is constituted by connecting two memory cells (1 bit / 2 cell mode) In a semiconductor memory that can be switched dynamically using a mode control line,
When the mode is switched from the 1 bit / 1 cell mode to the 1 bit / 2 cell mode, the holding data is transferred from the copy source memory cell (copy source cell) to the copy destination memory cell (copy destination cell). A method,
2-1) setting a pair of bit lines to a low level, setting a word line of the copy destination cell to a high level, and setting a power supply line of the copy destination cell to a ground potential;
2-2) setting the state of the word line of the copy destination cell to a low level;
2-3) controlling the mode control line to turn on the mode control switch unit;
2-4) returning the power supply line of the copy destination cell to the power supply voltage;
A method for copying data between memory cells.   The mode control switch unit has a configuration in which a pair of P-type MOS transistors are arranged between data holding nodes of adjacent memory cells, and the mode control line controls the gate of the P-type MOS transistor. 5. A method for copying data between memory cells according to claim 2 or 4, wherein: The mode control switch unit has a configuration in which a pair of N-type MOS transistors are disposed between data holding nodes of adjacent memory cells, and the mode control line controls the gate of the N-type MOS transistor. 5. A method for copying data between memory cells according to claim 1.