JP5252891B2 - Manufacturing method of semiconductor chip and manufacturing method of semiconductor chip laminated module - Google Patents

Description

  The present invention relates to a semiconductor chip stacked module in which a plurality of semiconductor chips are three-dimensionally stacked in one module, a semiconductor chip constituting the same, and a method for manufacturing the same.

  Conventionally, a technology for modularizing a plurality of semiconductor chips and packaging them through an interposer substrate has been performed. In many cases, however, semiconductor chips are two-dimensionally arranged on the interposer substrate, thereby improving functionality. Therefore, there is a problem that the mounting area increases as the number of semiconductor chips arranged increases. On the other hand, as an approach for reducing the package size, a technique has been attempted in which semiconductor chips are three-dimensionally stacked to form a module, and this module is packaged via an interposer substrate.

FIG. 11 shows the structure of a conventional semiconductor chip stacked module.
In FIG. 11, a protective film 102 made of SiO ₂ or the like is grown on the upper surface of the semiconductor chip 101 over the entire surface. Reference numeral 103 denotes a wiring pad that is formed of aluminum (Al) or the like and is electrically connected to the semiconductor integrated circuit. The protective film 102 is provided with a notch 104 that opens on the upper surface and side surfaces and is exposed to the outside. Reference numeral 105 denotes a wiring portion formed by metal deposition, and the wiring pads 103 of the different semiconductor chips 101 are electrically connected to each other by the wiring portion 105. Reference numeral 106 denotes a wire bonding pad formed of Al or the like, which is electrically connected to the semiconductor integrated circuit, and is exposed by providing an opening 107 having an upper surface opened in the protective film 102 of the uppermost semiconductor chip 101 (for example, Patent Literature 1).
JP-A-8-236690

  However, the conventional configuration disclosed in Patent Document 1 has a problem in that stacking can be performed only by a dedicated semiconductor chip manufactured in advance so that electrodes are exposed on the side surfaces for three-dimensional stacking.

  Regarding the process, first, the bonding surfaces of the stacked semiconductor chips are fixed with an adhesive, and then a photoresist is formed on the side surfaces of the bonded semiconductor chips for metal deposition of the side wiring. Then, the photoresist at a necessary portion is removed by exposure and development. Next, metal deposition to be the side wiring electrode is performed, and the side wiring is created by removing the photoresist and the metal deposited thereon. As another method, a metal is first deposited on the side surface of the laminated semiconductor chip bonded with an adhesive, and then a photoresist is formed on the metal surface, and a photoresist other than the wiring pad portion and its periphery is applied. After removing the metal by exposure and development to expose the metal, the exposed metal portion is removed by etching to create the side wiring. As described above, in order to perform three-dimensional lamination and form wiring on the side surface of the module, in any of the processes, an adhesive application process, a photoresist formation process, an exposure, a development process, a metal vapor deposition process, a photoresist The removal process and many processes are necessary, and there is a problem that it is complicated and requires time and cost. Further, when stacking semiconductor chips having different external dimensions, the process becomes more difficult.

  The present invention solves the above-mentioned conventional problems, and even in a semiconductor chip having a different external dimension or a semiconductor chip in which a wiring is not formed in advance on a side surface, it is easy to stack three-dimensionally with few steps. Objective.

In order to achieve the above object, according to the method for manufacturing a semiconductor chip of the present invention , a circuit and an electrode are formed on the first surface when manufacturing one semiconductor chip that is three-dimensionally stacked to form a semiconductor chip stacked module. A step of preparing a semiconductor chip to be manufactured, a step of supplying an insulating adhesive containing a conductive filler to the first surface of the semiconductor chip and a side surface in contact with the first surface, and applying pressure to reduce the volume Accordingly, and forming the conductive path from the semiconductor chip electrode on the side surface by aggregating the conductive filler of a desired portion of the insulating adhesive, the semiconductor chip laminated by using the conductive path The semiconductor chips at the time of module manufacture are electrically connected.

The insulating adhesive may have thermosetting properties at a predetermined temperature .
Further, the insulating adhesive and the edge surface insulating adhesive may comprise thermosetting at a given temperature.

  As described above, even a semiconductor chip having a different external dimension or a semiconductor chip in which a wiring is not formed in advance on a side surface can be easily three-dimensionally stacked with few steps.

  As described above, the adhesive containing the conductive filler is supplied to the entire first surface where the electrode pads are formed and the side surfaces of the stacked semiconductor chips, and the predetermined electrode pads are electrically connected between the first surface and the side surfaces. By forming a rewiring that connects to the semiconductor chip, semiconductor chips that do not have electrode pads for connecting the semiconductor chips stacked on the side surfaces are stacked, or semiconductor chips having different external dimensions Even in the case of stacking, it is possible to easily form an electrically connected semiconductor chip stacked module by forming the rewiring with the same material.

Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
1A and 1B are diagrams showing a configuration of a semiconductor chip laminated module according to Embodiment 1, FIG. 1A is a perspective view of the semiconductor chip laminated module, and FIG. 1B is a cross-sectional view of the semiconductor chip laminated module. Yes. In FIG. 1, the electrode leads 2 from the electrode pad 2 of the semiconductor chip 1 to the surface in contact with the first surface on which the electrode pad 2 is formed (hereinafter referred to as a side surface) by the rewiring 4a. A plurality of semiconductor chips 1 having the same specifications are formed, and in the case shown in the figure, four chips are three-dimensionally stacked and bonded to each other. Hereinafter, an example in which a conductive path is further formed by the rewiring 4b over the stacked side surface) is shown.

  In FIG. 1, each semiconductor chip 1 is supplied with a conductive filler-containing adhesive made of an insulating adhesive containing a conductive filler on the active surface (circuit forming surface) and the side surface of the rewiring lead side in advance. In this state, the conductive filler is agglomerated by heat energy or a pressing jig at a desired rewiring location to secure a rewiring 4a as a conductive path from the electrode pad 2 to the side surface of the laminate. A plurality of semiconductor chips 1 are stacked while the insulating adhesive at the portion where no pressure is applied by the pressure jig is not cured. After that, by applying predetermined heat to the whole surface, the insulating adhesive 5 containing the conductive filler existing on the bonding surface (thermosetting) is fixed while being kept in an insulating state. Similarly, the rewiring 4b extending over the side surfaces of the plurality of semiconductor chips after being bonded is in a state where rewiring has been made to the laminated side insulating adhesive supplied to the laminated side surface by thermal energy or a pressing jig. Thereby, the electrode pads 2 of each predetermined semiconductor chip are connected by the rewiring 4a and the rewiring 4b.

  FIG. 2 is a perspective view showing the manufacturing process of the semiconductor chip in the first embodiment, and FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor chip in the first embodiment. Hereinafter, the manufacturing process will be described with reference to FIGS.

  First, in FIG. 2A and FIG. 3A, a semiconductor circuit is formed on the first surface, and after the electrode pad 2 is formed, dicing is performed in a state where the portions other than the electrode pad 2 are covered with an insulating protective film. The semiconductor chip 1 is shown in which the laminated side surfaces separated from the semiconductor wafer by, and further diced are covered with an insulating protective film. Next, as shown in FIGS. 2B and 3B, an adhesive 3 containing a conductive filler is supplied to the active surface (circuit forming surface) which is the first surface of the semiconductor chip and the side surface of the stack. As a method for supplying the conductive filler-containing adhesive 3, a paste-like material is applied so as to have a substantially uniform thickness, or a material processed into a sheet shape with a predetermined thickness is attached. There is.

  Next, as shown in FIG. 2C and FIG. 3C, rewiring 4a is performed for drawing out the electrodes from the electrode pads 2 of the semiconductor chip 1 to the stacked side surfaces. As a means for the rewiring 4a, the irradiation spot diameter of the thermal energy 6 such as a laser beam or a light beam having a high thermal energy is adjusted from the electrode pad 2 in a state in which it is adjusted to a desired wiring width at the time of the rewiring. Trace the conductive path to the desired location on the side of the stack. The component (insulating adhesive) that prevents the conductive fillers in the adhesive 3 containing conductive fillers from contacting with each other by the thermal energy 6 is removed, and the conductive filler contacts only at the location where the thermal energy 6 is applied. Thus, conductivity is obtained, and the rewiring 4a is formed. At this time, the conductive filler-containing adhesive 3 where the thermal energy 6 is not applied is not cured and remains insulative. Note that the conductive path may be formed by applying a pressure only to a desired conductive path with a pressurizing jig to obtain contact between the conductive fillers.

  Finally, as shown in FIGS. 2 (d) and 3 (d), heat is applied to the entire adhesive filler-containing adhesive 3 under predetermined thermosetting conditions, and the conductive portions other than the portion where the rewiring 4a is formed. The adhesive 3 with filler is cured while maintaining the insulating property to obtain an adhesive 5 after curing. In this step, the adhesive containing the conductive filler 3 may be cured by irradiating the entire surface of the semiconductor chip with ultraviolet rays using a curing condition of the adhesive 3 containing the conductive filler.

FIG. 4 is a diagram showing a manufacturing process of the semiconductor chip laminated module in the first embodiment.
Hereinafter, the manufacturing process of the semiconductor chip laminated module will be described in order according to FIG.

  First, FIG. 4A shows a state in which the semiconductor chips 7 are stacked. Here, the semiconductor chip 7 is an adhesive 3 containing a conductive filler supplied from an active surface (circuit forming surface), which is the first surface of the chip, to the laminated side surface, and a rewiring 4a from the electrode pad 2 to the laminated side surface. This refers to a semiconductor chip that has been completed by irradiation with thermal energy 6 (see FIG. 3), etc., and has not yet been thermally cured with the conductive filler-containing adhesive 3 at a location where rewiring 4a has not been performed. Next, as shown in FIG. 4 (b), predetermined heat is applied to the whole of the plurality of semiconductor chips 7 that are aligned and overlapped, and the conductive filler in the uncured portion in FIG. 4 (a). The adhesive 3 is thermally cured to form an adhesive 5, and the bonding surfaces of the semiconductor chips 7 are bonded and fixed. At this stage, the module is fixed as a single module, but the electrodes of each chip are not connected or wired.

  Next, as shown in FIG. 4C, the adhesive 3 containing conductive filler is supplied as the laminated side insulating adhesive to the entire laminated side surface of the plurality of semiconductor chips 7 that are bonded and fixed. Note that the material supply means in this step also uses paste-like material application or sheet-like material application means. Next, as shown in FIG. 4D, the side surface rewiring 4b between the stacked semiconductor chips 7 is formed. In order to form a desired conductive path across the side surfaces of a plurality of semiconductor chips, thermal energy such as a laser is irradiated with a predetermined irradiation width to form a conductive path having a predetermined shape. Note that the conductive path may be formed by applying a pressure only to a desired conductive path with a pressurizing jig to obtain contact between the conductive fillers.

  Finally, as shown in FIG. 4 (e), by applying a predetermined temperature to the entire module, the uncured portion of the conductive filler-containing adhesive 3 supplied to the laminated side surface is cured to form an adhesive 5. Complete the laminated module.

  Note that the adhesive containing conductive filler supplied to the side surface of the laminate may be cured using ultraviolet (UV) curing as the curing condition, and the adhesive containing conductive filler is irradiated by irradiating the side surface with ultraviolet light.

As described above, the adhesive containing the conductive filler is supplied to the first surface on which the electrode pads are formed and to the entire side surface of the stacked semiconductor chips, and between the predetermined electrode pads through the first surface and the side surfaces. A semiconductor chip in which electrode pads for connecting between semiconductor chips stacked on the side surface are not formed by forming a rewiring to be electrically connected by contacting a conductive filler in an adhesive containing a conductive filler. Even when stacking semiconductor chips or stacking semiconductor chips with different external dimensions, the semiconductor chip stacking can be easily electrically connected by forming the rewiring all together with the same material as the adhesive. Modules can be formed.
(Embodiment 2)
FIG. 5 is a diagram showing a manufacturing process of the semiconductor chip laminated module in the second embodiment. Hereinafter, the manufacturing process of the semiconductor chip laminated module will be described in order according to FIG.

  First, FIG. 5A shows a state in which the semiconductor chips 7 manufactured by the same manufacturing process as that up to FIG. 4A of the first embodiment are stacked. Next, unlike Embodiment 1, in this step, the adhesive 3 containing conductive filler is supplied, and predetermined heat is applied to the entire semiconductor chip 7 and the semiconductor chip module to perform thermosetting while maintaining an insulating state. Later, to form a rewiring (4a or 4b), a material that prevents contact with the conductive filler is removed by applying thermal energy such as a laser or a light beam to form a desired conductive path, thereby aggregating the material. That is, after thermally curing the adhesive 3 with conductive filler, a conductive path is created by applying thermal energy. Therefore, in FIG. 5B, the same state as in FIG. 4B, that is, a predetermined heat is applied to the entire semiconductor chips 7 that are aligned and overlapped, and the uncured portion The conductive filler-containing adhesive 3 is thermally cured, and the bonding surfaces of the respective semiconductor chips 1 are bonded and fixed. In FIG. 5 (c), at this stage, the rewiring 4b on the laminated side surface is applied to a predetermined position of the adhesive 5 that has already been supplied on the laminated side surface by using thermal energy such as a laser or a light beam. Form. In other words, since the adhesive 5 with a thermally-cured conductive filler exists between the rewirings 4a drawn to the side surfaces of the stacked semiconductor chips 7, a conductive path is formed by applying thermal energy thereto. The rewiring 4b is used. Note that the thermal energy density for curing the conductive filler-containing adhesive 3 is lower than the thermal energy density for aggregating the conductive filler in the conductive filler-containing adhesive 3 to create a conductive path. Therefore, normally, the temperature at which the adhesive 3 with conductive filler is cured is lower than the temperature for aggregating the conductive filler in the adhesive 3 with conductive filler to create a conductive path. When the conductive filler in the adhesive 3 with conductive filler is agglomerated, contact between the conductive fillers is obtained by applying pressure only to a desired conductive path with a pressurizing jig or the like. It may be formed.

As described above, an electrically connected semiconductor chip laminated module can be formed in an easier way by forming rewiring from an already cured adhesive without forming laminated side insulating adhesive on the laminated side. can do.
(Embodiment 3)
FIG. 6 is a diagram showing the configuration of the semiconductor package according to the third embodiment. The semiconductor chip laminated module manufactured in the first or second embodiment is mounted on the interposer substrate 10 and solder is applied to the back electrode of the interposer substrate 10. This is an example of a final completed semiconductor package in which balls 11 are formed. 6A is a perspective view of the semiconductor package, and FIG. 6B is a cross-sectional view. As a means for mounting the semiconductor chip laminated module on the interposer substrate 10, solder bonding using a solder paste is generally used. FIG. 7 is a diagram showing the manufacturing process of the semiconductor package according to the third embodiment. In the process of mounting the semiconductor laminated module on the interposer substrate 10, the adhesive 3 containing the conductive filler is the same as in the case of producing the semiconductor laminated module. The method using is shown. This process will be described with reference to FIGS.

  First, as shown in FIG. 7A, an adhesive containing a conductive filler is provided around the electrode pad 12 of the interposer substrate 10 where the laminated semiconductor chip laminated module is placed on the interposer substrate 10, temporarily fixed, and bonded. 3 is supplied. Here, by irradiating thermal energy such as a laser between the terminal electrode of the semiconductor chip laminated module and the electrode pad 12 of the interposer substrate 10, the terminal electrode of the semiconductor chip laminated module and the electrode pad 12 of the interposer substrate 10 are electrically connected. Conductive paths to be connected are formed, and the bonding with the interposer substrate 10 is completed.

  In FIG. 7 (c), the semiconductor chips 7 before being stacked and modularized are positioned and stacked on the interposer substrate 10, each of them is temporarily fixed, and the periphery of the electrode pads 12 on the interposer from the stacked side surfaces. In this state, the adhesive 3 containing the conductive filler is supplied, and thereafter, as shown in FIG. 7 (d), the desired rebound from the stacked side surfaces of the stacked semiconductor chips 7 to the electrode pads 12 of the interposer substrate 10 is performed. A wiring 4b is formed. Thereafter, predetermined heat is applied to the entire package, and the packaging with the conductive filler other than the rewirings 4a and 4b is thermally cured to complete the packaging.

As described above, the semiconductor chip laminated module formed in the first embodiment or the second embodiment is mounted on the interposer substrate, and the wiring of the semiconductor chip laminated module or the semiconductor chip laminated is formed using the adhesive containing the conductive filler. By forming a desired rewiring from the electrode pad of the module to the electrode pad of the interposer substrate, electrical connection of the semiconductor package on which the semiconductor chip stacked module is mounted can be performed by an easy method.
(Embodiment 4)
FIG. 8 is a diagram showing the configuration of the semiconductor package according to the fourth embodiment. On the interposer substrate 10, semiconductor chips having different outer dimensions are stacked with a chip having a larger outer shape, and chips having a smaller outer shape are stacked as they go upward. In addition, the semiconductor chips placed thereon are stacked under the condition that they do not cover the electrode pads of the semiconductor chips immediately below. In this case, there is no need for rewiring to each side in advance as rewiring of the semiconductor chip. After stacking on the interposer substrate 10 and supplying the adhesive 3 with conductive filler to the entire surface, the electrode pads on each semiconductor chip and the interposer The desired rewiring 4c is performed on the electrode pads 12 on the substrate 10 to complete the packaging. Further, in this embodiment, even if the semiconductor chip stacked on top has an outer size that covers the electrode pad of the semiconductor chip immediately below, if the rewiring is drawn out to the side only in advance, the case shown in FIG. In the same manner as described above, it is possible to package and package the interposer substrate 10 at once.

  As described above, when the upper semiconductor chip is smaller than or equal to the semiconductor chip directly below, the rewiring 4c and the rewiring 4b, at least the rewiring 4c, are used to form predetermined electrodes between the stacked semiconductor chips. Pads can be electrically connected.

Hereinafter, a method for forming the rewiring will be described with reference to FIGS.
FIG. 9 is a perspective view showing the configuration of the rewiring portion of the present invention, and is a perspective view of the rewiring portion of the adhesive with conductive filler in the first to fourth embodiments of the present invention. The conductive filler in the rewiring 4a is agglomerated by partially irradiating the adhesive 3 with conductive filler supplied substantially uniformly with heat energy or by partially applying pressure with a pressing jig.

This state will be further described in detail with reference to a process cross-sectional view showing a rewiring forming process of the present invention in FIG.
First, FIG. 10A shows a state in which a conductive filler-containing adhesive 3 composed of a conductive filler 9 and an insulating adhesive 8 is supplied onto the semiconductor chip 1. Next, as shown in FIG. 10B, the insulating adhesive 8 is removed by irradiating the thermal energy 6 such as a laser to the rewiring 4a passing through the electrode pad 2 on the semiconductor chip 1 so as to be conductive. The filler 9 aggregates and the conductive fillers 9 come into contact with each other to obtain a conductive path. Thereafter, as shown in FIG. 10C, the adhesive 5 is thermally cured by applying predetermined heat to the whole, and is cured while maintaining insulation at portions other than the conductive path.

  The present invention enables a semiconductor chip to be easily three-dimensionally stacked with a small number of steps, a semiconductor chip stacked module in which a plurality of semiconductor chips are three-dimensionally stacked in one module, a semiconductor chip constituting the semiconductor chip, It is useful for their production methods.

The figure which shows the structure of the semiconductor chip lamination | stacking module in Embodiment 1. FIG. The perspective view which shows the manufacturing process of the semiconductor chip in Embodiment 1 Sectional drawing which shows the manufacturing process of the semiconductor chip in Embodiment 1. The figure which shows the manufacturing process of the semiconductor chip lamination | stacking module in Embodiment 1. The figure which shows the manufacturing process of the semiconductor chip lamination | stacking module in Embodiment 2. FIG. 5 shows a structure of a semiconductor package in Embodiment 3. The figure which shows the manufacturing process of the semiconductor package in Embodiment 3. FIG. 9 shows a structure of a semiconductor package in Embodiment 4. The perspective view which shows the structure of the rewiring part of this invention Process sectional drawing which shows the formation process of the rewiring of this invention The figure which shows the structure of the conventional semiconductor chip lamination module

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Electrode pad 3 Adhesive with conductive filler 4a Rewiring 4b Rewiring 4c Rewiring 5 Adhesive 6 Thermal energy 7 Semiconductor chip 8 Insulating adhesive 9 Conductive filler 10 Interposer substrate 11 Solder ball 12 Electrode pad 101 Semiconductor chip 102 Protective film 103 Wiring pad 104 Notch portion 105 Wiring portion 106 Wire bonding pad 107 Opening portion

Claims (5)

When manufacturing one semiconductor chip that is three-dimensionally stacked to form a semiconductor chip stacked module,
Preparing a semiconductor chip on which a circuit and electrodes are formed on the first surface;
Supplying an insulating adhesive containing a conductive filler to the first surface and the side surface in contact with the first surface of the semiconductor chip;
Forming a conductive path from the electrode of the semiconductor chip to the side surface by agglomerating the conductive filler at a desired location of the insulating adhesive by reducing the volume by applying pressure, and A method of manufacturing a semiconductor chip, wherein the semiconductor chips are electrically connected using a conductive path when the semiconductor chip stacked module is manufactured.   2. The method of manufacturing a semiconductor chip according to claim 1, wherein the insulating adhesive has thermosetting properties at a predetermined temperature. When manufacturing one semiconductor chip that is three-dimensionally stacked to form a semiconductor chip stacked module,
Preparing a semiconductor chip on which a circuit and electrodes are formed on the first surface;
Supplying an insulating adhesive containing a conductive filler to the first surface and the side surface in contact with the first surface of the semiconductor chip;
Forming a conductive path from the electrode of the semiconductor chip to the side surface by agglomerating the conductive filler at a desired location of the insulating adhesive, and the insulating adhesive is thermally cured at a predetermined temperature. 2. The method of manufacturing a semiconductor chip according to claim 1, wherein the semiconductor chips are electrically connected using the conductive path when the semiconductor chip stacked module is manufactured. When manufacturing a semiconductor chip laminated module by three-dimensionally laminating a plurality of semiconductor chips having circuits and electrodes formed on the first surface,
Supplying an insulating adhesive containing a conductive filler to the first surface and the side surface in contact with the first surface of the semiconductor chip;
Forming a first conductive path from the electrode of the semiconductor chip to the side surface by aggregating the conductive filler at a desired location of the insulating adhesive by reducing the volume by applying pressure;
A step of three-dimensionally laminating a plurality of the semiconductor chips provided with the insulating adhesive and the first conductive path;
Supplying a laminated side surface insulating adhesive containing a conductive filler on a side surface parallel to the laminating direction of the plurality of laminated semiconductor chips;
By applying pressure to reduce the volume, the conductive fillers at desired locations of the laminated side surface insulating adhesive are agglomerated to form a second side surface parallel to the laminating direction of the laminated semiconductor chips. Forming a conductive path, and electrically connecting the semiconductor chips of the semiconductor chip stacked module using the first conductive path and the second conductive path. A method for manufacturing a laminated module.   5. The method of manufacturing a semiconductor chip laminated module according to claim 4, wherein the insulating adhesive and the laminated side surface insulating adhesive have thermosetting properties at a predetermined temperature.

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