JP5247999B2 - Substrate processing method and computer-readable storage medium - Google Patents

Description

  The present invention relates to a substrate processing method and a computer-readable storage medium for performing a modification process for modifying a predetermined substance and a dissolution / removal process of the modified substance in a manufacturing process of a semiconductor device by, for example, a dual damascene method.

  In a semiconductor device, a reduction in the wiring interval due to miniaturization generates a large capacitance between the wirings, thereby causing a delay in operation speed by reducing the signal propagation speed. In order to solve this problem, development of an insulating material (Low-k material) having a low relative dielectric constant and development of a multilayer wiring using the same have been made. On the other hand, copper having a low resistance and high electromigration resistance has attracted attention as a wiring material, and a single damascene method or a dual damascene method is frequently used for forming copper trench wiring and connection holes.

  FIG. 11 is an explanatory diagram showing an example of the formation process of the multilayer copper wiring by the dual damascene method. First, a lower wiring 202 made of copper is formed on an insulating film (Low-k film) 200 made of a Low-k material on a silicon substrate (not shown) via a barrier metal layer 201, and an etching stopper film 203 is formed. Then, a low-k film 204 is formed as an interlayer insulating film through the film, and an antireflection film (BARC: Bottom Anti-Reflective Corting) 205 is formed on the surface thereof, and then a resist film 206 is formed on the surface of the antireflection film 205. Then, the resist film 206 is exposed with a predetermined pattern and developed to form a circuit pattern on the resist film 206 (FIG. 11A).

  Next, the low-k film 204 is etched using the resist film 206 as a mask to form a via hole 204a (FIG. 11B). After removing the antireflection film 205 and the resist film 206 by chemical treatment, ashing treatment, or the like, a sacrificial film 207 is formed on the surface of the insulating film 204 having the via hole 204a (FIG. 11C). At this time, the via hole 204 a is also filled with the sacrificial film 207.

  A resist film 208 is formed on the surface of the sacrificial film 207, the resist film 208 is exposed with a predetermined pattern, and developed to form a circuit pattern on the resist film 208 (FIG. 11D). Thereafter, the sacrificial film 207 and the low-k film 204 are etched using the resist film 208 as a mask, thereby forming a wider trench 204b on the via hole 204a (FIG. 11E). Thereafter, by removing the resist film 208 and the sacrificial film 207, a via hole 204a and a trench 204b are formed in the insulating film 204 (FIG. 11F). And copper is embedded in these as upper wiring.

  By the way, as the sacrificial film 207, Si—O-based inorganic materials are frequently used, and it is difficult to remove the sacrificial film 207 by the ashing process used for conventional resist film removal. In addition, attempts have been made to dissolve with a chemical solution, but the processing speed is extremely slow.

  As a technique for removing such a sacrificial film, a technique has been proposed in which the sacrificial film is solublely modified in a predetermined chemical solution with a processing gas containing water vapor and ozone, and then the sacrificial film is removed with the chemical solution (patent) Reference 1).

  However, when processing is performed using a processing gas containing water vapor and ozone, the interlayer insulating film made of the low-k material on which the pattern is formed may be damaged, and the damage to the pattern is manifested by subsequent chemical processing. There is a risk of becoming.

In addition, when a liquid solubilization process is performed with such a process gas containing water vapor and ozone, and then a cleaning process with a chemical solution is performed, the low-k material is damaged and the relative dielectric constant is increased, thereby causing interlayer insulation. The effect of using a low-k material as the film is reduced.
JP 2004-214388 A

The present invention has been made in view of such circumstances, and after etching the film to be etched, a process for removing the remaining material such as a sacrificial film is performed by solubilizing the remaining material in a predetermined liquid, and then performing the predetermined process. It is an object of the present invention to provide a substrate processing method with less damage such as pattern peeling when the remaining material is removed with the above solution.
In addition, another object of the present invention is to provide a substrate processing method capable of suppressing a decrease in electrical characteristics due to damage to a film to be etched during a removal process of a residual substance.
Furthermore, it aims at providing the computer-readable storage medium with which the control program which performs such a method was memorize | stored.

In order to solve the above-mentioned problems, in the first aspect of the present invention, a step of etching a film to be etched made of a low dielectric constant material formed on a substrate to form a predetermined pattern, and the etching process are terminated. A step of modifying so as to solubilize the remaining substance in a predetermined liquid, a step of silylating the surface of the film to be etched on which the pattern is formed, and then the predetermined liquid Supplying and dissolving and removing the modified substance, and the silylation treatment recovers damage formed in the film to be etched by the modifying step and dissolves and removes the modified substance. with pattern prevents peeling, the lowering of the dielectric constant of the film to be etched dielectric constant is increased by the damage, the step of the modification, containing water vapor and ozone To provide a substrate processing method, which comprises carrying out by supplying physical gas.

In a second aspect of the present invention, a sacrificial film is formed on a film to be etched made of a low dielectric constant material formed on a substrate, an etching mask is formed on the sacrificial film, and the sacrificial film Etching the film to be etched to form a predetermined pattern, modifying the sacrificial film and the etching mask so as to be solubilized in a predetermined liquid, and then etching the film on which the pattern is formed And a step of supplying the predetermined liquid to dissolve and remove the modified substance, and the silylation treatment is performed by the step of modifying the film to be etched. The dielectric constant of the film to be etched is recovered by recovering the damage formed on the substrate and preventing the peeling of the pattern in the step of dissolving and removing the dielectric constant. Decrease, the step of the modification is to provide a substrate processing method, which comprises carrying out by supplying a process gas containing water vapor and ozone.

In the third aspect of the present invention, a step of etching a film to be etched made of a low dielectric constant material formed on a substrate to form a predetermined pattern, and a substance remaining after the etching process is finished A step of modifying so as to be solubilized in a liquid, a step of silylating the surface of the film to be etched on which the pattern is formed, and then supplying the predetermined liquid to the modified substance And the silylation treatment recovers damage formed on the film to be etched by the step of modifying, prevents pattern peeling during the step of dissolving and removing, and The step of reducing the dielectric constant of the film to be etched whose dielectric constant has increased due to damage and performing the modification is performed by supplying a processing gas containing ozone. To provide that substrate processing method.

In a fourth aspect of the present invention, a sacrificial film is formed on a film to be etched made of a low dielectric constant material formed on a substrate, an etching mask is formed on the sacrificial film, and the sacrificial film Etching the film to be etched to form a predetermined pattern, modifying the sacrificial film and the etching mask so as to be solubilized in a predetermined liquid, and then etching the film on which the pattern is formed And a step of supplying the predetermined liquid to dissolve and remove the modified substance, and the silylation treatment is performed by the step of modifying the film to be etched. The dielectric constant of the film to be etched is recovered by recovering the damage formed on the substrate and preventing the peeling of the pattern in the step of dissolving and removing the dielectric constant. Decrease, the step of the modification is to provide a substrate processing method, which comprises carrying out by supplying a process gas containing ozone.

  In the first to fourth aspects, the step of recovering damage formed on the surface of the film to be etched in the step of silylating and dissolving and removing the surface of the film to be etched after the modified substance is removed Furthermore, it is preferable to have. As the low dielectric constant material, those having an alkyl group as a terminal group are particularly effective.

  The silylation treatment is preferably performed using a compound having a silazane bond (Si—N) in the molecule. The compound having a silazane bond in the molecule is preferably TMDS (1,1,3,3-Tetramethyldisilazane) or TMSDMA (Dimethylaminotrimethylsilane).

In the fifth aspect of the present invention, a film to be etched made of a low dielectric constant material is provided, a predetermined pattern is formed in the film to be etched by the etching process, and a substance remaining after the etching process is solubilized in a predetermined liquid And a step of silylating the surface of the film to be etched with respect to the substrate modified with the treatment gas containing water vapor and ozone or the treatment gas containing ozone, and then supplying the predetermined liquid. And the step of dissolving and removing the modified substance, the silylation treatment recovers the damage formed on the film to be etched when modified, and the pattern is peeled off during the step of dissolving and removing. And a substrate processing method characterized in that the dielectric constant of a film to be etched whose dielectric constant is increased by the damage is lowered.

According to a sixth aspect of the present invention, there is provided a computer-readable storage medium storing a control program that operates on a computer, wherein the control program is executed when the substrate processing methods according to the first to fifth aspects are performed. A computer-readable storage medium is provided that causes a computer to control a manufacturing apparatus.

According to the present invention, using the film to be etched made of damage enters easily low-k material, using a removing hard material of the sacrificial film, after etching the target etching film, the residual material of the sacrificial film eliminator When the residual material is solubilized in a predetermined liquid and then the residual material is dissolved and removed by the predetermined liquid, the film to be etched is protected from damage by silylation prior to the dissolution and removal. The recovery and dissolution removal process prevents pattern peeling and lowers the dielectric constant of the film to be etched whose dielectric constant has increased due to damage. damage rather difficulty occurs, it can also be lowering elevated dielectric constant by damage.

  Further, by performing the silylation treatment after the residual material dissolution and removal treatment, it is possible to recover the deterioration of the electrical characteristics due to the damage of the etching target film during the residual material removal treatment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Here, an example in which the present invention is applied when manufacturing a semiconductor device by a dual damascene method will be described.

  FIG. 1 is an explanatory diagram showing a schematic configuration of a wafer processing system used in a semiconductor device manufacturing process by a dual damascene method, to which a substrate processing method is applied according to an embodiment of the present invention. This wafer processing system includes an SOD (Spin On Dielectric) apparatus 101, a resist coating / developing apparatus 102, an exposure apparatus 103, a cleaning processing apparatus 104, an etching apparatus 105, and a sputtering apparatus 106 which is one of PVD apparatuses. And a processing unit 100 including an electrolytic plating apparatus 107 and a CMP apparatus 109 as a polishing apparatus, and a main control unit 110 including a process controller 111, a user interface 112, and a storage unit 113. Here, the SOD device 101, the sputtering device 106, and the electrolytic plating device 107 of the processing unit 100 are film forming devices. In addition, as a method for transferring the wafer W between apparatuses of the processing unit 100, a transfer method by an operator or a transfer method by a transfer device (not shown) is used.

  Each device of the processing unit 100 is connected to and controlled by a process controller 111 having a CPU. The process controller 111 includes a keyboard that allows a process manager to input commands to manage each device of the processing unit 100, a display that visualizes and displays the operating status of each device of the processing unit 100, and the like. The user interface 112 is connected to a storage unit 113 in which a control program for realizing various processes executed by the processing unit 100 under the control of the process controller 111 and a recipe storing processing condition data are stored. Yes.

Then, if necessary, the processing unit 100 receives an instruction from the user interface 112, calls an arbitrary recipe from the storage unit 113, and causes the process controller 111 to execute the desired recipe in the processing unit 100 under the control of the process controller 111. Various processes are performed. In addition, the recipe may be stored in a readable storage medium such as a CD-ROM, a hard disk, a flexible disk, and a nonvolatile memory. Alternatively, it may be transmitted from an external device as needed via, for example, a dedicated line and used online.
In addition, the overall control by the main control unit 110 is not performed, or a control including a process controller, a user interface, and a storage unit is provided for each device of the processing unit 100 in superposition with the overall control by the main control unit 110. It is also possible to employ a configuration in which the units are individually deployed and controlled.

  The SOD apparatus 101 is used for applying a chemical solution to the wafer W to form an interlayer insulating film such as a low-k film, an etching stopper film, and the like by a spin coating method. Although a detailed configuration of the SOD apparatus 101 is not shown, the SOD apparatus 101 includes a spin coater unit and a heat treatment unit that heat-treats the wafer W on which the coating film is formed. In the wafer processing system, a CVD apparatus that forms an insulating film or the like on the wafer W by a chemical vapor deposition (CVD) method may be used instead of the SOD apparatus 101.

  The resist coating / developing apparatus 102 is used to form a resist film, an antireflection film or the like used as an etching mask. Although a detailed configuration of the resist coating / developing apparatus 102 is not illustrated, the resist coating / developing apparatus 102 includes a resist coating processing unit that applies a resist solution or the like to the wafer W and spin-coats a resist film or the like, and a wafer W. A BARC coating processing unit for coating an antireflection film (BARC) on the substrate, a sacrificial film coating processing unit for coating a sacrificial film (SLAM) on the wafer W, and a developing process for the resist film exposed in a predetermined pattern in the exposure apparatus 103 A developing processing unit, a wafer W on which a resist film is formed, an exposed wafer W, a thermal processing unit for thermally processing the developed wafer W, and the like.

  The exposure apparatus 103 is used for exposing a predetermined circuit pattern to the wafer W on which a resist film is formed. As will be described in detail later, the cleaning processing apparatus 104 performs a cleaning process using pure water or a chemical solution, a modification process such as a polymer residue after the etching process, and a recovery process from damage caused by etching the interlayer insulating film.

  The etching apparatus 105 is for performing an etching process on an interlayer insulating film or the like formed on the wafer W. The etching process may use plasma or a chemical solution. The sputtering apparatus 106 is used, for example, to form a diffusion prevention film or a Cu seed. In the electrolytic plating apparatus 107, Cu is embedded in a groove wiring or the like in which a Cu seed is formed, and the CMP apparatus 109 is for performing a planarization process on the surface of the groove wiring or the like in which Cu is embedded.

  Next, the cleaning apparatus 104 that plays an important role for the present invention will be described in detail. 2 is a schematic plan view of the cleaning processing apparatus 104, FIG. 3 is a schematic front view thereof, and FIG. 4 is a schematic rear view thereof. In the cleaning processing apparatus 104, a carrier in which the wafer W is accommodated is sequentially carried from another processing apparatus or the like, and conversely, a processing apparatus or the like that performs the next processing on the carrier in which the wafer W in the cleaning processing apparatus 104 has been processed The wafer W is transferred between the processing station 2 and the carrier station 4, the processing station 2 provided with a plurality of processing units for performing cleaning processing, modification processing, and recovery processing, respectively. A transport station 3 is provided, and a chemical station 5 that manufactures, prepares, and stores chemicals, pure water, and gas used in the processing station 2 is provided.

  Inside the carrier C, the wafers W are accommodated at a constant interval in the vertical direction (Z direction) in a substantially horizontal posture. Such loading / unloading of the wafer W with respect to the carrier C is performed through one side surface of the carrier C, and this side surface is not shown in FIG. 2 (the state in which the lid body 10a is removed in FIGS. 3 and 4). Can be opened and closed freely.

  As shown in FIG. 2, the carrier station 4 has mounting tables 6 on which carriers C can be mounted at three locations along the Y direction in the figure. The carrier C is placed on the mounting table 6 such that the side surface on which the lid 10 a is provided faces the boundary wall 8 a between the carrier station 4 and the transfer station 3. A window portion 9a is formed at a position corresponding to the place where the carrier C is placed on the boundary wall 8a, and a shutter 10 for opening and closing the window portion 9a is provided on the transfer station 3 side of each window portion 9a. The shutter 10 has a gripping means (not shown) for gripping the lid 10a of the carrier C. As shown in FIGS. 3 and 4, the shutter 10 holds the lid 10a toward the transfer station 3 side. The lid 10a can be retracted.

  The wafer transfer device 7 provided in the transfer station 3 has a wafer transfer pick 7 a that can hold the wafer W. The wafer transfer device 7 is movable in the Y direction along a guide (see FIGS. 3 and 4) 7b provided on the floor of the transfer station 3 so as to extend in the Y direction. The wafer transfer pick 7a is slidable in the X direction, can be moved up and down in the Z direction, and is rotatable (θ rotation) in the XY plane.

  With such a structure, in a state where the shutter 10 is retracted so that the inside of the carrier C and the transfer station 3 communicate with each other via the window portion 9a, the wafer transfer pick 7a is all mounted on the mounting table 6. The wafer W can be accessed from the carrier C and can be unloaded from the carrier C. Conversely, the wafer W can be loaded to any position on the carrier C.

  The processing station 2 has two wafer mounting units (TRS) 13a and 13b on the transfer station 3 side. For example, the wafer placement unit (TRS) 13b is used to place the wafer W when receiving the wafer W from the transfer station 3, and the wafer placement unit (TRS) 13a completes predetermined processing at the processing station 2. This is used to place the wafer W when returning the wafer W to the transfer station 3.

On the back side of the processing station 2, a modification treatment for modifying the polymer residue, resist film, sacrificial film, etc. after the etching treatment so as to be solubilized in a predetermined chemical solution with a gas containing water vapor and ozone (O ₃ ). Units (VOS) 15a to 15f are arranged. In these modification processing units (VOS) 15a to 15f, the shape of the polymer residue, resist film, sacrificial film, etc. after the etching process is maintained as it is, and only the chemical properties are changed so as to be solubilized in a predetermined chemical solution. To do.

  On the modification processing units (VOS) 15a and 15d, silylation units (SCH) 11a and 11b for performing silylation treatment to recover the interlayer insulating film damaged by the modification processing and the cleaning processing from damage or the like are provided. Is provided.

  On the front side of the processing station 2, cleaning units (CNU) 12 a to remove modified polymer residues and the like by performing chemical treatment or water washing on the wafers W that have been processed in the modification processing units (VOS) 15 a to 15 f. 12d is arranged.

  In the processing station 2, the wafer W that has been processed by the cleaning processing units (CNU) 12 a to 12 d is heated and dried at a position facing the wafer placement units (TRS) 13 a and 13 b across the main wafer transfer device 14. Hot plate units (HP) 19a to 19d to be stacked are arranged in four stages. Furthermore, cooling plate units (COL) 21a and 21b for cooling the heat-dried wafer W are stacked on the upper side of the wafer mounting unit (TRS) 13a. The wafer placement unit (TRS) 13b can be used as a cooling plate unit. A fan filter unit (FFU) 25 that blows clean air into the processing station 2 is provided above the processing station 2.

  A main wafer transfer device 14 for transferring the wafer W in the processing station 2 is provided at a substantially central portion of the processing station 2. The main wafer transfer device 14 has a wafer transfer arm 14a for transferring the wafer W. The main wafer transfer device 14 is rotatable around the Z axis. Further, the wafer transfer arm 14a can move back and forth in the horizontal direction and can move up and down in the Z direction. With such a structure, the main wafer transfer device 14 can access each unit provided in the processing station 2 without moving itself in the X direction, and transfers the wafer W between these units. Be able to.

  The chemical station 5 includes a processing gas supply unit 16 that supplies ozone, water vapor, and the like as processing gases to the modification processing units (VOS) 15a to 15f provided in the processing station 2, and a cleaning liquid to the cleaning units (CNU) 12a to 12d. And a silylating agent supply unit 18 for supplying a silylating agent, a carrier gas or the like to the silylation processing units (SCH) 11a and 11b.

  Next, the structure of the modification processing unit (VOS) 15a will be described in detail with reference to the schematic cross-sectional view shown in FIG. The other denaturing units have the same structure. This denaturation processing unit (VOS) 15a has a sealed chamber 30 that accommodates a wafer W, and the chamber 30 includes a fixed lower container 41a and a lid 41b that covers the upper surface of the lower container 41a. The lid 41b can be moved up and down by a cylinder 43 fixed to a frame 42 of a membrane modification unit (VOS) 15a. FIG. 5 shows a state in which the lid 41b is in close contact with the lower container 41a, and a state in which the lid 41b is retracted above the lower container 41a.

  An O-ring 51 is disposed on the upper surface of the rising portion at the periphery of the lower container 41a. When the cylinder 43 is driven to lower the lid 41b, the peripheral edge of the back surface of the lid 41b comes into contact with the upper surface of the raised portion of the peripheral edge of the lower container 41a, and the O-ring 51 is compressed and sealed in the chamber 30. A processing space is formed.

  The lower container 41 a is provided with a stage 33 on which the wafer W is placed. Proximity pins 44 that support the wafer W are provided at a plurality of locations on the surface of the stage 33.

  A heater 45a is embedded in the stage 33 and a heater 45b is embedded in the lid body 41b, respectively, so that the stage 33 and the lid body 41b can be respectively held at a predetermined temperature. Thereby, the temperature of the wafer W is kept constant.

  On the back surface of the lid 41b, claw members 46 for holding the wafer W are provided, for example, at three locations (only two locations are shown in FIG. 5). The wafer transfer arm 14 a delivers the wafer W to the claw member 46. When the lid 41 b is lowered while the claw member 46 holds the wafer W, the wafer W is transferred to the proximity pins 44 provided on the stage 33 during the lowering.

  In the chamber 30, the lower container 41a is provided with a gas introduction port 34a for introducing the processing gas into the interior and a gas exhaust port 34b for exhausting the processing gas to the outside. The processing gas supply device 16 is connected to the gas inlet 34a, and the exhaust device 32 is connected to the gas outlet 34b.

  The processing of the wafer W with the processing gas is preferably performed while maintaining the interior of the chamber 30 at a constant positive pressure. For this purpose, not only the lower container 41 a and the lid 41 b are pressed by the cylinder 43, but also the projections 47 a and 47 b provided on these end surfaces are tightened by the lock mechanism 35.

  The lock mechanism 35 includes a support shaft 52, a rotating cylinder 55 that is rotatable by a rotating device 54, a disk 56 that is fixed to the rotating cylinder 55, and a clamping member 57 that is provided on the periphery of the disk 56. have. The clamping member 57 includes pressing rollers 59 a and 59 b and a roller holding member 48 that holds the rotation shaft 58.

  The protrusions 47a and 47b are provided at four positions at equal intervals, and a gap 49 is formed between them. The protrusions 47a and 47b are disposed at overlapping positions. In a state where the clamping member 57 is disposed at the position of the gap portion 49, the lid body 41b can be freely moved up and down.

  When the circular plate 56 is rotated by a predetermined angle together with the rotating cylinder 55, the pressing roller 59b stops on the upper surface of the protruding portion 47b, and the pressing roller 59a stops on the lower side of the protruding portion 47a.

Next, the silylation unit (SCH) 11a will be described in detail with reference to the schematic cross-sectional view shown in FIG. The silylation unit (SCH) 11a includes a chamber 61 that accommodates the wafer W. The chamber 61 includes a fixed lower container 61a and a lid 61b that covers the lower container 61a. The lid 61b is illustrated. It can be raised and lowered by a lifting device that does not. The lower container 61 a is provided with a hot plate 62, and nitrogen gas containing a silylating agent, for example, DMSDMA (Dimethylsilyldimethylamine) vapor is supplied into the chamber 61 from the periphery of the hot plate 62. DMSDMA is vaporized by the vaporizer 63, is carriered by N ₂ gas, and is supplied to the chamber 61.

  The hot plate 62 can be adjusted in temperature, for example, in the range of room temperature to 200 ° C., and pins 64 for supporting the wafer W are provided on the surface thereof. By not placing the wafer W directly on the hot plate 62, contamination of the back surface of the wafer W is prevented. A first seal ring 65 is provided on the upper surface of the outer peripheral portion of the lower container 61a, and the lower surface of the outer peripheral portion of the lid 61b contacts the first seal ring 65 when the lid 61b is pressed against the lower container 61a. A second seal ring 66 is provided. The space between the first and second seal rings 65 and 66 can be depressurized, and the airtightness of the chamber 61 is ensured by depressurizing the space. An exhaust port 67 for exhausting nitrogen gas containing DMSDMA supplied to the chamber 61 is provided at a substantially central portion of the lid 61b. The exhaust port 67 is connected to a vacuum pump via a pressure adjusting device 68. 69.

In FIG. 6, the liquid DMSDMA gas is vaporized by the vaporizer 63 and is supplied by the carrier with the N ₂ gas and supplied to the chamber 61. However, only the gas vaporized from the DMSDMA (that is, DMSDMA vapor) is supplied to the chamber 61. It is good also as a structure supplied to. When supplying DMSDMA into the chamber 61, the inside of the chamber 61 is maintained at a predetermined degree of vacuum. Therefore, the DMSDMA gas is introduced into the chamber 61 using the pressure difference between the vaporizer 63 and the chamber 61. Can be done easily. The silylated unit (SCH) 11b has the same structure as the silylated unit (SCH) 11a.

  Next, the cleaning unit 12a will be described in detail with reference to the schematic cross-sectional view shown in FIG. The cleaning unit (CNU) 12a has an annular cup (CP) disposed at the center thereof, and a spin chuck 71 disposed inside the cup (CP). The spin chuck 71 is rotationally driven by a drive motor 72 in a state where the wafer W is fixedly held by vacuum suction. A drain pipe 73 for discharging the cleaning liquid and pure water is provided at the bottom of the cup (CP).

  The drive motor 72 is disposed in an opening 74 a provided in the unit bottom plate 74 so as to be movable up and down, and is coupled to a lift drive mechanism 76 made of, for example, an air cylinder and a lift guide 77 through a cap-like flange member 75. A cylindrical cooling jacket 78 is attached to the side surface of the drive motor 72, and the flange member 75 is attached so as to cover the upper half of the cooling jacket 78.

  When supplying a chemical solution or the like to the wafer W, the lower end 75a of the flange member 75 is in close contact with the unit bottom plate 74 near the periphery of the opening 74a, thereby sealing the inside of the unit. When the wafer W is transferred between the spin chuck 71 and the wafer transfer arm 14a, the elevating drive mechanism 76 lifts the drive motor 72 and the spin chuck 71 upward so that the lower end of the flange member 75 is removed from the unit bottom plate 74. It comes to float.

  Above the cup (CP), on the surface of the wafer W on which a substance modified by any of the modification processing units (VOS) 15a to 15f (hereinafter referred to as a modified substance), for example, a modified sacrificial film, is present. A cleaning liquid supply mechanism 80 for supplying a predetermined cleaning liquid for dissolving the substance is provided.

  The cleaning liquid supply mechanism 80 includes a cleaning liquid discharge nozzle 81 that discharges the cleaning liquid onto the surface of the wafer W held by the spin chuck 71, a cleaning liquid supply unit 17 that supplies a predetermined cleaning liquid to the cleaning liquid discharge nozzle 81, and the cleaning liquid discharge nozzle 81. , A vertical support member 85 that is movable in the Y direction, a vertical support member 85 that supports the scan arm 82, and a guide rail 84 that is laid in the X-axis direction on the unit bottom plate 74. And an X-axis drive mechanism 96 for moving 85 in the X-axis direction. The scan arm 82 can be moved in the vertical direction (Z direction) by the Z-axis drive mechanism 97, thereby moving the cleaning liquid discharge nozzle 81 to an arbitrary position on the wafer W, and to a predetermined position outside the cup (CP). It can be evacuated.

  The cleaning liquid supply unit 17 dissolves and removes a denatured substance such as a sacrificial film modified by the denaturing treatment units (VOS) 15a to 15f, for example, a dilute hydrofluoric acid, an amine chemical solution, or the like, and pure water used as a rinse Can be selectively fed to the cleaning liquid discharge nozzle 81.

  The modification units (VOS) 15a to 15c and the modification units (VOS) 15d to 15f described above have a substantially symmetrical structure with respect to the boundary wall 22b, and the silylation unit (SCH) 11a and the silylation unit. (SCH) 11b has a substantially symmetrical structure with respect to the boundary wall 22b. Similarly, the cleaning units (CNU) 12a and 12b and the cleaning units (CNU) 12c and 12d have a substantially symmetrical structure with respect to the boundary wall 22a.

Next, a manufacturing process of a semiconductor device by a dual damascene method in which the substrate processing method is applied to one embodiment of the present invention will be described.
FIG. 8 is a flowchart showing a manufacturing process of a semiconductor device by the dual damascene method, and FIG. 9 is a process sectional view showing a flow of FIG.

  First, an insulating film 120 is formed on a Si substrate (not shown), a lower copper wiring 122 is formed on the upper portion of the insulating film 120 via a barrier metal layer 121, and a stopper is formed on the insulating film 120 and the lower copper wiring 122. A wafer on which a film (for example, SiN film, SiC film) 123 is formed is formed, and this wafer is loaded into the SOD device 101, where a low dielectric constant material (Low-k material) is formed on the stopper film 123. An interlayer insulating film (hereinafter referred to as a Low-k film) 124 made of is formed (step 1). As a result, the state of FIG. 9A is formed.

  Next, the wafer W on which the insulating film 124 is formed is carried into the resist coating / developing apparatus 102, where an antireflection film 125 and a resist film 126 are sequentially formed on the low-k film 124 using a resist coating processing unit. Then, the wafer W is transferred to the exposure apparatus 103, where it is exposed in a predetermined pattern, and the wafer W is returned to the resist coating / developing apparatus 102, and the resist film 126 is developed in the development processing unit. Thus, a predetermined circuit pattern is formed on the resist film 126 (step 2). Subsequently, the wafer is transferred to the etching apparatus 105, where an etching process is performed (step 3). As a result, as shown in FIG. 9B, a via hole 124 a reaching the stopper film 123 is formed in the Low-k film 124.

  The wafer on which the via hole 124a has been formed is then transferred to the cleaning processing apparatus 104 and subjected to chemical processing in any of the cleaning processing units (CNU) 12a to 12d, and the resist film 126 is removed from the wafer W (step) 4, FIG. 9 (c)).

  Subsequently, the wafer W is transferred to the resist coating / developing apparatus 102, where an inorganic material (for example, Si—O based material) is formed on the surface of the low-k film 124 having the via hole 124a using a sacrificial film coating processing unit. ) Is formed (step 5). At this time, the via hole 124 a is also filled with the sacrificial film 127. Subsequently, a resist film 128 serving as an etching mask is formed on the surface of the sacrificial film 127 in the resist coating processing unit, the resist film 128 is exposed with a predetermined pattern in the exposure device 103, and then the resist film 128 is developed in the development processing unit. (Step 6). As a result, a circuit pattern is formed on the resist film 128 as shown in FIG. Here, a groove wider than the width of the via hole 124a is formed in the resist film 128 above the via hole 124a.

  Next, the wafer W is transferred to the etching apparatus 105, where the surface of the wafer is etched (step 7). As a result, as shown in FIG. 9E, a wider trench 124b is formed above the via hole 124a. By forming the sacrificial film 127 on the Low-k film 124, the bottom surface of the etched portion of the Low-k film 124 can be made flat.

  The wafer W that has been subjected to the etching process is transferred to the cleaning processing apparatus 104, where the sacrificial film 127 and the resist film 128 are modified (step 8, FIG. 9F), and the low-k film 124 after the modification process is formed. A silylation process (step 9, FIG. 9 (g)) and a sacrificial film 127, a resist film 128, and a polymer residue are removed (step 10, FIG. 9 (h)).

  Specifically, first, the carrier C in which the wafer having been subjected to the etching process is placed is placed on the placing table 6, and the cover 10 a and the shutter 10 of the carrier C are retracted to the transfer station 3 side to thereby open the window portion 9 a. Is opened. Subsequently, one wafer W at a predetermined position of the carrier C is transferred to the wafer placement unit (TRS) 13b by the wafer transfer pick 7a.

  Then, the wafer placed on the wafer placement unit (TRS) 13b is carried into one of the modification processing units (VOS) 15a to 15h by the wafer transfer arm 14a, and the sacrificial film 127 and the resist film 128 in step 8 above. The denaturing process is performed (FIG. 9 (f)).

  In this case, the lid body 41b of the chamber 30 is first retracted above the lower container 41a, and then the portion of the claw member 46 provided on the lid body 41b that holds the wafer W (the portion that protrudes in the horizontal direction) The wafer transfer arm 14a holding the wafer W is advanced so that the wafer W enters a position slightly higher than (). Next, when the wafer transfer arm 14 a is lowered, the wafer W is transferred to the claw member 46.

  After retracting the wafer transfer arm 14a from the modification processing unit (VOS) 15a, the lid 41b is lowered, the lid 41b is brought into close contact with the lower container 41a, and the lock mechanism 35 is operated to seal the chamber 30. And The wafer W is transferred from the claw member 46 to the proximity pin 44 while the lid 41b is being lowered.

  The stage 33 is held at a predetermined temperature by the heaters 45a and 45b. For example, the stage 33 is held at 100 ° C., and the lid 41b is held at 110 ° C.

  When the stage 33 and the lid 41b are held at a predetermined temperature (for example, 110 ° C. to 120 ° C.) and the temperature distribution of the wafer W becomes substantially constant, first, an ozone / nitrogen mixed gas (from the processing gas supply device 16) For example, an ozone content of 9 wt% and a flow rate of 4 L / min) are supplied into the chamber 30, the inside of the chamber 30 is filled with an ozone / nitrogen mixed gas, and a predetermined positive pressure, for example, a gauge pressure To 0.2 MPa.

  Thereafter, a processing gas in which water vapor is mixed with ozone / nitrogen mixed gas (for example, the amount of water vapor is 16 ml / min in terms of water) is supplied from the processing gas supply device 16 into the chamber 30. The sacrificial film 127 formed on the wafer W by this processing gas is denatured into a property easily dissolved in a specific chemical solution, for example, HF, and a polymer residue (for example, after the etching process) attached to the resist film 128 and the wafer W. The resulting polymer residue is also easily dissolved by the chemical solution. Thus, the processing gas modifies the sacrificial film 127, the resist film, and the polymer residue. The supply amount of the processing gas to the chamber 30 and the exhaust amount from the chamber 30 are adjusted so that the inside of the chamber 30 has a predetermined positive pressure.

  When the processing of the wafer W with the processing gas is completed, the supply of the processing gas is stopped, nitrogen gas is supplied from the processing gas supply device 16 into the chamber 30, and the inside of the chamber 30 is purged with nitrogen gas. During the purge process, the ozone / nitrogen mixed gas does not flow back from the exhaust device 32 when the chamber 30 is opened, and the ozone / nitrogen mixed gas is not discharged from the chamber 30. The nitrogen mixed gas is exhausted completely.

  After the purge process using nitrogen gas is completed, it is confirmed that the internal pressure of the chamber 30 is the same as the external pressure. This is because if the chamber 30 is opened while the internal pressure of the chamber 30 is higher than the atmospheric pressure, the chamber 30 may be damaged. After confirming the internal pressure of the chamber 30, the locking of the lower container 41a and the lid body 41b by the lock mechanism 35 is released, and the lid body 41b is raised. When the lid 41b is raised, the wafer W is held by the claw member 46 and rises together with the lid 41b. The wafer transfer arm 14a is moved into the gap between the lower container 41a and the lid 41b, and the wafer W is transferred from the claw member 46 to the wafer transfer arm 14a.

  The sacrificial film 127 and the like are not removed from the wafer W when the modification process in any of the film modification units (VOS) 15a to 15f is completed. Therefore, a dissolution removal process (cleaning process) for removing the sacrificial film 127 and the like from the wafer W is performed (step 10 above). However, the treatment of water vapor and ozone in the denaturation treatment unit (VOS) may damage the low-k film 124 on which the pattern is formed. In such a state, the subsequent dissolution using the chemical solution is performed. If the removal process is performed, the pattern may be peeled off.

  Therefore, in the present embodiment, prior to the dissolution and removal process, the silylation process of Step 9 is performed in either of the silylation units 11a and 11b to recover the Low-k film 124 from damage, and during the dissolution and removal process. Such a pattern prevents peeling.

  As shown in FIG. 10, such a damaged portion is formed by the reaction of the low-k film 124 having a terminal group of a methyl group (Me) and hydrophobic, with water molecules during the modification treatment with water vapor and ozone. The methyl group in the vicinity of the side wall of the via hole 124a is decreased, the hydroxyl group is increased, and damage is entered. If the sacrificial film 127 or the like is removed in this state, the film may be peeled off due to damage. In this embodiment, however, silylation is performed to make the surface of the Low-k film hydrophobic. To recover damage. At this time, the dielectric constant of the low-k film increases due to the formation of hydrophilic damage portions, but the dielectric constant can also be lowered by silylation treatment. In FIG. 9F, the damaged portion 129 formed in the Low-k film 124 is clearly shown for convenience, but the boundary between the damaged portion 129 and the non-damage portion is not necessarily clear.

In the silylation process in Step 9, the wafer W is transferred to one of the silylation units (SCH) 11a and 11b and placed on the support pins 64 on the hot plate 62, and a silylating agent, for example, DMSDMA vapor is added to the N _Two gases are introduced into the chamber 61 as a carrier. The conditions for the silylation treatment may be selected according to the type of the silylating agent. For example, the temperature of the vaporizer 63 is room temperature to 50 ° C., the silylating agent flow rate is 0.6 to 1.0 g / min, N _2. The gas (purge gas) flow rate can be set as appropriate from a range of room temperature to 200 ° C., the processing pressure is 532 to 95976 Pa (4 to 720 Torr), and the temperature of the hot plate 62 is appropriately set. In the case of using DMSDMA as the silylating agent, for example, the temperature of the hot plate 62 is set to 100 ° C., the pressure in the chamber 61 is reduced to 5 Torr (= 666 Pa), and then the DMSDMA vapor is carriered in N ₂ gas and There is a method in which the pressure is supplied until the pressure reaches 55 Torr, and the pressure is maintained for 3 minutes while maintaining the pressure, for example. The silylation reaction using DMSDMA is represented by the following formula 1.

  The silylating agent is not limited to the above-described DMSDMA, and any substance that causes a silylation reaction can be used without particular limitation, but it is compared among compounds having a silazane bond (Si-N bond) in the molecule. Those having a particularly small molecular structure, for example, those having a molecular weight of 260 or less are preferred, and those having a molecular weight of 170 or less are more preferred. Specifically, for example, in addition to the above-described DMSDMA and HMDS, TMSDMA (Dimethylaminotrimethylsilane), TMDS (1,1,3,3-Tetramethyldisilazane), TMSPyrole (1-Trimethylsilylpyrole), BSTFA (N, O-Bis (trimethylsilyl) trifluoroacetamide) ), BDDMMS (Bis (dimethylamino) dimethylsilane), or the like can be used. These chemical structures are shown below.

  Among the above compounds, TMSDMA and TMDS are preferably used as those having a high dielectric constant recovery effect and a high leakage current reduction effect. Further, from the viewpoint of stability after silylation, a structure in which Si constituting the silazane bond is bonded to three alkyl groups (for example, methyl group) (for example, TMSDMA, HMDS, etc.) is preferable.

  The wafer W that has undergone such silylation processing is carried into one of the cleaning processing units (CNU) 12a to 12d, where a predetermined chemical solution (for example, dilute hydrofluoric acid, amine type) that can dissolve the sacrificial film 127 and the like there. The sacrificial film 127 and the like are dissolved and removed by the chemical solution (step 10, FIG. 9 (h)). Here, the sacrificial film 127 is solubilized in various chemical solutions by the modification treatment, but the damage to the pattern is large particularly in the case of an acidic chemical solution such as hydrofluoric acid. Therefore, in the case of an acidic chemical solution, the effect of the silylation treatment in step 9 is great.

  When performing this dissolution and removal processing, the wafer W is transferred onto one spin chuck 71 of the cleaning processing units (CNU) 12a to 12d, and is sucked and held in a substantially horizontal posture, and the cleaning liquid discharge nozzle 81 of the cleaning liquid supply mechanism 80 is used. Then, a chemical solution in which a denatured substance such as the sacrificial film 127 can be dissolved is supplied to the surface of the wafer W to form a paddle. After a predetermined time has elapsed, the wafer W is rotated to shake off the chemical solution from the surface of the wafer W. Further, the chemical solution is supplied to the surface of the wafer W while rotating the wafer W to completely remove the sacrificial film 127 and the like. The resist film 128 and the polymer residue are also dissolved and removed by the chemical solution used for removing the sacrificial film 127 and the like. After the treatment with the chemical solution, pure water is supplied to the wafer W while the wafer W is rotated by the drive motor 72, the wafer W is washed with water, and the wafer W is rotated at a high speed to perform spin drying. The spin drying of the wafer W may be performed while supplying a drying gas to the wafer W.

  During this process, a damaged portion 130 as shown in FIG. 9H may be formed on the surface portion of the low-k film 124. The damaged portion 130 is also a portion where the low-k film 124, which was initially hydrophobic, is damaged and hydrophilized by the dissolution and removal process in step 10, and increases the relative dielectric constant of the low-k film 124. Since the parasitic capacitance between the wirings is increased after the wirings are formed, there are problems in electrical characteristics such as signal delay and deterioration in insulation between the trench wirings. In this case as well, the damaged portion 130 formed in the low-k film 124 is clearly shown for convenience, but the boundary between the damaged portion 130 and the non-damaged portion is not necessarily clear.

  In such a case, after the dissolution removal process in Step 10, the silylation process is performed again in the same procedure as in Step 9 (Step 11, FIG. 9 (i)). Thereby, the damage which the Low-k film | membrane 124 received at the time of melt | dissolution removal of a modification | denaturation substance can be recovered on the same principle. Therefore, the relative dielectric constant of the low-k film 124 is also recovered, and the above-described problem in electrical characteristics can be solved.

  Thereafter, the wafer W is transferred to the sputtering apparatus 106, where a barrier metal film and a Cu seed layer (that is, a plating seed layer) are formed on the inner walls of the via hole 124a and the trench 124b, and then the wafer W is transferred to the electrolytic plating apparatus 108. Then, copper 131 is buried as a wiring metal in the via hole 124a and the trench 124b by electrolytic plating (step 12, FIG. 9 (j)). Thereafter, the wafer W is annealed to anneal the copper 131 embedded in the via hole 124a and the trench 124b (an annealing apparatus is not shown in FIG. 1), and the wafer W is further transferred to the CMP apparatus 109, where CMP is performed. A flattening process is performed by (Step 13). Thereby, a desired semiconductor device is manufactured.

  In order to remove the sacrificial film 127 and the like in this way, a technique is adopted in which the sacrificial film 127 and the like are denatured so as to be solubilized in a predetermined chemical solution, and then the denatured substance is dissolved and removed using such a chemical solution. In this case, since the damage given to the Low-k film after the modification treatment is recovered by the silylation treatment, the next dissolution and removal treatment is performed, so that there is a disadvantage that the pattern is easily peeled off in the next dissolution and removal treatment. It will be resolved. In addition, after the dissolution and removal treatment, the low-k film 124 is still damaged and the relative dielectric constant increases, but the relative dielectric constant can be greatly reduced by recovering it by the subsequent silylation treatment. is there.

  Next, an experiment for confirming the effect of the present invention will be described. Here, for example, SiCHO is used as the Low-k film 124, and after the procedure shown in FIG. 9 (e), the modification treatment is performed with a mixed gas of water vapor and ozone under conditions of 100 to 200 ° C. and normal pressure to 200 kPa. Thus, the sacrificial film 127 was denatured into a state soluble in HF. Thereafter, silylation treatment was performed under the conditions of 50 to 250 ° C. and 1.33 to 26.6 kPa, and subsequently, the removal of the sacrificial film 127 and the like was performed using HF. Thereafter, as a result of investigating the state of the pattern, no pattern peeling was observed. On the other hand, after the modification treatment was performed under the same conditions as above, the same dissolution removal treatment was performed without the silylation treatment. As a result, a pattern that was not in a normal state, such as pattern peeling, was observed. From this result, it was confirmed that pattern damage such as pattern peeling was remarkably reduced by inserting a silylation treatment between the modification treatment and the dissolution removal treatment.

  Next, modification treatment → silylation → dissolution removal treatment was sequentially performed under the same conditions as in the above example, and silylation was further performed under the same conditions. After this treatment, the relative dielectric constant (k value) of the Low-k film was measured, and as a result, it was confirmed that the low-k film had almost recovered to the initial vicinity. On the other hand, after the modification treatment was performed under the same conditions, the dissolution removal treatment was performed under the same conditions without performing the silylation treatment, and the final silylation treatment was not performed. Since no recovery was made, the k value was high. After sequentially performing modification treatment → silylation → dissolution removal treatment under the same conditions as in the above example, when the final silylation treatment is not performed, the value is lower than when no silylation treatment is performed. However, the value was higher than that obtained when the silylation treatment was applied last.

  In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible. For example, in the above-described embodiment, the modification treatment of the sacrificial film or the like is performed using a mixed gas of water vapor and ozone. However, the treatment may be performed using only ozone without using water vapor. In the case of treatment with ozone, the reactivity is lower than that in the case of water vapor + ozone, but the sacrificial film and the like modified by the subsequent dissolution and removal treatment with a chemical solution can be sufficiently dissolved.

The low-k film that can recover damage by silylation treatment is not particularly limited, but porous MSQ that is an SOD film can be used. In addition, for example, a SiOC-based film which is one of inorganic insulating films formed by CVD can be targeted. This is a mixture of Si—O ₃ in a conventional SiO ₂ film by introducing a methyl group (—CH ₃ ) and mixing the Si—CH ₃ bond. Black Diamond (Applied Materials), Coral (Novellus) , Aurora (ASM), etc. fall under this category. The SiOC film may be porous. Further, the MSQ insulating film is not limited to a porous film, and may be dense.

  Furthermore, in the above-described embodiment, the example in which the present invention is applied to the manufacturing process of the semiconductor device including the copper wiring by the dual damascene method has been described. However, the present invention is not limited to this, and there is a concern about deterioration of the etching target film. It can be applied as long as the process exists.

BRIEF DESCRIPTION OF THE DRAWINGS Explanatory drawing which shows schematic structure of the wafer processing system used for the manufacturing process of the semiconductor device by the dual damascene method with which the substrate processing method is applied to one Embodiment of this invention. The top view which shows schematic structure of the washing | cleaning processing apparatus used for the wafer processing system of FIG. The front view which shows schematic structure of the washing | cleaning processing apparatus of FIG. The rear view which shows schematic structure of the washing | cleaning processing apparatus of FIG. The schematic sectional drawing which shows the modification | denaturation processing unit mounted in the washing | cleaning processing apparatus. The schematic sectional drawing which shows the silylation unit mounted in the washing | cleaning processing apparatus. The schematic sectional drawing which shows the washing | cleaning unit mounted in the washing | cleaning processing apparatus. 6 is a flowchart showing a manufacturing process of a semiconductor device by a dual damascene method, to which a substrate processing method is applied according to an embodiment of the present invention. Process sectional drawing of the flow shown in FIG. The figure for demonstrating the damage of a Low-k film | membrane, and the recovery by silylation. Explanatory drawing which shows typically the formation process of the trench wiring by the conventional dual damascene method.

Explanation of symbols

2; processing stations 11a and 11b; silylation unit (SCH)
12a to 12d; washing unit (CNU)
15a-15f; Denaturing unit (VOS)
DESCRIPTION OF SYMBOLS 100; Processing part 101; SOD apparatus 102; Resist coating / development apparatus 103; Exposure apparatus 104; Cleaning processing apparatus 105; Etching apparatus 106; Sputtering apparatus 107; Electroplating apparatus 109; CMP apparatus 110; 112; user interface 113; storage unit W; wafer (substrate)
120; interlayer insulating film 122; lower copper wiring 123; stopper film 124; interlayer insulating film (low-k film)
124a: via 124b; trench 125; antireflection film 126; resist film 127; sacrificial film 128; resist film 129, 130;

Claims (11)

Etching a film to be etched made of a low dielectric constant material formed on a substrate to form a predetermined pattern;
A step of modifying the substance remaining after the etching process to be solubilized in a predetermined liquid;
Next, a step of silylating the surface of the etching target film on which the pattern is formed,
Thereafter, the step of supplying the predetermined liquid to dissolve and remove the denatured substance,
The silylation treatment recovers damage formed on the etched film by the modifying step, prevents pattern peeling during the dissolving and removing process, and increases the dielectric constant due to the damage. dielectric constant of lowering the,
The substrate treatment method is characterized in that the step of modifying is performed by supplying a treatment gas containing water vapor and ozone . Forming a sacrificial film on an etching target film made of a low dielectric constant material formed on a substrate;
Forming an etching mask on the sacrificial film, and etching the sacrificial film and the etching target film to form a predetermined pattern;
Modifying the sacrificial film and the etching mask so as to be solubilized in a predetermined liquid;
Next, a step of silylating the surface of the etching target film on which the pattern is formed,
Thereafter, the step of supplying the predetermined liquid to dissolve and remove the denatured substance,
The silylation treatment recovers damage formed on the etched film by the modifying step, prevents pattern peeling during the dissolving and removing process, and increases the dielectric constant due to the damage. dielectric constant of lowering the,
The substrate treatment method is characterized in that the step of modifying is performed by supplying a treatment gas containing water vapor and ozone . Etching a film to be etched made of a low dielectric constant material formed on a substrate to form a predetermined pattern;
  A step of modifying the substance remaining after the etching process to be solubilized in a predetermined liquid;
  Next, a step of silylating the surface of the etching target film on which the pattern is formed,
  Thereafter, supplying the predetermined liquid to dissolve and remove the denatured substance;
Have
  The silylation treatment recovers damage formed on the etched film by the modifying step, prevents pattern peeling during the dissolving and removing process, and increases the dielectric constant due to the damage. Reducing the dielectric constant of
  The substrate treatment method is characterized in that the step of modifying is performed by supplying a treatment gas containing ozone.   Forming a sacrificial film on an etching target film made of a low dielectric constant material formed on a substrate;
  Forming an etching mask on the sacrificial film, and etching the sacrificial film and the etching target film to form a predetermined pattern;
  Modifying the sacrificial film and the etching mask so as to be solubilized in a predetermined liquid;
  Next, a step of silylating the surface of the etching target film on which the pattern is formed,
  Thereafter, supplying the predetermined liquid to dissolve and remove the denatured substance;
Have
  The silylation treatment recovers damage formed on the etched film by the modifying step, prevents pattern peeling during the dissolving and removing process, and increases the dielectric constant due to the damage. Reducing the dielectric constant of
  The substrate treatment method is characterized in that the step of modifying is performed by supplying a treatment gas containing ozone. 2. The method according to claim 1 , further comprising a step of recovering damage formed on the surface of the film to be etched in the step of silylating and dissolving and removing the surface of the film to be etched after the modified substance is removed. The substrate processing method according to claim 1 . The low dielectric constant material, a substrate processing method according to claim 1 to any one of claims 5, characterized in that it comprises an alkyl group as an end group.   The substrate processing method according to claim 1, wherein the predetermined liquid is an acid or an alkaline chemical liquid.   The substrate treatment method according to claim 1, wherein the silylation treatment is performed using a compound having a silazane bond (Si—N) in a molecule.   9. The substrate processing method according to claim 8, wherein the compound having a silazane bond in the molecule is TMDS (1,1,3,3-Tetramethyldisilazane) or TMSDMA (Dimethylaminotrimethylsilane). Contains a film to be etched made of a low dielectric constant material , and includes a water vapor and ozone so that a predetermined pattern is formed in the film to be etched by the etching process and so that a substance remaining after the etching process is solubilized in a predetermined liquid A step of silylating the surface of the film to be etched on a substrate that has been modified by being supplied with a processing gas or a processing gas containing ozone ;
Thereafter, the step of supplying the predetermined liquid to dissolve and remove the denatured substance,
The silylation treatment recovers damage formed in the etched film when it is modified, prevents pattern peeling during the dissolution and removal process, and increases the dielectric constant due to the damage. The substrate processing method characterized by lowering the dielectric constant of the substrate. A computer-readable storage medium storing a control program that runs on a computer,
The computer-readable storage medium, wherein the control program causes a computer to control the manufacturing apparatus so that the substrate processing method according to any one of claims 1 to 10 is performed at the time of execution. .

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