JP5246810B2 - Output control circuit, output control circuit control method and control program thereof - Google Patents

Description

  The present invention relates to an output control circuit, a control method for the output control circuit, and a control program therefor.

  Various techniques have been proposed for a FIFO (First In, First Out) circuit that outputs input data in the input order. For example, Patent Document 1 discloses a technology of a data storage device that can appropriately provide a FIFO function for a plurality of systems of data with a small circuit scale. Patent Document 2 discloses a technique for realizing a processing order specifying operation by sending a synchronization command to a specific FIFO circuit when it is desired to specify the order of data processing in a plurality of FIFO circuits.

  Patent Document 3 discloses a technique for detecting and avoiding the possibility of deadlock occurring between a request FIFO circuit and a response FIFO circuit. Patent Document 4 discloses a technique for interlocking a FIFO data path.

JP 2001-209811 A Japanese Patent Laid-Open No. 06-162206 Japanese Patent Laid-Open No. 08-249295 Japanese Patent Laid-Open No. 11-003206

  However, in Patent Documents 1 to 4, when data is input and output, it is output after other data input before that data and before other data input after that data. There is no disclosure of a technique for processing predetermined data that needs to be output (hereinafter referred to as order matching data) using a plurality of FIFO circuits.

  The present invention has been made to solve such problems, and provides an output control circuit capable of processing order matching data by a plurality of FIFO circuits, a control method for the output control circuit, and a control program therefor The purpose is to do.

  The output control circuit according to the present invention includes a data analysis unit that generates identification information for identifying the order matching data when the order matching data is input among the two types of data of the order matching data and the non-order matching data. And the first and second FIFO circuits to which different order matching data are allocated, and when the input data is order matching data, the order matching data is obtained from the order matching data based on the identification information. The first and second FIFO circuits are controlled so that the data is output after the unordered data input before and output before the unordered data input after the ordered data. A control unit is provided.

  The control method of the output control circuit according to the present invention includes a first step of detecting whether the input data is order-matched data or non-order-matched data, and if the input data is order-matched data, the order-matching data A second step of generating identification information for identifying and assigning different order matching data to the first and second FIFO circuits, and based on the identification information, the order matching data is more than the order matching data. The first and second FIFO circuits are controlled so that they are output after the unordered matching data input before and output before the unordered matching data input after the ordered matching data. A third step is provided.

  The control program for the output control circuit according to the present invention includes a first process for detecting whether the input data is order-aligned data or non-order-matched data, and if the input data is order-aligned data, A second process of generating identification information for identifying the matching data and allocating different order matching data to the first and second FIFO circuits, and the order matching data is based on the identification information. The first and second FIFO circuits are output after the non-order-matching data inputted before and before the non-order-matching data inputted after the order-matching data. The output control circuit is caused to execute the third process to be controlled.

  According to the present invention, it is possible to provide an output control circuit capable of processing order matching data by a plurality of FIFO circuits, a control method for the output control circuit, and a control program therefor.

1 is a block diagram illustrating an example of the overall configuration of an output control circuit according to a first embodiment; FIG. 4 is a diagram illustrating an example of output control of order matching data and non-order matching data according to the first exemplary embodiment. FIG. 3 is a block diagram illustrating an example of the overall configuration of an output control circuit according to a second embodiment. FIG. 3 is a block diagram illustrating an example of the overall configuration of a FIFO circuit control unit according to a second embodiment; FIG. 6 is a block diagram illustrating an example of the overall configuration of a FIFO output order control unit according to a second embodiment. FIG. 10 is a diagram illustrating a first state example of each FIFO circuit during data input according to the second embodiment; FIG. 10 is a diagram illustrating a second state example of each FIFO circuit during data input according to the second embodiment; FIG. 10 is a diagram illustrating a third state example of each FIFO circuit during data input according to the second embodiment; FIG. 10 is a diagram illustrating a fourth state example of each FIFO circuit during data input according to the second embodiment; FIG. 10 is a diagram illustrating an example of operation timing related to data input of a plurality of FIFO circuits according to the second embodiment; FIG. 10 is a diagram illustrating a first state example of each FIFO circuit during data output according to the second embodiment; FIG. 10 is a diagram illustrating a second state example of each FIFO circuit during data output according to the second embodiment; FIG. 10 is a diagram illustrating a third state example of each FIFO circuit during data output according to the second embodiment; FIG. 10 is a diagram illustrating a fourth state example of each FIFO circuit during data output according to the second exemplary embodiment; FIG. 10 is a diagram illustrating a fifth state example of each FIFO circuit during data output according to the second embodiment; FIG. 10 is a diagram illustrating a sixth state example of each FIFO circuit during data output according to the second embodiment; FIG. 10 is a diagram illustrating an example of operation timing related to data output of the FIFO circuit A according to the second exemplary embodiment; FIG. 10 is a diagram illustrating an example of operation timing related to data output of the FIFO circuit B according to the second embodiment; FIG. 5 is a block diagram illustrating an example of the overall configuration of an output control circuit according to a third embodiment.

Embodiment 1
Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating an example of the overall configuration of the output control circuit 100. The output control circuit 100 includes a data analysis unit 101, a FIFO circuit 102 (first FIFO circuit), a FIFO circuit 103 (second FIFO circuit), and a control unit 104. The output control circuit 100 can acquire and output data, and can store input data by the FIFO circuits 102 and 103.

  The output control circuit 100 is mounted on a computer and acquires data from other circuits in the computer. The output control circuit 100 temporarily stores the acquired data, and then outputs it to other circuits in the computer in an appropriate order.

  The data analysis unit 101 detects whether the input data to the output control circuit 100 is the above-described order matching data. When the input data is order matching data, the data analysis unit 101 outputs identification information indicating that the input data is order matching data to the control unit 104. This identification information only needs to be information that can identify which data to which data is order-aligned data in the input data. For example, the data analysis unit 101 may output identification information to the control unit 104 only when the first data and the last data of the order matching data are input. Alternatively, the data analysis unit 101 may output identification information to the control unit 104 for all data in the order matching data. The data analysis unit 101 specifically includes a processor such as a CPU.

  When the output control circuit 100 outputs data, the above-mentioned “order matching data” composed of a plurality of data does not need to be output in the order of input as long as the order matching data is between them. However, in the case of data output, mixing of ordered data and non-ordered data is not allowed. The processing of the order matching data and the non-order matching data in the case of this data input and output will be described later. Note that the order matching data is data for setting the system, for example, and the data input before the system setting needs to be output in the order before the data input after the setting. It is.

  The FIFO circuits 102 and 103 acquire input data to the output control circuit 100, and each outputs the acquired input data in the order of input. Under the control of the control unit 104, different order matching data is allocated to the FIFO circuits 102 and 103. Specifically, the FIFO circuits 102 and 103 include a memory such as a RAM.

  The control unit 104 controls data input and output of the FIFO circuits 102 and 103. As for the data input of the FIFO circuits 102 and 103, as described above, the control unit 104 outputs control information to the FIFO circuits 102 and 103 so that different order matching data is allocated to the FIFO circuits 102 and 103. As for the data output of the FIFO circuits 102 and 103, the control unit 104 outputs control information to the FIFO circuits 102 and 103 so that the FIFO circuits 102 and 103 output input data at a predetermined timing. Specifically, the control unit 104 includes a processor such as a CPU.

  An example of output control for order-aligned data and non-order-aligned data when outputting input data will be described with reference to FIG. In the “input data” diagram in FIG. 2, the data composed of the data A to E is order matching data. Data composed of data 1 to 4 and 5 to 8 is non-order matching data. Further, data 1 to 4 are first non-order matched data input before order matched data, and data 5 to 8 are second non-order matched data inputted after order matched data. Data A to E and 1 to 8 indicate data of one unit of order matching data and non-order matching data. The unordered data of data 1 to 8 need not be output in the same order as input. In the drawing showing data input and output in FIG. 2, the left data indicates that the data is input or output earlier.

  At the time of input in FIG. 2, the first non-order matching data is input to the output control circuit 100 first. Next, order matching data is input, and then second non-order matching data is input. When the data input is in this order, the output control circuit 100 can output the input data in the order shown in “data output order 1”, for example. In the order shown in the “data output order 1”, the order-aligned data is different from the order in the data A to E, but the data A to E is not mixed with the non-order matched data. This is because it is output as a lump. In other words, the ordered data is output after the first non-ordered data input before the ordered data, and before the second non-ordered data input after the ordered data. Is output.

  However, the output control circuit 100 cannot output input data in the order shown in “data output order 2”. In the order shown in “Data Output Order 2”, the data A to E which are the order matching data are not a group of A to E but mixed with the non-order matching data (data 2 and 6 in the example of FIG. 2). Is output. In other words, the ordered data is output after the first non-ordered data input before the ordered data, and before the second non-ordered data input after the ordered data. It is not supposed to be output.

  As described above, when the output control circuit 100 outputs data, the order of the data in the order matching data may be changed, but it is allowed to mix the order matching data and the non-order matching data. Not. Note that the order matching data may be any kind of data as long as the data satisfies this property.

  Note that different order matching data is input to the FIFO circuits 102 and 103 under the control of the control unit 104 as described above. For example, in FIG. 2, data A, C, and E are input to the FIFO circuit 102, and data B and D are input to the FIFO circuit 103. Different data is also input to the FIFO circuits 102 and 103 as data 1 to 8 which are non-order matching data.

  In addition, the data analysis unit 101 outputs identification information indicating that the data A to E is the order matching data in the “input data” in FIG. 2 to the control unit 104. For example, when the data analysis unit 101 acquires the data A and E, the data analysis unit 101 outputs identification information to the control unit 104 to notify the control unit 104 that the data A to E are order matching data. That is, this identification information indicates the first and last data of the order matching data. Alternatively, when each of the data A to E is acquired, the data analysis unit 101 outputs identification information to the control unit 104, so that the data A to E is transmitted to the control unit 104 that is the order matching data. Good.

  Hereinafter, processing of the output control circuit 100 when the input data to the output control circuit 100 is order matching data will be described. First, the data analysis unit 101 detects whether or not the input data to the output control circuit 100 is order matching data. This is the first step. When the input data is order matching data, the data analysis unit 101 generates identification information for identifying the order matching data and outputs the identification information to the control unit 104. Further, the control unit 104 allocates different order matching data to the FIFO circuits 102 and 103. This is the second step. When the FIFO circuits 102 and 103 output the order matching data, the control unit 104 performs the following control based on the identification information. In other words, based on the identification information, the order matching data output by the FIFO circuits 102 and 103 is output after the first non-order matching data input before the order matching data. Control is performed so that the data is output before the second non-order-matching data input later. This is the third step.

  With the above configuration, it is possible to provide an output control circuit capable of processing order matching data by a plurality of FIFO circuits, a control method for the output control circuit, and a control program therefor.

Embodiment 2
The second embodiment of the present invention will be described below with reference to the drawings. Note that the description similar to that of Embodiment 1 is omitted as appropriate. First, an example of the overall configuration of the output control circuit 200 in this embodiment will be described with reference to the block diagram of FIG. The output control circuit 200 includes a data analysis unit 201, a FIFO circuit A202, a FIFO circuit B203, and a FIFO circuit control unit 210. The data analysis unit 201, the FIFO circuit A202, the FIFO circuit B203, and the FIFO circuit control unit 210 in FIG. 3 correspond to the data analysis unit 101, the FIFO circuit 102, the FIFO circuit 103, and the control unit 104 in the first embodiment. Further, the FIFO circuit A202 and the FIFO circuit B203 are connected in parallel.

  The output control circuit 200 can acquire data from the outside and output the data, and can store input data by the FIFO circuits A202 and B203.

  When the data analysis unit 201 acquires input data RD from the outside to the output control circuit 200, the data analysis unit 201 determines which of the FIFO circuits A202 and B203 processes the input data RD, and uses the determined content as a selection signal as a FIFO. Output to the circuit controller 210. When it is determined to input data to the FIFO circuit A 202, the selection signal S_A indicating the information is validated and output to the FIFO circuit control unit 210. When it is determined to input data to the FIFO circuit B 203, the selection signal S_B indicating the information is validated and output to the FIFO circuit control unit 210. The determination of the FIFO circuit in the data analysis unit 201 may be determined by replacing the input FIFO circuit every time data arrives, or may be determined according to the processing speed of each FIFO circuit.

  When the data analysis unit 201 acquires the input data RD, the data analysis unit 201 outputs either the selection signal S_A or the selection signal S_B. In other words, both the selection signal S_A and the selection signal S_B are not output at the same time, or neither is output at the same time. This is to prevent the same input data RD from being processed by both the FIFO circuits A202 and B203, or the occurrence of input data RD that is not processed by either of the FIFO circuits A202 and B203.

  Further, the data analysis unit 201 analyzes the input data RD and detects whether or not the input data RD is order matching data. When the input data RD is order matching data, the data analysis unit 201 validates and outputs the order matching signal OE indicating that the input data RD is order matching data to the FIFO circuit control unit 210. This order matching signal OE corresponds to the identification information of the first embodiment. The order matching signal OE is output to the FIFO circuit control unit 210 when the first data and the last data of the order matching data are input. By acquiring the order matching signal OE, the FIFO circuit control unit 210 can identify which data from which data is the order matching data in the input data RD. Since the description of the order matching data is the same as that of the first embodiment, the description is omitted.

  Here, when the data analysis unit 201 detects that the input data RD is order matching data, the data analysis unit 201 performs control so that different order matching data is allocated to the FIFO circuits A 202 and B 203. For example, the data analysis unit 201 may alternately output the selection signals S_A and S_B every time the order matching data is received in order to allocate the order matching data to the FIFO circuits A202 and B203 alternately. Further, the order matching data may be allocated according to the processing speed of the FIFO circuits A202 and B203. However, the data analysis unit 201 is not allowed to perform control so that the order matching data is allocated to only one of the FIFO circuits A202 and B203.

  The FIFO circuit A202 acquires input data RD from the outside, and outputs the acquired data in the order of input. Further, the FIFO circuit A202 acquires the input valid signal WE_A, the input address signal WP_A, and the output address signal RP_A output from the FIFO circuit control unit 210.

  The input valid signal WE_A is output from the FIFO circuit control unit 210 to the FIFO circuit A202 when the FIFO circuit control unit 210 determines that the input data RD is data to be input and output in the FIFO circuit A202. Signal. The FIFO circuit A202 determines that the input data RD is valid only when the input data RD is acquired simultaneously with the input valid signal WE_A, and inputs the input data RD to the internal address. On the other hand, when the input data RD is acquired but the input valid signal WE_A is not acquired, the FIFO circuit A202 considers that the input data RD is not valid and does not input the address inside the FIFO circuit A202.

  The input address signal WP_A is a signal that the FIFO circuit control unit 210 outputs to the FIFO circuit A202 simultaneously with the input valid signal WE_A, and includes information on an address for storing the input data RD in the FIFO circuit A202. The FIFO circuit A202 inputs the input data RD to a predetermined address based on the input address signal WP_A.

  The output address signal RP_A is a signal for the FIFO circuit control unit 210 to control the output order of the FIFO circuit A202, and is an instruction for outputting data input to a specific address of the FIFO circuit A202. The FIFO circuit A202 outputs the data input to the address indicated by the output address signal RP_A to the outside as output data. In FIG. 2, the data signal output from the FIFO circuit A202 is represented as output data TD_A.

  The FIFO circuit B203 acquires input data RD from the outside, and outputs the acquired data in the order of input. The FIFO circuit B203 acquires the input valid signal WE_B, the input address signal WP_B, and the output address signal RP_B output from the FIFO circuit control unit 210. Regarding the input valid signal WE_B, the input address signal WP_B, the output address signal RP_B, and the processing of the FIFO circuit B203 when each signal is acquired, the input valid signal WE_A, the input address signal WP_A, Since it is the same as the description about the output address signal RP_A, the description is omitted. The output data TD_B is the same as the output data TD_A in the above-described FIFO circuit A202, and thus description thereof is omitted.

  The FIFO circuit control unit 210 controls the data input order of the FIFO circuits A202 and B203 based on the order matching signal OE, the selection signal S_A, the selection signal S_B, and the externally input data valid signal RV output from the data analysis unit 201. . The input data valid signal RV is output from the outside when the input data RD to the output control circuit 200 is valid. The FIFO circuit control unit 210 determines that the input data RD is valid only when the input data RD is acquired simultaneously with the input data valid signal RV, and causes the FIFO circuit A 202 or the FIFO circuit B 203 to process the data.

  For example, when the FIFO circuit control unit 210 acquires the input data valid signal RV and the selection signal S_A, the input valid signal WE_A and the input address signal WP_A are output to the FIFO circuit A202. The FIFO circuit A202 processes the input data RD as described above according to the acquired input valid signal WE_A and the input address signal WP_A. On the other hand, when the FIFO circuit control unit 210 acquires the input data valid signal RV and the selection signal S_B, it outputs the input valid signal WE_B and the input address signal WP_B to the FIFO circuit B203. The FIFO circuit B203 processes the input data RD as described above according to the acquired input valid signal WE_B and the input address signal WP_B.

  If the FIFO circuit control unit 210 has acquired the input data RD but has not acquired the input data valid signal RV at the same time, the FIFO circuit control unit 210 regards the acquired input data RD as invalid. In this case, the FIFO circuit control unit 210 does not allow the input data RD to be processed by the FIFO circuit A202 or the FIFO circuit B203.

  The FIFO circuit control unit 210 controls the data output order of the FIFO circuits A202 and B203 based on the output request signal TR_A and the output request signal TR_B output from the outside. The output request signal TR_A is a request signal from the outside, and requests the FIFO circuit A202 to output data to the outside. The same applies to the output request signal TR_B. When the FIFO circuit control unit 210 acquires the output request signal TR_A, when the FIFO circuit A 202 determines that data can be output to the outside, the FIFO circuit control unit 210 outputs an output request acceptance notification TA_A to the outside. At the same time, the output address signal RP_A is output to the FIFO circuit A202. The FIFO circuit A202 outputs the data input to the address inside the FIFO circuit A202 indicated by the output address signal RP_A as output data TD_A. The FIFO circuit control unit 210 performs the same processing when acquiring the output request signal TR_B and also when the FIFO circuit B 203 determines that data output to the outside is possible. The FIFO circuit control unit 210 makes the determination as described above based on the order matching signal OE.

  When there is an address that can be input in the FIFO circuits A 202 and B 203, the FIFO circuit control unit 210 outputs a data acceptance signal RR to the outside. Externally, the input data RD is output to the output control circuit 200 in response to the data acceptance signal RR.

  Details of the inside of the FIFO circuit control unit 210 will be described with reference to FIGS. FIG. 4 is a block diagram illustrating an example of the overall configuration of the FIFO circuit control unit 210. The FIFO circuit control unit 210 includes a FIFO address control unit 211 and a FIFO output order control unit 220.

  The FIFO address control unit 211 controls the addresses of the FIFO circuits A202 and B203. For example, when the FIFO address control unit 211 acquires the input valid signal WE_A output from the FIFO output order control unit 220, the FIFO address control unit 211 determines an address at which data can be input to the FIFO circuit A202. The FIFO address control unit 211 generates a signal indicating the address information as an input address signal WP_A and outputs the signal to the FIFO output order control unit 220 and the FIFO circuit A. When the input valid signal WE_B output from the FIFO output order control unit 220 is acquired, the FIFO address control unit 211 similarly uses a signal indicating an address where data can be input in the FIFO circuit B203 as the input address signal WP_B. And output to the FIFO output order controller 220 and the FIFO circuit B.

  Further, when the FIFO address control unit 211 acquires the output valid signal RE_A output from the FIFO output order control unit 220, the FIFO address control unit 211 determines an address at which data output of the FIFO circuit A202 is possible. The FIFO address control unit 211 generates a signal indicating the address information as an output address signal RP_A and outputs the signal to the FIFO output order control unit 220 and the FIFO circuit A. Even when the output valid signal RE_B output from the FIFO output order control unit 220 is acquired, the FIFO address control unit 211 similarly uses a signal indicating an address at which data can be output in the FIFO circuit B203 as the output address signal RP_B. And output to the FIFO output order controller 220 and the FIFO circuit B.

  Furthermore, when data is input to an address in the FIFO circuit A202, the FIFO address control unit 211 outputs the information to the FIFO output order control unit 220 as a status signal E_A. Also for the FIFO circuit B 203, similar information is output to the FIFO output order control unit 220 as the status signal E_B. Further, when both FIFO circuits A202 and B203 can be input (when there is an address in which no data is input in the address in the FIFO circuit A202 and the address in the FIFO circuit B203), the data acceptance signal RR is notified to the outside. To do.

  In FIG. 4, the FIFO output order control unit 220 manages data input and output of the FIFO circuits A202 and B203 based on the input address signal WP_A, the input address signal WP_B, the output address signal RP_A, and the output address signal RP_B. Thereby, the FIFO circuits A202 and B203 can output the order matching data in the input data RD so as not to be mixed with the non-order matching data.

  For example, when the FIFO output order control unit 220 simultaneously acquires the input data valid signal RV from the outside and the selection signal S_A from the data analysis unit 201 and determines that there is an address that can be input in the FIFO circuit A202, the input valid signal WE_A Is output to the FIFO address control unit 211 and the FIFO circuit A202. Similarly, when the input data valid signal RV and the selection signal S_B from the data analysis unit 201 are simultaneously acquired from the outside and it is determined that there is an address that can be input in the FIFO circuit B203, the input valid signal WE_B is sent to the FIFO address control unit 211 and The data is output to the FIFO circuit B203.

  The FIFO output order controller 220 controls the data output order of the FIFO circuits A202 and B203 based on the output request signal TR_A and the output request signal TR_B output from the outside. When the FIFO output order control unit 220 determines that the FIFO circuit A 202 can output data to the outside, the FIFO output order control unit 220 outputs an output request acceptance notification TA_A to the outside and an output valid signal RE_A to the FIFO address control unit 211. . The same applies to the FIFO circuit B203. In this case, the FIFO output order control unit 220 uses the status signal E_A, the status signal E_B, and the order matching signal OE to determine whether the FIFO circuit A 202 or the FIFO circuit B 203 can output data to the outside. judge.

  Note that the FIFO output order control unit 220 uses the input address signal WP_A, the input address signal WP_B, and the output address signal RP_A as information on which address of the FIFO circuits A202 and B203 the data is input to. , Updated and held by the output address signal RP_B. Further, when the order matching signal OE is acquired from the data analysis unit 201, it is determined that the data input to the FIFO circuits A202 and B203 is the first data or the last data of the order matching data, and the order matching signal OE is determined. Is stored in the FIFO output order control unit 220 as data information.

  Next, details of the inside of the FIFO output order control unit 220 will be described with reference to FIG. FIG. 5 is a block diagram showing an example of the overall configuration of the FIFO output control circuit 200. The FIFO output order controller 220 includes an order management number generator 221, a FIFO circuit A data information manager 222, a FIFO circuit B data information manager 223, and a FIFO data control manager 224.

  The order management number generation unit 221 generates an order management number common to the management of the FIFO circuits A202 and B203 based on the input data valid signal RV and the order matching signal OE. The sequence management number generation unit 221 outputs the sequence management number information to the FIFO circuit A data information management unit 222 and the FIFO circuit B data information management unit 223 as the sequence management signal RO_N.

  Here, the order management number is controlled by a counter, and when the order management number generation unit 221 acquires the order matching signal OE in which the input data valid signal RV is valid, it is counted up at the next clock.

  For example, in the initial state where the input data RD is non-order matched data, the order management number is set to “0”. When the first order matching signal OE is output (when the input data RD becomes order matching data), the order management number is counted up to “1”. Thereafter, when the second order matching signal OE is output (when the input data RD becomes non-order matching data), the order management number is counted up to “2”. As described above, the order management number is counted up.

  The FIFO circuit A data information management unit 222 acquires the order matching signal OE, the order management signal RO_N, the output valid signal RE_A, the input valid signal WE_A, the input address signal WP_A, and the output address signal RP_A, and inputs the data of the FIFO circuit A202. And manage output. That is, the FIFO circuit A data information management unit 222 updates and holds the information indicating which address of the FIFO circuit A 202 is input with data and which address is not input with the above-described signal.

  The FIFO circuit A data information management unit 222 internally holds addresses corresponding to the respective addresses of the FIFO circuit A202. When the FIFO circuit A data information management unit 222 acquires the input valid signal WE_A, the FIFO circuit A data information management corresponding to the address to which data is input in the FIFO circuit A202 based on the input address signal WP_A acquired simultaneously. The sequence management number generated by the sequence management number generation unit 221 is input to the address inside the unit 222. This order management number is information that the order management number generation unit 221 outputs as the order management signal RO_N. When the FIFO circuit A data information management unit 222 acquires the order matching signal OE simultaneously with the input valid signal WE_A and the input address signal WP_A, the data information related to the order matching signal OE (hereinafter referred to as order matching information) is also Input to the address in the FIFO circuit A data information management unit 222. As described above, the FIFO circuit A data information management unit 222 stores the order management number and the order matching information in association with the input data RD of the FIFO circuit A202.

  Further, when the FIFO circuit A data information management unit 222 acquires the output valid signal RE_A, the FIFO circuit A data corresponding to the address to which data is output in the FIFO circuit A202 based on the output address signal RP_A acquired at the same time. The address in the information management unit 222 is referred to. The FIFO circuit A data information management unit 222 outputs information on the order management number at the referenced address to the FIFO data control management unit 224 as an output order management signal TON_A. Further, when the referred address has the above-mentioned order matching information, the information is output to the FIFO data control management unit 224 as the output order matching signal TO_A.

  The FIFO circuit B data information management unit 223 processes the data input and output of the FIFO circuit B 203 in the same manner as the FIFO circuit A data information management unit 222, and thus the description thereof is omitted.

  The FIFO data control management unit 224 generates a signal for managing the FIFO circuits A202 and B203. The FIFO data control management unit 224 generates an input valid signal WE_A for controlling the input of the FIFO circuit A202 from the input data valid signal RV and the selection signal S_A. The input valid signal WE_A is output to the FIFO circuit A data information management unit 222, the FIFO address control unit 211, and the FIFO circuit A202. Similarly, the FIFO data control management unit 224 generates an input valid signal WE_B for controlling the input of the FIFO circuit B203 from the input data valid signal RV and the selection signal S_B. The input valid signal WE_B is output to the FIFO circuit B data information management unit 223, the FIFO address control unit 211, and the FIFO circuit B203.

  Next, a method in which the FIFO data control management unit 224 manages the output of the FIFO circuit A202 or B203 will be described. The FIFO data control management unit 224 determines whether the output of the FIFO circuit A202 is possible when the output request signal TR_A from the outside is acquired. When it is determined that the output of the FIFO circuit A202 is possible, the FIFO data control management unit 224 outputs the output valid signal RE_A and the output request acceptance notification TA_A. When it is determined that the output of the FIFO circuit A202 is not possible, the FIFO data control management unit 224 does not output the output valid signal RE_A and the output request acceptance notification TA_A.

  Here, the above-mentioned “determination of whether or not the output of the FIFO circuit A 202 is possible” will be described. The FIFO data control management unit 224 generates an outputable management number for controlling the output order of the FIFO circuits A202 and B203. When the FIFO data control management unit 224 acquires the output order matching signal TO_A or the output order matching signal TO_B, the output possible management number is the clock when the output of the output order matching signal TO_A or the output order matching signal TO_B is stopped. Count up.

  The FIFO data control management unit 224 determines whether or not the status signal E_A is output (whether or not data is input in the FIFO circuit A202) in determining whether or not the FIFO circuit A202 can output. When the status signal E_A is output (data is input in the FIFO circuit A202), the FIFO data control management unit 224 determines the order management number (hereinafter referred to as the output order management number A) as information in the output order management signal TON_A. The same is true for B.) and the outputable management number are compared. If the value of the output order management number A is equal to or less than the value of the outputable management number, the FIFO data control management unit 224 determines that the FIFO circuit A202 can output. Note that either of the determination of whether or not the status signal E_A is output and the determination of the size of the output order management number A and the output possible management number may be processed first.

  When the FIFO data control management unit 224 acquires the output request signal TR_B from the outside, it similarly determines whether or not the FIFO circuit B203 can output. When the FIFO circuit B 203 determines that output is possible, the FIFO data control management unit 224 outputs the output valid signal RE_B and the output request acceptance notification TA_B. Details of “determination of whether or not the FIFO circuit B 203 can output” are the same as described above, and thus the description thereof is omitted.

  Now, for an output request from the outside, the output request signal TR_A and the output request signal TR_B are output at the same time, and both the status signal E_A and the status signal E_B are output (both the FIFO circuits A202 and B203 can output data). And In this case, it is assumed that both the values of the output order management number A and the output order management number B are less than the value of the output possible management number, and the value of the output order management number A and the value of the output order management number B are different. The In this case, the FIFO data control management unit 224 can output only the FIFO circuit having a small output order management number value. That is, if the value of the output order management number A is smaller than the value of the output order management number B, the FIFO data control management unit 224 can output only the FIFO circuit A202. If the value of the output order management number B is smaller than the value of the output order management number A, the FIFO data control management unit 224 can output only the FIFO circuit B203.

  In addition, the output request signal TR_A, the output request signal TR_B, the status signal E_A, and the status signal E_B are output, and the values of the output order management number A and the output order management number B are the same as the output possible management number values, and the output order matching It is also assumed that either the signal TO_A or the output order matching signal TO_B is output. In that case, the FIFO data control management unit 224 performs control so that the data of the FIFO circuit to which the output order matching signal is not output is output first. That is, when the output order matching signal TO_A is output, the FIFO data control management unit 224 causes the data of the FIFO circuit B203 to be output first. When the output order matching signal TO_B is output, the FIFO data control management unit 224 causes the data of the FIFO circuit A202 to be output first. In other words, when the order management numbers of the FIFO circuits are the same, the data output next from one FIFO circuit is the order matching data, and the other FIFO circuit is the non-order matching data, the FIFO data control is performed. The management unit 224 performs control to output the same type of input data as that output immediately before.

  The output request signal TR_A, the output request signal TR_B, the status signal E_A, and the status signal E_B are output, and the values of the output order management number A and the output order management number B are the same as the values of the output possible management numbers, and the output order matching It is assumed that neither the signal TO_A nor the output order matching signal TO_B is output. In that case, the data output of the FIFO circuit A202 and the data output of the FIFO circuit B203 are optional, and either one may be first. The data output from the FIFO circuit A202 and the data output from the FIFO circuit B203 may be performed simultaneously. The control of each part of the output control circuit 200 has been described above.

  Next, specific operations of the FIFO circuits A202 and B203 when data is input in the output control circuit 200 will be described with reference to FIGS. 6 to 9 are diagrams illustrating specific state examples of the FIFO circuits A202 and B203 at times t0 to t4. Time t0 is the initial time.

  In FIG. 6, the figure described as “FIFO circuit A” shows the state of the FIFO circuit A 202. The numbers (0) to (4) with parentheses in the figure are the address numbers of the FIFO circuit A202, and the numbers without parentheses are the order management numbers input to the addresses inside the FIFO circuit A data information management unit 222. is there. Further, the dot pattern in the figure described as “FIFO circuit A” in the lower diagram of FIG. 6 indicates that data is input to the address (0) of the FIFO circuit A202. Data with a low dot pattern density indicates non-order matching data, and data with a high dot pattern density indicates order matching data. The above description is the same for the figure labeled “FIFO circuit B”. Moreover, the arrow in FIG. 6 is an arrow which shows progress of time, and shows that time passed from the time t0 to t1. 7 to 9 and FIGS. 11 to 16 are similarly described.

  Hereinafter, specific states of the FIFO circuits A202 and B203 will be described. FIG. 6 shows the state of each FIFO circuit when the time elapses from time t0 and reaches time t1. At time t0, there is no data input to the FIFO circuits A202 and B203. At time t0 to t1, data is input to the address (0) of the FIFO circuits A202 and B203. Here, the input data is unordered data.

  Reference is now made to FIG. FIG. 7 shows the state of each FIFO circuit when the time elapses from the time t1 and the time t2 is reached and the first data of the order matching data is input to the address (1) of the FIFO circuit A202. At times t1 to t2, the order matching signal OE is input to the address in the FIFO circuit A data information management unit 222 corresponding to the address (1) of the FIFO circuit A 202 to which the first data of the order matching data is input. . Details of the input are as described above.

  Reference is now made to FIG. FIG. 8 shows the state of each FIFO circuit when the time elapses from time t2 and reaches time t3. Specifically, FIG. 8 shows that after the head data of the order matching data is input to the FIFO circuit A202, the data included in the subsequent order matching data is the address (2) of the FIFO circuit A202 and the address of the FIFO circuit B203. The input state is shown in (1). Here, the order management number corresponding to the data included in the subsequent order matching data is “1”. This is because the sequence management number generation unit 221 counts up the sequence management number at the next clock after the sequence management number generation unit 221 acquires the sequence matching signal OE.

  Reference is now made to FIG. FIG. 9 shows the state of each FIFO circuit when the time elapses from time t3 and reaches time t4. Specifically, FIG. 9 shows that after the last data of the order matching data is input to the address (2) of the FIFO circuit B203, the non-order matching data becomes the address (3) of the FIFO circuit A202 and the FIFO circuit B203. The state input to the addresses (3) and (4) is shown.

  Here, the order matching signal OE is input to the address in the FIFO circuit B data information management unit 223 corresponding to the address (2) of the FIFO circuit B 203 to which the last data of the order matching data is input. Further, the order management number corresponding to the non-order-matched data is incremented by the order management number generation unit 221 and becomes “2”.

  Referring to FIG. 10, an example of operation timing related to data input of FIFO circuits A202 and B203 in FIGS. FIG. 10 shows the output timing of the input data valid signal RV, the input valid signal WE_A, the input valid signal WE_B, and the order matching signal OE. FIG. 10 also shows the update of the input address number and order management number of each FIFO circuit accompanying each signal. The input address number of the FIFO circuit A202 means an address number that can be input by the FIFO circuit A202, which is information included in the input address signal WP_A. (Hereinafter referred to as the input address number A. The same applies to the input address number of the FIFO circuit B203.) The input address numbers A and B and the order management number are the input address signal WP_A, input address signal WP_B and It is indicated by each number of the order management signal RO_N. FIG. 10 also shows time information at times t0 to t4.

  Hereinafter, the operation timing at each time of FIG. 10 will be described. At time t0 (initial time) in FIG. 10, the output control circuit 200 has not acquired the input data valid signal RV. Therefore, there is no input data to the FIFO circuits A202 and B203. The order management number is “0” in the initial state.

  At time t0 to t1 (state shown in FIG. 6) in FIG. 10, the output control circuit 200 acquires the input data valid signal RV for two clock cycles. That is, the output control circuit 200 totals the input data RD to obtain 2 units. In FIG. 10, out of two units of input data RD at times t0 to t1, data processed by the FIFO circuits A202 and B203 is one unit. This is indicated by the fact that the input valid signal WE_A and the input valid signal WE_B are output one period at a time corresponding to the input data valid signal RV at times t0 to t1. The input valid signal WE_A and the input valid signal WE_B are output from the FIFO data control management unit 224 based on the selection signals S_A and S_B of the data analysis unit 201.

  The FIFO circuits A202 and B203 input one unit of data to the address (0), respectively, according to the input valid signals WE_A and WE_B. The order management number “0” corresponding to the input data is the address of the FIFO circuit A data information management unit 222 and the FIFO circuit B data information management unit 223 corresponding to the address (0) of the FIFO circuits A202 and B203. Is remembered. The above is the state of the FIFO circuits A202 and B203 at times t0 to t1.

  At time t1 to t2 (state shown in FIG. 7) in FIG. 10, the output control circuit 200 totals the input data RD to acquire one unit. When the output control circuit 200 acquires the input data RD, the data analysis unit 201 outputs the order matching signal OE at the same time. That is, the input data RD at time t1 to t2 is the first unit data in the order matching data. In the case of acquiring the input data RD, the selection signal S_A is output from the data analysis unit 201, and the FIFO data control management unit 224 that has acquired the selection signal S_A outputs the input valid signal WE_A, so that the input data RD is the FIFO circuit. It is input to address (1) of A202. Further, by acquiring the order matching signal OE, the order management number generation unit 221 counts up the order management number after the next clock and sets it to “1”. The order management number “0” is stored in the address of the FIFO circuit A data information management unit 222 corresponding to the address (1) of the FIFO circuit A202. (When the first unit data in the order matching data is acquired, the order management number is not counted up.) The above is the state of the FIFO circuits A202 and B203 at times t1 to t2.

  At time t2 to t3 in FIG. 10 (state shown in FIG. 8), the output control circuit 200 totals the input data RD to obtain 2 units. The input data RD acquired by the output control circuit 200 at the times t2 to t3 by the same process as that at the time t0 to t1 is one unit at a time, the address (2) of the FIFO circuit A202 and the address (1) of the FIFO circuit B203. ). Note that the order management number corresponding to the input data RD is “1”, and is stored in the addresses of the FIFO circuit A data information management unit 222 and the FIFO circuit B data information management unit 223 as described above. The above is the state of the FIFO circuits A202 and B203 at times t2 to t3.

  At time t3 to t4 in FIG. 10 (state shown in FIG. 9), the output control circuit 200 totals the input data RD to obtain 3 units. When the output control circuit 200 acquires the first data of the input data RD at times t3 to t4, the data analysis unit 201 outputs the order matching signal OE at the same time. That is, the first input data RD at time t3 to t4 is the last unit data of the order matching data. Since the order matching signal OE is acquired here, the order management number generation unit 221 counts up the order management number after the next clock and sets it to “2”. Input data RD at times t3 to t4 is input to addresses (2), (3), and (4) of the FIFO circuit B203 by the same processing as described above. Similarly, the order management number is stored in the address of the FIFO circuit B data information management unit 223. The above is the state of the FIFO circuits A202 and B203 at times t3 to t4.

  Next, a specific state of the FIFO circuits A202 and B203 when data is output from the output control circuit 200 after time t4 will be described. FIGS. 11 to 16 are diagrams illustrating specific state examples of the FIFO circuits A202 and B203 at times t4 to t10.

  First, referring to FIG. FIG. 11 shows the state of each FIFO circuit when the time elapses from time t4 and reaches time t5. Specifically, FIG. 11 shows a state in which data input to the address (0) of the FIFO circuit A202 is output from time t4 to t5. The data output at times t4 to t5 is non-order matching data because the order management number is 0 and the order matching signal OE is not input.

  The output process of the FIFO circuit A202 from time t4 to t5 is performed when the FIFO data control management unit 224 that has acquired the output request signal TR_A from the outside outputs the output valid signal RE_A to the FIFO circuit A202 based on the status signal E_A. The The address of the data output from the FIFO circuit A202 is specified as follows. The FIFO address control unit 211 that has acquired the output valid signal RE_A outputs address information (in this case, address (0)) to which the data output from the FIFO circuit A202 is input to the FIFO circuit A202 as the output address signal RP_A. The FIFO circuit A202 outputs the data input to the address corresponding to the output address signal RP_A.

  Reference is now made to FIG. FIG. 12 shows the state of each FIFO circuit when the time elapses from time t5 and reaches time t6. Specifically, FIG. 12 shows a state in which the data input to the address (0) of the FIFO circuit B203 is output at times t5 to t6. This output data is also out-of-order matching data, similar to the data output at times t4 to t5.

  At time t5, the next data output from the FIFO circuit A202 is the data at the address (1), and the next data output from the FIFO circuit B203 is the data at the address (0). The order management number of the data of the address (1) of the FIFO circuit A202 and the data of the address (0) of the FIFO circuit B203 is the same “0”, but the data of the address (1) of the FIFO circuit A202 has an order matching signal. OE is input. That is, the data of the address (1) of the FIFO circuit A202 is the first unit data of the order matching data. In this case, the FIFO data control management unit 224 performs control so that the data of the FIFO circuit to which the output order matching signal is not output, that is, the data of the FIFO circuit B 203 is output first. In FIG. 12, the data input to the address (0) of the FIFO circuit B203 is output by the above control.

  Reference is now made to FIG. FIG. 13 shows the state of each FIFO circuit when the time elapses from time t6 and reaches time t7. Specifically, FIG. 13 shows a state in which the data input to the address (1) of the FIFO circuit A202 is output from time t6 to t7. This output data is order matching data.

  At time t6, the next data output from the FIFO circuit A202 is the data at the address (1), and the next data output from the FIFO circuit B203 is the data at the address (1). The order management number of the data at the address (1) of the FIFO circuit A202 is “0”, and the order management number of the data at the address (0) of the FIFO circuit B203 is “1”. In this case, the FIFO data control management unit 224 can output data only from the FIFO circuit having a small output order management number, that is, the FIFO circuit A202. In FIG. 13, the data input to the address (1) of the FIFO circuit A202 is output by the above control.

  Reference is now made to FIG. FIG. 14 shows the state of each FIFO circuit when the time elapses from time t7 and reaches time t8. Specifically, FIG. 14 shows a state in which data input to the address (2) of the FIFO circuit A202 and the address (1) of the FIFO circuit B203 is output from time t7 to t8. All of the output data is order matching data.

  At time t7, the next data output from the FIFO circuit A202 is the data at the address (2), and the next data output from the FIFO circuit B203 is the data at the address (1). In this case, the output order management number of all the data is “1”, and the output order matching signal is not output. In the above case, the FIFO data control management unit 224 determines which data is output first depending on whether or not the output request signal TR_A, the output request signal TR_B, the state signal E_A, and the state signal E_B are output. In FIG. 14, the data input to the address (2) of the FIFO circuit A202 and the address (1) of the FIFO circuit B203 are output by the above control.

  Reference is now made to FIG. FIG. 15 shows the state of each FIFO circuit when the time elapses from time t8 and reaches time t9. Specifically, FIG. 15 shows a state in which the data input to the address (2) of the FIFO circuit B203 is output from time t8 to t9. This output data is the last unit data of the order matching data.

  From time t8 to time t9, the FIFO data control management unit 224 enables data output only for the FIFO circuit having a small output order management number as in the case of time t6 to time t7. That is, from time t8 to t9, only the data of the address (2) of the FIFO circuit B203 is output under the control of the FIFO data control management unit 224.

  Reference is now made to FIG. FIG. 16 shows the state of each FIFO circuit when the time elapses from time t9 and reaches time t10. Specifically, FIG. 16 shows a state in which the data input to the address (3) of the FIFO circuit A202 is output from time t9 to time t10. This output data is non-order consistent data.

  From time t9 to t10, the FIFO data control manager 224 determines which one of the output request signal TR_A, the output request signal TR_B, the state signal E_A, and the state signal E_B is output, as in the case of time t7 to t8. Whether to output the data first. In FIG. 16, the status signal E_A and the status signal E_B are output (because both the FIFO circuit A 202 and the FIFO circuit B 203 can output data), and the FIFO data control management unit 224 operates between times t7 and t8. In response to acquiring only the output request signal TR_A, the data input to the address (3) of the FIFO circuit A202 is output.

  In addition, after time t10, since there is no input data to the FIFO circuit A202, the status signal E_A is not output. Therefore, when the FIFO data control management unit 224 acquires the output request signal TR_B, the FIFO data control management unit 224 appropriately controls the data output order of the FIFO circuit B203.

  Examples of operation timing related to data input of the FIFO circuits A202 and B203 in FIGS. 11 to 16 are shown in FIGS. FIG. 17 shows an output request signal TR_A, an output valid signal RE_A (output request acceptance notification TA_A), an output order matching signal TO_A, an output timing of the output order matching signal TO_B, an output address number A associated with each signal, an output management number A, and The updateable management number TC is updated. The output address number A refers to an address number that can be output by the FIFO circuit A202, which is information included in the output address signal RP_A. The output management number A is an order management number of an address that can be output by the FIFO circuit A202, which is information included in the output order management signal TON_A. The output address number A, the output management number A, and the output possible management number TC are indicated by the numbers of the output address signal RP_A and the output order management signals TON_A and TC in FIG. 17 and 18 also show time information of times t4 to t10.

  FIG. 18 shows an output request signal TR_B, an output valid signal RE_B (output request acceptance notification TA_B), an output order matching signal TO_A, an output timing of the output order matching signal TO_B, an output address number B associated with each signal, an output management number B, and The updateable management number TC is updated. The output address number B and the output management number B are the same numbers as the output address number A and the output management number A, and description thereof is omitted.

  17 and 18 (state shown in FIG. 11), only the output request signal TR_A is output as an output request to the FIFO data control management unit 224. Based on this, the FIFO data control management unit 224 outputs an output valid signal RE_A to the FIFO circuit A 202 and the FIFO circuit A data information management unit 222 and outputs an output request acceptance notification TA_A to the outside. The FIFO circuit A data information management unit 222 that has acquired the output valid signal RE_A sets the address (0) of the FIFO circuit A 202 with the data to be output as the output address number A. The FIFO circuit A data information management unit 222 outputs information including the output address number A to the FIFO circuit A 202 as the output address signal RP_A. Through the above processing, the FIFO circuit A202 outputs the data input at the address (0). Further, the FIFO circuit A data information management unit 222 updates the data information of the FIFO circuit A202 based on the output valid signal RE_A and the output address signal RP_A. The above is the state of the FIFO circuits A202 and B203 from time t4 to t5.

  17 and 18, the output request signal TR_A and the output request signal TR_B are output from the outside for the output request to the FIFO data control management unit 224 at the time t5 to t6 (state shown in FIG. 12). Based on this, the FIFO data control management unit 224 determines which data is output first, the data input to the address (1) of the FIFO circuit A202 and the data input to the address (0) of the FIFO circuit B203. judge.

  Here, the output management number (order management number) of the data of the address (1) of the FIFO circuit A202 and the data of the address (0) of the FIFO circuit B203 is the same “0”, but the address (1) of the FIFO circuit A202. ) Is input with an order matching signal OE. That is, the output order matching signal TO_A is output from the FIFO circuit A data information management unit 222. In this case, the FIFO data control management unit 224 performs control so that the data for which the output order matching signal is not output, that is, the data of the FIFO circuit B 203 is output first. In FIG. 12, the data input to the address (0) of the FIFO circuit B203 is output by the above control. Further, the FIFO circuit B data information management unit 223 updates the data information of the FIFO circuit B 203 based on the output valid signal RE_B and the output address signal RP_B. Thereafter, the FIFO circuit A data information management unit 222 and the FIFO circuit B data information management unit 223 similarly update the data information. (The description of the update process in the following is omitted.) The above is the state of the FIFO circuits A202 and B203 at times t5 to t6.

  17 and 18 (state shown in FIG. 13), an output request signal TR_A and an output request signal TR_B are output from the outside as an output request to the FIFO data control management unit 224. Based on this, the FIFO data control management unit 224 determines which data is output first, the data input to the address (1) of the FIFO circuit A202 and the data input to the address (1) of the FIFO circuit B203. judge.

  Here, the output management number A of the data of the address (1) of the FIFO circuit A202 is “0”, and the output management number B of the data of the address (1) of the FIFO circuit B203 is “1”. In this case, the output enable management number TC is “0”, and the FIFO data control management unit 224 determines that the data of the FIFO circuit A 202 whose output management number is equal to or less than the output enable management number TC can be output. (Alternatively, it may be said that the FIFO data control management unit 224 compares the output management number A and the output management number B and determines that the FIFO circuit corresponding to the smaller value can be output. This is because when the values of the management number A and the output management number B are different, the output possible management number TC becomes the same value as the value of the smaller output management number.) From here, the FIFO data control management unit 224 Control is performed so that the data with the smaller output management number, that is, the data of the FIFO circuit A 202 is output first. In FIG. 12, the data input to the address (1) of the FIFO circuit A202 is output by the above control. Further, since the order matching signal is not input to the data input to the FIFO circuit A 202 address (2), the FIFO circuit A data information management unit 222 outputs the output order matching signal TO_A after the next clock. Not performed. Therefore, at the next clock, the FIFO data control management unit 224 counts up the output management number TC from “0” to “1”. The above is the state of the FIFO circuits A202 and B203 from time t6 to time t7.

  17 and 18 (state shown in FIG. 14), an output request signal TR_A and an output request signal TR_B are output from the outside as an output request to the FIFO data control management unit 224. Based on this, the FIFO data control management unit 224 controls to output both the data input to the address (2) of the FIFO circuit A202 and the data input to the address (1) of the FIFO circuit B203. In this case, since both the output management numbers A and B are the same “1” value as the output possible number, the FIFO data control management unit 224 determines that both the data of the FIFO circuits A 202 and B 203 can be output. ing. (The outputable management number TC is “1”, and the values of the output management numbers A and B are both values less than or equal to the outputable management number TC.) The above is the description of the FIFO circuits A202 and B203 at times t7 to t8. State.

  17 and 18 (state shown in FIG. 15), the output request signal TR_A and the output request signal TR_B are output from the outside for the output request to the FIFO data control management unit 224. Based on this, the FIFO data control management unit 224 has the output management number A of “2”, the output management number B of “1”, and the outputable management number TC of “1”, so that the address (2) of the FIFO circuit B 203 It is determined that the data can be output. Details of the determination are as described above. The FIFO data control management unit 224 controls to output the data input to the address (2) of the FIFO circuit B203. At the next clock, the FIFO data control management unit 224 counts up the output possible management number TC from “1” to “2” as described above. The above is the state of the FIFO circuits A202 and B203 from time t8 to t9.

  17 and 18 (state shown in FIG. 16), only the output request signal TR_A is output from the outside as an output request to the FIFO data control management unit 224. Based on this, the FIFO data control management unit 224 controls to output the data input to the address (3) of the FIFO circuit A202. The above is the state of the FIFO circuits A202 and B203 from time t9 to t10.

  In summary, in the output control circuit 200 of the present embodiment, the data analysis unit 201 determines whether or not the input data RD is order matching data. When the input data RD is out-of-order matching data, the FIFO circuits A202 and B203 connected in parallel output the input data RD independently of each other. However, when the input data RD is order matching data, the order management number generation unit 221 generates a management number indicating the order of data input between the FIFO circuits A202 and B203 based on the order matching signal OE output from the data analysis unit 201. Are generated as an order management number and output to the FIFO circuit A data information management unit 222 and the FIFO circuit B data information management unit 223. Under the control of the FIFO data control management unit 224 based on this order management number, the output control circuit 200 matches the output order by providing an order relationship between the data output from the FIFO circuits A202 and B203.

  Further, when the output of the order matching data is completed, the FIFO data control management unit 224 performs control based on only the selection signal with respect to data output, and does not perform control based on the order matching signal OE and the order management number. That is, the FIFO circuits A202 and B203 do not output data based on the order of data input between both circuits. Both circuits can independently output the input data RD according to the input order of the data input to each circuit.

  In general, an output control circuit including a plurality of FIFO circuits can be controlled to output data using a different FIFO circuit depending on the data contents when outputting data. However, when the input data is order matching data used for system setting, the data output before the system setting needs to be output before the data output after the system setting. In that case, when data is output by a plurality of FIFO circuits, it is necessary to output the data in the order of data input across the plurality of FIFO circuits. There has been no output control circuit for controlling the output order in accordance with the data input order between the plurality of FIFO circuits.

  According to this embodiment, it is possible to provide an output control circuit capable of processing order matching data by a plurality of FIFO circuits. The first effect of the output control circuit 200 according to the present embodiment is that the output efficiency of the order matching data is improved because the order matching data can be processed by a plurality of FIFO circuits. The second effect is that, when a plurality of FIFO circuits normally operating independently acquire order matching data, data output control associated with the plurality of FIFOs can be performed. The third effect is that since the FIFO circuit control unit can control all the FIFO circuits, the physical circuit amount is reduced compared to the output control circuit in which each of the FIFO circuits includes the control unit. It can be done. Thereby, for example, in a computer provided with the output control circuit 200, there is a possibility that buffer circuits can be reduced.

Embodiment 3
The third embodiment of the present invention will be described below with reference to the drawings. FIG. 19 is a block diagram showing an example of the overall configuration of the output control circuit 300 when four FIFO circuits are connected in parallel. The output control circuit 300 includes a data analysis unit 301, a FIFO circuit A302, a FIFO circuit B303, a FIFO circuit C304, and a FIFO circuit D305.

  The FIFO circuits A302 to D305 operate as normal FIFO circuits independently when the input data RD is out-of-order matching data. When the input data RD is order matching data, the data analysis unit 301 outputs the order matching signal OE to the FIFO circuit control unit 306. The FIFO circuit control unit 306 controls the output order of the FIFO circuits A302 to D305 by creating an order management number based on the acquired order matching signal OE. Specifically, the order matching data output in combination by the FIFO circuits A302 to D305 is output after the non-order matching data input before the order matching data, and is input after the order matching data. The control is such that it is output before the unordered data. Since the detailed description of the processing of the output control circuit 300 is the same as that of the second embodiment, the description thereof is omitted.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, in the second embodiment, the order management number may be counted down instead of being counted up based on the order matching signal OE. The data analysis unit 201 may be included in the FIFO circuit control unit 210.

  When the FIFO data control management unit 224 acquires the order matching signal, it counts up the order management number with the next clock. However, the FIFO data control management unit 224 may count up the order management number with the clock when the order matching signal OE is acquired. Alternatively, the order management number may be counted up so that the same order management number is associated with all the data in the order matching data and the non-order matching data.

DESCRIPTION OF SYMBOLS 100 Output control circuit 101 Data analysis part 102 FIFO circuit 103 FIFO circuit 104 Control part 200 Output control circuit 201 Data analysis part 202 FIFO circuit A
203 FIFO circuit B
210 circuit control unit 211 FIFO address control unit 220 FIFO output order control unit 221 sequence management number generation unit 222 FIFO circuit A data information management unit 223 FIFO circuit B data information management unit 224 FIFO data control management unit 300 output control circuit 301 data analysis Part 302 FIFO circuit A
303 FIFO circuit B
304 FIFO circuit C
305 FIFO circuit D
306 FIFO circuit controller

Claims (8)

A data analysis unit that generates identification information for identifying the order-matched data when the order-matched data is input among the two types of data of the order-matched data and the non-order-matched data;
First and second FIFO circuits to which different order matching data are allocated;
When the input data is order-aligned data, based on the identification information, the order-aligned data is output after the non-order-aligned data input before the order-aligned data, and the order-aligned data A control unit that controls the first and second FIFO circuits to be output before the non-order matched data input later than
An output control circuit comprising: The data analysis unit outputs an order matching signal indicating the first and last data of the order matching data to the control unit as the identification information,
The control unit controls output of the order matching data based on the order matching signal.
The output control circuit according to claim 1. The control unit generates an order management number capable of discriminating between order matching data and non-order matching data based on the order matching signal, and the first and second FIFO circuits generate the order management number. Control the output of ordered data by associating with the acquired data.
The output control circuit according to claim 2. The sequence management number is counted up based on the sequence matching signal.
The output control circuit according to claim 3. The control unit, when acquiring a data output request from the outside, compares the values of the order management numbers, and controls to output the data having a small value of the order management number first,
The output control circuit according to claim 4. The control unit outputs the same type of data as the data output immediately before when the first and second FIFO circuits have different types of data to be output next and the order management numbers are the same. To control,
The output control circuit according to claim 5. A first step of detecting whether the input data is ordered data or non-ordered data;
A second step of generating identification information for identifying the order matching data and allocating different order matching data to the first and second FIFO circuits when the input data is order matching data;
Based on the identification information, the order matching data is output after the non-order matching data input before the order matching data, and the non-order matching data input after the order matching data. A third step of controlling the first and second FIFO circuits to be output before;
A method for controlling an output control circuit comprising: A first process for detecting whether the input data is ordered data or non-ordered data;
A second process of generating identification information for identifying the ordered data and allocating different ordered data to the first and second FIFO circuits when the input data is ordered data;
Based on the identification information, the order matching data is output after the non-order matching data input before the order matching data, and the non-order matching data input after the order matching data. A third process for controlling the first and second FIFO circuits to be output before;
Is a control program that causes the output control circuit to execute.

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