JP5244509B2 - Gated clock cell and scan test control circuit - Google Patents

Description

  The present invention relates to a scan test control circuit for a scan test of a memory such as an embedded LSI, and more particularly to a gated clock cell included in the scan test control circuit.

  Scan tests are regularly used in the actual design of memory circuits. In a typical scan test, operation is confirmed by scanning all elements constituting the memory circuit, such as flip-flops and master = slave latches. In recent years, an LSI circuit designer designs in advance a scan test control circuit for performing a scan test in a design and manufacturing process, and the scan test control circuit is mounted on the LSI as a part of the function of the LSI.

  In the scan test, an operation clock different from that in actual use is used. Further, there are often cases where it is necessary to divide the scan process into predetermined processes and to execute the scan test because of process convenience or a request for adjustment of load capacity. For this reason, a gated clock circuit for supplying a test clock to each memory element for each clock tree is practically essential for all test circuits.

  Examples of conventional techniques include those disclosed in ITC01 An Analysis of Power Reduction Techniques in Scan Testing (Non-patent Document 1). This adds a scan chain clock supply decoder to each clock tree, and stops the clock supply of a predetermined clock tree when testing each clock tree. Here, the scan chain refers to a test execution unit when performing a scan test.

  Japanese Patent Laying-Open No. 2006-84314 (Patent Document 1) discloses a technique for stopping clock supply to a hard macro that is not a target of a scan test during a scan test.

  In Japanese Patent Laid-Open No. 5-264664 (Patent Document 2), the function of the setting register is stopped for each function in the boundary scan circuit.

In this way, the circuit is divided and designed based on the execution of the scan test. In particular, the circuit is divided for each clock tree and the test is performed to achieve low power consumption.
JP 2006-84314 A JP-A-5-264664 ITC01 An Analysis of Power Reduction Techniques in Scan Testing

  However, the technique disclosed in the above document has a problem.

  In the invention described in Non-Patent Document 1, the clock supply of the clock chain is limited by the decoder. However, in many cases, a gated clock circuit is already included in the clock signal in order to reduce power consumption. When a decoder for a scan test is added in addition to normal clock control, there is a problem that the clock latency increases.

  The method described in Patent Document 1 aims at not performing a general-purpose hard macro inspection, and does not have a positive effect on a scan test for other memories.

  Patent Document 2 specializes in boundary scan, and cannot be used in general in a scan test for a memory.

  An object of the present invention is to provide means for avoiding an increase in test power and a prolonged test period by partially stopping an operation clock during a scan in which the clock cannot be stopped in general. is there.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A gated clock cell with a scan power control terminal according to a representative embodiment of the present invention receives a clock enable signal, a scan mode signal, a scan power control signal, and an operation clock. Even if any one of the scan mode signals is “1”, if the scan power control signal is “0”, the input operation clock is not output.

  Another gated clock cell with a scan power control terminal according to a representative embodiment of the present invention includes a latch, a first AND gate, and a second AND gate, and an operation clock and a scan power control signal are input thereto. The second AND gate takes the logical product of the latch output and the scan power control signal, and the first AND gate takes the logical product of the output of the second AND gate and the operation clock and outputs the logical product.

  Another gated clock cell with a scan power control terminal according to a representative embodiment of the present invention includes a latch, a first AND gate, and a second AND gate, and an operation clock and a scan power control signal are input thereto. The second AND gate takes the logical product of the scan power control signal and other signals, the latch latches the output of the second AND gate with the inverted signal of the operation clock, and the first AND gate takes the logical product of the output of the latch and the operation clock. It is characterized by taking.

  Another gated clock cell with a scan power control terminal according to an exemplary embodiment of the present invention includes a latch, a first AND gate, and a second AND gate, and includes a clock enable signal, a scan mode signal, and an operation. The clock and scan power control signal are input, the latch latches the clock enable signal with the inverted signal of the operation clock, and the second AND gate takes the logical product of the output of the latch and the scan mode signal and the scan power control signal. The first AND gate outputs the logical product of the output of the second AND gate and the operation clock.

  A scan test control circuit according to a representative embodiment of the present invention includes a gated cell with a first scan power control terminal using the above-described gated clock cell with a scan power control terminal, and a gated with the above scan power control terminal. A gated cell with a second scan power control terminal using a clock cell, and the gated cell with the first scan power control terminal operates only on the first scan chain that is part of the flip-flop group to be tested The gated cell with the second scan power control terminal supplies a clock, and supplies an operation clock only to the second scan chain which is another part of the flip-flop group to be inspected.

  An RTL level design method of a scan test control circuit according to a representative embodiment of the present invention is directed to a scan test control circuit including a gated clock cell with two or more scan power control terminals and a scan power control circuit. A gated clock logic estimation step that estimates gated clock logic without a power control terminal and places it on the clock tree, a gated clock cell logic analysis step that analyzes gated clock cell logic with a scan power control terminal, and a gated clock logic estimation step The gated clock logic insertion step in which the gated clock logic without the scan power control terminal estimated in step 1 is replaced with the gated clock cell logic with the scan power control terminal estimated in the gated clock cell logic analysis step. And a gated clock tree analysis step that re-evaluates the configuration of the clock tree replaced with gated clock cell logic with a scan power control terminal, a resolution number determination step that determines the required resolution number, and a resolution number determination step. A scan power control circuit insertion step for inserting the scan power control circuit with a high resolution, and information on flip-flops connected to each clock tree connected to a gated clock cell having two or more scan power control terminals. Including a flip-flop grouping step for performing the processing, and a scan chain configuration step for assembling a scan chain based on a result of the gated clock tree analysis step and a result of the flip-flop grouping step. .

  The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

  In the scan test control circuit according to the representative embodiment of the present invention, in general, when the clock cannot be stopped, the operation clock is partially stopped to increase the test power and to extend the test period. Can be avoided. These can be realized by performing a scan test without dividing the test.

  Hereinafter, the present invention will be described with reference to the drawings.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described.

  FIG. 1 is a configuration diagram of a gated clock cell 1000 with a scan power control terminal according to the present embodiment, and FIG. 2 is a configuration diagram of a gated clock cell 1100 with a scan power control terminal according to a modification. On the other hand, FIG. 3 is a configuration diagram of a conventional gated clock cell 2000.

  First, a conventional example will be described with reference to FIG.

  A conventional gated clock cell 2000 has an SMC terminal 2001, a CEN terminal 2002, and a CLK terminal 2003 as input terminals. In addition, a GCLK terminal 2011 is provided as an output terminal. The gated clock cell 2000 includes an OR gate 2021, a latch 2022, and a first AND gate 2023.

SMC terminal 2001 is a scan mode control (S can M ode C ontrol) terminal to enable all clocks in scan test. A signal input to the SMC terminal is referred to as a scan mode signal.

CEN terminal 2002 is a clock enable (C lock EN able) terminal for controlling the enabling and disabling of the clock signal input from the CLK terminal 2003. The gated clock cell 2000 does not accept the input of the CLK terminal 2003 when the CEN terminal 2002 is “0”, and accepts the input of the CLK terminal 2003 when the CEN terminal 2002 is “1”. In other words, when the CEN terminal 2002 is “1”, the input of the CLK terminal 2003 is directly output from the GCLK terminal 2011. The signal input to the CEN terminal 2002 is referred to as a clock enable signal.

  A CLK terminal 2003 is a terminal to which an operation clock signal is input.

  The OR gate 2021 is a logic gate that takes the logical sum of the input signal of the SMC terminal 2001 and the input signal of the CEN terminal 2002. That is, if any one of the SMC terminal 2001 and the CEN terminal 2002 is “1”, “1” is input to the data terminal of the latch 2022.

  A latch 2022 is a latch circuit that holds an input of a data terminal. As described above, the logical sum of the input signal of the SMC terminal 2001 and the input signal of the CEN terminal 2002 is input to the input terminal of the latch 2022. On the other hand, an inverted signal of the clock signal is input as the latch timing. That is, the output of the latch 2022 is determined earlier than the first AND gate 2023 by a half clock signal.

  The first AND gate 2023 is a logic gate that takes the logical product of the output of the latch 2022 and the clock signal from the CLK terminal 2003. That is, if the output of the latch 2022 is “1”, it is input from the CLK terminal.

  With this configuration, if either the SMC terminal 2001 or the CEN terminal 2002 is “1”, the clock signal input to the CLK terminal 2003 is output from the GCLK terminal 2011. On the other hand, if both the SMC terminal 2001 and the CEN terminal 2002 are “0”, no output is made from the GCLK terminal 2011.

  Next, the gated clock cell 1000 with a scan power control terminal according to the present invention will be described.

  A gated clock cell 1000 according to the present invention has an SPC terminal 1004 in addition to an SMC terminal 1001, a CEN terminal 1002, and a CLK terminal 1003. In addition to the OR gate 1021, the latch 1022, and the first AND gate 1023, a second AND gate 1024 is provided.

SPC (S can P ower C ontrol ) terminal 1004 is a terminal that can control the enabling and disabling of the clock signal for each gated clock cell in scan test. That is, the SMC terminal 2001 is a terminal for determining the operation mode, and when there are a plurality of gated clock cells, all the gated clock cells need to have the same value. On the other hand, in the present invention, the operation of the SPC terminal 1004 coexisting with the SMC terminal 1001 can be controlled for each gated clock cell. As a result, the test can be performed continuously without interruption. A signal input to the SPC terminal 1004 is referred to as a scan power control signal.

  The second AND gate 1024 is disposed between the OR gate 1021 and the latch 1022. The second AND gate 1024 is a logic gate that takes the logical product of the output of the OR gate 1021 and the input of the SPC terminal 1004. In other words, if the SPC terminal is “0”, it is possible to stop supplying the clock to the clock tree under the gated clock cell 1000.

  Note that a gated clock cell 1100 with a scan power control terminal shown in FIG. 2 is a modified example that exhibits substantially the same function as the gated clock cell 1000 with a scan power control terminal. In this example, the second AND gate 1024 ANDs the output of the latch 1022 and the input from the SPC terminal 1004. Even in this form, the same operation as the gated clock cell 1000 with the scan power control terminal is possible.

  Thus, by preparing an SPC terminal separately from the SMC terminal in the gated clock cell and inputting “0” into the SPC terminal, the GCLK output from each gated clock cell is controlled separately from the mode of the entire scan test control circuit. Make it possible.

  Next, still another embodiment of the first embodiment of the present invention will be described.

  Next, a case where the present invention is applied to another type of gated clock cell will be described.

  FIG. 4 is a configuration diagram of another gated clock cell 1200 with a scan power control terminal according to the present embodiment, while FIG. 5 is a configuration diagram of another conventional gated clock cell 2200.

  As can be seen from FIG. 5, unlike the gated clock cell 2000, the original gated clock cell 2200 has an OR gate 2221 inserted on the output side of the latch 2022. That is, only the input signal from the CEN terminal 2002 is set as the target of setting of the latch 2022, and the mode control by the SMC terminal 2001 is performed on the output side.

  FIG. 4 is a configuration diagram of a gated clock cell 1200 with a scan power control terminal to which this embodiment is applied in contrast to this embodiment. The insertion positions of the OR gate 1221 and the second AND gate 1224 are different due to the difference in the configuration of the basic gated clock cell.

  That is, the second AND gate 1224 is inserted on the output side of the OR gate 1221. Then, the logical product of the input from the SPC terminal 1004 and the output of the OR gate 1221 is obtained. Thereby, the function equivalent to the gated clock cell 1000 with a scanning power control terminal can be secured.

(Second Embodiment)
Next, a second embodiment of the present invention will be described.

  In the first embodiment, the gated clock cell with individual scan power control terminals has been described. In the second embodiment, a description will be given of how the scan test control circuit is configured using the gated clock cell with the scan power control terminal described in the first embodiment.

  FIG. 6 is a diagram showing a configuration of a scan test control circuit according to the present embodiment. On the other hand, FIG. 7 shows a scan test control circuit using a conventional gated clock cell.

  First, a conventional scan test control circuit will be described with reference to FIG.

  In the configuration of this scan test control circuit, seven gated clock cells A, B, A1, A2, A3, B1, and B2 constitute the main part.

  The gated clock cells A and B are gated clock cells that receive the scan mode signal from the SMC_MODE terminal 3004 and the operation clock from the clock generation circuit 4001 and output GCLK as the operation clock signal of the scan clock tree. The gated clock cell used here is shown in FIG. 3 or FIG.

  The gated clock cells A1, A2, A3, B1, and B2 are gated clock circuits that supply an operation clock to each scan clock tree. A plurality of flip-flops exist under these gated clock cells, and an output of the GCLK terminal 2011, that is, an operation clock is output to them. A group of flip-flops that receive the operation clock from one gated clock cell is called a clock tree. The gated clock cell used here is also shown in FIG. 3 or FIG.

  The SMC_MODE terminal 3004 receives “0” and “1” values. “0” represents a user operation time of a circuit including the scan test control circuit, and “1” represents a scan test operation.

  An SMC_Mode signal is connected to the SMC terminal 2001 of each gated clock cell. In the SMC_Mode signal, “0” represents a user operation, that is, a non-scan test time, and “1” represents a scan test time. Therefore, it is necessary to set the SMC_Mode signal input from SMC_MODE to 1 during the scan test.

  A clock generation circuit 4001 is a circuit that generates an operation clock for a scan test. How the clock generation circuit 4001 generates an operation clock for a scan test is a design matter and will not be described here.

  The clock generation circuit 4001 outputs an operation clock generated for the gated clock cell A and the gated clock cell B. The GCLK terminal 2011 of the gated clock cell A is connected to the CLK terminals 2003 of the gated clock cells A1, A2, and A3. Similarly, the GCLK terminal of the gated clock cell B is connected to the CLK terminal 2003 of the gated clock cells B1 and B2.

  The GCLK terminals 2011 of the gated clock cells A1, A2, A3, B1, and B2 are connected to the CLK terminals of the flip-flops to be inspected that are in charge of the respective gated clock cells, and the operation clock for the scan test is supplied.

  The gated clock cell control circuit 4002 is a circuit that determines whether the operation clock output from the clock generation circuit 4001 is valid via the CEN terminal 2002 of each gated clock cell.

  The gated clock cell control circuit 4002 has a plurality of output terminals. CEN_CNTA is an output terminal for determining whether to enable the input of the CLK terminal of the gated clock cell A, and CEN_CNTB is the gate terminal of the gated clock cell B. On the other hand, CEN_CNTA [0: 2] is an output terminal that determines whether gated clock cells A1, A2, and A3 are valid, and CEN_CNTB [0: 1] is whether or not gated clock cells B1 and B2 are valid.

  That is, an output from the gated clock cell control circuit 4002 is prepared for each CEN terminal 2002 of all gated clock cells.

  In this way, the control signal from the gated clock cell control circuit is supplied to the CEN terminal 2002 of all gated clock cells. Conventionally, a scan tree is configured in consideration of the operation of a clock (CLOCK of the clock generation circuit 4001) supplied simultaneously to all flip-flops used in the scan shift operation. For this reason, flip-flops belonging to the scan chain are arranged across the scan tree without distinction. That is, when verifying the scan chain input from SIN_1 and output from SOUT_1, in FIG. 7, since the scan chain passes through all the scan trees, it is necessary to keep all the scan trees in operation during the scan test period. It was.

  On the other hand, the scan test control circuit 3000 according to the present embodiment is configured using the gated clock cell with the scan power control terminal with the SPC terminal shown in FIG. 1, FIG. 2, and FIG. The scan test control circuit 3000 is significantly different from the scan test control circuit 4000 in the presence of the scan power control circuit 3003.

  The gated clock cell a with a scan power control terminal a outputs the output of the GCLK terminal 1011 to the CLK terminal 1003 of the gated clock cells a1, a2, and a3 with subordinate scan power control terminals, like the gated clock cell A of FIG. Further, the gated clock cell b with the scan power control terminal outputs the output of the GCLK terminal 1011 to the CLK terminal 1003 of the gated clock cells b1 and b2 with the subordinate scan power control terminal.

  An operation clock for scan test from the clock generation circuit 3001 is supplied to the CLK terminal 1003 of the gated clock cells a and b with the scan power control terminal. The clock generation circuit 3001 may have the same configuration as the clock generation circuit 4001.

  The gated clock cell control circuit 3002 is a circuit that determines whether the operation clock output from the clock generation circuit 3001 is valid via the CEN terminal 1002 of each gated clock cell. This may be the same circuit as the gated clock cell control circuit 4002.

  In this embodiment, not only the CEN terminal 1002 but also the SPC terminal 1004 is controlled. Accordingly, the processing of the SPC terminal 1004 in the gated clock is also different accordingly.

  The scan test control circuit of FIG. 6 operates by dividing the gated clock cells a1, a2, and a3 with scan power control terminals under the gated clock cell a with scan power control terminals. Therefore, the output from the scan power control circuit 3003 is connected not only to the gated clock cell a with the scan power control terminal but also to the SPC terminals 1004 of the gated clock cells a1, a2, and a3 with the scan power control terminal.

  On the other hand, it is assumed that the gated clock cell b with the scan power control terminal simultaneously operates the subordinate gated clock cells b1 and b2 with the scan power control terminal. Accordingly, the output from the scan power control circuit 3003 is supplied to the SPC terminal 1004 of the gated clock cell b with the scan power control terminal, but the voltage is applied to the SPC terminal 1004 of the gated clock cells b1 and b2 with the scan power control terminal. It becomes a fixed state.

  The scan power control circuit 3003 is a decoder circuit that specifies a scan test execution target via the SPC terminal 1004 of the gated clock cell with the scan power control terminal.

  The scan power control circuit 3003 has a PC_SIN terminal and a PC_update terminal as input terminals. The scan power control circuit 3003 of this embodiment includes a 4-bit internal flip-flop group 3033. The number of flip-flops determines the resolution of the scan power control circuit 3003 and the scan test control circuit 3000. In addition, a scan power control circuit dedicated scan chain 3043 for performing a scan test of the internal flip-flop group 3033 is included.

  The internal flip-flop group 3033 is composed of a number of flip-flops necessary for ensuring the assumed resolution. Depending on ON / OFF of this flip-flop, which of the gated clock cells with the scan power control terminal is to be subjected to the scan test is determined. A PC_update terminal 3023 for initialization is connected to each flip-flop belonging to the internal flip-flop group 3033, thereby initializing each flip-flop.

  The operation of the internal flip-flop group 3033 also needs to be a scan test target. A flip-flop group for performing a scan test of the internal flip-flop group 3033 is a scan chain 3043 dedicated to the scan power control circuit, and an input terminal for this is a PC_SIN terminal 3013 and an output terminal is PC_SOUT 3053. When the test for the scan chain 3043 dedicated to the scan power control circuit is completed, the internal flip-flop group 3033 is controlled using this.

  A value set in each flip-flop of the internal flip-flop group 3033 is transmitted to the corresponding gated clock cell with a scan power control terminal, and determines whether the operation of the cell is possible. In order to supply the operation clock to the CLK terminal 1003, when operating the gated clock cells a1, a2, a3 with the scan power control terminal, it is necessary to simultaneously set the gated clock cell a with the scan power control terminal to “1”. is there. Accordingly, the scan power control circuit 3003 includes an OR gate 3103 that takes the logical sum of the outputs of the flip-flops corresponding to the gated clock cells a1, a2, and a3 with these scan power control terminals, and the output of the OR gate 3103 is scanned. It is output to the SPC terminal 1004 of the gated clock cell a with a power control terminal.

  A PC_SIN terminal 3013 is a terminal for inputting an input signal of the scan chain 3043 dedicated to the scan power control circuit. On the other hand, the PC_SOUT terminal 3053 is a terminal for outputting an operation result at the time of a scan test of the scan chain 3043 dedicated to the scan power control circuit.

  Unlike the scan chain of the scan test control circuit shown in FIG. 7, the scan chain of the flip-flop to be inspected by the scan test control circuit is arranged in a form that is unevenly distributed in a specific scan tree.

  In this figure, the second scan chain 3062 and the third scan chain 3063 are connected to the gated clock cell a3 with scan power control terminal so that the first scan chain 3061 belongs only to the gated clock cells a1 and a2 with scan power control terminal. The fourth scan chain 3064 is arranged so as to belong to a gated clock cell b with a scan power control terminal (that is, b1 and b2).

  SIN_n (n: chain number; n = 1 in the case of the first scan chain), which is an input terminal of each scan chain, is an input terminal for inputting a predetermined input pattern during a scan test. On the other hand, SOUT_n (n: the number of the chain; n = 1 in the case of the first scan chain) confirms whether the flip-flop in the scan chain is operating normally based on the output result from here.

  The first scan chain 3061 includes 30 flip-flops, the second scan chain 3062 and the third scan chain 3063 each include 25 flip-flops, and the fourth scan chain 3064 includes 20 flip-flops.

  As already described, there are four scan chains in the scan test control circuit of FIG. This is because the resolution of the scan power control circuit 3003 is 4.

  Based on the description of the above configuration, the operation of the scan test control circuit of FIG. 6 will be described.

  In this embodiment, the level of flip-flops belonging to one scan chain is leveled according to the resolution of the scan power control circuit 3003, and the scan chain is sequentially inspected so that the scan test can be performed. The purpose is to reduce power consumption.

  Also in this figure, assuming that there are 100 flip-flops to be scanned, it is desirable to have 25 flip-flops per scan chain. It is difficult to do so in an actual circuit. Also in this drawing, the first scan chain 3061 and the fourth scan chain 3064 are biased.

  FIG. 8 is a table showing the correspondence of input signals when a scan test is performed in the present embodiment.

  When performing a scan test on the first scan chain 3061 (30 internal flip-flops), the internal flip-flop group 3033 of the scan power control circuit 3003 is set to operate the gated clock cells a1 and a2 with scan power control terminals. In addition, data is set at the input terminal SIN_1 of the first scan chain (the number of internal flip-flops 30), and the normality of the operation is confirmed by looking at the output result of SOUT_1.

  Similarly, when performing a scan test on the second scan chain 3062 (25 internal flip-flops) and when performing a scan test on the third scan chain 3063 (25 internal flip-flops), a gated clock cell with a scan power control terminal is provided. In order to operate a3, the internal flip-flop group 3033 of the scan power control circuit 3003 is set. At this time, terminals other than the input terminal for setting data (SIN_2 at the time of the second scan chain 3062 scan, SIN_3 at the time of the third scan chain 3063 scan) are fixed to “0” or “1”.

  Further, the internal flip-flop group 3033 of the scan power control circuit 3003 is set to operate the gated clock cell b with the scan power control terminal even when the fourth scan chain 3064 (the number of internal flip-flops 20) is scan-tested.

  Then, the first scan chain 3061 to the fourth scan chain 3064 are scanned in order, and the operation of the flip-flop is confirmed to inspect the memory circuit.

  Thus, in general, the operation clock is partially stopped at the time of scanning where the clock cannot be stopped. As a result, it is possible to prevent a decrease in detection rate and an increase in test time due to test division, and to avoid an increase in test power.

  Further, by leveling the number of flip-flops to be scanned, the maximum power consumption required for testing one scan chain is made substantially constant. Thereby, the power consumption in the entire scan test can be made constant, and as a result, it is possible to reduce the power during the test.

  In the scan test control circuit 3000 according to the second embodiment, the first scan chain 3061 and the fourth scan chain 3064 include the origins of two scan clock trees. The second scan chain 3062 and the third scan chain 3063 are supplied with an operation clock from the origin of the same scan clock tree.

  On the other hand, it should also be considered to draw up the scan chain with one scan clock tree origin. FIG. 9 is a logic circuit diagram of another scan test control circuit according to the second embodiment when the scan clock tree origins of FIG. 6 are collected. When taking the configuration of FIG. 9, the correspondence of the input signals when the scan test is performed is as shown in FIG.

(Third embodiment)
Next, a third embodiment of the present invention will be described.

  The present embodiment describes the above-described scan test control circuit and the accompanying scan tree and scan chain generation method.

  FIG. 11 is a flowchart showing a method for generating various information of design and scan test at the RTL (register transfer level) of the scan test control circuit according to the present embodiment. The present embodiment will be described using this.

  First, logic synthesis is performed (step S1). At this time, the following gated clock logic is estimated.

always @ (possible clk)
if (cen)
data_out <= data_in; (logic 1)
In other words, (logic 1) determines whether the cen (clock enable) signal is “1” at the timing of the clock edge when the clk signal changes from “0” to “1”. This means that the contents of data_in are set as is. This (logic 1) is close to the conventional gated clock cell shown in FIG. 3 (there is a difference depending on the presence or absence of the SMC terminal).

  The estimated gated clock logic is arranged as a module on the clock tree. At this time, it is arranged that has the origin of the clock tree, and in FIG. 6, corresponds to the gated cells a1, a2, a3, b1, and b2 with scan power control terminals.

  Next, the clock tree is analyzed (step S2). Here, clock tree analysis is performed in consideration of gated clock logic, and information on the clock start point and end point is collected.

  Subsequent to step S2, logic analysis of the gated clock is performed (step S3). At this time, the operation logic is estimated in consideration of the information of the SMC terminal and the SPC terminal which have been excluded in S1.

  Thereafter, a gated clock logic insertion process is performed in which the gated clock cell logic arranged on the clock tree is replaced with the gated clock cell with the scan power control terminal logically estimated in step S3 (step S4).

  After the gated clock logic insertion processing, the clock tree configuration is re-evaluated by gated clock tree analysis (step S5). At this time, the insertion position of the gated clock cell with the scan power control terminal is registered in the database, and the number of flip-flops to be scanned driven by each gated clock cell with the scan power control terminal is grasped.

  If the number of gated clock cells with scan power control terminals is determined, the upper limit of the required number of resolutions is also determined. The resolution number (required resolution number) of the scan power control circuit 3003 to be used as appropriate is determined from the upper limit of the resolution number (step S6). The upper limit of the number of resolutions and the actual number of resolutions of the scan power control circuit 3003 are design matters.

  The scan power control circuit 3003 is inserted in accordance with the required resolution number of the scan power control circuit 3003 (step S7).

  After that, the resolution of the scan power control circuit 3003 and the information of the flip-flops connected to the gated cell with the scan power control terminal are organized, and grouping for forming a scan chain is performed (step S8). At this point, the scan chain has not yet been formed.

  FIG. 12 shows an example of this grouping. FIG. 12 assumes that the scan test control circuit of FIG. 6 is being created. As described in the second embodiment, when the number of flip-flops is 100 and the resolution of the scan power control circuit 3003 is 4, the number of control flip-flops for each scan chain is divided so as to approach 25. In the second embodiment, 30 pieces belong to the first scan chain 3061, 25 pieces each belong to the second scan chain 3062 and the third scan chain 3063, and 20 pieces belong to the fourth scan chain 3064. It is also a result.

  In this step, the fan-out of the gated cell with the scan power control terminal is analyzed, and the gated cells a and b with the scan power control terminal may be inserted so that the branch clock source can be controlled. Whether or not to insert a gated cell with a scan power control terminal is a design matter of the designer.

  Thereafter, a scan chain is assembled based on the group information obtained in step S8 and information on each flip-flop analyzed in step S5 and the GCLK terminal of the gated cell with the scan power control terminal that drives the flip-flop (step S9). At this time, a netlist including the scanned scan chain and an SCAN-DEF file defining the scan chain configuration are output for the purpose of passing to the layout tool. The “scan chain” drawn here means a specific connection from SIN_1 to SOUT_1 in the case of the first scan chain 3061 of the second embodiment, for example.

  Refer to FIG. 6 for an image of wiring as a result of assembling the chain.

  Then, based on the scan chain information created in step S9 and the clock tree information belonging to the chain, the clock tree information whose application value is indefinite and the output expected value indefinite clock tree information are output (step S10). The information output at this time is the one shown in FIG.

  Here, the conditions for pattern generation by the layout tool are determined by the scan chain information and the clock tree information belonging thereto. For each “chain information” and “stop clock tree” information, “applied value is undefined” and “output expected value undefined” information is held as shown in FIG. By inputting this into the layout tree, it becomes control information of each flip-flop and the scan chain composed thereof.

  The layout tool reads the SCAN-DEF file output in step S9, arranges it in a group of flip-flops driven under the same gated cell with the same scan power control terminal, and changes the order of the scan flip-flops in consideration of timing constraints ( Step S11).

  Using the information shown in FIG. 13, data is input from the PC_SIN terminal 3013 of the scan test circuit of FIG. 6 to the PC_SOUT terminal 3053 chain, and the data is input to the PC_update terminal 3023, so that the internal flip-flop group 3033 and the scan power control are controlled. The flip-flop of the circuit dedicated scan chain 3043 is updated to control power.

  After this, the ATPG process will be described.

ATPG (A utomatic T est P attern G enerater) is a tool for generating test patterns when performing a scan test automatically. FIG. 14 is a flowchart showing an execution procedure in ATPG.

  The ATPG is made to read the net list of the scan test control circuit, the pattern generation constraint, the ratio of the operation flip-flops, etc. (step S21). In addition, scan information when the operation clocks of some scan chains are stopped is read (step S22).

  Clock stop information is generated from the information read so far, the test sequence of the scan chain to be scanned, etc. (step S23). This means that in the second embodiment, information on which SPC terminal 1004 of the gated cell with the scan power control terminal is set to “0” is generated.

  Next, the process moves to the generation of test patterns for individual scan chains. First, a scan chain for stopping the operation clock is selected (step S24). Then, the table of FIG. 13 is inspected for the conditions of “applied value is indefinite” and “expected output value indeterminate” in the corresponding scan chain. Step S25).

  Thereafter, faults to be detected in the scan chain are listed (step S26). This is determined by the input of the ATPG operator.

  After the determination so far, the ATPG automatically generates a pattern for inspection (step S27). At this time, the ATPG performs pattern generation by distinguishing the following four types of flip-flops based on the scan tree in which the clock is stopped.

1) Flip-flop that can input / output without the influence of clock stop:
Flip-flops in the scan chain that do not belong to the stopped clock tree 2) Flip-flops with no change in applied value:
Flip-flops in the clock tree where the operation clock supply is stopped 3) Flip-flops whose applied value becomes indefinite:
A flip-flop on the scan-out side when the scan chain includes two or more clock trees and the clock tree whose operation clock is stopped is on the scan-out side. 4) A flip-flop in which the expected output value is indefinite:
A flip-flop on the scan-in side when the scan chain includes two or more clock trees and the clock tree whose operation clock is stopped is on the scan-in side. Based on the above four pieces of information, the applied value at the time of pattern generation 2) uses the applied values of all patterns, and 3) treats it as indefinite. Further, 4) is treated as indefinite as an expected value for pattern generation.

  Repeat all of the above scan chains to stop, and the test pattern is finally completed.

  By automatically generating test patterns in this way, it is possible to save labor in design man-hours.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied to a scan test control circuit using a gated clock cell for a scan test of a memory such as a large capacity memory or an embedded LSI.

FIG. 3 is a logic circuit diagram of a gated clock cell according to the first embodiment of the present invention. FIG. 3 is a logic circuit diagram of another gated clock cell according to the first embodiment of the present invention. It is a logic circuit diagram of a conventional gated clock cell. FIG. 3 is a logic circuit diagram of another gated clock cell according to the first embodiment of the present invention. It is a logic circuit diagram of another conventional gated clock cell. It is a logic circuit diagram of the scan test control circuit concerning the 2nd Embodiment of this invention. It is a logic circuit diagram of a conventional scan test control circuit. It is a table | surface showing the correspondence of the input signal at the time of scan test implementation of the scan test control circuit concerning the 2nd Embodiment of this invention, and a stop (operation | movement) clock tree. It is a logic circuit diagram of another scan test control circuit according to the second embodiment of the present invention. 10 is a table showing correspondence between input signals and stop (operation) clock tree when a scan test of the scan test control circuit of FIG. 9 is performed. It is a flowchart showing the scan test control circuit in connection with the 3rd Embodiment of this invention, and the production | generation method of the various information of a scan test. It is drawing showing the example of the grouping in connection with the 3rd Embodiment of this invention. 12 is a table showing a correspondence between an input signal and a stop clock tree when the scan test control circuit of FIG. 11 performs a scan test. It is a flowchart showing the execution procedure in ATPG in connection with the 3rd Embodiment of this invention.

Explanation of symbols

1000, 1100, 1200
... Gated clock cell with scan power control terminal,
2000, 2100 ... gated cell,
1001 ... SMC terminal, 1002 ... CEN terminal, 1003 ... CLK terminal,
1004 ... SPC terminal, 1011 ... GCLK terminal, 1021 ... OR gate,
1022 ... Latch, 1023 ... First AND gate, 1024 ... Second AND gate,
1221 ... OR gate, 1224 ... first AND gate,
2001 ... SMC terminal, 2002 ... CEN terminal, 2003 ... CLK terminal,
2011 ... GCLK terminal, 2021 ... OR gate, 2022 ... latch,
2023 ... 1st AND gate, 2221 ... OR gate,
3001 ... Clock generation circuit, 3002 ... Gated clock cell control circuit,
3003 ... Scan power control circuit, 3013 ... PC_SIN terminal,
3023 ... PC_Update terminal, 3033 ... Internal flip-flop group,
3043 ... Scan power control circuit dedicated scan chain,
3053 ... PC_SOUT terminal,
3061 ... first scan chain, 3062 ... second scan chain,
3063 ... third scan chain, 3064 ... fourth scan chain,
3103: OR gate,
a, b, a1, a2, a3, b1, b2
... Gated clock cell with scan power control terminal.

Claims (5)

A gated clock cell with a scan power control terminal to which a clock enable signal, a scan mode signal, a scan power control signal, and an operation clock are input,
Even if one of the clock enable signal and the scan mode signal is “1”, if the scan power control signal is “0”, the input operation clock is not output. Gated clock cell with power control terminal. A gated clock cell having a scan power control terminal having a latch, a first AND gate, and a second AND gate, to which an operation clock and a scan power control signal are input;
The second AND gate takes the logical product of the output of the latch and the scan power control signal,
The gated clock cell with a scan power control terminal, wherein the first AND gate outputs a logical product of the output of the second AND gate and the operation clock. A gated clock cell having a scan power control terminal having a latch, a first AND gate, and a second AND gate, to which an operation clock and a scan power control signal are input;
The second AND gate takes a logical product with the scan power control signal and other signals,
The latch latches the output of the second AND gate with an inverted signal of the operation clock,
The gated clock cell with a scan power control terminal, wherein the first AND gate takes a logical product of the output of the latch and the operation clock. A gated clock cell with a scan power control terminal having a latch, a first AND gate, and a second AND gate, to which a clock enable signal, a scan mode signal, an operation clock and a scan power control signal are input;
The latch latches the clock enable signal with an inverted signal of the operation clock,
The second AND gate takes a logical product of the logical output of the output of the latch, the scan mode signal, and the scan power control signal,
The gated clock cell with a scan power control terminal, wherein the first AND gate outputs a logical product of the output of the second AND gate and the operation clock. The gated cell with a first scan power control terminal using the gated clock cell with a scan power control terminal according to any one of claims 1 to 4, and the scan according to any one of claims 1 to 4. A scan test control circuit including a second gated cell with a scan power control terminal using a gated clock cell with a power control terminal,
The gated cell with the first scan power control terminal supplies an operation clock only to the first scan chain that is a part of the flip-flop group to be tested, and the gated cell with the second scan power control terminal is the test target. An operation clock is supplied only to a second scan chain which is another part of the flip-flop group of the scan test control circuit.

Images