JP5239910B2 - Receiver having automatic offset calibration circuit for A / D converter - Google Patents

Description

  The present invention relates to a receiver having an automatic offset calibration circuit for an A / D converter.

  In recent years, there has been a great demand for downsizing and low power consumption of electronic devices, and the demand is also great for mobile terminals in mobile communication systems.

  FIG. 1 is a block diagram illustrating a configuration example of a radio device included in a mobile terminal. In FIG. 1, a transmission system 3 and a reception system 4 are connected to an antenna 1 via a duplexer 2, and radio signals are transmitted and received.

  In the reception system 3, the RF / IF circuit 5 down-converts the reception signal received via the antenna 1 and the duplexer 2 from a high frequency to an intermediate frequency. An automatic gain control amplifier (AGC amplifier) 6 amplifies the output signal of the RF / IF circuit 5, and the quadrature detection circuit 7 performs quadrature detection to obtain a baseband I signal and Q signal. The A / D converter 8 performs A / D conversion on the I and Q signals, which are output analog signals, and the demodulation circuit 10 in the demodulator 11 demodulates the A / D converted digital signal. An automatic gain control circuit (AGC circuit) 9 in the demodulator 11 controls the gain of the automatic gain control amplifier 6 according to the amplitude level of the output signal of the A / D converter 8, and makes the amplitude level constant.

  In response to the above demands for miniaturization and low power consumption, the receiving system 4 often has a configuration that operates with a single power source in order to reduce the number of wires and the amount of power consumption. In the receiving system 4, the received signal is reproduced as an electrical analog signal. In particular, in the receiving system 4 operating with a single power source, the center level of the received signal is offset by a predetermined level with respect to the ground. . That is, the received signal is reproduced as an analog signal having a relatively positive sign and magnitude (amplitude) with reference to the offset center level. Since the A / D converter 8 converts this analog signal, the center level of the converted digital signal is similarly offset with respect to the ground. Hereinafter, in the analog signal before A / D conversion, this center level is referred to as an analog center level, and in the digital signal after A / D conversion, it is referred to as a digital center level. In addition, the analog center level and the digital center level are substantially the same only by the difference between the analog amount and the digital amount before and after the A / D conversion.

  The A / D converter 8 in the receiving system 4 operates with a single power source. Further, the A / D converter 8 is separately supplied with a reference voltage Vref, for example, from the outside, and the reference level in A / D conversion is defined according to the reference voltage Vref. The A / D converter 8 converts the analog signal described above into a digital signal having a positive / negative sign with reference to the center of the reference level (hereinafter referred to as the reference center level).

In addition, in order for this A / D conversion to be performed properly, the digital center level that is the reference level of the signal to be converted and the reference center level that is the reference level of the A / D converter 8 need to match.
However, the digital center level varies depending on the product error of the analog circuit up to the previous stage of the A / D converter 8 and the temperature change accompanying the operation of the analog circuit. Hereinafter, these digital center level fluctuations are referred to as offset errors.

  If the digital center level and the reference center level do not match in accordance with the offset error, the digital signal is not converted into an appropriate digital signal, and appropriate received data is not reproduced. Along with this, the performance as a receiver also deteriorates, for example, the synchronization signal cannot be detected and a synchronization failure occurs.

  In mobile terminals that have been put into practical use in recent years, π / 4 shift QPSK, MSK, or CDMA based on spread spectrum is used as the modulation method. As described above, the signal received by the receiver at the mobile terminal is reproduced as an analog signal having a positive and negative sign and magnitude (amplitude) with reference to a predetermined center level. Is almost equally included. Therefore, for example, the digital signal that is the output of the A / D converter 8 is monitored, and the digital center level offset error can be calculated by averaging over a predetermined period. Therefore, conventionally, an automatic offset calibration circuit (AOC (Automatic Offset Control) circuit) 20 included in the demodulation unit 11 calculates this error and calibrates the reference level according to the error. Thereby, the reference center level follows the digital center level, and appropriate A / D conversion is performed.

  In Patent Document 1, the signal reception level is measured at a time equal to or longer than the burst signal period before the burst signal is detected, the maximum value or the average value is held, and the automatic determination is performed based on the held reception level value. It is described that burst detection is started after the gain control amplifier (AGC amplifier) is adjusted.

  Patent Document 2 measures the level of an input burst signal, stores an error from a desired level, determines the gain of a subsequent burst signal according to the error, and determines an automatic gain control amplifier (AGC amplifier). ) Is to be adjusted.

  Patent Documents 1 and 2 above relate to automatic gain control, and are different from the gist of the present invention relating to offset calibration of an A / D converter.

JP2005-20629 JP 5-90854

  However, when the TDMA (Time Division Multiple Access) method is used in which multiple channels are created by time-dividing signals in the same frequency band as in the conventional multiple access method, and a time slot is assigned to each channel, the following inconvenience occurs. It was. In the TDMA system, there is a case where a channel is not used or there is a case where synchronization is not achieved in the channel. Therefore, a signal transmitted and received in each channel (hereinafter referred to as a burst signal) is always present in an assigned time slot. Do not mean. Further, in the TDMA system, when the receiver receives a burst signal transmitted on each channel, a time interval (hereinafter referred to as a guard time) is provided to prevent the burst signals from overlapping each other. That is, the TDMA system has a burst signal non-reception period such as a period in which no burst signal exists due to channel non-use or synchronization failure, and a guard time period for preventing overlap of burst signals.

  In this non-reception period, the receiver receives only the noise component, but since the electric field strength of this noise component is small, the gain of the automatic gain control amplifier 6 is controlled to the maximum by the operation of the automatic gain control circuit 9. . In general, since the gain of the automatic gain control amplifier 6 is designed to have a certain margin, the gain for noise components tends to be very high. Then, offset calibration based on the average value of the amplified noise components is performed, and the reference level is calibrated. If the noise component is AWGN (additive white Gaussian noise), the average value of the noise component does not fluctuate significantly in the long term, but since the gain is maximized, the variance of the noise distribution is large and short-term The average value varies. That is, since offset calibration is performed based on the average value of the fluctuating noise component, the reference level also fluctuates.

  As described above, in the TDMA system, when a receiver having the automatic offset calibration circuit 20 of the A / D converter 8 shown in FIG. 1 is used, depending on the noise component, due to the existence of a non-reception period. Since the reference level fluctuates, there is a problem that proper offset calibration cannot be performed.

  Therefore, an object of the present invention is to provide a receiver having an automatic offset calibration circuit that can avoid inappropriate offset calibration in a non-reception period.

  According to one aspect, in a receiver operating with a single power source, an analog circuit that processes a received signal and outputs an analog signal, and A / D conversion that converts the analog signal into a digital signal based on a reference level Detector, a demodulating circuit for demodulating the digital signal, a center level of the A / D converted digital signal, and an offset calibration for matching the detected center level of the digital signal with the center level of the reference level And an automatic offset calibration circuit that performs the offset calibration during a burst signal reception period, and stops the offset calibration during a burst signal non-reception period.

  According to the above invention, it is possible to provide a receiver having an automatic offset calibration circuit that can avoid inappropriate offset calibration in a non-reception period.

It is a block diagram which shows the structural example of the radio | wireless machine with which a mobile terminal is provided. It is a block diagram which shows the structural example of a general receiver. FIG. 6 is an operation conceptual diagram of A / D conversion before offset calibration in the A / D converter 8 operating with a single power source. FIG. 6 is an operation conceptual diagram of A / D conversion before offset calibration when the analog center level fluctuates. FIG. 6 is an operation concept diagram of the A / D converter 8 after offset calibration. FIG. 3 is a diagram showing an operation example in the TDMA scheme of the receiver shown in FIG. 3 is a block diagram showing a configuration of a receiver in the first embodiment. FIG. FIG. 8 is a diagram showing an operation example in the TDMA scheme of the receiver shown in FIG. FIG. 6 is a block diagram showing a modification of the receiver shown in the first embodiment. FIG. 6 is a block diagram showing a configuration of a receiver in the second embodiment. FIG. 11 is a diagram illustrating an operation example in the TDMA scheme of the receiver illustrated in FIG. FIG. 10 is a block diagram showing a configuration of a receiver in a third embodiment. FIG. 13 is a diagram illustrating an operation example in the TDMA scheme of the receiver illustrated in FIG. FIG. 14 is a diagram illustrating an operation example different from that in FIG. FIG. 10 is a block diagram showing a configuration of a receiver in a fourth embodiment. FIG. 16 is a diagram showing an operation example in the TDMA scheme of the receiver shown in FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof.

[Example of general receiver configuration]
FIG. 2 is a block diagram illustrating a configuration example of a general receiver. First, the configuration of a general receiver having an automatic offset calibration circuit 20 that performs offset calibration will be described with reference to FIG. The automatic gain control amplifier 6 amplifies the reception signal sig1 with a gain corresponding to the automatic gain control signal Sg input from the automatic gain control circuit 9, and outputs the amplified signal to the quadrature detection circuit 7. The quadrature detection circuit 7 is an analog circuit in the present embodiment, and demultiplexes an input signal into an I signal (in-phase component) and a Q signal (quadrature component), and the demultiplexed signals are mixed by mixers Mixa and Mixb. Downconvert, remove the high frequency band by the low pass filter LPF, and output the I signal and Q signal which are analog signals in the baseband.

  In this configuration example, two A / D converters 8a and 8b are provided in order to individually perform A / D conversion on each of the I signal and the Q signal. In the present embodiment, the subscript “a” represents a component related only to the I signal, and the subscript “b” represents a component related only to the Q signal. In addition, since the same processing is performed on the I signal and the Q signal, the subscripts a and b are appropriately omitted in the following description.

  The A / D converter 8 defines a reference level based on the input reference voltage Vref, and converts the I signal and the Q signal into digital signals. The demodulation circuit 10 generates a demodulated signal from the input I signal and Q signal. The synchronization detection circuit 12 detects a synchronization signal in the demodulated signal. Based on this synchronization signal, the received signal is synchronized at a later stage. The automatic gain control circuit 9 monitors the amplitude level of the output signal of the A / D converter 8, and outputs an automatic gain control signal Sg corresponding to the level to the automatic gain control amplifier 6 via the D / A converter 13. To do. The D / A converter 13 converts the digital automatic gain control signal Sg generated by the automatic gain control circuit 9 into an analog signal.

  Since the automatic gain control circuit 9 is intended to control the output level of the automatic gain control amplifier 6, it is the output of the automatic gain control amplifier 6 and is A / D converted by the A / D converter 8. You may monitor the output level of the analog signal until it is.

  The automatic offset calibration circuit 20 performs offset calibration of the A / D converter 8. Offset calibration is performed individually for the I signal and the Q signal, and as described above, the subscripts a and b corresponding to the I signal and the Q signal are added to the reference numerals of the constituent elements. The averaging circuit 15 averages the digital signal that is the output of the A / D converter 8 over a predetermined period and outputs the average value. The adder 17 subtracts the reference value Ref from the average value. The reference control circuit 16 generates a reference voltage Vref that defines the reference level of the A / D converter 8 according to the subtraction result, and outputs the reference voltage Vref to the A / D converter 8.

[Operation example of offset calibration]
Next, an operation example of offset calibration will be described with reference to FIGS.

  FIG. 3 is an operation conceptual diagram of A / D conversion before offset calibration in the A / D converter 8 operating with a single power source. The left side represents an analog signal side that is an input to the A / D converter 8, and the right side represents a digital signal side that is an output after A / D conversion. The analog signal A1 indicated by a thick line in FIG. 3 is an I signal or Q signal that is input to the A / D converter 8 after the received signal sig1 is amplified by the automatic gain control amplifier 6 and subjected to quadrature detection by the quadrature detection circuit 7. Represents a part of

  Note that the analog signal A1 shown in FIG. 3 is a rectangular wave, but the waveform is not limited thereto. As described above, the center level of the analog signal A1 is offset with respect to the ground GND by the offset level Voff, and has a relatively positive sign and magnitude (amplitude) with the offset level Voff being the analog center level. As described above, this analog center level represents the center level (digital center level) of the digital signal after A / D conversion.

  The A / D converter 8 is supplied with the reference voltage Vref from the reference calibration circuit 20, and the reference level in the A / D conversion is defined based on the reference voltage Vref. In this configuration, for example, a level that is 1/2 of the reference voltage Vref or the same level is set as the reference center level Vcr in the A / D conversion described above.

  The A / D converter 8 uses the reference center level Vrc as a reference, quantizes the input analog signal A1 at a predetermined sampling frequency, and has a relatively positive and negative sign and magnitude (amplitude) digital signal. Converted to D1.

  In FIG. 3, since the analog center level and the reference center level Vrc coincide with each other, it is converted into an appropriate digital signal D1.

  However, as described above, the analog center level varies according to the product error of the analog circuit up to the previous stage of the A / D converter 8 and the temperature change accompanying the operation of the analog circuit. Therefore, it is necessary to calibrate the deviation between the analog center level and the reference center level of the A / D converter 8.

  FIG. 4 is an operation conceptual diagram of A / D conversion before offset calibration when the analog center level fluctuates. In FIG. 4, the analog center level of the analog signal A2 is an offset level Voff ′, and has an offset error ΔVoff as compared with the analog center level Voff in FIG. 3 indicated by a broken line on the analog signal side in FIG.

  On the other hand, when the reference voltage Vref supplied from the reference calibration circuit 20 to the A / D converter 8 does not change, the reference level does not change and the reference center level Vcr does not change. In that case, when the analog center level Voff 'and the reference center level Vrc are different and the analog signal A2 is A / D converted in this state, the digital signal D2 in FIG. 4 is output. This digital signal D2 is different from the appropriate digital signal D1 in FIG.

  The broken line shown on the digital signal side in FIG. 4 represents the digital center level that is substantially the same as the analog center level, as described above. Similarly, the offset error ΔVoff on the digital signal side is the same as that on the analog signal side.

  That is, in the diagram shown on the digital signal side in FIG. 4, when the offset error ΔVoff exists between the digital center level Voff ′ and the reference center level Vrc, and they do not coincide with each other, appropriate A / D conversion is not performed and the desired value is obtained. Indicates that no digital signal is output. Therefore, offset calibration is performed to avoid this.

  The mode of offset calibration performed by the automatic offset calibration circuit 20 will be described below using FIG. 4 as an example. First, the digital signal D2 that is the output after A / D conversion is averaged. When the level of the digital signal D2 indicated by a positive value with respect to the ground GND is averaged, the digital center level Voff 'is calculated. Then, by subtracting the reference center level Vrc from the digital center level Voff ′, an offset error ΔVoff having a sign is calculated with reference to the reference center level Vrc. Further, when the level of the digital signal D2 having a positive / negative sign with the reference center level Vrc as a reference zero is averaged, the above-described offset error ΔVoff is calculated as it is. Then, the automatic offset calibration circuit 20 eliminates the offset error ΔVoff and calibrates the reference voltage Vref so that the reference center level Vrc in FIG. 4 matches the digital center level Voff ′. The actual offset error ΔVoff is calculated by averaging A / D converted digital signals over a certain period.

  FIG. 5 is a conceptual diagram of the operation of the A / D converter 8 after offset calibration. In FIG. 5, the calibrated reference voltage Vref ′ is given to the A / D converter 8 as described above, and the A / D converter 8 defines a reference level based on the reference voltage Vref ′. Accordingly, the reference center level Vrc 'coincides with the digital center level Voff'.

  By the offset calibration described above, the analog signal A3 that is subsequently input to the A / D converter 8 is converted into a digital signal D3 equivalent to the appropriate digital signal D1 shown in FIG.

  Returning to FIG. 2, the operation of the automatic offset calibration circuit 20 when offset calibration is performed on the I signal will be described below. The A / D converter 8a A / D converts the input analog signal into a digital signal based on the reference level defined by the reference voltage Vrefa. The averaging circuit 15a averages the digital signals in a predetermined period, calculates a digital center level Voff ', and outputs the digital center level Voff' to the adder 17a.

  The reference value Ref input to the adder 17a is an ideal reference center level Vrc before the offset calibration is performed. The adder 17a subtracts this reference value Ref from the digital center level Voff 'input from the averaging circuit 15a to calculate an offset error ΔVoff.

  The reference control circuit 16a controls the reference voltage Vrefa so that the offset error ΔVref becomes 0 based on the offset error ΔVoff which is a subtraction result. For example, feedback control such as PID control is employed. By this control, the reference center level Vrc 'of the A / D converter 8 gradually matches the digital center level Voff'.

[Description of operation in TDMA system]
Next, the operation when the receiver shown in FIG. 2 is used in the TDMA system will be described.

  FIG. 6 is a diagram illustrating an operation example in the TDMA scheme of the receiver illustrated in FIG. FIG. 6 shows a conventional problem. Although three graphs GR1 to GR3 are individually shown in FIG. 6, the time change shown on the horizontal axis is synchronized between the respective graphs. The first graph GR1 shows a change in the received electric field strength of a burst signal that is a TDMA received signal with respect to a time change. In the TDMA scheme, a plurality of channels are individually assigned to time-divided time slots, so the first graph GR1 shows the reception status of burst signals B1, B2,... Transmitted to each channel. The burst signal reception period T3 indicates a non-reception period in which the burst signal B3 is not received. Further, the guard times GT1, GT2,... Are time intervals set to prevent overlapping of the received burst signals as described above, and the guard times GT1, GT2,.

  In addition, the electric field strength of each of the burst signals B1, B2, and B4 received by the receiver is attenuated by the influence of the propagation environment such as the propagation distance, the weather, and the presence or absence of an obstacle. Therefore, the electric field strengths of the burst signals B1, B2, and B4 received by the receiver in the first graph GR1 are different from each other. Note that the electric field strengths of the received individual burst signals B1, B2, and B4 are constant in the burst signal reception periods T1, T2, and T4.

  In the present embodiment, the burst signal has predetermined header information. The receiver first performs gain adjustment by automatic gain control (AGC) on each received burst signal in accordance with the reception level. Therefore, the header information includes an AGC control code used for gain adjustment. Further, the header information includes timing information such as a synchronization signal (unique word) and guard time period information necessary for the burst signal synchronization processing.

  Next, the second graph GR2 shows the relationship between the time change and the automatic gain control signal Sg output from the automatic gain control circuit 9. Times t1 to t7 indicate times at the change points of the graph. The change represented by the second graph GR2 will be described later.

  The third graph GR3 shows whether or not the offset calibration of the automatic offset calibration circuit 20 is operated. When “on”, the operation is performed, and when “off”, the operation is stopped. The third graph GR3 shows that the automatic offset calibration circuit 20 is always operated.

  As described above, the electric field strength of each burst signal varies depending on each propagation environment. Therefore, the received burst signal is amplified by the automatic gain control amplifier 6, and the automatic gain control amplifier 6 is configured with a feedback loop for the amplitude level of the output signal of the A / D converter 8. That is, as automatic gain control (AGC), gain adjustment of the automatic gain control amplifier 6 is performed so that the amplitude level of the digital signal that is the output signal of the A / D converter 8 is constant.

  The automatic gain control circuit 9 monitors the level of the output signal of the A / D converter 8 and outputs an automatic gain control signal Sg to the automatic gain control amplifier 6 according to the output level. Then, the automatic gain control amplifier 6 amplifies the received signal with a gain corresponding to the automatic gain control signal Sg. As the level required for the output signal of the A / D converter 8, for example, the most effective level that can cope with the processing in the demodulation circuit 10 at the subsequent stage is defined by design.

  The dynamic range of the received burst signal can be assumed in consideration of the propagation environment described above. From the dynamic range and the amplitude level required for the output signal of the A / D converter 8, a range necessary for the automatic gain control signal Sg is assumed. However, since there is an individual gain difference in the radio section up to the previous stage of the automatic gain control amplifier 6, in general, the range of the automatic gain control signal Sg can be set to a wide range with a certain margin added.

  In the receiver, automatic gain control (AGC) always operates even during a non-reception period such as a guard time in the TDMA scheme or a non-reception of a burst signal. Therefore, in the non-reception period, offset calibration based on the noise component shown below is performed.

  First, in the non-reception period, only a noise component having a small electric field strength is received, so that a digital signal that does not reach a predetermined amplitude level is output from the A / D converter 8 via the automatic gain control amplifier 6. . The automatic gain control circuit 9 adjusts the automatic gain control signal Sg so that the amplitude level of the digital signal output from the A / D converter 8 is always a constant value. The automatic gain control signal Sg having the maximum width value Sg_max is output. As a result, the automatic gain control amplifier 6 amplifies the noise component with the maximum gain, and the amplified noise component is output via the A / D converter 8. Then, the automatic offset calibration circuit 20 performs offset calibration based on the noise component, and the reference level of the A / D converter 8 is calibrated. Thus, in the non-reception period, the reference level fluctuates according to the noise component, and the A / D converter 8 performs A / D conversion on the subsequent burst signal based on the fluctuating reference level. Cannot convert to signal.

  Returning to FIG. 6, in the first graph GR1, the guard time GT1 after receiving the burst signal B1 is a non-reception period. Since the received signal at the guard time GT1 is only a noise component having a small electric field strength, the automatic gain control signal Sg is the maximum value Sg_max within the controllable range during the period from time t1 to t2 in the second graph GR2. Increase towards. Then, the gain adjustment for the next burst signal B2 is performed from time t2 after the elapse of the guard time GT1. Therefore, the automatic gain control circuit 9 first performs gain adjustment on the burst signal B2 using the AGC control code in the header information of the burst signal B2.

  In the second graph GR2, the period from time t2 to t3 represents the period until the gain is stabilized by the gain adjustment for the burst signal B2. Further, in this operation example, as shown in the first graph GR1, since the reception electric field strength of the burst signal B2 in the burst signal reception period T2 is constant, correspondingly, in the second graph G2, the time t3 to The automatic gain control signal Sg is constant during the period t4. As described above, the automatic gain control circuit 9 operates so as to make the amplitude level of the output signal of the A / D converter 8 constant. Therefore, in the first graph GR1, it corresponds to the received electric field strength of the burst signal B2 being larger than the received electric field of the burst signal B1, and in the second graph GR2, the burst than the automatic gain control signal Sg in the burst signal B1. The automatic gain control signal Sg in the signal B2 is controlled to be smaller.

  Next, since the burst signal B3 is not received, the period from time t4 to t6 after reception of the burst signal B2 is a non-reception period. Therefore, the automatic gain control signal Sg increases toward the maximum value Sg_max, and reaches the maximum value Sg_max at time t5. Then, in response to reception of burst signal B4 at time t6, automatic gain control signal Sg decreases.

  Further, as shown in the third graph GR3, the automatic offset calibration circuit 20 always performs automatic offset calibration while the receiver is operating. That is, as described above, in the non-reception period, the reference level of the A / D converter 8 is offset calibrated based on the noise component. For this reason, for example, for the burst signal B4 received after a long non-reception period, such as the time t4 to t6 shown in the second graph GR2, the reference level is offset calibrated based on the noise component. Since the A / D conversion is performed, the burst signal B4 input thereafter is not converted into an appropriate digital signal at least at the start.

[First embodiment]
As described above, if the automatic gain control circuit 20 is always operated, the offset calibration based on the noise component is always performed on the reference level of the A / D converter 8 in the non-reception period of the burst signal. Therefore, in order to avoid this, the automatic offset calibration circuit in the present embodiment detects the burst signal reception status, performs offset calibration during the burst signal reception period, and performs offset calibration during the burst signal non-reception period. Stop.

  FIG. 7 is a block diagram showing a configuration of the receiver in the first embodiment. The difference from the block diagram showing the configuration example of the general receiver shown in FIG. 2 is that the automatic offset calibration circuit 20 has a gain comparison circuit 24 that outputs a stop signal S1 for stopping the offset calibration. The same or corresponding components are denoted by the same reference numerals. In the following, the stop signal related to the stop of offset calibration is set to Low active.

  Similar to the configuration shown in FIG. 2, the automatic offset calibration circuit 20 includes an averaging circuit 15, a reference control circuit 16, and an adder circuit 17, adjusts the reference level of the A / D converter, and controls the center of the digital signal. Match the level with the central level of the reference level.

  The gain comparison circuit 24 monitors the automatic gain control signal Sg corresponding to the gain of the automatic gain control amplifier 6 as shown in FIG. 7, and detects the reception status of the burst signal from the gain status. As described above, in the non-reception period of the burst signal, the receiver receives only the noise component with a small electric field strength, and the gain of the automatic gain control amplifier 6 increases, so the reception status of the burst signal can be detected from the gain status. is there. The gain comparison circuit 24 detects the burst signal reception period when the automatic gain control signal Sg is less than the specified value Sg_r, and detects the burst signal non-reception period when the automatic gain control signal Sg is equal to or greater than the specified value Sg_r. Then, the stop signal S1 is output to the averaging circuit 15.

  The averaging circuit 15 averages the digital signal that is the output of the A / D converter 8 within a certain period. Then, the average value is updated, and the reference center level is calibrated. The averaging circuit 15 stops updating the average value in response to the reception of the stop signal S1, and outputs the average value immediately before receiving the stop signal S1 to the adder 17. Therefore, when the automatic gain control signal Sg is equal to or greater than the specified value Sg_r, the reference control circuit 16 stops offset calibration of the A / D converter 8. That is, in the non-reception period of the burst signal, the automatic offset calibration circuit 20 stops the offset calibration by stopping the update in the averaging circuit 15.

  Further, although not shown, the reference control circuit 16 may receive the stop signal S1. In this case, the reference control circuit 16 stops the calibration of the reference voltage Vref in response to the stop signal S1, and outputs the reference voltage immediately before receiving the stop signal S1. That is, the automatic offset calibration circuit 20 stops the offset calibration by stopping the calibration of the reference voltage Vref in the reference control circuit 16 in the non-reception period of the burst signal.

  FIG. 8 is a diagram illustrating an operation example in the TDMA scheme of the receiver illustrated in FIG. Similar to FIG. 6, FIG. 8 also shows three graphs GR1 to GR3.

  The prescribed value Sg_r of FIG. 7 described above is shown in the second graph G2. The specified value Sg_r is a value determined by design or adjustment. When the automatic gain control signal Sg is equal to or less than the specified value Sg_r, the gain comparison circuit 24 detects the burst signal reception period, and the automatic offset calibration circuit 20 performs offset calibration. On the other hand, when the automatic gain control signal Sg exceeds the specified value Sg_r, the gain comparison circuit 24 detects the non-reception period of the burst signal and outputs the stop signal S1, and the automatic offset calibration circuit 20 stops the offset calibration. To do.

  In the second graph GR2, the gain comparison circuit 24 detects the burst signal reception period until the time Ta when the automatic gain control signal Sg at the guard time GT1 reaches the specified value Sg_r. A signal non-reception period is detected, and a stop signal S1 is output. Then, the gain comparison circuit 24 detects the non-reception period of the burst signal from time Ta until time Tb when the automatic gain control signal Sg decreases and reaches the specified value Sg_r according to reception of the burst signal B2. From Tb, the reception period of the burst signal is detected, and the output of the stop signal S1 is canceled.

  Similarly, the gain comparison circuit 24 detects the non-reception period of the burst signal at Tc and outputs the stop signal S1, and detects the reception period of the burst signal at times Tb and Td and cancels the output of the stop signal S1. .

  The third graph GR3 represents “on” and “off” of the offset calibration performed by the automatic offset calibration circuit 20, and represents the level change of the stop signal S1 corresponding thereto. The automatic offset calibration circuit 20 stops offset calibration at times Ta to Tb and times Tc to Td when the low level stop signal S1 is output from the gain comparison circuit 24.

  In this manner, for example, offset calibration based on the noise component can be stopped in the long non-reception period shown at times Tc to Td of the second graph GR2, so that an appropriate reference level for the burst signal B4 received thereafter A / D conversion is performed at, and an appropriate digital signal is output.

  Note that the guard times GT1 to GT3 are extremely shorter than the burst signal reception periods T1 to T4. Therefore, the fluctuation of the reference level of the A / D converter at the guard time GT1 is also very small. Therefore, the automatic offset calibration circuit 20 continues offset calibration during a short non-reception period in the guard times GT1 to GT3, and stops offset calibration only during a long non-reception period such as the burst signal reception period T3. Good.

  In the offset calibration described above, the automatic offset calibration circuit 20 controls the reference voltage Vref so that the offset error ΔVoff between the reference center level Vrc and the digital center level Voff ′ in FIG. Then, the reference center level Vrc is made to follow the digital center level Voff ′ so as to coincide with each other.

  However, as an offset calibration, the reference voltage Vref input to the A / D converter 8 is always constant, i.e., the reference center level Vrc is constant, and the analog center level (or digital center level) Voff ′ is changed to the reference center level Vrc. You may control so that it may correspond.

  FIG. 9 is a block diagram showing a modification of the receiver shown in the first embodiment. The receiver shown in FIG. 9 has a circuit that performs level adjustment on a received analog signal.

  A DC offset circuit 18 that calibrates the analog signal level is arranged in front of the A / D converter 8, and the DC offset circuit 18 is based on the DC offset signal Vdc from the DC offset control circuit 19 in the automatic offset calibration circuit 20. Calibrate the analog signal level of the input signal.

  The offset error ΔVoff calculated based on the averaging of the digital signal is input to the DC offset control circuit 19 as in the reference calibration circuit 16 of FIG. Then, the DC offset control circuit 19 adjusts the DC offset signal Vdc output to the DC offset circuit 18 based on the offset error ΔVoff. Further, since a separately specified constant reference voltage Vref is input to the A / D converter, the reference center level Vrc is always constant.

  In the following, a mode for the input analog signal in the DC offset circuit 18 will be specifically described with reference to FIGS.

  The aforementioned offset error ΔVoff is indicated by the offset error ΔVoff included in the analog signal A2 shown in FIG. Further, since the reference voltage Vref input to the A / D converter 8 is a prescribed value, the reference center level Vrc in FIG. 4 is always constant. The analog signal A2 is input to the DC offset circuit 18 before being input to the A / D converter 8, and the DC offset circuit 18 generates an offset error ΔVoff based on the DC offset signal Vdc input from the DC offset control circuit 19. The analog signal A2 is calibrated to the analog signal A1 shown in FIG. As a result, the analog center level (digital center level) Voff and the reference center level Vrc calibrated as shown in FIG. 3 coincide, and the analog signal A1 is converted to an appropriate digital signal D1 by the A / D converter 8. The

  Similarly to the automatic offset circuit 20 that calibrates the reference level shown in FIG. 7 described above, the automatic offset calibration circuit 20 that calibrates the analog signal level shown in FIG. 9 performs automatic offset calibration during the non-reception period of the burst signal. Stop.

  That is, the averaging circuit 15 stops the updating of the average value in response to the stop signal S1 that the gain comparison circuit 24 detects and outputs the non-reception period of the burst signal, and the average value immediately before receiving the stop signal S1. Is output to the adder 17. Alternatively, although not shown, the DC offset control circuit 19 receives the stop signal S1, stops the calibration of the DC offset signal Vdc in response thereto, and outputs the DC offset signal Vdc immediately before receiving the stop signal S1. Also good.

  As described above, the offset calibration in the case where the DC offset circuit 18 is arranged in the front stage of the A / D converter 8 and the reference level of the A / D converter 8 is made constant has been shown. However, the A / D conversion device 8 itself May have a function of calibrating the analog center level. In the above description, offset calibration is performed on an analog signal before A / D conversion. However, similar DC offset calibration may be performed on a digital signal after A / D conversion.

  Although the offset calibration based on the average value of the digital signal has been described above, the offset calibration may be performed based on an intermediate value between the maximum value and the minimum value of the digital signal that is the output of the A / D converter 8. . For example, an intermediate value between the maximum value and the minimum value of the detected digital signal corresponds to the average value described above. Therefore, instead of the averaging circuit 15, a circuit that detects the maximum and minimum values of the digital signal and calculates an intermediate value thereof may be used.

  As described above, in the first embodiment, offset calibration is performed during the burst signal reception period, and offset calibration is stopped during the non-reception period. Then, the gain status of the automatic gain control amplifier 6 is monitored as means for detecting the reception status of the burst signal, and the reception period is detected if the gain status is equal to or less than a predetermined specified value. Is detected.

  As a result, the reference level of the A / D converter 8 is calibrated based on the noise component during the non-reception period of the burst signal, so that proper A / D conversion is not performed and proper digital signals are not output. Is avoided.

  In the first embodiment, the automatic gain control signal Sg is referred to in order to monitor the gain status of the automatic gain control amplifier 6. However, the present invention is not limited to this. The amplitude level of the analog signal or digital signal may be referred to.

[Second Embodiment]
FIG. 10 is a block diagram showing a configuration of a receiver in the second embodiment. The difference from the block diagram showing the configuration example of a general receiver shown in FIG. 2 is that the automatic offset calibration circuit 20 receives a stop signal (low level) S2 for stopping offset calibration from the synchronization detection circuit 12. . Other identical or corresponding components are denoted by the same reference numerals. The second embodiment will be described below except for the explanation described above.

  As described above, the burst signal has predetermined header information. The header information includes information on a synchronization signal (unique word) and guard time period required for burst signal synchronization processing. The synchronization detection circuit 12 detects these timing information.

  Therefore, it is possible to detect the reception status of the burst signal from the detection status of the synchronization signal. For example, the fact that the synchronization signal is not detected by the synchronization detection circuit 12 corresponds to the detection of the non-reception period of the burst signal.

  The synchronization detection circuit 12 monitors the synchronization signal and guard time period information included in the header information of the demodulated signal demodulated by the demodulation circuit 10, and when the synchronization signal is not detected or according to the detected guard time period, A stop signal S2 is output to the averaging circuit 15 in the automatic offset calibration circuit 20. The operation of the automatic offset calibration circuit 20 for the stop signal S2 is the same as the operation of the automatic offset calibration circuit 20 for the stop signal S1 in the first embodiment. As a result, the offset calibration is stopped in response to the stop signal S2. To do.

  FIG. 11 is a diagram illustrating an operation example in the TDMA scheme of the receiver illustrated in FIG. Similar to FIG. 6, three graphs GR1 to GR3 are shown.

  In the third graph GR3, times Te to Tj indicate times at which “on” and “off” of automatic offset calibration are switched according to a change in the level of the stop signal S2. The time Te is the time at which the guard time GT1 starts, and the synchronization detection circuit 12 can calculate this time Te from the information of the guard time period that is the header information of the burst signal B1. Therefore, the synchronization detection circuit 12 outputs a stop signal S2 at the timing Te when the guard time GT1 starts, and stops offset calibration.

  The time Tf is the time when offset calibration is resumed in advance in preparation for the reception of the next burst signal B2 after the guard time GT1, and the synchronization detection circuit 12 calculates the time Tf from the guard time period information. To do. For example, the synchronization detection circuit 12 calculates the guard time GT1 end time from the guard time GT1 period in the guard time period information, and calculates the time Tf after the guard time GT1 start time Te and before the guard time GT1 end time. . Then, the synchronization detection circuit 12 cancels the output of the stop signal S2 at the timing Tf before reception of the burst signal B2, and restarts offset calibration. Further, the synchronization detection circuit 12 operates in the same manner as the times Te and Tf at the times Tg and Th.

  The time Ti indicates the time when the offset calibration is stopped when the synchronization detection circuit 12 does not detect the synchronization signal of the burst signal B3 that has been scheduled. The non-detection of the synchronization signal in the synchronization detection circuit 12 corresponds to the detection of the non-reception period of the burst signal. In response to this, the synchronization detection circuit 12 outputs the stop signal S2 and stops the offset calibration.

  In addition, the synchronization detection circuit 12 performs the same operation at time Tj as at times Tf and Th. In the burst signal B3, information on the guard time period in the header information is not detected. However, since the burst signal reception periods T1 to T4 and the guard times GT1 to GT3 are constant, the synchronization detection circuit 12 can calculate the time Tj from the header information of the burst signal B2, for example.

  As described above, in the second embodiment, the synchronization detection circuit 12 monitors the synchronization signal of the burst signal in order to detect the reception status of the burst signal. When the synchronization signal is detected, the synchronization detection circuit 12 does not output the stop signal S2, and the automatic offset calibration circuit 20 performs offset calibration. If no synchronization signal is detected, the synchronization detection circuit 12 outputs a stop signal S2, and the automatic offset calibration circuit 20 stops offset calibration.

  Furthermore, the synchronization detection circuit 12 outputs a stop signal S2 during the guard time period based on the detected guard time period information, and the automatic offset calibration circuit 20 detects the non-reception period and stops offset calibration.

  From the above, for example, offset calibration based on noise components can be avoided in the long non-reception period shown at times Ti to Tj in the third graph GR3, so that the burst signal B4 received thereafter can be at an appropriate reference level. A / D conversion is performed and an appropriate digital signal is output.

  Note that the guard times GT1 to GT3 are extremely shorter than the burst signal reception periods T1 to T4. Therefore, the automatic offset calibration circuit 20 may continue the offset calibration during a short non-reception period in the guard times GT1 to GT3.

[Third embodiment]
FIG. 12 is a block diagram illustrating a configuration of a receiver according to the third embodiment. The configuration is a combination of the first embodiment and the second embodiment, the stop signal (Low level) S1 of the first embodiment and the stop signal (Low level) S2 of the second embodiment are The stop signal (low level) S3 input to the logic operation circuit 25 and subjected to the logic operation is output to the averaging circuit 15. The logical operation circuit 25 causes the stop signal S3 to be stopped (Low level) when both of the stop signals S1 and S2 are stopped (Low level). As in the first and second embodiments, the automatic offset calibration circuit 20 stops offset calibration in response to the stop signal S3. In the third embodiment, the function of the logical operation circuit 25 performs more reliable offset calibration as shown below.

  FIG. 13 is a diagram illustrating an operation example in the TDMA scheme of the receiver illustrated in FIG. Similar to FIG. 6, three graphs GR1 to GR3 are shown. This example shows the operation when the burst signal B3 is received but the synchronization signal cannot be detected due to a timing error or the like. In this case, since the burst signal B3 is actually received, it is desirable not to stop the offset calibration. Therefore, the logic operation circuit 25 outputs the stop signal S3 in the stop state (Low level) only when both the stop signal S1 and the stop signal S2 are at the Low level.

  In the second graph GR2 in FIG. 13, as in the first embodiment, the automatic gain control signal Sg changes according to the reception status of the burst signal indicated by the first graph GR1. When the specified value Sg_r is exceeded, the burst signal non-reception period is detected, and the stop signal S1 is output. A graph gr_1 shown in the third graph GR3 represents a change in the level of the stop signal S1.

  The graph gr_2 represents the level change of the stop signal S2 corresponding to the detection state of the synchronization signal, as in the second embodiment. The time Ti in the graph gr_2 indicates the time when the stop signal S2 is output because the synchronization signal of the burst signal B3 cannot be detected due to a timing error or the like although the burst signal B3 is received.

  The graph gr_3 represents the change in the level of the stop signal S3 and represents “on” and “off” of offset calibration performed by the corresponding automatic offset calibration circuit 20. Due to the function of the logical operation circuit 25 described above, the offset calibration is stopped only in the period from the time Ts to Tj when both the stop signals S1 and S2 are at the low level.

  As described above, when the burst signal B3 is received but the synchronization signal cannot be detected, the offset calibration is stopped in response to the output of the stop signal S2 at the time Ti in the second embodiment. However, in the third embodiment, as shown in the period P1 of the graph gr_3, even if the synchronization of the burst signal B3 cannot be detected, the stop signal is caused by the drop in the automatic gain control signal Sg accompanying the reception of the burst signal B3. Since S1 is not stopped, it can be avoided that offset calibration stops.

  As another example of FIG. 13, a case where the level of the burst signal B3 is very low can be considered. In this case, the stop signal S1 enters the stop state, but if the synchronization is detected, the stop signal S2 enters the non-stop state, so the stop signal S3 enters the non-stop state (High level), and offset calibration continues.

  FIG. 14 is a diagram illustrating an operation example different from that of FIG. 13 in the TDMA scheme of the receiver illustrated in FIG. Similar to FIG. 13, three graphs GR1 to GR3 are shown. Similarly to the case of FIG. 13, the logic operation circuit 25 outputs the stop signal S3 only when both the stop signal S1 and the stop signal S2 are at the low level. The reception status of the burst signal is the same as that in FIGS. 6, 8, and 11, and the burst signal B3 is not received.

  In FIG. 14, since the burst signal B3 is not received, the automatic gain signal Sg increases toward the maximum value Sg_max of the control range. On the other hand, at the time Ti of the graph gr_2 in the third graph GR3, the synchronization signal is not detected and the stop signal S2 is output, and further the stop signal S1 is output, so the stop signal S3 is as shown in the graph gr_3. The stopped state is entered and offset calibration is stopped. Then, as in the second embodiment, the output of the stop signal S2 is canceled at time Tj, and offset calibration is resumed at the same time.

  In the first embodiment, offset calibration is performed according to the level of the stop signal s1 shown in the graph gr_1, and offset calibration is restarted from time Td, so even during the burst signal reception, during the period P2 Offset calibration is not performed. On the other hand, as shown in the graph gr_3, in the third embodiment, the offset calibration can be reliably performed even in the period P2 that is the burst signal reception period.

  As the logical operation circuit 25, a logical sum (OR) circuit is used when the stop signal indicates a stop state at a low level as in this embodiment. On the contrary, if the stop signal indicates a stop state at a high level, a logical product (AND) circuit is used as the logical operation circuit 25.

[Fourth embodiment]
FIG. 15 is a block diagram illustrating a configuration of a receiver according to the fourth embodiment. Unlike FIG. 7, the automatic offset calibration circuit 20 has a limiter circuit 26 that limits the automatic gain control signal Sg of the automatic gain control circuit 9 to a specified value Sg_r2.

  FIG. 16 is a diagram illustrating an operation example in the TDMA scheme of the receiver illustrated in FIG. Similar to FIG. 6, three graphs GR1 to GR3 are shown.

  The limiter circuit 26 monitors the automatic gain control signal Sg from the automatic gain control circuit 9, and outputs the signal Sg to the D / A converter 13. Further, the limiter circuit 26 is supplied with a specified value Sg_r2, and the limiter circuit 26 outputs a stop signal S4 to the automatic gain control circuit 9 when the automatic gain control signal Sg exceeds the specified value Sg_r2. The automatic gain control circuit 9 stops the gain increase in the circuit in response to the stop signal S4.

  In FIG. 16, as in the first embodiment, when the automatic gain control signal Sg exceeds the specified value Sg_r, the offset calibration is stopped by the stop signal S1, as shown in the third graph GR3. In the second graph GR2, the specified value Sg_r2 input to the limiter circuit 26 of FIG. 15 is shown, and the change of the automatic gain control signal Sg when there is no limiter circuit 26 is shown by a broken line.

  When the limiter circuit 26 is not provided, the automatic gain control signal Sg increases to the gain Sg_max at the time t5 of the guard time GT2, the burst signal reception period T3, and the guard time GT3 non-reception period, but the automatic gain control signal Sg It does not increase beyond the specified value Sg_r2 by 26 functions. Then, the automatic gain control signal Sg decreases to the gain Sg_b4 in response to the reception of the burst signal B4, but becomes the specified value Sg_r or less at the time Tn, and the offset calibration is resumed. On the other hand, when there is no limiter circuit 26, offset calibration is restarted from time Tp later than time Tn.

  In this way, if the limiter circuit 26 prevents the internal gain of the automatic gain control circuit 9 from becoming abnormally high during the non-reception period of the burst signal by limiting the gain by the limiter circuit 26, the automatic gain after the next burst signal B4 is received. The decrease of the control signal Sg can be accelerated. For this reason, the automatic offset calibration circuit 20 can advance the start time of offset calibration when receiving the burst signal B4.

  Furthermore, the time Tk until the automatic gain control signal Sg decreases to the gain Sg_b4 is earlier than the time Tm when the limiter circuit 26 is not provided. That is, by providing the limiter circuit 26 in the automatic offset calibration circuit 20, the response of automatic gain control (AGC) to the received signal is improved.

  In the fourth embodiment, the limiter circuit 26 is provided in the first embodiment. However, the limiter circuit 26 may be used in the second and third embodiments, and the same effect can be obtained.

  The above embodiment is summarized as follows.

(Appendix 1)
In a receiver that operates with a single power supply,
An analog circuit that processes the received signal and outputs an analog signal;
An A / D converter that converts the analog signal into a digital signal based on a reference level;
A demodulation circuit for demodulating the digital signal;
An automatic offset calibration circuit that detects the center level of the A / D converted digital signal and performs offset calibration to match the detected center level of the digital signal with the center level of the reference level;
A receiver that performs the offset calibration during a burst signal reception period and stops the offset calibration during a burst signal non-reception period.

(Appendix 2)
Furthermore, an automatic gain control amplifier that controls the gain of the received signal according to an automatic gain control signal;
An automatic gain control circuit that generates the automatic gain control signal according to the amplitude level of the output signal of the automatic gain control amplifier;
The receiver according to claim 1, wherein the automatic offset calibration circuit detects a non-reception period of the burst signal when the automatic gain control signal exceeds a specified value, and detects a reception period of the burst signal when the automatic gain control signal does not exceed the specified value. .

(Appendix 3)
The receiver according to claim 2, wherein the automatic offset calibration circuit limits the automatic gain control signal of the automatic gain control circuit to the specified value when the automatic gain control signal exceeds a specified value.

(Appendix 4)
The automatic offset calibration circuit detects a non-reception period of the burst signal when a synchronization signal is not detected in the digital signal, and detects a reception period of the burst signal when the synchronization signal is detected. The receiver according to -3.

(Appendix 5)
The receiver according to appendix 1, wherein the automatic offset calibration circuit detects a non-reception period of the burst signal at a guard time obtained from a timing at which a synchronization signal is detected in the digital signal.

(Appendix 6)
The receiver according to appendix 1, wherein the automatic offset calibration circuit adjusts the reference level in the offset calibration to match the center level of the digital signal with the center level of the reference level.

(Appendix 7)
The receiver according to claim 6, wherein the automatic offset calibration circuit stops the adjustment of the reference level in a non-reception period of the burst signal.

(Appendix 8)
7. The receiver according to appendix 1 or 6, wherein the automatic offset calibration circuit updates a center level of the reference level based on an average value of the digital signal within a predetermined period in the offset calibration.

(Appendix 9)
The receiver according to appendix 1 or 6, wherein the automatic offset calibration circuit updates a center level of the reference level based on an intermediate value between a maximum value and a minimum value of the digital signal in the offset calibration.

(Appendix 10)
The receiver according to appendix 8 or 9, wherein the automatic offset calibration circuit stops the update in a non-reception period of the burst signal.

(Appendix 11)
The receiver according to appendix 1, wherein the automatic offset calibration circuit adjusts the level of the analog signal in the offset calibration to match the center level of the digital signal with the center level of the reference level.

(Appendix 12)
The receiver according to claim 11, wherein the automatic offset calibration circuit stops adjusting the level of the analog signal during a non-reception period of the burst signal.

(Appendix 13)
The receiver according to claim 11, wherein the automatic offset calibration circuit updates the level of the analog signal based on an average value of the digital signal within a predetermined period in the offset calibration.

(Appendix 14)
The receiver according to claim 11, wherein the automatic offset calibration circuit updates the level of the analog signal based on an intermediate value between the maximum value and the minimum value of the digital signal in the offset calibration.

(Appendix 15)
15. The receiver according to appendix 13 or 14, wherein the automatic offset calibration circuit stops the update during a non-reception period of the burst signal.

(Appendix 16)
2. The receiver according to appendix 1, wherein the analog circuit includes a down converter that down-converts the frequency of the received signal.

3 Transmission system
4 Receiving system
6 Automatic gain control amplifier
7 Quadrature detection circuit
8 A / D converter
9 Automatic gain control circuit
10 Demodulator circuit
11 Demodulator
12 Sync detection circuit
15 Averaging circuit
16 Reference control circuit
17 Addition
18 DC offset circuit
19 DC offset control circuit
20 Automatic gain control amplifier
24 gain control amplifier
25 Logical operation circuit
26 Limiter

Claims (6)

In a receiver that operates with a single power supply,
An analog circuit that has an automatic gain control amplifier that amplifies the received signal, processes the received signal, and outputs an analog signal;
An A / D converter that converts the analog signal into a digital signal based on a reference level;
A demodulator that demodulates the digital signal and outputs a demodulated signal;
Wherein detecting the central level of the digital signal output from A / D converter, and an automatic offset calibration circuit for performing offset calibration to match the the central level of the detected the digital signal the reference level central level,
An automatic gain control circuit for generating an automatic gain control signal for controlling a gain of the automatic gain control amplifier according to an amplitude level of the digital signal;
A synchronization detection circuit for detecting a synchronization signal included in the demodulated signal;
Have
The automatic gain control amplifier amplifies the received signal in a reception period for receiving a burst signal and a non-reception period in which the burst signal is not received,
The automatic offset calibration circuit detects the non-reception period when the automatic gain control signal exceeds a specified value, the detection result of the non-reception period, and the synchronization signal that does not detect the synchronization signal of the synchronization detection circuit The offset calibration is stopped based on the detection result of the non-detection period . The automatic offset calibration circuit, receiver of claim 1 wherein the limiting of the automatic gain control signal to the specified value of the automatic gain control circuit when the automatic gain control signal exceeds a prescribed value.   2. The receiver according to claim 1, wherein the automatic offset calibration circuit adjusts the reference level in the offset calibration to match the center level of the digital signal with the center level of the reference level. 4. The receiver according to claim 3, wherein the automatic offset calibration circuit stops the adjustment of the reference level in a non-reception period of the burst signal. The receiver according to claim 1 or 3, wherein the automatic offset calibration circuit updates a center level of the reference level based on an average value of the digital signal within a predetermined period in the offset calibration.   2. The receiver according to claim 1, wherein the automatic offset calibration circuit adjusts the level of the analog signal in the offset calibration to match the center level of the digital signal with the center level of the reference level.

Images