JP5238126B2 - Display device and driving method thereof - Google Patents

Description

  The present invention relates to a display device including a light emitting element, a liquid crystal element, and the like, and a driving method thereof.

  2. Description of the Related Art In recent years, flat panel display devices that are widely used not only for medium and large display devices but also for display units of portable information terminals have increased the number of pixels as their definition increases. For this reason, when the number of pixels is large due to a drive that employs a line sequential method in which data is simultaneously written (input data) to each pixel in an active matrix structure that can hold image data for each pixel. In addition, it is necessary to write a video signal to each pixel using a sufficient time.

  The gradation method of a display device having an active matrix pixel is roughly divided into an analog gradation method and a digital gradation method. Among these, the digital gradation method includes a time division gradation method, an area gradation method, a method in which a time division gradation method and an area gradation method are mixed, and the like. In any digital gradation method, each pixel or sub-pixel is driven with a binary value of an on state or an off state. For this reason, there is an advantage that a reduction in image quality due to variations in threshold voltage (Vth) of a thin film transistor (hereinafter referred to as TFT) can be reduced as compared with the analog gradation method. In addition, Japanese Patent Application Laid-Open No. 2004-228688 discloses that gradation display is performed using a digital time-division method.

  FIG. 5 shows a configuration example of a digital gray scale display device in which binary data is input to pixels having an active matrix structure by a line sequential method. The pixel portion has M rows and N columns of pixels (M and N are natural numbers, respectively). In the periphery of the pixel portion 501, a shift register 504, a first latch circuit 505, a second latch circuit 506, a level shifter 507, a source line driver circuit 502 including a buffer 508, a shift register 509, a level shifter 510, A gate line driver circuit 503 having a buffer 511 is provided.

  The shift register 509 sequentially outputs selection pulses from the first stage according to the clock signal (GCK) and the start pulse (GSP). After that, amplitude conversion is performed by the level shifter 510, and gate lines are sequentially selected from the first row to the m-th row and the M-th row by the buffer 511 (2 ≦ m ≦ M, where m is a natural number).

  In the row where the gate line is selected, the shift register 504 sequentially outputs sampling pulses from the first stage according to the clock signal (SCK) and the start pulse (SSP). The first latch circuit 505 captures a video signal (Video) at a timing when a sampling pulse is input, and the video signal captured at each stage is held in the first latch circuit 505.

  When a latch pulse (LAT) is input after the capture of the video signal for one row is completed, the video signals held in the first latch circuit 505 are transferred to the second latch circuit 506 all at once. All the source lines are charged / discharged all at once. Therefore, when the latch pulse (LAT) is input after the capture of the video signal of the m-th row is completed also in the m-th row, the video signals held in the first latch circuit are The data is transferred to the latch circuit 506, and all the source lines are charged / discharged simultaneously through the level shifter 507 and the buffer 508.

The above operation is repeated from the first row to the last row (here, M rows), and writing to all pixels is completed. The same operation is repeated to display an image.
JP 2001-5426 A

  In the analog gradation method, gradation expression is possible by inputting data to the source line at least once per frame.

  On the other hand, in a digital gradation method such as a time gradation method, an area gradation method, or a time + area gradation method in which each pixel is driven with a binary value of an on state or an off state, gradation representation is performed. In this case, it is necessary to input data to the source line a plurality of times per frame. In a display device, a plurality of TFTs and parasitic capacitances provided in a pixel portion are load capacitances attached to source lines that need to be moved by a buffer. In the digital gray scale method, when the data input to the source line changes from the low potential (m−1 line) to the high potential (m line), the external positive power source is connected to the low potential (m−) through the Pch TFT of the buffer. The load capacity is charged from the first line) to the high potential (mth line). On the other hand, when the data input to the source line changes from the High potential (m-1 row) to the Low potential (m row), the external negative power source is connected to the load capacitance from the High potential to the Low potential through the Nch TFT of the buffer. Discharge from. Since these electric powers are consumed when the potential of the source line changes, the power consumption of the external power source increases if the output changes frequently. For this reason, in the digital gradation method, an image that requires a large number of gradations, such as a natural image, or a special pattern in which the logic is frequently reversed, has a large number of voltage changes in data input to the source line. The power consumption of the external power supply will increase.

  Therefore, in the digital gray scale method, power consumption required for inputting data to the source line is a big problem for a small display device for a portable terminal that requires low power consumption. In addition, in a display device such as a television, it is difficult to avoid an increase in parasitic capacitance of a source line due to an increase in size, and a reduction in power consumption is a problem as in a small display device.

  The present invention has been made in view of the above-described problems, and provides a display device and a driving method thereof for realizing a reduction in power consumption of a power source required for charging and discharging a source line in a digital gradation method.

  In order to solve the above-described problems, the following measures are taken in the present invention.

The present invention includes M rows and N columns (M and N are natural numbers),
M gate lines,
N source lines,
A circuit for storing a data signal of the (m−1) th row (2 ≦ m ≦ M, where m is a natural number);
a circuit that compares the m-th row data signal with the (m−1) -th row data signal before inputting the m-th row data signal to the source line;
A switch that electrically connects the source line to a power supply circuit; and a switch that electrically connects the N source lines.

It has pixels of M rows and N columns (M and N are natural numbers, respectively)
In an active matrix display device having M gate lines and N source lines,
(M-1) The data signal of the line (2 ≦ m ≦ M, m is a natural number) is input to the source line,
Electrically disconnecting the source line from the power supply circuit;
Before inputting the m-th row data signal to the source line, the m-th row data signal is compared with the (m−1) -th row data signal,
Among the N source lines, the m-th row data signal is electrically connected to different source lines from the (m−1) -th row data signal,
Each of the connected source lines is electrically disconnected and then electrically connected to a power supply circuit to input an m-th row data signal to the source line.

In an active matrix display device having pixels of M rows and N columns (M and N are natural numbers, respectively), and having M gate lines and N source lines,
(M-1) The data signal of the line (2 ≦ m ≦ M, m is a natural number) is input to the source line,
Before inputting the m-th row data signal to the source line, the m-th row data signal is compared with the (m−1) -th row data signal,
When the data signal of the m-th row is different from the data signal of the (m−1) -th row, the source line to which the m-th row data signal is input is electrically disconnected from the power supply circuit,
Among the N source lines, the m-th row data signal is electrically connected to different source lines from the (m−1) -th row data signal,
Each of the connected source lines is electrically cut off and electrically connected to a power supply circuit to input an m-th row data signal to the source line.

  Before comparing the data signals, a step of holding the data signal of the (m−1) th row (2 ≦ m ≦ M, where m is a natural number) and inputting the data signal of the (m−1) th row to the source line is performed. You may have. The present invention is also used in line sequential driving. For the comparison, an exclusive OR circuit can be used. The source line may be connected to the power supply circuit through a buffer circuit.

  In the pixel portion, a TFT, a pixel electrode, a light emitting element, a liquid crystal element, or the like is provided at an intersection of the gate line and the source line.

  It has M rows and N columns (M and N are natural numbers), an active matrix structure pixel, M gate lines and N source lines. In the display device that performs the above, as described above, binary data is input to each source line for each row. Among these, in the period before the data input of the current row (m row) is performed after the data input of the previous row (m−1 row, 2 ≦ m ≦ M, m is a natural number) is completed, the previous row (m−1 The source line in which the data in the row (m) and the data in the row (m row) are electrically disconnected from the external power supply, and the source lines in which the data in the previous row (m-1 row) and the data in the row (m row) are different Connect electrically.

  With the above configuration, out of the source lines in which the data in the previous row (m−1 row) and the data in the current row (m row) are different, the load capacitance of the source line that was at the high potential in the previous row (m−1 row) The charges move to the load capacitance of the source line whose logic is the low potential in the row (m−1 row) to an intermediate potential where the respective potentials are equal. At this time, since the source line and the external power source are electrically cut off, the power of the external power source is not consumed for charging and discharging up to the intermediate potential. In addition, the intermediate potential at this time is the number of source lines that are the previous row (m-1 row) High potential and this row (m row) Low potential, and the previous row (m-1 row) Low potential and this row ( m row) It is ideally determined by the ratio of the number of source lines that are high potentials.

  Data of the current row (m row) is input after the intermediate potential charge / discharge of the source line in which the previous row (m-1 row) data and the current row (m row) data are different. At this time, the external power supply only needs to charge and discharge from the intermediate potential to the High potential or Low potential. For this reason, data rewriting of the source line can be performed with less power than the conventional method.

  As described above, according to the present invention, the data of the previous row (m-1 row) in the period before the data input of the current row (m row) is performed after the data input of the previous row (m-1 row) is completed. Among the source lines having different data for this row (m row), the logic in the previous row (m-1 row) is low in potential from the load capacity of the source line that was High potential in the previous row (m-1 row). The charge moves to the load capacitance of the source line to an intermediate potential at which the respective potentials are equal. At this time, since the source line and the external power source are electrically cut off, the power of the external power source is not consumed for charging and discharging up to the intermediate potential. Thereafter, in the data input period of m rows, the external power supply only needs to charge and discharge from the intermediate potential to the High potential or Low potential. For this reason, data rewriting of the source line can be performed with less power than the conventional method.

  According to the display device and the driving method of the present invention configured as described above, an image or a line that requires a large number of gradations, such as a natural image, in which a large amount of power is consumed in the conventional display device. Even in a special pattern in which the logic is frequently reversed, it is possible to display with a small amount of power because the power of the external power source is not consumed for charging and discharging up to the intermediate potential.

  The best mode for carrying out the invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention should not be construed as being limited to the description of the embodiments. In the drawings, common portions are denoted by the same reference numerals, and detailed description thereof is omitted.

(Embodiment 1)
FIG. 1 is a block diagram of a line-sequential source line driver circuit used in the display device of the present invention. Similar to the conventional line-sequential type shown in FIG. 5, the shift register 101, the first latch circuit 102, the second latch circuit 103, the second level shifter circuit 108, and the buffer circuit 109 are included. Although not shown, the pixel portion has pixels of M rows and N columns, and has M gate lines and N source lines. Similarly to the circuit shown in FIG. 5, it also has a gate line driver circuit having a shift register, a level shifter, and a buffer. In the pixel portion, a TFT, a pixel electrode, a light emitting element, or a liquid crystal element is provided at an intersection of the gate line and the source line.

In addition to the connection to the second level shifter circuit 108, the output terminal of the second latch circuit 103 is exclusive to the third latch circuit 104 (also referred to as exclusive OR or XOR; hereinafter referred to as exclusive OR). Connected to the circuit 105. The output terminal of the third latch circuit 104 is connected to the exclusive OR circuit 105. The output terminal of the exclusive OR circuit 105 is connected to the first level shifter circuit 107. The output terminal of the first level shifter circuit 107 is connected to the Nch TFT side gate terminal of the second transmission gate 113. The output terminal of the buffer circuit 109 is electrically connected to the source line 114 via the first transmission gate 112. That is, the first transmission gate 112 has a function of a switch for electrically connecting the source line and the buffer circuit. The buffer circuit is connected to a positive power supply 110 and a negative power supply 111 which are external power supply circuits.
The first transmission gate 112 receives the buffer circuit 109 according to the SWE signal (source write enable signal: a signal for instructing connection / disconnection between the buffer circuit and the source line and controlling the enable / disable of the signal input to the source line). And the source line 114 are connected and disconnected. The SWE signal is input to the Pch TFT side gate terminal of the first transmission gate 112. The source lines 114 (S 1, S 2, S 3,..., Sn−1, Sn) are electrically connected through the second transmission gate 113. That is, the second transmission gate 113 has a function of a switch for electrically connecting the source lines.

  Although an exclusive OR circuit and a transmission gate are used here, the present invention is not limited to this. A circuit having a comparison function or a circuit having a switch function can be used.

  The operation will be described. First, the shift register 101, the first latch circuit 102, the second latch circuit 103, the second level shifter circuit 108, and the buffer circuit 109, which operate in the same manner as those of the conventional line sequential method shown in FIG. A description will be given using 1 and 2. The shift register 101 outputs sampling pulses sequentially from the first stage to the final stage according to the start pulse (SSP). In the first latch circuit 102, the video signal (Video) is captured sequentially from the stage where the sampling pulse is output. The video signal captured here is held in the first latch circuit 102 until the next sampling pulse output from the shift register 101 is input. In the second latch circuit 103, after the capture of the video signal is completed from the first stage to the last stage (here, the N stage) of the first latch circuit 102, that is, all of one row, the latch pulse (LATa ) Is input, and all video signals (LAT2-1, LAT2-2, LAT2-3, LAT2-4,..., LAT2-N) for one line are output. FIG. 2 shows a case where the waveform indicated by the video signals (LAT2-1, LAT2-2, LAT2-3, LAT2-4 to LAT2-N) is output. Note that the video signals (LAT2-4 to LAT2-N) in FIG. 2 indicate that either the High potential is fixed or the Low potential is fixed. The second level shifter circuit 108 converts the video signal output from the second latch circuit 103 into a desired amplitude. The buffer circuit 109 outputs binary data input to the source line 114.

  Next, the circuit newly added in this embodiment, the third latch circuit 104, the exclusive OR circuit 105, the first level shifter circuit 107, the first transmission gate 112, and the second transmission gate 113 will be described. do.

  In the third latch circuit 104, after the latch pulse (LATa) is input to the second latch circuit 103, the latch pulse (LATb) is input and the video signals (LAT3-1, LAT3-2, LAT3-3) are input. , LAT3-4,..., LAT3-N) are output. The output data of the third latch circuit 104 is equal to the output data of the second latch circuit 103 delayed by approximately the same time as the delay time from the latch pulse (LATa) to the latch pulse (LATb). Assuming that the output of the second latch circuit 103 is the current row (m row) data, the third latch circuit 104 is in the previous row (m−) during the period from the latch pulse (LATa) input to the latch pulse (LATb) input. 1 line) of data is output.

  In the exclusive OR circuit 105, the output signal of the second latch circuit 103 and the output signal of the third latch circuit 104 are compared, and signals (Ex.OR-1, Ex.OR-2, Ex.OR--) are compared. 3, Ex.OR −4,,,,, Ex.OR −N). The signals (Ex.OR-1, Ex.OR-2, Ex.OR-3, Ex.OR-4,,,,, Ex.OR-N) are output signals of the second latch circuit 103 and the third signal. When the output signal of the latch circuit 104 is different, such as a high potential and a low potential, or a low potential and a high potential, it becomes a high potential, and when the output signal is the same, such as a high potential and a high potential, or a low potential and a low potential, the low potential. It becomes.

  A circuit 106 that compares the data in the previous row (m−1 row) and the data in the current row (m row) includes a third latch circuit 104 and an exclusive OR circuit 105. In the period from the input of the latch pulse (LATa) to the input of the latch pulse (LATb), the circuit 106 that compares the data of the previous row (m−1 row) and the data of the current row (m row) is the previous row (m− When the data of the present row (m-th row) changes from the High potential to the Low potential or from the Low potential to the High potential, the High potential is output. On the contrary, in the period from the input of the latch pulse (LATa) to the input of the latch pulse (LATb), the data of the previous row (m−1 row) to the data of this row (m row) are changed from the High potential to the High potential or Low. When the potential does not change like the low potential, the low potential is output. Also, an exclusive OR circuit that compares the data of the previous row (m−1 row) and the data of this row (m row) in the period from the input of the latch pulse (LATb) to the input of the next latch pulse (LATa). 105 always outputs a low potential.

  In the first level shifter circuit 107, the signal (Ex.OR-1, Ex.OR-2, Ex.OR-3, Ex.OR-4,,,,,, Ex.OR-N) is transmitted to a desired amplitude. Convert to

  The timing for cutting off the source line 114 and the buffer circuit 109 by the first transmission gate 112 will be described. All the source lines 114 and the buffer circuit 109 are interrupted once by the first transmission gate 112 after the writing of the previous row (m−1 row) is completed. As a result, each source line is disconnected from the external positive power source 110 and negative power source 111. The timing for connecting the source line 114 and the buffer circuit 109 will be described later.

  In the period from the input of the latch pulse (LATa) to the input of the latch pulse (LATb) after the cutoff timing of the source line 114 and the buffer circuit 109, the second transmission gate 113 is connected to the previous row (m−1 row). ) And the source line 114 (S1, S2, S3,..., SN-1, SN) in which the data of this bank (m line) are different are connected. At this time, the source line 114 in which the data in the previous row (m−1 row) is the High potential and the data in the current row (m row) is the Low potential as shown in S1 in FIG. −1 row) data is low potential and the current (m row) data is high potential source line 114 and each load capacitor 115 has a positive power source 110 of a buffer circuit as an external power source. Some intermediate potential is precharged without using the negative power supply 111 of the buffer circuit. On the contrary, when the data of the previous row (m−1 row) and the data of this row (m row) are the same, the second transmission gate 113 is connected to the source lines 114 (S1, S2, S3,. , SN-1, SN) are not connected. In the period from the input of the latch pulse (LATb) to the input of the next latch pulse (LATa), the second transmission gate 113 is connected to the source lines 114 (S1, S2, S3,. SN-1, SN) is blocked.

  After the precharge is performed, the source line 114 and the buffer circuit 109 are connected by the first transmission gate 112. Thereby, each source line is electrically connected to the external positive power source 110 and the negative power source 111. Simultaneously with this connection, the current line (m line) data is input to the source line 114. At this time, since the battery is precharged to a certain intermediate potential in advance, the power consumed for charging is reduced as compared with the conventional configuration.

  An arbitrary image can be displayed by repeating the above operation for each row.

  According to the display device and the driving method of the present invention configured as described above, an image or a line that requires a large number of gradations, such as a natural image, in which a large amount of power is consumed in the conventional display device. Even in a special pattern in which the logic is frequently reversed, it is possible to display with a small amount of power because the power of the external power source is not consumed for charging and discharging up to the intermediate potential.

  An example of the special pattern is shown in FIG. Reference numerals 601, 604, and 607 denote pixel portions, 602, 605, and 608 denote source line driver circuits, and 603, 606, and 609 denote gate line driver circuits.

  Among the special patterns in which the logic is frequently inverted for each row, in the 1 dot lattice shown in FIG. The line is different from the data in the previous row (m-1 row) and the data in this row (m row), and half of all the source lines are high potential in the previous row (m-1 row), and the remaining half of the sources The line is at the low potential in the previous row (m−1 row). For this reason, according to the display device and the driving method of the present invention configured as described above, the power of the external power source is not consumed for charging / discharging up to the intermediate potential for each row. A special pattern can be displayed.

  Among the special patterns in which the logic is frequently reversed for each row, in the display such as the horizontal stripe displayed only by the straight line parallel to the gate line shown in FIG. The source lines in which the data in the (m-1 row) and the data in the current row (m row) are different are all at the same potential in the previous row (m-1 row). For this reason, even with the display device and the driving method of the present invention configured as described above, charging / discharging up to an intermediate potential is not performed, but there is no problem because power consumption is the same as that of a conventional display device.

  In an image that requires a large number of gradations such as the natural image shown in FIG. 6C, there are source lines in which the data of the previous row (m-1 row) and the data of this row (m row) are different. Often to do. Further, in an image that requires a large number of gradations such as a natural image, at least one source line of the source lines in which the data in the previous row (m−1 row) and the data in the current row (m row) are different is the previous one. In many cases, the row (m−1 row) has a high potential, and at least one source line has a low potential in the previous row (m−1 row). According to the display device and the driving method of the present invention configured as described above, at least one of the source lines in which the data in the previous row (m−1 row) and the data in the current row (m row) are different is the previous one. When the row (m−1 row) has a high potential and at least one source line has a low potential in the previous row (m−1 row), the power of the external power source is used for charging and discharging up to the intermediate potential. Do not consume. Conversely, when there is no source line in which the data of the previous row (m-1 row) and the data of this row (m row) are different, or the data of this row (m row) is changed from the data of the previous row (m-1 row). When there is only a source line that changes from a High potential to a Low potential, or when there is only a source line that changes data from the previous row (m−1 row) to the current row (m row) from a Low potential to a High potential. However, charging / discharging up to the intermediate potential is not performed, but power consumption is the same as that of the conventional display device. Therefore, according to the display device and the driving method of the present invention configured as described above, an image that requires a large number of gradations such as a natural image can be displayed with less power.

(Embodiment 2)
FIG. 3 is a block diagram showing a line-sequential source line driver circuit used in the display device of the present invention and having a configuration different from that of the first embodiment. Similar to the conventional line-sequential type shown in FIG. 5, the shift register 301, the first latch circuit 302, the second latch circuit 303, the second level shifter circuit 308, and the buffer circuit 309 are provided. Although not shown, the pixel portion has pixels of M rows and N columns, and has M gate lines and N source lines. Similarly to the circuit shown in FIG. 5, it also has a gate line driver circuit having a shift register, a level shifter, and a buffer. In the pixel portion, a TFT, a pixel electrode, a light emitting element, or a liquid crystal element is provided at an intersection of the gate line and the source line.

  The output terminal of the second latch circuit 303 is connected to the third latch circuit 304 and the exclusive OR circuit 305 in addition to the connection to the second level shifter circuit 308. A circuit 306 for comparing the data of the previous row (m−1 row) and the data of this row (m row) is composed of a third latch circuit 304 and an exclusive OR circuit 305. The output terminal of the third latch circuit 304 is connected to the exclusive OR circuit 305. The output terminal of the exclusive OR circuit 305 is connected to the first level shifter circuit 307. The output terminal of the first level shifter circuit 307 is connected to the Pch TFT side gate terminal of the first transmission gate 312 and the Nch TFT side gate terminal of the second transmission gate 313. The output terminal of the buffer circuit 309 is electrically connected to the source line 314 through the first transmission gate 312. The respective source lines 314 (S1, S2, S3,..., Sn-1, Sn) can be electrically connected via the second transmission gate 313.

  The operation will be described. Shift register 301, first latch circuit 302, second latch circuit 303, third latch circuit 304, first level shifter circuit 307, second level shifter circuit 308, buffer circuit 309, exclusive OR circuit 305, The second transmission gate 313 operates in the same manner as in the first embodiment.

  Although an exclusive OR circuit and a transmission gate are used here, the present invention is not limited to this. A circuit having an arbitrary comparison function and a circuit having a switch function can be used.

  In the period from the input of the latch pulse (LATa) to the input of the latch pulse (LATb), the first transmission gate 312 has different sources for the previous row (m−1 row) data and the current row (m row) data. Only the line 314 and the buffer circuit 309 are cut off. As a result, the source line is disconnected from the power supply circuit. At the same time, in the period from the input of the latch pulse (LATa) to the input of the latch pulse (LATb), the second transmission gate 313 has the previous row (m-1 row) data and the current row (m row) data. Are connected to each other (S1, S2, S3,..., SN-1, SN). At this time, the source line 314 in which the data in the previous row (m−1 row) is the high potential and the data in the current row (m row) is the low potential as shown in S1 in FIG. -1 row) data and the source line 314 in which the current row (m row) data is at a high potential, and the load capacitor 315 has a positive power supply 310 and a buffer of a buffer circuit as an external power supply. Some intermediate potential is precharged without using the negative power supply 311 of the circuit. On the contrary, when the data of the previous row (m−1 row) and the data of this row (m row) are the same, the first transmission gate 312 connects the source line 314 and the buffer circuit 309, and the second The transmission gate 313 does not connect the source lines 314 (S1, S2, S3,..., SN-1, SN). In the period from the input of the latch pulse (LATb) to the input of the next latch pulse (LATa), the first transmission gate 312 keeps the source line 314 and the buffer circuit 309 connected. At the same time, in the period from the input of the latch pulse (LATb) to the input of the next latch pulse (LATa), the second transmission gate 313 is connected to the source lines 314 (S1, S2, S3,. -1, SN) is not connected.

  After the precharge, the current row (m row) data is input to the source line 314. At this time, since the battery is precharged to a certain intermediate potential in advance, the power consumed by the external power supply for charging is reduced as compared with the conventional configuration.

  An arbitrary image can be displayed by repeating the above operation for each row.

  In the present embodiment, the first transmission gate 312 is controlled in accordance with the output of the circuit 106 that compares the data of the previous row (m−1 row) and the data of this row (m row). Therefore, it is not necessary to externally input a signal for controlling the first transmission gate 312. This contributes to a reduction in the number of input pins to the panel. In a display device used for a portable information terminal or the like, the reduction in the number of input pins is very effective for reducing the panel size.

  According to the display device and the driving method of the present invention configured as described above, an image or a line that requires a large number of gradations, such as a natural image, in which a large amount of power is consumed in the conventional display device. Even in a special pattern in which the logic is frequently reversed, it is possible to display with a small amount of power because the power of the external power source is not consumed for charging and discharging up to the intermediate potential.

  Among the special patterns in which the logic is frequently inverted for each row, in the 1 dot lattice shown in FIG. The line is different from the data in the previous row (m-1 row) and the data in this row (m row), and half of all the source lines are high potential in the previous row (m-1 row), and the remaining half of the sources The line is at the low potential in the previous row (m−1 row). For this reason, according to the display device and the driving method of the present invention configured as described above, the power of the external power source is not consumed for charging / discharging up to the intermediate potential for each row. A special pattern can be displayed.

  Among the special patterns in which the logic is frequently reversed for each row, in the display such as the horizontal stripe displayed only by the straight line parallel to the gate line shown in FIG. The source lines in which the data in the (m-1 row) and the data in the current row (m row) are different are all at the same potential in the previous row (m-1 row). For this reason, even with the display device and the driving method of the present invention configured as described above, charging / discharging up to an intermediate potential is not performed, but there is no problem because power consumption is the same as that of a conventional display device.

  In an image that requires a large number of gradations such as the natural image shown in FIG. 6C, there are source lines in which the data of the previous row (m-1 row) and the data of this row (m row) are different. Often to do. Further, in an image that requires a large number of gradations such as a natural image, at least one source line of the source lines in which the data in the previous row (m−1 row) and the data in the current row (m row) are different is the previous one. In many cases, the row (m−1 row) has a high potential, and at least one source line has a low potential in the previous row (m−1 row). According to the display device and the driving method of the present invention configured as described above, at least one of the source lines in which the data in the previous row (m−1 row) and the data in the current row (m row) are different is the previous one. When the row (m−1 row) has a high potential and at least one source line has a low potential in the previous row (m−1 row), the power of the external power source is used for charging and discharging up to the intermediate potential. Do not consume. Conversely, when there is no source line in which the data of the previous row (m-1 row) and the data of this row (m row) are different, or the data of this row (m row) is changed from the data of the previous row (m-1 row). When there is only a source line that changes from a High potential to a Low potential, or when there is only a source line that changes data from the previous row (m−1 row) to the current row (m row) from a Low potential to a High potential. However, charging / discharging up to the intermediate potential is not performed, but power consumption is the same as that of the conventional display device. Therefore, according to the display device and the driving method of the present invention configured as described above, an image that requires a large number of gradations such as a natural image can be displayed with less power.

(Embodiment 3)
In this embodiment mode, an example of manufacturing a dual emission display device that can be used in the present invention will be described.

  First, as shown in FIG. 7A, a base film 1501 is formed over a substrate 1500. As the substrate 1500, for example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a stainless steel substrate, or the like can be used. It is also possible to use a substrate made of a plastic such as PET, PES, or PEN, or a flexible synthetic resin such as acrylic.

  The base film 1501 is provided to prevent alkali metal such as Na or alkaline earth metal contained in the substrate 1500 from diffusing into the semiconductor film and adversely affecting the characteristics of the semiconductor element. Therefore, an insulating film such as silicon nitride or silicon oxide containing nitrogen that can suppress diffusion of alkali metal or alkaline earth metal into the semiconductor film is used. In this embodiment, a silicon oxide film containing nitrogen is formed to a thickness of 10 nm to 400 nm (preferably 50 nm to 300 nm) by a plasma CVD method.

  Note that even though the base film 1501 is a single layer of an insulating film such as silicon nitride, silicon oxide containing nitrogen, or silicon nitride containing oxygen, insulation such as silicon oxide, silicon nitride, silicon oxide containing nitrogen, or silicon nitride containing oxygen is used. A plurality of laminated films may be used.

  Next, a semiconductor film 1502 is formed over the base film 1501. The thickness of the semiconductor film 1502 is 25 nm to 100 nm (preferably 30 nm to 60 nm). Note that the semiconductor film 1502 may be an amorphous semiconductor or a polycrystalline semiconductor. As the semiconductor, not only silicon (Si) but also silicon germanium (SiGe) can be used. When silicon germanium is used, the concentration of germanium is preferably about 0.01 to 4.5 atomic%.

  Next, as shown in FIG. 7B, the semiconductor film 1502 is irradiated with a linear laser 1499 to be crystallized. In the case of performing laser crystallization, heat treatment for 1 hour at 500 ° C. may be applied to the semiconductor film 1502 in order to increase the resistance of the semiconductor film 1502 to the laser before laser crystallization.

  As a method for crystallizing, a method of irradiating with laser light, a method of crystallizing by heating with an element that promotes crystallization of a semiconductor film, a crystal by heating with an element that promotes crystallization of a semiconductor film Then, a method of irradiating with laser light can be used. Here, it is crystallized by irradiation with laser light.

  For laser crystallization, a pulsed laser having an oscillation frequency of 10 MHz or more, preferably 80 MHz or more can be used as a continuous wave laser or a pseudo CW laser.

Specifically, as a continuous wave laser, Ar laser, Kr laser, CO ₂ laser, YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, GdVO ₄ laser, Y ₂ O ₃ laser, ruby laser, alexandrite laser Ti: sapphire laser, helium cadmium laser, and the like.

As a pseudo CW laser, an Ar laser, a Kr laser, an excimer laser, a CO ₂ laser, a YAG laser, a YVO4 laser, a YLF laser, a YAlO can be used as long as it can oscillate a pulse having an oscillation frequency of 10 MHz or more, preferably 80 MHz or more. A pulsed laser such as a ₃ laser, a GdVO ₄ laser, a Y ₂ O ₃ laser, or a ruby laser can be used.

  Such a pulsed laser has an effect equivalent to that of a continuous wave laser as the oscillation frequency is increased.

For example, when a solid-state laser capable of continuous oscillation is used, a crystal having a large grain size can be obtained by irradiating laser light of second to fourth harmonics. Typically, it is desirable to use the second harmonic (532 nm) or the third harmonic (355 nm) of a YAG laser (fundamental wave 1064 nm). Power density may be about 0.01 to 100 MW / cm ² (preferably 0.1~10MW / cm ^2).

  By irradiation of the semiconductor film 1502 with laser light, the crystalline semiconductor film 1504 with high crystallinity is formed.

  Next, as illustrated in FIG. 7C, the crystalline semiconductor film 1504 is etched, so that island-shaped semiconductor films 1507 to 1509 are formed.

Next, impurities for controlling the threshold value of the TFT are introduced into the island-shaped semiconductor films 1507 to 1509. In this embodiment mode, boron (B) is introduced into the island-shaped semiconductor film by doping diborane (B ₂ H ₆ ).

  Next, an insulating film 1700 is formed so as to cover the island-shaped semiconductor films 1507 to 1509 (FIG. 8A). For the insulating film 1700, for example, silicon oxide, silicon nitride, silicon oxide containing nitrogen, or the like can be used. As a film formation method, a plasma CVD method, a sputtering method, or the like can be used.

  Next, after a conductive film is formed over the insulating film 1700, the conductive film is etched, so that gate electrodes 1707 to 1709 are formed.

  The gate electrodes 1707 to 1709 are formed using a structure in which a single conductive film or two or more conductive films are stacked. In the case where two or more conductive films are stacked, an element selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), and aluminum (Al), or the element as a main component The gate electrodes 1707 to 1709 may be formed by stacking alloy materials or compound materials to be stacked. Alternatively, the gate electrode may be formed using a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus (P).

  In this embodiment, gate electrodes 1707 to 1709 are formed using a stacked film in which tantalum nitride and tungsten (W) are stacked to have a thickness of 30 nm and 370 nm, respectively. In this embodiment mode, upper layer gate electrodes 1701 to 1703 are formed using tungsten (W), and lower layer gate electrodes 1704 to 1706 are formed using tantalum nitride.

  The gate electrodes 1707 to 1709 may be formed as part of the gate wiring, or a gate wiring may be formed separately and the gate electrodes 1707 to 1709 may be connected to the gate wiring.

  Then, an impurity imparting n-type or p-type conductivity is added to the island-shaped semiconductor films 1507 to 1509 using the gate electrodes 1707 to 1709 or a resist film formed and selectively exposed as a mask. Then, a source region, a drain region, a low concentration impurity region, and the like are formed.

First, phosphorus (P) is introduced into the island-shaped semiconductor film using phosphine (PH ₃ ) with an acceleration voltage of 60 to 120 kV and a dose of 1 × 10 ¹³ to 1 × 10 ¹⁵ atoms · cm ⁻² .

Further, in order to manufacture a p-channel TFT, diborane (B ₂ H ₆ ) is applied with an applied voltage of 60 to 100 kV, for example, 80 kV, and a dose amount of 1 × 10 ^{13 to} 5 × 10 ¹⁵ atoms · cm ⁻² , for example, 3 × 10 ^15. Boron (B) is introduced into the island-shaped semiconductor film under the condition of atoms · cm ⁻² . Thus, a source region or a drain region 1717 of the p-channel TFT 1763 and a channel formation region 1718 are formed (FIG. 8B).

  Next, the insulating film 1700 is etched to form gate insulating films 1721 to 1723. As a result, a part of the semiconductor film is exposed.

An applied voltage of 40 to 80 kV, for example, 50 kV, a dose of 1.0 × 10 ^{15 to} 2.5 × 10 ^{16 is} applied to the island-shaped semiconductor films 1507 and 1508 to be the n-channel TFTs 1761 and 1762 by using phosphine (PH ₃ ). Phosphorus (P) is introduced at atoms · cm ⁻² , for example, 3.0 × 10 ¹⁵ atoms · cm ⁻² . Thus, channel formation regions 1713 and 1716, low-concentration impurity regions 1712 and 1715, and source or drain regions 1711 and 1714 of n-channel TFTs 1761 and 1762 are formed (FIG. 8B).

In this embodiment mode, the source or drain regions 1711 and 1714 of the n-channel TFTs 1761 and 1762 each contain phosphorus (P) at a concentration of 1 × 10 ^{19 to} 5 × 10 ²¹ atoms · cm ^−3. Will be. Each of the low-concentration impurity regions 1712 and 1715 of the n-channel TFTs 1761 and 1762 contains phosphorus (P) at a concentration of 1 × 10 ^{18 to} 5 × 10 ¹⁹ atoms · cm ⁻³ . Further, the source region or the drain region 1717 of the p-channel TFT 1763 contains boron (B) at a concentration of 1 × 10 ^{19 to} 5 × 10 ²¹ atoms · cm ⁻³ .

  In this embodiment mode, the p-channel TFT 1762 is used as a pixel TFT of the dual emission display device. Further, the n-channel TFTs 1761 and 1762 are used as TFTs of a driving circuit that drives the pixel TFT 1762. However, the pixel TFT is not necessarily a p-channel TFT, and an n-channel TFT may be used. In addition, the driving circuit does not have to be a circuit in which a plurality of n-channel TFTs are combined. May be.

  Next, an insulating film 1730 containing hydrogen is formed. As the insulating film containing hydrogen, a silicon oxide film containing nitrogen obtained by a PCVD method is used. Alternatively, a silicon nitride film containing oxygen (SiNO film) may be used. Note that the insulating film 1730 containing hydrogen is a first interlayer insulating film and a light-transmitting insulating film containing silicon oxide.

  Thereafter, the impurity element added to the island-like semiconductor film is activated. The activation of the impurity element may be performed by laser beam irradiation, RTA, or heating in a nitrogen atmosphere at 550 ° C. for 4 hours to activate the impurity. In the case where the semiconductor film is crystallized using a metal element that promotes crystallization, typically nickel, gettering that reduces nickel in the channel formation region at the same time as activation can be performed.

  Thereafter, the whole is heated at 410 ° C. for 1 hour to hydrogenate the island-shaped semiconductor film. However, it is not necessary when heat treatment is performed at 550 ° C. for 4 hours in a nitrogen atmosphere as described above.

Next, a planarization film to be the second interlayer insulating film 1731 is formed. As the planarizing film, a light-transmitting inorganic material (silicon oxide, silicon nitride, silicon nitride containing oxygen, etc.), a photosensitive or non-photosensitive organic material (polyimide, acrylic, polyamide, polyimide amide, resist or benzo Cyclobutene) or a laminate of these. In addition, other light-transmitting films used for the planarizing film include insulating films made of SiO _x films containing alkyl groups obtained by a coating method, such as silica glass, alkylsiloxane polymers, alkylsilsesquioxane polymers, An insulating film formed using a hydrogenated silsesquioxane polymer, a hydrogenated alkylsilsesquioxane polymer, or the like can be used. Examples of the siloxane polymer include PSB-K1 and PSB-K31, which are Toray-made coating insulating film materials, and ZRS-5PH, which is a catalytic chemical coating insulating film material.

  Next, a third interlayer insulating film 1732 having a light-transmitting property is formed. The third interlayer insulating film 1732 is provided as an etching stopper film for protecting the planarizing film that is the second interlayer insulating film 1731 when the transparent electrode 1750 is etched in a later step. However, when the transparent electrode 1750 is etched, the third interlayer insulating film 1732 is not necessary if the second interlayer insulating film 1731 becomes an etching stopper film.

Next, contact holes are formed in the first interlayer insulating film 1730, the second interlayer insulating film 1731, and the third interlayer insulating film 1732 using a new mask. Next, after removing the mask and forming a conductive film (a laminated film of titanium nitride, aluminum and titanium nitride), etching (dry etching with a mixed gas of BCl ₃ and Cl ₂ ) is performed using another mask. Then, electrodes or wirings 1741 to 1745 (TFT source wiring and drain wiring, current supply wiring, and the like) are formed (FIG. 8C). However, although the electrode and the wiring are integrally formed in this embodiment mode, the electrode and the wiring may be separately formed and electrically connected. Titanium nitride is one of materials that have good adhesion to the high heat resistant planarization film. In addition, the N content of titanium nitride is preferably less than 44 atomic% in order to make good ohmic contact with the source region or drain region of the TFT.

  Next, the transparent electrode 1750, that is, the anode of the organic light emitting element is formed in a thickness of 10 nm to 800 nm using a new mask. The transparent electrode 1750 was formed using, in addition to indium tin oxide (ITO), for example, a target in which 2 to 20 wt% zinc oxide (ZnO) was mixed with indium tin oxide containing Si element or indium oxide. A transparent conductive material having a high work function (work function of 4.0 eV or more) such as IZO (Indium Zinc Oxide) can be used (FIG. 9A).

Next, an insulator 1733 (referred to as a partition wall, a barrier, or the like) that covers an end portion of the transparent electrode 1750 is formed using a new mask. As the insulator 1733, a photosensitive or non-photosensitive organic material (polyimide, acrylic, polyamide, polyimide amide, resist or benzocyclobutene) obtained by a coating method, or an SOG film (for example, an SiO _x film containing an alkyl group) ) Is used in a thickness range of 0.8 μm to 1 μm.

Next, a first layer 1751, a second layer 1752, a third layer 1753, a fourth layer 1754, and a fifth layer 1755 that form a light-emitting element are formed by an evaporation method or a coating method. Note that in order to improve the reliability of the light-emitting element, it is preferable to perform deaeration by performing vacuum heating before the formation of the layer 1751 containing an organic compound. For example, before vapor deposition of the organic compound material, it is desirable to perform a heat treatment at 200 ° C. to 300 ° C. in a reduced pressure atmosphere or an inert atmosphere in order to remove gas contained in the substrate. In the case where the interlayer insulating film and the partition wall are formed of SiO _x films having high heat resistance, higher heat treatment (for example, 410 ° C.) can be applied.

  Molybdenum oxide (MoOx), 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (α-NPD) selectively on the transparent electrode 1750 using a vapor deposition mask Then, rubrene is co-evaporated to form a layer (first layer) 1751 containing an organic compound.

In addition to MoOx, copper phthalocyanine (CuPC), vanadium oxide (VOx),
A material having a high hole-injection property such as ruthenium oxide (RuOx) or tungsten oxide (WOx) can be used. In addition, a material in which a high hole-injection polymer material such as poly (ethylenedioxythiophene) / poly (styrenesulfonic acid) aqueous solution (PEDOT / PSS) is used as a first layer 1751 is formed by a coating method. Also good.

  Next, α-NPD is selectively deposited using a deposition mask, so that a hole-transporting layer (second layer) 1752 is formed over the first layer 1751. In addition to α-NPD, 4,4′-bis [N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD), 4,4 ′, 4 ″ -tris (N , N-diphenyl-amino) -triphenylamine (abbreviation: TDATA), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: A material having a high hole transporting property typified by an aromatic amine compound such as MTDATA) can be used.

  Next, a light-emitting layer 1753 (third layer) is selectively formed. In order to obtain a full-color display device, the vapor deposition mask is aligned for each of the emission colors (R, G, B) to selectively deposit each.

For the light-emitting layer 1753R that emits red light, a material such as Alq ₃ : DCM or Alq ₃ : rubrene: BisDCJTM is used. For the light-emitting layer 1753G that emits green light, a material such as Alq ₃ : DMQD (N, N′-dimethylquinacridone) or Alq ₃ : coumarin 6 is used. For the light-emitting layer 1753B that emits blue light, a material such as α-NPD or tBu-DNA is used.

Next, Alq ₃ (tris (8-quinolinolato) aluminum) is selectively evaporated using an evaporation mask, so that an electron-transporting layer (fourth layer) 1754 is formed over the light-emitting layer 1753. In addition to Alq ₃ , tris (5-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo [h] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl) A material having a high electron transport property typified by a metal complex having a quinoline skeleton such as -8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq) or a benzoquinoline skeleton can be used. In addition, bis [2- (2-hydroxyphenyl) -benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) -benzothiazolate] zinc (abbreviation: Zn ( A metal complex having an oxazole-based or thiazole-based ligand such as BTZ) ₂ ) can also be used. In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5 -(P-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl-5 (4-Biphenylyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2 1, 4-triazole (abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), and the like can also be used as the electron-transport layer 1754 because of their high electron-transport properties.

Next, 4,4-bis (5-methylbenzoxazol-2-yl) stilbene (abbreviation: BzOs) and lithium (Li) are co-evaporated to cover the electron transport layer and the insulator, and an electron injection layer is formed over the entire surface. (Fifth layer) 1755 is formed. By using the benzoxazole derivative (BzOS), damage due to the sputtering method at the time of forming the transparent electrode 1756 performed in a later process is suppressed. In addition to BzOs: Li, a material having a high electron-injection property such as an alkali metal or alkaline earth metal compound such as CaF ₂ , lithium fluoride (LiF), and cesium fluoride (CsF) can be used. . In addition, a mixture of Alq ₃ and magnesium (Mg) can also be used.

  Next, a transparent electrode 1756, that is, a cathode of the organic light emitting element is formed in a thickness range of 10 nm to 800 nm on the electron injection layer (fifth layer) 1755. In addition to indium tin oxide (ITO), the transparent electrode 1756 is formed using, for example, a target in which 2 to 20 wt% zinc oxide (ZnO) is mixed with indium tin oxide containing Si element or indium oxide. IZO (Indium Zinc Oxide) can be used.

  As described above, a light emitting element is manufactured. The materials for the anode, the layer containing the organic compound (first to fifth layers), and the cathode constituting the light-emitting element are appropriately selected, and the thicknesses of the materials are also adjusted. It is desirable that the same material is used for the anode and the cathode, and the film thickness is approximately the same, preferably approximately 100 nm.

Further, if necessary, a transparent protective layer 1757 which covers the light emitting element and prevents moisture from entering is formed. As the transparent protective layer 1757, a silicon nitride film, a silicon oxide film, a silicon nitride film containing oxygen (SiN _x O _y film (x>y> 0)) or a silicon oxide film containing nitrogen obtained by a sputtering method or a CVD method is used. (SiO _x N _y film (x>y> 0)), a thin film mainly containing carbon (for example, a DLC film or a CN film), or the like can be used (FIG. 9B).

  Next, the second substrate 1770 and the substrate 1500 are attached to each other using a sealant containing a gap material for securing the gap between the substrates. The second substrate 1770 may also be a light-transmitting glass substrate or quartz substrate. In addition, a desiccant may be disposed as a gap (inert gas) between the pair of substrates, or a transparent sealing material (such as an ultraviolet curing or thermosetting epoxy resin) is filled between the pair of substrates. (FIG. 10).

  In the light emitting element, since the transparent electrodes 1750 and 1756 are formed of a light-transmitting material, light can be taken from one light emitting element in two directions, that is, from both sides.

  With the panel configuration described above, light emission from the upper surface and light emission from the lower surface can be made substantially the same.

  Finally, optical films (polarizing plates or circularly polarizing plates) 1771 and 1772 are provided to improve contrast (FIG. 10).

  FIG. 11 is a cross-sectional view of a light emitting element for each emission color (R, G, B). The red (R) light-emitting element includes a pixel TFT 1763R, a transparent electrode (anode) 1750R, a first layer 1751R, a second layer (hole transport layer) 1752R, a third layer (light-emitting layer) 1753R, and a fourth layer. A layer (electron transport layer) 1754R, a fifth layer (electron injection layer) 1755, a transparent electrode (cathode) 1756, and a transparent protective layer 1757;

  The green (G) light-emitting element includes a pixel TFT 1763G, a transparent electrode (anode) 1750G, a first layer 1751G, a second layer (hole transport layer) 1752G, a third layer (light-emitting layer) 1753G, A fourth layer (electron transport layer) 1754G, a fifth layer (electron injection layer) 1755, a transparent electrode (cathode) 1756, and a transparent protective layer 1757.

  Further, the blue (B) light-emitting element includes a pixel TFT 1763B, a transparent electrode (anode) 1750B, a first layer 1751B, a second layer (hole transport layer) 1752B, a third layer (light-emitting layer) 1753B, A fourth layer (electron transport layer) 1754B, a fifth layer (electron injection layer) 1755, a transparent electrode (cathode) 1756, and a transparent protective layer 1757.

  Note that in this embodiment mode, the TFT is a top gate type TFT, but the present invention is not limited to this structure, and a bottom gate type (reverse stagger type) TFT or a stagger type TFT can be used as appropriate. . Further, the TFT is not limited to a single-gate TFT, and may be a multi-gate TFT having a plurality of channel formation regions, for example, a double-gate TFT.

(Embodiment 4)
As an electronic device to which the present invention is applied, a video camera, a digital camera, a goggle type display, a navigation system, a sound reproduction device (car audio component, etc.), a computer, a game device, a portable information terminal (mobile computer, cellular phone, portable type) A game machine or an electronic book), an image playback device provided with a recording medium (specifically, a device provided with a display capable of playing back a recording medium such as a Digital Versatile Disc (DVD) and displaying the image). It is done. Specific examples of these electronic devices are shown below.

  FIG. 12 shows a liquid crystal module or an EL module in which a display panel 5001 and a circuit board 5011 are combined. A circuit board 5011 is provided with a control circuit 5012, a signal dividing circuit 5013, and the like, and is electrically connected to the display panel 5001 through a connection wiring 5014.

  The display panel 5001 includes a pixel portion 5002 provided with a plurality of pixels, a scanning line driver circuit 5003, and a signal line driver circuit 5004 for supplying a video signal to the selected pixel. Note that in the case of manufacturing an EL module, the display panel 5001 may be manufactured using the above embodiment mode. Further, not only EL but also a liquid crystal module can be used. In addition, the control driver circuit portions such as the scan line driver circuit 5003 and the signal line driver circuit 5004 which are described in the above embodiment modes can be used. A liquid crystal television receiver or an EL television receiver can be completed with the liquid crystal module or the EL module shown in FIG.

  FIG. 13 is a block diagram illustrating a main configuration of a liquid crystal television receiver or an EL television receiver. A tuner 5101 receives a video signal and an audio signal. The video signal includes a video signal amplifying circuit 5102, a video signal processing circuit 5103 that converts a signal output from the video signal into a color signal corresponding to each color of red, green, and blue, and the video signal as input specifications of the driver IC. Processing is performed by a control circuit 5012 for conversion. The control circuit 5012 outputs a signal to each of the scanning line side and the signal line side. In the case of digital driving, a signal dividing circuit 5013 may be provided on the signal line side so that an input digital signal is divided into m pieces and supplied.

  Of the signals received by the tuner 5101, the audio signal is sent to the audio signal amplifier circuit 5105, and the output is supplied to the speaker 5107 through the audio signal processing circuit 5106. The control circuit 5108 receives control information on the receiving station (reception frequency) and volume from the input unit 5109 and sends a signal to the tuner 5101 and the audio signal processing circuit 5106.

  As shown in FIG. 14A, a television receiver can be completed by incorporating a liquid crystal module or an EL module into a housing 5201. A display screen 5202 is formed by a liquid crystal module or an EL module. In addition, a speaker 5203, an operation switch 5204, and the like are provided as appropriate.

  FIG. 14B shows a television receiver that can carry only a display wirelessly. A housing and a signal receiver are incorporated in the housing 5212, and the display portion 5213 and the speaker portion 5217 are driven by the battery. The battery can be repeatedly charged by a charger 5210. The charger 5210 can transmit and receive a video signal, and can transmit the video signal to a signal receiver of the display. The housing 5212 is controlled by operation keys 5216. The device illustrated in FIG. 14B can also be referred to as a video / audio two-way communication device because a signal can be sent from the housing 5212 to the charger 5210 by operating the operation key 5216. In addition, by operating the operation key 5216, a signal is transmitted from the housing 5212 to the charger 5210, and further, a signal that can be transmitted by the charger 5210 is received by another electronic device, thereby controlling communication of the other electronic device. It can be said to be a general-purpose remote control device. The present invention can be applied to the display portion 5213, a control circuit portion, and the like.

  By using the present invention for the television receiver shown in FIGS. 12 to 14, a television receiver with low power consumption can be manufactured.

  Of course, the present invention is not limited to a television receiver, and is applied to various uses as a display medium of a particularly large area such as a monitor of a personal computer, an information display board in a railway station or airport, an advertisement display board in a street, etc. can do.

  FIG. 15A shows a module in which a display panel 5301 and a printed wiring board 5302 are combined. The display panel 5301 includes a pixel portion 5303 provided with a plurality of pixels, a first scan line driver circuit 5304, a second scan line driver circuit 5305, and a signal line driver circuit that supplies a video signal to the selected pixel. 5306 is provided. The signal line driver circuit described in any of the above embodiments can be used.

  The printed wiring board 5302 is provided with a controller 5307, a central processing unit (CPU) 5308, a memory 5309, a power supply circuit 5310, an audio processing circuit 5311, a transmission / reception circuit 5312, and the like. The printed wiring board 5302 and the display panel 5301 are connected by a flexible wiring board (FPC) 5313. The printed wiring board 5302 may be provided with a capacitor, a buffer circuit, or the like so that noise is added to the power supply voltage or the signal or the rise of the signal is not slowed. The controller 5307, the audio processing circuit 5311, the memory 5309, the CPU 5308, the power supply circuit 5310, and the like can be mounted on the display panel 5301 using a COG (Chip On Glass) method. The scale of the printed wiring board 5302 can be reduced by the COG method.

  Various control signals are input and output through an interface (I / F) 5314 provided in the printed wiring board 5302. An antenna port 5315 for transmitting and receiving signals to and from the antenna is provided on the printed wiring board 5302.

  FIG. 15B shows a block diagram of the module shown in FIG. This module includes a VRAM 5316, a DRAM 5317, a flash memory 5318, and the like as the memory 5309. The VRAM 5316 stores image data to be displayed on the panel, the DRAM 5317 stores image data or audio data, and the flash memory 5318 stores various programs.

  The power supply circuit 5310 is connected to supply power for operating the display panel 5301, the controller 5307, the CPU 5308, the sound processing circuit 5311, the memory 5309, and the transmission / reception circuit 5312. Depending on the specifications of the panel, the power supply circuit 5310 may be provided with a current source.

  The CPU 5308 includes a control signal generation circuit 5320, a decoder 5321, a register 5322, an arithmetic circuit 5323, a RAM 5324, an interface 5319 for the CPU 5308, and the like. Various signals input to the CPU 5308 through the interface 5319 are temporarily held in the register 5322 and then input to the arithmetic circuit 5323, the decoder 5321, and the like. The arithmetic circuit 5323 performs an operation based on the input signal and designates a place to send various commands. On the other hand, the signal input to the decoder 5321 is decoded and input to the control signal generation circuit 5320. The control signal generation circuit 5320 generates a signal including various instructions based on the input signal, and a location designated by the arithmetic circuit 5323, specifically, a memory 5309, a transmission / reception circuit 5312, an audio processing circuit 5311, a controller 5307, and the like. Send to.

  The memory 5309, the transmission / reception circuit 5312, the sound processing circuit 5311, and the controller 5307 operate according to the received commands. The operation will be briefly described below.

  A signal input from an input unit 5325 such as a pointing device or a keyboard is sent to a CPU 5308 mounted on a printed wiring board 5302 via an interface (I / F) 5314. The control signal generation circuit 5320 converts the image data stored in the VRAM 5316 into a predetermined format according to a signal sent from the input unit 5325 such as a pointing device or a keyboard, and sends the image data to the controller 5307.

  The controller 5307 performs data processing on a signal including image data sent from the CPU 5308 in accordance with the specifications of the panel, and supplies the processed signal to the display panel 5301. In addition, the controller 5307 generates an Hsync signal (Horizontal Synchronizing signal), a Vsync signal (Vertical Synchronizing signal), a clock signal CLK, an AC signal, an AC signal based on the power supply voltage input from the power supply circuit 5310 and various signals input from the CPU 5308. AC Cont) and a switching signal L / R are generated and supplied to the display panel 5301.

  In the transmission / reception circuit 5312, signals transmitted / received as radio waves in the antenna 5328 are processed. Specifically, high-frequency signals such as an isolator, a band-pass filter, a VCO (Voltage Controlled Oscillator), an LPF (Low Pass Filter), a coupler, and a balun. Includes circuitry. A signal including audio information among signals transmitted and received in the transmission / reception circuit 5312 is sent to the audio processing circuit 5311 in accordance with a command from the CPU 5308.

  A signal including audio information sent in accordance with a command from the CPU 5308 is demodulated into an audio signal by the audio processing circuit 5311 and sent to the speaker 5327. An audio signal sent from the microphone 5326 is modulated in the audio processing circuit 5311 and sent to the transmission / reception circuit 5312 in accordance with a command from the CPU 5308.

  The controller 5307, the CPU 5308, the power supply circuit 5310, the sound processing circuit 5311, and the memory 5309 can be mounted as a package of this embodiment mode. This embodiment can be applied to any circuit other than a high-frequency circuit such as an isolator, a band-pass filter, a VCO (Voltage Controlled Oscillator), an LPF (Low Pass Filter), a coupler, and a balun.

  FIG. 16 illustrates one mode of a mobile phone including the module illustrated in FIGS. 15A to 15B. The display panel 5301 is incorporated in a housing 5330 so as to be detachable. The shape and size of the housing 5330 can be changed as appropriate in accordance with the size of the display panel 5301. The housing 5330 to which the display panel 5301 is fixed is fitted to the printed board 5331 and assembled as a module.

  The display panel 5301 is connected to the printed board 5331 through the FPC 5313. A signal processing circuit 5335 including a speaker 5332, a microphone 5333, a transmission / reception circuit 5334, a CPU, a controller, and the like is formed over the printed circuit board 5331. Such a module is combined with the input means 5336, the battery 5337, and the antenna 5340 and stored in the housing 5339. The pixel portion of the display panel 5301 is arranged so that it can be seen from an opening window formed in the housing 5339.

  The mobile phone according to the present embodiment can be transformed into various modes depending on the function and application. For example, the above-described effects can be obtained even when a plurality of display panels are provided, or the housing is divided into a plurality of cases and is opened and closed by a hinge.

  By using the present invention for the module shown in FIG. 15 and the mobile phone shown in FIG. 16, a mobile phone with low power consumption can be manufactured.

  FIG. 17A illustrates a liquid crystal display or an OLED display, which includes a housing 6001, a support base 6002, a display portion 6003, and the like. The structure of the liquid crystal module or the EL module illustrated in FIG. 12 and the display panel illustrated in FIG. 15A can be used for the display portion 6003.

  By using the present invention, a display with low power consumption can be manufactured.

  FIG. 17B illustrates a computer, which includes a main body 6101, a housing 6102, a display portion 6103, a keyboard 6104, an external connection port 6105, a pointing mouse 6106, and the like. The structure of the liquid crystal module or the EL module illustrated in FIG. 12 and the display panel illustrated in FIG. 15A can be applied to the display portion 6103.

  By using the present invention, a computer with low power consumption can be manufactured.

  FIG. 17C illustrates a portable computer, which includes a main body 6201, a display portion 6202, a switch 6203, operation keys 6204, an infrared port 6205, and the like. The structure of the liquid crystal module or the EL module illustrated in FIG. 12 and the display panel illustrated in FIG. 15A can be used for the display portion 6202.

  By using the present invention, a computer with low power consumption can be manufactured.

  FIG. 17D illustrates a portable game machine including a housing 6301, a display portion 6302, speaker portions 6303, operation keys 6304, a recording medium insertion portion 6305, and the like. The structure of the liquid crystal module or the EL module illustrated in FIG. 12 and the display panel illustrated in FIG. 15A can be used for the display portion 6302.

  By using the present invention, a game machine with low power consumption can be manufactured.

  FIG. 17E illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 6401, a housing 6402, a display portion A 6403, a display portion B 6404, and a recording medium (such as a DVD). A reading unit 6405, operation keys 6406, a speaker unit 6407, and the like are included. The display portion A 6403 mainly displays image information, and the display portion B 6404 mainly displays character information. The structure of the liquid crystal module or the EL module illustrated in FIG. 12 and the display panel illustrated in FIG. 15A can be applied to the display portion A 6403, the display portion B 6404, a control circuit portion, and the like. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.

  By using the present invention, an image reproducing device with low power consumption can be manufactured.

  Display devices used in these electronic devices can use not only a glass substrate but also a heat-resistant plastic substrate depending on the size, strength, or purpose of use. As a result, the weight can be reduced.

  Note that the example shown in the present embodiment is only an example, and is not limited to these applications.

  This embodiment mode can be implemented freely combining with any description in the above embodiment modes.

The figure which shows the circuit diagram of one Embodiment of this invention. The figure which shows the timing chart of one Embodiment of this invention. The figure which shows the circuit diagram of other embodiment of this invention. The figure which shows the timing chart of other embodiment of this invention. The figure which shows the structure of the conventional line sequential type display apparatus. The figure which shows a display pattern. 8A and 8B illustrate a manufacturing process of an EL display device. 8A and 8B illustrate a manufacturing process of an EL display device. 8A and 8B illustrate a manufacturing process of an EL display device. 8A and 8B illustrate a manufacturing process of an EL display device. 8A and 8B illustrate a manufacturing process of an EL display device. FIG. 11 illustrates an example of an electronic device to which the present invention is applied. FIG. 11 illustrates an example of an electronic device to which the present invention is applied. FIG. 11 illustrates an example of an electronic device to which the present invention is applied. FIG. 11 illustrates an example of an electronic device to which the present invention is applied. FIG. 11 illustrates an example of an electronic device to which the present invention is applied. FIG. 11 illustrates an example of an electronic device to which the present invention is applied.

Explanation of symbols

Reference Signs List 101 shift register 102 first latch circuit 103 second latch circuit 104 third latch circuit 105 exclusive OR circuit 106 circuit for comparing data in the previous row (m-1 row) and data in this row (m row) 107 first level shifter circuit 108 second level shifter circuit 109 buffer circuit 110 positive power supply 111 negative power supply 112 first transmission gate 113 second transmission gate 114 source line 115 load capacitance

Claims (2)

M rows and N columns (M and N are natural numbers, respectively),
M gate lines, N source lines,
A first circuit and a second circuit; and a first switch and a second switch;
The first circuit has a function of storing a digital data signal of the (m−1) th row (2 ≦ m ≦ M, m is a natural number),
The second circuit has a function of comparing the digital data signal of the (m−1) th row stored in the first circuit and the digital data signal of the mth row,
The first switch has a function of electrically cutting off the source line and a wiring having a function of supplying a power supply voltage;
In a period in which wiring and having a function of supplying the power supply voltage and the source line is electrically disconnected, the second switch, the digital data signal compared with the second circuit different for Luso over Has the function of electrically connecting the wires together,
After the period, the first switch electrically connects the cut-off source line and a wiring having a function of supplying the power supply voltage, and connects the connected source line to the m-th row. display device, characterized in that it have the function of inputting the digital data signal. It has pixels of M rows and N columns (M and N are natural numbers, respectively)
In a display device having M gate lines and N source lines,
(M-1) inputting a digital data signal of the row (2 ≦ m ≦ M, m is a natural number) to the source line;
Electrically disconnecting the source line from a power circuit;
comparing the m-th row digital data signal with the (m−1) -th row digital data signal before inputting the m-th row digital data signal to the source line;
Electrically connecting source lines different from the digital data signal in the (m−1) th row among the N source lines, wherein the digital data signal in the mth row is different from the digital data signal in the (m−1) th row;
Electrically connecting each of the connected source lines, electrically connecting to a power supply circuit, and inputting a digital data signal in the m-th row to the source line, and driving the display device Method.

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