JP5237203B2

JP5237203B2 - Jitter detection circuit

Info

Publication number: JP5237203B2
Application number: JP2009144322A
Authority: JP
Inventors: 祐輔大友; 正史野河; 清隆一山; 雅裕石田; 隆弘山口
Original assignee: Advantest Corp; Nippon Telegraph and Telephone Corp
Current assignee: Advantest Corp; Nippon Telegraph and Telephone Corp
Priority date: 2009-06-17
Filing date: 2009-06-17
Publication date: 2013-07-17
Anticipated expiration: 2029-06-17
Also published as: JP2011002298A

Description

本発明は、クロック信号の時間的揺らぎであるジッタの大きさを検出するジッタ検出回路に関する。 The present invention relates to a jitter detection circuit that detects the magnitude of jitter, which is a temporal fluctuation of a clock signal.

図８は、従来のジッタ検出回路の構成例を示す（非特許文献１）。
図において、従来のジッタ検出回路は、ゲーティング回路１０、積分回路２０、ピーク検出回路３０から構成される。ゲーティング回路１０は、クロック信号を入力する遅延回路１１および排他的論理和回路（ＥＸＯＲ）１２で構成され、クロック信号がハイレベルおよびローレベルに遷移した時に一定の時間幅の差動パルスＶ0,Ｖ0'を出力する。積分回路２０は、ゲーティング回路１０から出力される差動パルスＶ0,Ｖ0'を各ベースに入力するトランジスタＱ１，Ｑ２、トランジスタＱ１，Ｑ２の各エミッタに共通接続される電流源ＩＳ１、トランジスタＱ１，Ｑ２の各コレクタと電源との間に接続される電流源ＩＳ２，ＩＳ３、トランジスタＱ１，Ｑ２のコレクタ間に接続される容量Ｃ1 で構成され、トランジスタＱ１，Ｑ２の各コレクタから差動出力Ｖ1', Ｖ1 を取り出し、ピーク検出回路３０に入力する。なお、積分回路２０の差動出力を増幅回路で増幅して出力し、外部に備えたピーク検出回路でピーク検出を行う構成としてもよいが、ここではジッタ検出時の課題を説明するため、ピーク検出回路３０を含む構成として説明する。 FIG. 8 shows a configuration example of a conventional jitter detection circuit (Non-Patent Document 1).
In the figure, the conventional jitter detection circuit includes a gating circuit 10, an integration circuit 20, and a peak detection circuit 30. The gating circuit 10 is composed of a delay circuit 11 for inputting a clock signal and an exclusive OR circuit (EXOR) 12, and when the clock signal transits to a high level and a low level, a differential pulse V0, having a constant time width, V0 'is output. The integrating circuit 20 includes transistors Q1 and Q2 that input differential pulses V0 and V0 ′ output from the gating circuit 10 to their respective bases, a current source IS1 commonly connected to the emitters of the transistors Q1 and Q2, and transistors Q1 and Q1. The current sources IS2 and IS3 connected between the collectors of the transistors Q2 and the power source, and the capacitors C1 connected between the collectors of the transistors Q1 and Q2, and the differential outputs V1 ′, V1 is taken out and inputted to the peak detection circuit 30. Note that the differential output of the integration circuit 20 may be amplified and output by an amplifier circuit, and peak detection may be performed by a peak detection circuit provided outside, but here, in order to explain the problem at the time of jitter detection, A configuration including the detection circuit 30 will be described.

以下、従来のジッタ検出回路の動作例を図８および図９を参照して説明する。
ゲーティング回路１０は、周期Ｔのクロック信号がハイレベルおよびローレベルに遷移した時に、時間幅Ｔ／４の差動パルスＶ0,Ｖ0'を出力する。なお、本例ではＥＸＯＲ１２を用いて、クロック信号がハイレベルおよびローレベルに遷移したときにパルスを出力する構成であるが、ＮＡＮＤ回路によりクロック信号がハイレベルに遷移したときだけパルスを出力しても同様のジッタ検出が可能である。 An example of the operation of the conventional jitter detection circuit will be described below with reference to FIGS.
The gating circuit 10 outputs differential pulses V0 and V0 ′ having a time width T / 4 when a clock signal having a period T transits to a high level and a low level. In this example, the EXOR 12 is used to output a pulse when the clock signal transitions to a high level and a low level, but a pulse is output only when the clock signal transitions to a high level by a NAND circuit. The same jitter detection is possible.

差動型の積分回路２０では、差動パルスＶ0 がハイレベルになるとトランジスタＱ１がオンになり、容量Ｃ1 の一端Ｖ1'から基準電流Ｉだけ電荷を引き抜くとともに、差動パルスＶ0'がローレベルになるのでトランジスタＱ２がオフになり、容量Ｃ1 の他端Ｖ1 に基準電流Ｉだけ電荷をチャージする。このため、ジッタのないクロックが入力すると、積分回路２０の差動出力Ｖ1 の電位は、ゲーティング回路１０がパルスを出力している時間Ｔ／４でＩ＊(Ｔ／４)だけ上昇し、パルスを出力していない時間でＩ＊(Ｔ／４)だけ下降する。よって、図９(4) に示すように、クロック信号にジッタがない場合には差動出力Ｖ1', Ｖ1 の電位は、電圧振幅Ｉ＊(Ｔ／２)、周期Ｔ／２で振動するが、周期より十分長い時間で時間平均すると一定の電位を保つ。ここでは、積分回路２０において、容量Ｃ1 へ流し込む電流と流し出す電流が等しいと仮定して、ゲーティング回路１０の遅延時間をＴ／４と設定した。ただし、積分回路２０において、容量Ｃ1 に流し込む電流と遅延時間の積と、流し出す電流とＴ／２から遅延時間を引いた時間の積が等しければ、遅延時間はＴ／４でなくてもよい。 In the differential integration circuit 20, the transistor Q1 is turned on when the differential pulse V0 becomes high level, the charge is drawn out from the one end V1 'of the capacitor C1 by the reference current I, and the differential pulse V0' becomes low level. Therefore, the transistor Q2 is turned off, and the other end V1 of the capacitor C1 is charged with the reference current I. For this reason, when a jitter-free clock is input, the potential of the differential output V1 of the integrating circuit 20 rises by I * (T / 4) at the time T / 4 when the gating circuit 10 outputs a pulse. It falls by I * (T / 4) in the time when no pulse is output. Therefore, as shown in FIG. 9 (4), when there is no jitter in the clock signal, the potentials of the differential outputs V1 ′ and V1 oscillate with the voltage amplitude I * (T / 2) and the period T / 2. If the time is averaged for a time sufficiently longer than the period, a constant potential is maintained. Here, in the integrating circuit 20, the delay time of the gating circuit 10 is set to T / 4 on the assumption that the current flowing into the capacitor C1 is equal to the current flowing out. However, in the integration circuit 20, if the product of the current flowing into the capacitor C1 and the delay time is equal to the product of the current flowing out and the time obtained by subtracting the delay time from T / 2, the delay time may not be T / 4. .

一方、クロック信号がジッタをもつ場合は、図９(3) に示すように、クロック信号がハイレベルに遷移するタイミングが、前の遷移の周期Ｔ後ではなく、周期ＴからΔＴだけずれる。この時、積分回路２０の放電時間は(Ｔ／４)−ΔＴとなるため、差動出力Ｖ1 の電位はＩ＊ΔＴだけ上昇する。クロック信号のジッタ量は、図９(5) のジッタ表示出力（太線）に示すように、差動出力Ｖ1'，Ｖ1 の差分電位の最大値をピーク検出回路３０により保持するか、単純に増幅して出力することで、ジッタ表示出力電位の初期値からの増分として検出される。 On the other hand, when the clock signal has jitter, as shown in FIG. 9 (3), the timing at which the clock signal transitions to the high level is shifted from the period T by ΔT, not after the period T of the previous transition. At this time, since the discharging time of the integrating circuit 20 is (T / 4)-. DELTA.T, the potential of the differential output V1 increases by I * .DELTA.T. As shown in the jitter display output (thick line) in FIG. 9 (5), the jitter amount of the clock signal is held by the peak detection circuit 30 with the maximum value of the differential potential between the differential outputs V1 'and V1 or simply amplified. As a result, the jitter display output potential is detected as an increment from the initial value.

K.Ichiyama, M.Ishida, T.J.Yamaguchi, and M.Soma, "An on-chip delta-time-to-voltage converter for real-time measurement of clock jitter", in Proc. Int. Symp. Circuits Syst., New Orleans, LA, May 2007K. Ichiyama, M. Ishida, TJYamaguchi, and M. Soma, "An on-chip delta-time-to-voltage converter for real-time measurement of clock jitter", in Proc. Int. Symp. Circuits Syst., New Orleans, LA, May 2007

従来のジッタ検出回路では、次の２つの値が規定通りになっていなければジッタを高精度に検出することが困難である。値の１つは、積分回路２０の電流源ＩＳ２と電流源ＩＳ３の電流の和が電流源ＩＳ１の電流値と一致していることである。もう１つは、ゲーティング回路１０の遅延時間（Ｔ／４）がパルス幅に正確に一致していることである。 In the conventional jitter detection circuit, it is difficult to detect jitter with high accuracy unless the following two values are as specified. One of the values is that the sum of the currents of the current source IS2 and the current source IS3 of the integrating circuit 20 matches the current value of the current source IS1. The other is that the delay time (T / 4) of the gating circuit 10 exactly matches the pulse width.

前者が不一致であれば、積分回路２０の差動出力Ｖ1'，Ｖ1 の両方が増加または減少する同相ドリフトを引き起こす。そして、一定時間後にはＶ1'，Ｖ1 は積分回路２０が正常に動作する電圧出力を超えてしまい、ジッタ検出動作ができなくなる。後者が不一致であれば、積分回路２０の差動出力Ｖ1'，Ｖ1 が逆方向に増加または減少する差動ドリフトを引き起こす。ジッタ検出回路は、ジッタを積分回路２０の差動出力Ｖ1'，Ｖ1 の差分のピーク値で表示するが、差動ドリフトによりＶ1'，Ｖ1 の差が増大し、検出ジッタのピーク値に誤差を与える。さらに、一定時間後にはＶ1'，Ｖ1 は積分回路２０が正常に動作する電圧出力を超えてしまい、ジッタ検出動作ができなくなる。 If the former is inconsistent, it causes a common mode drift in which both differential outputs V1 'and V1 of the integrating circuit 20 increase or decrease. After a certain time, V1 'and V1 exceed the voltage output at which the integrating circuit 20 operates normally, and the jitter detection operation cannot be performed. If the latter does not match, the differential outputs V1 ′ and V1 of the integrating circuit 20 cause a differential drift that increases or decreases in the opposite direction. The jitter detection circuit displays the jitter as a peak value of the difference between the differential outputs V1 ′ and V1 of the integration circuit 20, but the difference between V1 ′ and V1 increases due to the differential drift, and an error is detected in the peak value of the detected jitter. give. Further, after a certain time, V1 'and V1 exceed the voltage output at which the integrating circuit 20 operates normally, and the jitter detection operation cannot be performed.

一方、ジッタ検出回路を半導体集積回路やハイブリッド部品により構成した場合、上記の電流値および遅延時間は、プロセスバラツキ、温度や電源変動の影響を受けるので、適宜調整しなければ所定の精度で上記の２つの値をそれぞれ一致させることが困難である。なお、従来手法として一定期間だけ検出を行い、他の期間はキャリブレーション期間としてＶ1'，Ｖ1 の電位、遅延時間および電流バランスを調整する手法もあるが、検出する時間と追加システムが必要になり、ジッタ検出回路が大規模かつ複雑になり、検出効率が悪くなる問題があった。 On the other hand, when the jitter detection circuit is composed of a semiconductor integrated circuit or a hybrid component, the current value and delay time are affected by process variations, temperature, and power supply fluctuations. It is difficult to match the two values. As a conventional method, there is a method of detecting only for a certain period and adjusting the potentials of V1 ′ and V1, delay time and current balance as a calibration period in other periods. However, a detection time and an additional system are required. However, there is a problem that the jitter detection circuit becomes large and complicated, and the detection efficiency is deteriorated.

また、低周波の差動ドリフトおよび同相ドリフトはハイパスフィルタで除去することにより、高い周波数のジッタに対して一定期間は測定できる場合もある。しかし、低い周波数をもつジッタを検出する際には、フィルタによる選別精度が低下するため、さらなる精度の低下を招く。加えて、積分回路２０の電流源ＩＳ２，ＩＳ３の出力インピーダンスが低く、ジッタによる積分回路２０の差動出力Ｖ1'，Ｖ1 の変化が電流量による電流源両端の電圧差の変化に打ち消されてしまう元来の課題との相乗効果により、特に低周波のジッタのジッタ量を精度よく検出できない問題があった。 Further, by removing low frequency differential drift and common mode drift with a high pass filter, it may be possible to measure high frequency jitter for a certain period of time. However, when detecting a jitter having a low frequency, the accuracy of selection by the filter is lowered, so that the accuracy is further lowered. In addition, the output impedance of the current sources IS2 and IS3 of the integrating circuit 20 is low, and the change in the differential outputs V1 ′ and V1 of the integrating circuit 20 due to jitter is canceled out by the change in the voltage difference across the current source due to the amount of current. Due to a synergistic effect with the original problem, there was a problem that the jitter amount of low frequency jitter, in particular, could not be detected accurately.

このように、従来のジッタ検出回路では、差動型の積分回路２０の複数の電流源の電流値が外乱を受けてばらついたり、ゲーティング回路１０の遅延時間が外乱を受けて揺らぐと、クロック信号のジッタと関係なく積分値がドリフトを起こし、ジッタ検出回路の動作が不安定になって正しいジッタを検出できないことがあった。 As described above, in the conventional jitter detection circuit, when the current values of the plurality of current sources of the differential integration circuit 20 vary due to disturbance or the delay time of the gating circuit 10 fluctuates due to disturbance, In some cases, the integrated value drifts regardless of the signal jitter, and the jitter detection circuit becomes unstable and correct jitter cannot be detected.

本発明は、外乱によるドリフトの周波数成分が低周波であることに着目し、積分回路の差動出力から外乱に起因する低周波の同相ドリフトおよび差動ドリフトを除去し、安定かつ高精度のジッタ検出を可能にするジッタ検出回路を提供することを目的とする。 The present invention pays attention to the fact that the frequency component of drift due to disturbance is low frequency, and removes low-frequency common-mode drift and differential drift caused by disturbance from the differential output of the integration circuit, thereby providing stable and highly accurate jitter. An object of the present invention is to provide a jitter detection circuit that enables detection.

本発明は、クロック信号を入力し、その立ち上がりまたは立ち下がりの少なくとも一方のタイミングを示すパルスを出力するゲーティング回路と、ゲーティング回路の出力パルスの間隔を電圧レベルで出力する積分回路とを備え、積分回路の出力からクロック信号のジッタを検出するジッタ検出回路において、積分回路は、ゲーティング回路の出力パルスの間隔に応じた電圧レベルを差動信号として出力する差動増幅器を含み、その差動増幅器に含まれる電流源の電流値が調整可能な構成であり、積分回路の差動出力を分岐して入力し、検出対象であるジッタの周波数成分を遮断し、かつ除去すべき同相ドリフトの周波数成分を透過する第１のローパスフィルタと、該第１のローパスフィルタを介した差動出力の同相分を出力電位に変換する同相レベル変換増幅器を含み、その出力電位を積分回路の電流源の電流値の調整に供する同相ドリフト補償回路を備える。 The present invention includes a gating circuit that inputs a clock signal and outputs a pulse indicating at least one timing of rising or falling thereof, and an integrating circuit that outputs an interval between output pulses of the gating circuit at a voltage level. In the jitter detection circuit for detecting the jitter of the clock signal from the output of the integration circuit, the integration circuit includes a differential amplifier that outputs a voltage level corresponding to the interval between the output pulses of the gating circuit as a differential signal, and the difference The current value of the current source included in the dynamic amplifier is adjustable, and the differential output of the integration circuit is branched and input to block the frequency component of the jitter to be detected, and the common-mode drift to be removed It is converting a first low-pass filter which transmits frequency components, the common mode of the differential output via the first low-pass filter to the output voltage It includes a phase level conversion amplifier comprises a common mode drift compensation circuit to provide the output potential to the adjustment of the current value of the current source of the integrator circuit.

本発明のジッタ検出回路において、ゲーティング回路は、クロック信号に所定の遅延時間を設定し、出力パルスのパルス幅を設定する遅延回路を含み、その遅延時間が調整可能な構成であり、積分回路の差動出力を分岐して入力し、検出対象であるジッタの周波数成分を遮断し、かつ除去すべき差動ドリフトの周波数成分を透過する第２のローパスフィルタと、該第２のローパスフィルタを介した差動出力の差分を出力電位に変換する差動レベル変換増幅器を含み、その出力電位をゲーティング回路の遅延時間の調整に供する差動ドリフト補償回路を備える。 In the jitter detection circuit of the present invention, the gating circuit includes a delay circuit that sets a predetermined delay time in the clock signal and sets the pulse width of the output pulse, and is configured to adjust the delay time. A second low-pass filter that cuts off the frequency component of the jitter to be detected and transmits the frequency component of the differential drift to be removed, and the second low-pass filter. A differential level conversion amplifier that converts the difference between the differential outputs to an output potential, and a differential drift compensation circuit that uses the output potential to adjust the delay time of the gating circuit.

本発明のジッタ検出回路において、積分回路の差動出力を同相ドリフト補償回路に分岐する分岐点から後段に、差動出力における除去すべき同相ドリフトの周波数成分を遮断し、かつ検出対象であるジッタの周波数成分を透過するハイパスフィルタを備える。 In the jitter detection circuit of the present invention, downstream from the branch point for branching the differential output of the integration circuit in phase drift compensation circuit to cut off a frequency component of the phase drift to be the definitive removal differential output, and is detected A high-pass filter that transmits the frequency component of jitter is provided.

本発明のジッタ検出回路において、積分回路の差動出力を同相ドリフト補償回路および差動ドリフト補償回路に分岐する分岐点から後段に、差動出力における除去すべき同相ドリフトおよび差動ドリフトの周波数成分を遮断し、かつ検出対象であるジッタの周波数成分を透過するハイパスフィルタを備える。 In the jitter detection circuit of the present invention, the frequency components of the in- phase drift and the differential drift to be removed in the differential output from the branch point where the differential output of the integration circuit branches to the in-phase drift compensation circuit and the differential drift compensation circuit. And a high-pass filter that transmits a frequency component of jitter to be detected .

本発明のジッタ検出回路において、積分回路の差動出力の電位差の最大値を保持し、ジッタ検出信号として出力するピーク検出回路を備える。また、本発明のジッタ検出回路において、ハイパスフィルタの差動出力の電位差の最大値を保持し、ジッタ検出信号として出力するピーク検出回路を備える。 The jitter detection circuit of the present invention includes a peak detection circuit that holds the maximum value of the potential difference of the differential output of the integration circuit and outputs it as a jitter detection signal. Further, the jitter detection circuit of the present invention includes a peak detection circuit that holds the maximum value of the potential difference of the differential output of the high-pass filter and outputs it as a jitter detection signal.

本発明のジッタ検出回路において、差動増幅器に含まれる電流源は、積分回路の差動出力端子と電源との間にトランジスタと抵抗を直列に接続し、該トランジスタと抵抗の接続点を負入力とし、同相ドリフト補償回路の出力電位を正入力とし、出力を該トランジスタのゲートに接続する演算増幅器を備える。 In the jitter detection circuit of the present invention, the current source included in the differential amplifier has a transistor and a resistor connected in series between the differential output terminal of the integrating circuit and the power supply, and the connection point of the transistor and the resistor is negatively input. And an operational amplifier for connecting the output to the gate of the transistor with the output potential of the common-mode drift compensation circuit as a positive input.

本発明のジッタ検出回路は、プロセス、温度、電源変動に起因する積分回路の差動出力ノードＶ1', Ｖ1 の同相ドリフトおよび差動ドリフトの影響を除去することができるので、その差動出力の電位の最大値を保持することにより、簡易かつ高精度にクロック信号のジッタ検出が可能となる。 The jitter detection circuit of the present invention can eliminate the effects of common mode drift and differential drift of the differential output nodes V1 ′ and V1 of the integrating circuit due to process, temperature, and power supply fluctuations. By holding the maximum potential value, it is possible to detect the jitter of the clock signal easily and with high accuracy.

さらに、温度、電源変動に起因する遅延時間や電流値の変動に伴う同相ドリフト成分および差動ドリフト成分は低周波であるので、フィルタでこの低周波成分を遮断し、かつジッタ成分を含む高周波成分を透過させることにより、簡易かつ高精度にクロック信号のジッタ検出が可能となる。
In addition, since the common-mode drift component and differential drift component due to fluctuations in delay time and current values due to temperature and power supply fluctuations are low-frequency, the low-frequency component is blocked by a filter, and high-frequency components including jitter components By transmitting the signal, it is possible to detect the jitter of the clock signal easily and with high accuracy .

また、本発明のジッタ検出回路は、積分回路の出力インピーダンスを高ることにより、検出可能なジッタ周波数の低域限界を低減することができ、低い周波数のジッタを精度よる検出することができる。 In addition, the jitter detection circuit of the present invention can reduce the lower limit of the detectable jitter frequency by increasing the output impedance of the integration circuit, and can detect low frequency jitter with high accuracy.

本発明のジッタ検出回路の実施例１の構成例を示す図である。It is a figure which shows the structural example of Example 1 of the jitter detection circuit of this invention. 実施例１の動作例を示す図である。FIG. 6 is a diagram illustrating an operation example of the first embodiment. 実施例１のシミュレーションによる効果を説明する図である。It is a figure explaining the effect by the simulation of Example 1. FIG. 本発明のジッタ検出回路の実施例２の構成例を示す図である。It is a figure which shows the structural example of Example 2 of the jitter detection circuit of this invention. 実施例２のシミュレーションおよび計算による効果を説明する図である。It is a figure explaining the effect by the simulation of Example 2, and calculation. 実施例１，２のフィルタ帯域と観測可能ジッタ周波数を示す図である。It is a figure which shows the filter zone | band of Example 1, 2 and an observable jitter frequency. 本発明のジッタ検出回路の実施例３の構成例を示す図である。It is a figure which shows the structural example of Example 3 of the jitter detection circuit of this invention. 従来のジッタ検出回路の構成例を示す図である。It is a figure which shows the structural example of the conventional jitter detection circuit. 従来のジッタ検出回路の動作例を示す図である。It is a figure which shows the operation example of the conventional jitter detection circuit.

図１は、本発明のジッタ検出回路の実施例１の構成例を示す。
図において、実施例１のジッタ検出回路は、従来回路と同様のゲーティング回路１０、積分回路２０およびピーク検出回路３０に加えて、同相ドリフト補償回路４０、差動ドリフト補償回路５０、ハイパスフィルタ６０から構成される。ゲーティング回路１０は、従来構成と同様に遅延回路１１およびＥＸＯＲ１２により構成されるが、本実施例の遅延回路１１は差動ドリフト補償回路５０の出力電位Ｖ4 に応じて遅延量を調整できる機能を有する。ＥＸＯＲ１２は、上記のようにＮＡＮＤに置き換え可能である。積分回路２０は、従来構成と同様にトランジスタＱ１，Ｑ２、電流源ＩＳ１，ＩＳ２，ＩＳ３、容量Ｃ１により構成されるが、トランジタＱ１，Ｑ２のエミッタに接続される本実施例の電流源ＩＳ２，ＩＳ３は、同相ドリフト補償回路４０の出力電位Ｖ3 に応じて電流値を調整できる機能を有する。 FIG. 1 shows a configuration example of the first embodiment of the jitter detection circuit of the present invention.
In the figure, the jitter detection circuit according to the first embodiment includes an in-phase drift compensation circuit 40, a differential drift compensation circuit 50, and a high-pass filter 60 in addition to the gating circuit 10, the integration circuit 20, and the peak detection circuit 30 similar to the conventional circuit. Consists of The gating circuit 10 includes a delay circuit 11 and an EXOR 12 as in the conventional configuration. The delay circuit 11 of this embodiment has a function of adjusting the delay amount according to the output potential V4 of the differential drift compensation circuit 50. Have. The EXOR 12 can be replaced with NAND as described above. The integrating circuit 20 includes transistors Q1, Q2, current sources IS1, IS2, IS3, and a capacitor C1 as in the conventional configuration, but the current sources IS2, IS3 of this embodiment connected to the emitters of the transistors Q1, Q2. Has a function of adjusting the current value in accordance with the output potential V3 of the common-mode drift compensation circuit 40.

同相ドリフト補償回路４０は、積分回路２０の差動出力Ｖ1', Ｖ1 を分岐して入力するローパスフィルタ４１、ローパスフィルタ４１の差動出力の同相分を出力電位Ｖ3 に変換する同相レベル変換増幅器４２から構成される。なお、同相レベル変換増幅器４２の通過帯域が低い場合は、同相レベル変換増幅器４２にローパスフィルタ４１の機能を兼用させることができる。 The common-mode drift compensation circuit 40 is a low-pass filter 41 that branches and inputs the differential outputs V1 ′ and V1 of the integrating circuit 20, and a common-mode level conversion amplifier 42 that converts the common-mode component of the differential output of the low-pass filter 41 into an output potential V3. Consists of When the passband of the common-mode level conversion amplifier 42 is low, the common-mode level conversion amplifier 42 can also function as the low-pass filter 41.

差動ドリフト補償回路５０は、積分回路２０の差動出力Ｖ1', Ｖ1 を分岐して入力するローパスフィルタ５１、ローパスフィルタ５１の差動出力の差分を出力電位Ｖ4 に変換する差動レベル変換増幅器５２から構成される。なお、差動レベル変換増幅器５２の通過帯域が低い場合は、差動レベル変換増幅器５２にローパスフィルタ５１の機能を兼用させることができる。 The differential drift compensation circuit 50 is a low-pass filter 51 that branches and inputs the differential outputs V1 ′ and V1 of the integrating circuit 20, and a differential level conversion amplifier that converts the difference between the differential outputs of the low-pass filter 51 into an output potential V4. 52. If the pass band of the differential level conversion amplifier 52 is low, the differential level conversion amplifier 52 can also function as the low-pass filter 51.

ハイパスフィルタ６０は、積分回路２０の差動出力を同相ドリフト補償回路４０および差動ドリフト補償回路５０に分岐する分岐点以降に接続され、積分回路２０の差動出力Ｖ1', Ｖ1 に含まれる低周波のドリフト成分を遮断し、ジッタに対応する高周波成分をピーク検出回路３０に出力する。ただし、ハイパスフィルタ６０は、同相ドリフト補償回路４０および差動ドリフト補償回路５０の補償精度に応じて省略可能であり、またジッタ成分より遥かに高周波のクロック周波数成分を遮断するバンドパスフィルタで置き換えてもよい。 The high-pass filter 60 is connected after the branch point where the differential output of the integration circuit 20 branches to the common-mode drift compensation circuit 40 and the differential drift compensation circuit 50, and is included in the differential outputs V1 ′ and V1 of the integration circuit 20. The frequency drift component is cut off, and the high frequency component corresponding to the jitter is output to the peak detection circuit 30. However, the high-pass filter 60 can be omitted depending on the compensation accuracy of the in-phase drift compensation circuit 40 and the differential drift compensation circuit 50, and is replaced with a band-pass filter that cuts off a clock frequency component far higher than the jitter component. Also good.

以下、実施例１のジッタ検出回路の動作例を図１および図２を参照して説明する。
ゲーティング回路１０は、周期Ｔのクロック信号がハイレベルおよびローレベルに遷移した時に、時間幅Ｔ／４の差動パルスＶ0,Ｖ0'を出力する。 Hereinafter, an operation example of the jitter detection circuit according to the first embodiment will be described with reference to FIGS.
The gating circuit 10 outputs differential pulses V0 and V0 ′ having a time width T / 4 when a clock signal having a period T transits to a high level and a low level.

差動型の積分回路２０では、差動パルスＶ0 がハイレベルになるとトランジスタＱ１がオンになり、容量Ｃ1 の一端Ｖ1'から基準電流Ｉだけ電荷を引き抜くとともに、差動パルスＶ0'がローレベルになるのでトランジスタＱ２がオフになり、容量Ｃ1 の他端Ｖ1 に基準電流Ｉだけ電荷をチャージする。また、差動パルスＶ0 がローレベルになるとトランジスタＱ１がオフになり、容量Ｃ1 の一端Ｖ1'に基準電流Ｉだけ電荷をチャージするとともに、差動パルスＶ0'がハイレベルになるのでトランジスタＱ２がオンになり、容量Ｃ1 の他端Ｖ1 から基準電流Ｉだけ電荷を引き抜く。このため、ジッタのないクロックが入力すると、積分回路２０の差動出力Ｖ1 の電位は、ゲーティング回路１０がパルスを出力している時間Ｔ／４でＩ＊(Ｔ／４)だけ上昇し、パルスを出力していない時間でＩ＊(Ｔ／４)だけ下降する。よって、クロック信号にジッタがない場合には差動出力Ｖ1', Ｖ1 の電位は、電圧振幅Ｉ＊(Ｔ／２)、周期Ｔ／２で振動するが、周期より十分長い時間で時間平均すると一定の電位を保つ。 In the differential integration circuit 20, the transistor Q1 is turned on when the differential pulse V0 becomes high level, the charge is drawn out from the one end V1 'of the capacitor C1 by the reference current I, and the differential pulse V0' becomes low level. Therefore, the transistor Q2 is turned off, and the other end V1 of the capacitor C1 is charged with the reference current I. Further, when the differential pulse V0 becomes low level, the transistor Q1 is turned off, one end V1 'of the capacitor C1 is charged by the reference current I, and the differential pulse V0' becomes high level so that the transistor Q2 is turned on. Thus, charge is extracted from the other end V1 of the capacitor C1 by the reference current I. For this reason, when a jitter-free clock is input, the potential of the differential output V1 of the integrating circuit 20 rises by I * (T / 4) at the time T / 4 when the gating circuit 10 outputs a pulse. It falls by I * (T / 4) in the time when no pulse is output. Therefore, when there is no jitter in the clock signal, the potentials of the differential outputs V1 ′ and V1 oscillate with the voltage amplitude I * (T / 2) and the period T / 2. Keep a constant potential.

一方、クロック信号がジッタをもつ場合、クロック信号がハイレベルに遷移するタイミングが、前の遷移の周期Ｔ後ではなく、周期ＴからΔＴだけずれる。この時、積分回路２０の放電時間は(Ｔ／４)−ΔＴとなるため、差動出力Ｖ1 の電位はＩ＊ΔＴだけ上昇する。 On the other hand, when the clock signal has jitter, the timing at which the clock signal transitions to the high level is shifted from the period T by ΔT, not after the period T of the previous transition. At this time, since the discharging time of the integrating circuit 20 is (T / 4)-. DELTA.T, the potential of the differential output V1 increases by I * .DELTA.T.

ハイパスフィルタ６０は、入出力端子間に接続した容量と出力端子と接地間に接続した抵抗で構成される。抵抗と容量の積の逆数が低域カットオフ周波数である。プロセス、温度、電源変動に起因する積分回路２０の差動出力Ｖ1', Ｖ1 の電位の変動周波数に比較して、このカットオフ周波数を十分高く設定する。例えば、クロック信号の周波数が５ＧHzで、検出したいジッタ周波数の下限周波数が１ＭHzの場合、カットオフ周波数を10ｋHz程度に設定する。図２(3) の差動出力Ｖ1'，Ｖ1 の周波数成分のうち、プロセス、温度、電源変動に起因する周波数成分は通常１ｋHz未満となるため、ハイパスフィルタ６０の差動出力Ｖ2'，Ｖ2 にはその周波数成分が伝搬しない。また、クロックの基本成分である５ＧHzの信号は、積分回路２０の電流源の出力抵抗と容量Ｃ1 の積で表わされる時定数の逆数の周波数である約 100ＭHzでカットオフされる。あるいは、バンドパスフィルタを用いて低周波成分とともに高周波のクロック周波数成分を遮断してもよい。これにより、クロック信号のジッタに起因する差動出力Ｖ1'，Ｖ1 の１ＭHzから 100ＭHzの電位変動だけ、差動出力Ｖ2'，Ｖ2 として伝搬する。 The high pass filter 60 includes a capacitor connected between the input / output terminals and a resistor connected between the output terminal and the ground. The reciprocal of the product of resistance and capacitance is the low frequency cutoff frequency. This cut-off frequency is set sufficiently high compared to the fluctuation frequency of the potentials of the differential outputs V1 ′ and V1 of the integrating circuit 20 due to process, temperature, and power supply fluctuations. For example, when the frequency of the clock signal is 5 GHz and the lower limit frequency of the jitter frequency to be detected is 1 MHz, the cut-off frequency is set to about 10 kHz. Of the frequency components of the differential outputs V1 ′ and V1 in FIG. 2 (3), the frequency components due to process, temperature, and power supply fluctuations are usually less than 1 kHz, so that the differential outputs V2 ′ and V2 of the high-pass filter 60 Does not propagate its frequency components. Further, the signal of 5 GHz which is the basic component of the clock is cut off at about 100 MHz which is the frequency of the reciprocal of the time constant represented by the product of the output resistance of the current source of the integrating circuit 20 and the capacitance C1. Alternatively, a high-frequency clock frequency component may be blocked together with a low-frequency component using a band-pass filter. As a result, only the potential fluctuation of 1 MHz to 100 MHz of the differential outputs V1 ′ and V1 due to the jitter of the clock signal propagates as the differential outputs V2 ′ and V2.

クロック信号のジッタ量は、図２(7) のジッタ表示出力（太線）に示すように、差動出力Ｖ2'，Ｖ2 の差分電位の最大値をピーク検出回路３０により保持するか、単純に増幅して出力することで、ジッタ表示出力電位の初期値からの増分として検出される。ここでピーク検出回路３０の帯域を、検出したいジッタ周波数の上限（例えば、上記の 100ＭHz）に設定することにより、クロックの基本周波数（例えば、上記の５ＧHz）の影響を受けずに検出したい周波数のジッタを検出することができる。 As shown in the jitter display output (thick line) in FIG. 2 (7), the jitter amount of the clock signal is held by the peak detection circuit 30 with the maximum value of the differential potential between the differential outputs V2 'and V2, or simply amplified. As a result, the jitter display output potential is detected as an increment from the initial value. Here, by setting the band of the peak detection circuit 30 to the upper limit of the jitter frequency to be detected (for example, the above 100 MHz), the frequency of the frequency to be detected without being affected by the fundamental frequency of the clock (for example, the above 5 GHz). Jitter can be detected.

差動ドリフト補償回路５０は、積分回路２０の差動出力Ｖ1'，Ｖ1 の差分電位の低周波での増減を、ローパスフィルタ５１を通過後に差動レベル変換増幅回路５２で検出して差分電位Ｖ４として出力する。例えば、ゲーティング回路１０の出力パルス幅がＴ／４より長ければ、定常的に差動出力Ｖ1 への充電と差動出力Ｖ1'からの放電がその逆の時間より長くなり、図２(3) に示すように、差動出力Ｖ1 はハイ方向、差動出力Ｖ1'がロー方向に変化する。この場合、図２(6) に示すように、Ｖ4 が下降してゲーティング回路１０の遅延時間を削減する。このフィードバック制御はジッタ周期に比較して非常に長い周期となるため、差動ドリフトはジッタ検出出力に影響しない。 The differential drift compensation circuit 50 detects the increase / decrease of the differential potential of the differential outputs V1 ′ and V1 of the integrating circuit 20 at a low frequency by the differential level conversion amplifier circuit 52 after passing through the low-pass filter 51 and detects the differential potential V4. Output as. For example, if the output pulse width of the gating circuit 10 is longer than T / 4, the charging to the differential output V1 and the discharging from the differential output V1 ′ are constantly longer than the opposite time, and FIG. ), The differential output V1 changes in the high direction and the differential output V1 ′ changes in the low direction. In this case, as shown in FIG. 2 (6), V4 falls and the delay time of the gating circuit 10 is reduced. Since this feedback control has a very long period compared to the jitter period, the differential drift does not affect the jitter detection output.

同相ドリフト補償回路４０は、積分回路２０の差動出力Ｖ1'，Ｖ1 の同相電位の低周波での増減を、ローパスフィルタ４１を通過後に同相レベル変換増幅回路４２で検出して差分電位Ｖ３として出力する。例えば、積分回路２０の電流源ＩＳ２，ＩＳ３の供給電流値がＩＳ１の電流値の１／２より大きいければ、定常的に差動出力Ｖ1'，Ｖ1 への充電電流が放電電流を上回り、図２(3) に示すように、差動出力Ｖ1'，Ｖ1 はハイ方向に変化する。この場合、図２(5) に示すように、Ｖ3 が上昇して、積分回路２０の電流源ＩＳ２，ＩＳ３の電流値を削減する。このフィードバック制御はジッタ周期に比較して非常に長い周期となるため、同相ドリフトはジッタ検出出力に影響しない。 The common-mode drift compensation circuit 40 detects the increase / decrease in the low-frequency of the common-mode potential of the differential outputs V1 ′ and V1 of the integrating circuit 20 after passing through the low-pass filter 41 and outputs it as a differential potential V3. To do. For example, if the supply current value of the current sources IS2 and IS3 of the integration circuit 20 is larger than ½ of the current value of IS1, the charging current to the differential outputs V1 ′ and V1 steadily exceeds the discharge current. As shown in 2 (3), the differential outputs V1 'and V1 change in the high direction. In this case, as shown in FIG. 2 (5), V3 rises and the current values of the current sources IS2 and IS3 of the integrating circuit 20 are reduced. Since this feedback control has a very long period compared to the jitter period, the common-mode drift does not affect the jitter detection output.

よって、図３(2) に示すように、プロセス、温度、電源変動に起因する差動出力Ｖ1'，Ｖ1 の同相ドリフト、差動ドリフトの影響を除去でき、さらに必要に応じて挿入されるハイパスフィルタ６０を介して出力される差動出力Ｖ2'，Ｖ2 の電位差の最大値をピーク検出回路３０により保持することにより、簡易かつ高精度にジッタ検出が可能となる。 Therefore, as shown in FIG. 3 (2), the effects of common-mode drift and differential drift of differential outputs V1 'and V1 due to process, temperature, and power supply fluctuations can be removed, and a high-pass inserted as necessary. By holding the maximum value of the potential difference between the differential outputs V2 ′ and V2 output through the filter 60 by the peak detection circuit 30, it is possible to detect the jitter easily and with high accuracy.

図４は、本発明のジッタ検出回路の実施例２の構成例を示す。図４(1) は、従来の積分回路の構成例を示す。図４(2) は、実施例２における積分回路２０の構成例を示す。 FIG. 4 shows a configuration example of the second embodiment of the jitter detection circuit of the present invention. FIG. 4 (1) shows a configuration example of a conventional integrating circuit. FIG. 4 (2) shows a configuration example of the integrating circuit 20 in the second embodiment.

従来の積分回路は、電流源ＩＳ２，ＩＳ３が例えば負荷ＰＭＯＳトランジスタＭ１，Ｍ２で構成される。電流調整端子Ｖ３をゲートに接続し、電流調整端子Ｖ３に印加される電位が低いときは多くの電流を流し、高いときは電流が減少する。しかし、図５(1) に「従来」と示すように、従来の負荷ＰＭＯＳトランジスタＭ１，Ｍ２では、ＭＯＳトランジスタのドレイン−ソース間電位が大きくなると、ゲート長変調効果によりドレイン−ソース間電流も増加し、理想定電流源の特性から乖離する。これは、積分回路２０の出力インピーダンスが低下することを意味する。本ジッタ検出回路では、積分回路２０の出力インピーダンスと容量Ｃ1 の容量値の積が、検出可能なジッタ周波数の下限を決定する。積分回路自身の電流出力変動が差動出力Ｖ1'，Ｖ1 に現れると、ジッタによる電位変動との区別がつかなくなる。 In the conventional integrating circuit, the current sources IS2 and IS3 are constituted by, for example, load PMOS transistors M1 and M2. The current adjustment terminal V3 is connected to the gate. When the potential applied to the current adjustment terminal V3 is low, a large amount of current flows, and when the potential is high, the current decreases. However, as shown in FIG. 5 (1), “conventional”, in the conventional load PMOS transistors M1 and M2, when the drain-source potential of the MOS transistor increases, the drain-source current also increases due to the gate length modulation effect. However, it deviates from the characteristics of the ideal constant current source. This means that the output impedance of the integrating circuit 20 is lowered. In the present jitter detection circuit, the product of the output impedance of the integration circuit 20 and the capacitance value of the capacitance C1 determines the lower limit of the detectable jitter frequency. If the current output fluctuation of the integrating circuit itself appears in the differential outputs V1 'and V1, it becomes impossible to distinguish from the potential fluctuation due to jitter.

実施例２におけるジッタ検出回路の積分回路２０は、負荷ＰＭＯＳトランジスタＭ１，Ｍ２のソースと電源の間にそれぞれ抵抗Ｒ１，Ｒ２を挿入し、抵抗Ｒ１，Ｒ２と負荷ＰＭＯＳトランジスタＭ１，Ｍ２の各接続点をマイナス入力とし、同相ドリフト補償回路４０の出力電位Ｖ３をプラス入力とする演算増幅器Ｏｐ１，Ｏｐ２を付加し、その演算増幅器Ｏｐ１，Ｏｐ２の各出力を負荷ＰＭＯＳトランジスタＭ１，Ｍ２の各ゲートに接続した。電流の増減を抵抗Ｒ１，Ｒ２で電圧に変換し、演算増幅回路Ｏｐ１，Ｏｐ２によりゲート電位に負帰還をかける構成である。これにより、負荷ＰＭＯＳトランジスタＭ１，Ｍ２のソース電位は常に一定電流を流す電位に保たれる。図５(1) に「本発明」と示すように、ドレイン電圧を変更しても一定の電流が得られる。これは、本ジッタ検出回路において図５(2) に示すような特別に顕著な効果となって現れる。すなわち、検出できるジッタ周波数の下限は、従来のＰＭＯＳトランジスタのみであれば出力インピーダンスが30ｋΩ程度であり、１ＭHzを超える値に止まる。これに対し、実施例２の積分回路２０によると、出力インピーダンスが 500ｋΩ程度に改善され、検出できるジッタ周波数の下限は 100ｋHzと桁を超えた改善効果が得られる。 In the integrating circuit 20 of the jitter detection circuit in the second embodiment, resistors R1 and R2 are inserted between the sources of the load PMOS transistors M1 and M2 and the power supply, respectively, and each connection point between the resistors R1 and R2 and the load PMOS transistors M1 and M2 is inserted. Is added as a negative input, and operational amplifiers Op1 and Op2 are added with the output potential V3 of the common-mode drift compensation circuit 40 as a positive input, and the outputs of the operational amplifiers Op1 and Op2 are connected to the gates of the load PMOS transistors M1 and M2. . In this configuration, increase / decrease in current is converted to voltage by resistors R1 and R2, and negative feedback is applied to the gate potential by operational amplifier circuits Op1 and Op2. As a result, the source potentials of the load PMOS transistors M1 and M2 are always maintained at a potential that allows a constant current to flow. As indicated by “present invention” in FIG. 5A, a constant current can be obtained even if the drain voltage is changed. This appears as a particularly remarkable effect as shown in FIG. 5 (2) in this jitter detection circuit. In other words, the lower limit of the jitter frequency that can be detected is about 30 kΩ when the conventional PMOS transistor alone is used, and it is limited to a value exceeding 1 MHz. On the other hand, according to the integrating circuit 20 of the second embodiment, the output impedance is improved to about 500 kΩ, and the lower limit of the detectable jitter frequency is 100 kHz, which is an improvement effect exceeding the digit.

実施例１および実施例２において、配置したハイパスフィルタ６０、ローパスフィルタ４１，５１の帯域と検出可能なジッタ周波数の関係を図６に示す。実施例１，２の場合には、図３に示すように、プロセス、温度、電源変動に起因する差動出力Ｖ1'，Ｖ1 の同相ドリフトおよび差動ドリフトの影響を除去でき、差動出力Ｖ2'，Ｖ2 の電位差の最大値をピーク検出回路３０により保持することで簡易かつ高精度にジッタ検出が可能になるが、実施例２の場合は、さらに図６に示すように、実施例１と比較して約１桁低い周波数のジッタを精度良く検出することが可能となる。 FIG. 6 shows the relationship between the bands of the high-pass filter 60 and the low-pass filters 41 and 51 arranged in the first and second embodiments and the detectable jitter frequency. In the case of the first and second embodiments, as shown in FIG. 3, the effects of the common mode drift and differential drift of the differential outputs V1 'and V1 due to process, temperature, and power supply fluctuations can be eliminated, and the differential output V2 By holding the maximum value of the potential difference of ', V2 by the peak detection circuit 30, it becomes possible to detect jitter easily and with high precision. In the case of the second embodiment, as shown in FIG. In comparison, it is possible to accurately detect a jitter having a frequency lower by about one digit.

図７は、本発明のジッタ検出回路の実施例３の構成例を示す。
実施例３のジッタ検出回路は、実施例１のジッタ検出回路におけるゲーティング回路１０および積分回路２０の構成を変更したものである。 FIG. 7 shows a configuration example of the jitter detection circuit according to the third embodiment of the present invention.
The jitter detection circuit of the third embodiment is obtained by changing the configurations of the gating circuit 10 and the integration circuit 20 in the jitter detection circuit of the first embodiment.

実施例３のゲーティング回路１０は、例えば遅延回路１１と位相周波数検出器（ＰＦＤ）１３から構成され、遅延回路１１は差動ドリフト補償回路５０の出力電位Ｖ4 に応じて遅延量を調整できる機能を有する。実施例３の積分回路２０は、例えば差動チャージポンプ回路と容量Ｃ1 から構成される。差動チャージポンプ回路の電流源ＩＳ１，ＩＳ２，ＩＳ３，ＩＳ４は、同相ドリフト補償回路４０の出力電位Ｖ3 に応じて電流値を調整できる機能を有する。 The gating circuit 10 according to the third embodiment includes, for example, a delay circuit 11 and a phase frequency detector (PFD) 13, and the delay circuit 11 has a function capable of adjusting a delay amount according to the output potential V 4 of the differential drift compensation circuit 50. Have The integrating circuit 20 of the third embodiment is composed of, for example, a differential charge pump circuit and a capacitor C1. The current sources IS1, IS2, IS3, and IS4 of the differential charge pump circuit have a function of adjusting the current value according to the output potential V3 of the common-mode drift compensation circuit 40.

実施例３のゲーティング回路１０では、実施例１のＥＸＯＲ１２に代えて位相周波数検出器１３を用いているため、ゲーティングパルスによる三角波ではなく、ジッタ量を直接に電位変動をＵＰ信号およびＤＮ信号として積分回路２０に入力し、さらに差動出力Ｖ1,Ｖ1'として出力することができる。このため、差動出力Ｖ1,Ｖ1'でのジッタ量に対する電位変動のＳＮ比が実施例１に比較して大きくなり、より高い精度でジッタを検出することが可能となる。 In the gating circuit 10 of the third embodiment, since the phase frequency detector 13 is used instead of the EXOR 12 of the first embodiment, the jitter amount is not directly changed to the triangular wave due to the gating pulse, but the potential fluctuation is directly changed to the UP signal and the DN signal. Can be input to the integrating circuit 20 and further output as differential outputs V1, V1 '. For this reason, the SN ratio of the potential fluctuation with respect to the jitter amount at the differential outputs V1 and V1 ′ becomes larger than that in the first embodiment, and the jitter can be detected with higher accuracy.

１０ゲーティング回路
１１遅延回路
１２排他的論理和回路（ＥＸＯＲ）
１３位相周波数検出器（ＰＦＤ）
２０積分回路
３０ピーク検出回路
４０同相ドリフト補償回路
４１ローパスフィルタ
４２同相レベル変換増幅器
５０差動ドリフト補償回路
５１ローパスフィルタ
５２差動レベル変換増幅器
６０ハイパスフィルタ 10 Gating circuit 11 Delay circuit 12 Exclusive OR circuit (EXOR)
13 Phase frequency detector (PFD)
DESCRIPTION OF SYMBOLS 20 Integral circuit 30 Peak detection circuit 40 In-phase drift compensation circuit 41 Low-pass filter 42 In-phase level conversion amplifier 50 Differential drift compensation circuit 51 Low-pass filter 52 Differential level conversion amplifier 60 High-pass filter

Claims

A gating circuit for inputting a clock signal and outputting a pulse indicating timing of at least one of the rising edge and the falling edge;
An integration circuit that outputs an interval between output pulses of the gating circuit at a voltage level, and a jitter detection circuit that detects jitter of the clock signal from the output of the integration circuit.
The integrating circuit includes a differential amplifier that outputs a voltage level corresponding to the output pulse interval of the gating circuit as a differential signal, and the current value of a current source included in the differential amplifier is adjustable. Yes,
A first low-pass filter that branches and inputs the differential output of the integration circuit, blocks a frequency component of jitter to be detected, and transmits a frequency component of in-phase drift to be removed; and the first low-pass filter A common-mode level conversion amplifier that converts a common-mode component of a differential output through a filter into an output potential, and a common-mode drift compensation circuit that uses the output potential to adjust a current value of a current source of the integration circuit. Jitter detection circuit.

The jitter detection circuit according to claim 1,
The gating circuit includes a delay circuit that sets a predetermined delay time in the clock signal and sets a pulse width of the output pulse, and the delay time is adjustable.
A second low-pass filter that branches and inputs the differential output of the integration circuit, blocks the frequency component of jitter to be detected, and transmits the frequency component of the differential drift to be removed; A differential level conversion amplifier that converts a difference between differential outputs through a low-pass filter into an output potential, and a differential drift compensation circuit that uses the output potential to adjust the delay time of the gating circuit. Jitter detection circuit.

The jitter detection circuit according to claim 1,
Downstream from the branch point for branching the differential output of the integrator circuit to the phase drift compensation circuit to cut off a frequency component removal to be in phase drift definitive to the differential output, and the jitter of frequency components to be detected A jitter detection circuit comprising a high-pass filter that transmits light .

The jitter detection circuit according to claim 2,
From the branch point where the differential output of the integration circuit branches to the common-mode drift compensation circuit and the differential drift compensation circuit, the frequency component of the common-mode drift and differential drift to be removed in the differential output is cut off. A jitter detection circuit comprising a high-pass filter that transmits a frequency component of jitter to be detected.

The jitter detection circuit according to claim 1 or 2,
A jitter detection circuit comprising: a peak detection circuit that holds a maximum value of a potential difference of the differential output of the integration circuit and outputs it as a jitter detection signal.

In the jitter detection circuit according to claim 3 or 4,
A jitter detection circuit comprising: a peak detection circuit that holds a maximum value of a potential difference of a differential output of the high-pass filter and outputs the maximum value as a jitter detection signal.

The jitter detection circuit according to claim 1,
The current source included in the differential amplifier includes a transistor and a resistor connected in series between the differential output terminal of the integrating circuit and a power source, and a connection point between the transistor and the resistor is a negative input, and the common-mode drift compensation A jitter detection circuit, comprising: an operational amplifier that takes an output potential of the circuit as a positive input and connects an output to a gate of the transistor.