JP5235331B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit.

  Generally, a semiconductor integrated circuit in which a digital circuit is configured on a semiconductor chip is configured with a synchronous circuit. This synchronization circuit operates using a clock signal distributed inside the circuit as a source of timing. The synchronization of the semiconductor integrated circuit is achieved by inputting a clock signal input to the semiconductor integrated circuit to the clock terminal of each flip-flop via the main clock buffer and the sub block buffer.

  In this configuration, if a clock signal time difference (clock skew) occurs at the clock terminal of each flip-flop, it causes a malfunction. Therefore, in a conventional semiconductor integrated circuit clock supply circuit, a clock tree in which buffers are inserted, arranged and wired so that the delay values to the clock terminals of all flip-flops are the same in consideration of wiring delay and load. The circuit was configured.

  For example, Patent Document 1 proposes a technique in which a clock wiring and a buffer are configured by a combination of a buffer and a panel having a constant wiring distance in order to configure a clock tree circuit with a small clock skew. Conventionally, clock tree synthesis (CTS) that automatically adjusts the arrangement of clock drivers and flip-flops to keep the clock skew within a certain range has been widely used (for example, Non-Patent Document 1).

Japanese Patent Laid-Open No. 7-86416 (page 3 to page 5, FIG. 1) Masayuki Fukayama, Akio Kitagawa, Junichi Akita, Masakuni Suzuki "VLSI design by HDL" Kyoritsu Shuppan, June 20, 1999, P117

  Conventional semiconductor integrated circuits reduce clock skew that occurs due to the difference in clock wiring distance for each flip-flop, depending on the arrangement of the buffer serving as the clock supply source and the arrangement of the flip-flop from which the clock arrives. The effect was expected for this purpose.

  The cause of the clock skew includes not only the above-described difference in the wiring distance of the clock wiring, but also variations in wiring dimensions, element characteristics, performance, etc. in semiconductor manufacturing. With the clock frequency of the conventional semiconductor integrated circuit, the clock skew due to such variations is sufficiently small with respect to the delay time of the signal to be managed. Therefore, it is sufficient to consider only the clock skew due to the difference in the wiring distance described above. there were.

  However, as the semiconductor manufacturing process becomes finer, the operating clock frequency tends to increase, thereby reducing the delay value of the signal, resulting in a relatively large clock skew due to semiconductor manufacturing variations. It is no longer possible to ignore the effects.

  In particular, when the skew caused by this variation is taken into account in the conventional design method in a semiconductor integrated circuit, the timing margin of the synchronous design must be cut by an amount corresponding to the clock skew, and the timing margin becomes very small. For this reason, there is a problem that a remarkably enormous design period is required or design becomes difficult.

  In addition, there are cases where designing and manufacturing are performed on the premise that the inspection conditions of the semiconductor chip after manufacture are strict in order to secure a timing margin. In this case, the defect rate of the manufactured semiconductor chip increases and the yield deteriorates. There was a problem to do. This significantly increases the cost per good chip.

  The present invention has been made in order to solve the above-described problems, and provides a semiconductor integrated circuit that can alleviate constraints on timing design due to variations in semiconductor manufacturing processes and improve yield after manufacturing. With the goal.

The semiconductor integrated circuit according to the present invention includes a first semiconductor chip having a bump for external connection and a first signal wiring electrically connected to the bump, and a mirror symmetry with the bump in the first semiconductor chip. A second semiconductor chip having a pad for external connection disposed at a position and a second signal wiring electrically connected to the pad, and each of the first semiconductor chip and the second semiconductor chip. The signal wiring has a delay characteristic that cancels out the dispersion of the delay characteristics of each other, and the first semiconductor chip and the second semiconductor chip are bonded so that the bumps and pads arranged in mirror symmetry are in contact with each other, The first signal wiring and the second signal wiring, which are arranged and wired in a mirror-symmetrical position via the bump and the pad, are electrically connected, and the signal is arranged on the first semiconductor chip and the second semiconductor chip. All or part of the line, characterized in that a clock line for supplying a clock signal to the flip-flop clock terminal.

According to the present invention, each signal wiring in the first semiconductor chip and the second semiconductor chip has a delay characteristic that cancels out a variation in the delay characteristic of each other, and the bump and the pad arranged in mirror symmetry contact each other. The first semiconductor chip and the second semiconductor chip are bonded together, and the first signal wiring and the second signal wiring, which are arranged and laid in a mirror-symmetrical position via the bumps and the pads, are electrically connected. Since all or part of the signal wirings arranged on the first semiconductor chip and the second semiconductor chip are clock wirings for supplying clock signals to the clock terminals of the flip-flops, timing design due to variations in semiconductor manufacturing processes The above constraints can be relaxed and the yield after manufacturing can be improved. In addition, it is possible to cancel the variation in delay characteristics of each signal wiring, and to eliminate the influence due to variations in dimensions and characteristics in the clock wiring. As a result, the conventional clock synchronization design method can be applied as it is, and a CAD application used for designing a semiconductor integrated circuit can be applied with a minimum change.

Embodiment 1 FIG.
FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. FIG. 1A schematically shows a semiconductor chip constituting the semiconductor integrated circuit according to the first embodiment. FIG. 1B is a cross-sectional view taken along line A1-A1 (A2-A2 line) of a semiconductor integrated circuit obtained by bonding the semiconductor chips in FIG. In FIG. 1A, a semiconductor chip (first semiconductor chip) 1 has a clock distribution circuit 2 inside the chip, and is an external connection terminal electrically connected to the clock distribution circuit 2 on the chip surface. Bumps 3 are provided. In addition, user circuits 7 a, 7 b, and 7 c are mounted on the semiconductor chip 1.

  The semiconductor chip (second semiconductor chip) 101 has a clock distribution circuit 102 having the same function as the clock distribution circuit 2 arranged and wired on the semiconductor chip 1, and the clock distribution circuit 102 is on the semiconductor chip 1. The clock distribution circuit 2 is arranged and wired in a mirror-symmetrical position. A pad 103 is disposed on the surface of the semiconductor chip 101 at a position mirror-symmetrical to the bump 3 of the semiconductor chip 1. Further, the semiconductor chip 101 includes user circuits 107a, 107b, and 107c that perform signal transmission with the user circuits 7a, 7b, and 7c via the bumps 3 and the pads 103 in the semiconductor integrated circuit 201 shown in FIG. Implemented.

  Here, the bump 3 refers to a protruding terminal that is formed on the surface of the semiconductor chip 1 and directly exchanges signals with another semiconductor chip or a connection substrate, etc., and is a process such as vapor deposition, plating or printing. It is formed. In the present invention, the material and forming method of the bump 3 are not particularly limited. The user circuits 7a, 7b, and 7c and the user circuits 107a, 107b, and 107c are internal circuits that realize the functions of the semiconductor integrated circuit according to the first embodiment.

  As shown in FIG. 1B, in the semiconductor integrated circuit 201 according to the first embodiment, the semiconductor chip 1 and the semiconductor chip 101 are arranged so that the clock distribution circuits 2 and 102 arranged in mirror symmetry are opposed to each other. It is composed by bonding. In this configuration, the bumps 3 of the semiconductor chip 1 and the pads 103 of the semiconductor chip 102 are in contact with each other and are electrically connected.

  FIG. 2 is a diagram showing an example of an electric circuit in the semiconductor integrated circuit in FIG. 1B. The clock wiring 4 of the semiconductor chip 1 and the clock wiring 104 of the semiconductor chip 101 are electrically connected via the bumps 3 and the pads 103. The electric circuit comprised by connecting is shown. In FIG. 2, a clock wiring (first signal wiring) 4 is a wiring constituting a part of the clock distribution circuit 2 shown in FIG. 1A, and a clock wiring (second signal wiring) 104 is a clock distribution. This wiring is part of the circuit 102.

  As described above, the clock distribution circuit 2 and the clock distribution circuit 102 have the same configuration except that the clock distribution circuit 2 and the clock distribution circuit 102 are arranged on the mirror surface. Therefore, the clock buffer 5 connected to one end of the clock wiring 4; The clock buffer 105 connected to one end of the clock wiring 104 is a buffer having the same specifications. The other ends of the clock wirings 4 and 104 are input to the clock terminals of the flip-flops 6 and 106. Similarly in this case, the flip-flop 6 connected to the clock wiring 4 and the flip-flop 106 connected to the clock wiring 104 have the same configuration.

  The semiconductor chip 1 and the semiconductor chip 2 are manufactured by an existing general semiconductor process for forming a circuit on the surface of a silicon wafer. The performance of a semiconductor chip manufactured by this existing semiconductor manufacturing process has a variation within a certain range for each semiconductor chip according to the variation in the semiconductor manufacturing process, and even within a certain range even when compared within the same semiconductor chip. And have random variations.

  Therefore, the characteristics of elements such as metal wires and buffers on the clock wires 4 and 104 are also affected by variations in the semiconductor manufacturing process. That is, the clock wiring 4 and the clock wiring 104 and the buffer 5 and the buffer 105 shown in FIG. 2 are manufactured with dimensions and characteristics that deviate from a theoretical value in design by a random variation that cannot be predicted within a certain range.

  Further, as shown in FIG. 2, since the clock wirings 4 and 104 are connected by the contacts of the bumps 3 and the pads 103, the buffers for driving the clock signals are the buffers 5 and 105. That is, the characteristics of the driver are a combination of the characteristics of the buffers 5 and 105.

  In the semiconductor integrated circuit 201 according to the first embodiment, the buffer 5 and the buffer 105 are elements formed on different semiconductor chips, the semiconductor chip 1 and the semiconductor chip 101, respectively. As described above, the performance of the semiconductor chip varies randomly for each semiconductor chip in accordance with variations in the semiconductor manufacturing process, so that the buffer element is also manufactured with random variations for each semiconductor chip.

  For the sake of convenience, the characteristics are good when the switch speed of the transistor is shifted in the direction of higher speed than the theoretical value. On the other hand, the characteristics of the characteristics near the theoretical value are poor. , And into three groups. As described above, the characteristics of the elements of the buffer 5 and the elements of the buffer 105 have no correlation. Therefore, when the semiconductor integrated circuit 201 is manufactured by randomly selecting and combining the individual semiconductor chips 1 and 101, the buffers 5 and 105 of the semiconductor chips 1 and 101 have good characteristics and poor characteristics. There is a possibility that all possible combinations such as combinations of things, good and bad characteristics, etc. may occur.

  Therefore, in the first embodiment, a semiconductor chip is selected from a group in which the variation in characteristics is canceled out from a large number of grouped individuals in which the semiconductor chip 1 and the semiconductor chip 101 are manufactured, and FIG. The semiconductor integrated circuit 201 shown in FIG.

  Examples of combinations of groups that cancel out variations in characteristics of semiconductor chips include, for example, a combination of a semiconductor chip 1 having elements of the buffer 5 with good characteristics and a semiconductor chip 101 having elements of the buffer 105 having poor characteristics, or a buffer having poor characteristics. A semiconductor chip 1 having 5 elements and a semiconductor chip 101 having a buffer 105 element having good characteristics, a semiconductor chip 1 having a buffer 5 element having moderate characteristics and a semiconductor having a buffer 105 element having moderate characteristics A combination with the chip 101 is conceivable.

  With such a configuration, a single element can be configured to be combined with even a device whose characteristics are to be determined to be defective outside the allowable range, so that a semiconductor integrated circuit capable of normal operation can be obtained. In addition, although the grouping by the characteristic has been described with three examples, the number of groups can be arbitrarily increased or decreased. In other words, more strict clock skew management can be performed by increasing the grouping.

  The semiconductor integrated circuit 201 obtained as described above is used as a component of various electronic devices by being sealed in an appropriate package or the like, or after being directly mounted on a board.

  As described above, according to the first embodiment, elements that are part of different semiconductor chips and have no correlation in characteristics with each other are combined so as to cancel the variation in characteristics, and the clock signal is driven. Thus, the influence of variations in the size and characteristics of the clock wiring can be eliminated. As a result, the conventional clock synchronization design method can be applied as it is, and a CAD application used for designing a semiconductor integrated circuit can be applied with a minimum change.

  Further, according to the first embodiment, since the user circuit is mounted on both the semiconductor chips 1 and 101, the package of the semiconductor integrated circuit 201 is compared with the user circuit configured by one normal semiconductor chip. The size of the user circuit per area can be nearly doubled. For this reason, it is possible to improve the mounting efficiency when mounting the semiconductor integrated circuit 201 on the substrate. This is suitable for a semiconductor integrated circuit that realizes a plurality of circuit blocks having the same function called a multi-core or multi-processor in one chip or package.

  In the first embodiment, the semiconductor integrated circuit 201 in which the user circuit is mounted on both the two semiconductor chips 1 and 101 is shown. However, the user circuit is mounted on either the semiconductor chip 1 or the semiconductor chip 101. It is good also as a structure. For example, the user circuits 7a to 7c are mounted on the semiconductor chip 1 shown in FIG. 1A, and the clock distribution circuit 102 and the pad 103 are mounted on the semiconductor chip 101 without mounting the user circuits 107a to 107c.

  In this case, the operation related to the clock skew is the same as that of the first embodiment, but the mounting scale of the user circuit is approximately halved. On the other hand, it is not necessary to allocate the bumps 3 and pads 103 for connection for signal transmission between the user circuits of the semiconductor chips 1 and 101, and all of the bumps 3 and pads 103 can be used for clock skew countermeasures. Therefore, more detailed clock skew adjustment is possible.

  In addition, since the functions to be mounted on the semiconductor chip 101 can be minimized, the probability of occurrence of a defect due to a manufacturing defect can be reduced, and as a result, the manufacturing yield of the semiconductor integrated circuit can be improved. It is.

  In addition to the above, a user circuit equivalent to both the semiconductor chips 1 and 101 can be mounted, and the semiconductor integrated circuit 201 can be configured to use the user circuit of one of the semiconductor chips. In this case, even if a manufacturing defect occurs in the user circuit, if the clock distribution circuit is not defective, a semiconductor chip having a good user circuit is selected as the counterpart semiconductor chip and the semiconductor integrated circuit 201 is configured. A good product can be obtained as the semiconductor integrated circuit 201 as a whole.

  Although the first embodiment has been described focusing on the user circuit and the buffer electrically connected via the bump formed on the surface of the semiconductor chip, another circuit on the semiconductor chip is electrically connected. The same effect can be obtained even with bumps. Further, although the number of bumps and pads is small in FIG. 1, the present invention can be applied to a large number of bumps and pads.

  In addition, in the synchronous circuit of the semiconductor integrated circuit, the signal that needs to be subjected to the strictest delay management is a clock signal. Therefore, in the first embodiment, a circuit that propagates a clock signal is described as an application target of the present invention. However, the present invention can be directly applied to a reset signal other than the clock signal and other user-defined signals.

1 is a diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. It is a figure which shows the example of an electric circuit in the semiconductor integrated circuit in FIG.1 (b).

Explanation of symbols

  1, 101 semiconductor chip (first semiconductor chip, second semiconductor chip), 2,102 clock distribution circuit, 3 bumps, 4, 104 clock wiring (first signal wiring, second signal wiring), 5, 105 buffer, 6, 106 flip-flop, 7a-7c, 107a-107c user circuit, 103 pad, 201 semiconductor integrated circuit.

Claims (2)

A first semiconductor chip having a bump for external connection and a first signal wiring electrically connected to the bump, and for external connection arranged in a mirror-symmetrical position with respect to the bump in the first semiconductor chip And a second semiconductor chip having a second signal wiring electrically connected to the pad,
Each signal wiring in the first semiconductor chip and the second semiconductor chip has a delay characteristic that cancels a variation in the delay characteristic of each other,
The first semiconductor chip and the second semiconductor chip are bonded so that the bumps and the pads arranged in mirror symmetry are in contact with each other, and the wiring is arranged in a mirror symmetry position via the bumps and the pads. The first signal wiring and the second signal wiring are electrically connected, and all or a part of the signal wiring arranged in the first semiconductor chip and the second semiconductor chip is a clock terminal of a flip-flop. A semiconductor integrated circuit characterized in that it is a clock wiring for supplying a clock signal to. At least one of the first semiconductor chip and second semiconductor chip, No placement claim 1 Symbol, characterized in that is signaled via the signal line is mounted an internal circuit for realizing functions of the semiconductor integrated circuit Semiconductor integrated circuit.

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