JP5221153B2 - 正確なプレデコードを保証する方法及び装置 - Google Patents

正確なプレデコードを保証する方法及び装置 Download PDF

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Publication number
JP5221153B2
JP5221153B2 JP2007557203A JP2007557203A JP5221153B2 JP 5221153 B2 JP5221153 B2 JP 5221153B2 JP 2007557203 A JP2007557203 A JP 2007557203A JP 2007557203 A JP2007557203 A JP 2007557203A JP 5221153 B2 JP5221153 B2 JP 5221153B2
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Japan
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instruction
padding
embedded data
instructions
length
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Expired - Fee Related
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JP2007557203A
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English (en)
Japanese (ja)
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JP2008535043A5 (ru
JP2008535043A (ja
Inventor
スミス、ロドニー・ウェイン
ディーフェンダーファー、ジェームズ・ノリス
ブリッジス、ジェフリー・トッド
サートリウス、トマス・アンドリュー
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/447—Target code generation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
  • Executing Machine-Instructions (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
JP2007557203A 2005-02-25 2006-02-24 正確なプレデコードを保証する方法及び装置 Expired - Fee Related JP5221153B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/066,957 2005-02-25
US11/066,957 US7376815B2 (en) 2005-02-25 2005-02-25 Methods and apparatus to insure correct predecode
PCT/US2006/006677 WO2006091857A1 (en) 2005-02-25 2006-02-24 Methods and apparatus to insure correct predecode

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2011133198A Division JP2011238251A (ja) 2005-02-25 2011-06-15 正確なプレデコードを保証する方法及び装置

Publications (3)

Publication Number Publication Date
JP2008535043A JP2008535043A (ja) 2008-08-28
JP2008535043A5 JP2008535043A5 (ru) 2011-03-17
JP5221153B2 true JP5221153B2 (ja) 2013-06-26

Family

ID=36570932

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2007557203A Expired - Fee Related JP5221153B2 (ja) 2005-02-25 2006-02-24 正確なプレデコードを保証する方法及び装置
JP2011133198A Pending JP2011238251A (ja) 2005-02-25 2011-06-15 正確なプレデコードを保証する方法及び装置

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2011133198A Pending JP2011238251A (ja) 2005-02-25 2011-06-15 正確なプレデコードを保証する方法及び装置

Country Status (9)

Country Link
US (1) US7376815B2 (ru)
EP (1) EP1866745B1 (ru)
JP (2) JP5221153B2 (ru)
KR (1) KR101019393B1 (ru)
CN (1) CN101160560B (ru)
CA (1) CA2598704A1 (ru)
IL (1) IL185427A0 (ru)
RU (1) RU2405188C2 (ru)
WO (1) WO2006091857A1 (ru)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE602005007216D1 (de) * 2004-05-27 2008-07-10 Nxp Bv Mikroprozessor und verfahren zur anweisungsausrichtung
US7376815B2 (en) * 2005-02-25 2008-05-20 Qualcomm Incorporated Methods and apparatus to insure correct predecode
US8214376B1 (en) * 2007-12-31 2012-07-03 Symantec Corporation Techniques for global single instance segment-based indexing for backup data
US9268573B2 (en) * 2012-11-02 2016-02-23 Michael Rolle Methods for decoding and dispatching program instructions
US9495542B2 (en) * 2013-02-28 2016-11-15 Trustees Of Boston University Software inspection system
TWI522102B (zh) * 2013-04-30 2016-02-21 長庚醫療財團法人 組合物於製備治療或預防性治療痤瘡的藥物之用途
US10795681B2 (en) * 2014-12-23 2020-10-06 Intel Corporation Instruction length decoding
US11836035B2 (en) 2021-08-06 2023-12-05 Western Digital Technologies, Inc. Data storage device with data verification circuitry

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5448746A (en) * 1990-05-04 1995-09-05 International Business Machines Corporation System for comounding instructions in a byte stream prior to fetching and identifying the instructions for execution
US5193180A (en) * 1991-06-21 1993-03-09 Pure Software Inc. System for modifying relocatable object code files to monitor accesses to dynamically allocated memory
US6460116B1 (en) * 1998-09-21 2002-10-01 Advanced Micro Devices, Inc. Using separate caches for variable and generated fixed-length instructions
US6253309B1 (en) * 1998-09-21 2001-06-26 Advanced Micro Devices, Inc. Forcing regularity into a CISC instruction set by padding instructions
US6192465B1 (en) * 1998-09-21 2001-02-20 Advanced Micro Devices, Inc. Using multiple decoders and a reorder queue to decode instructions out of order
US6247097B1 (en) * 1999-01-22 2001-06-12 International Business Machines Corporation Aligned instruction cache handling of instruction fetches across multiple predicted branch instructions
DE602005007216D1 (de) 2004-05-27 2008-07-10 Nxp Bv Mikroprozessor und verfahren zur anweisungsausrichtung
US7376815B2 (en) * 2005-02-25 2008-05-20 Qualcomm Incorporated Methods and apparatus to insure correct predecode

Also Published As

Publication number Publication date
RU2007135359A (ru) 2009-03-27
US20060195830A1 (en) 2006-08-31
CA2598704A1 (en) 2006-08-31
CN101160560B (zh) 2012-03-28
JP2008535043A (ja) 2008-08-28
EP1866745B1 (en) 2014-07-23
US7376815B2 (en) 2008-05-20
RU2405188C2 (ru) 2010-11-27
EP1866745A1 (en) 2007-12-19
IL185427A0 (en) 2008-01-06
CN101160560A (zh) 2008-04-09
KR101019393B1 (ko) 2011-03-07
KR20070106789A (ko) 2007-11-05
WO2006091857A1 (en) 2006-08-31
JP2011238251A (ja) 2011-11-24

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