JP5215894B2 - Communication control circuit, communication node, communication system, and communication control method and program - Google Patents

Description

  The present invention relates to a communication control circuit, a communication node, a communication system, a communication control method, and a program, and more particularly to a technique suitable for data communication conforming to FlexRay.

  FlexRay is one of LAN (Local Area Network) standards formulated for the purpose of application to communication systems related to automobile control and the like. As a communication method, a method (time trigger method) in which a data transmission right is given at a certain timing for each communication node constituting the communication system is adopted.

  As shown in FIG. 7, the communication cycle in the FlexRay includes a static segment 700 and a dynamic segment 800 that are communication periods, and an idle time 900 that is a non-communication period.

  Among these, the static segment 700 is composed of l static slots 710_1 to 710_1 having a fixed time length (hereinafter may be collectively referred to as reference numeral 710). Each static slot 710 is used for data (frame) transmission by one communication node.

  On the other hand, the dynamic segment 800 is configured by m dynamic slots 810_1 to 810_m (hereinafter may be collectively referred to as reference numeral 810). Each dynamic slot 810 includes n minislots 820_1 to 820_n (hereinafter, may be collectively referred to as reference numeral 820) having a fixed time length. However, n is a variable value different for each dynamic slot. That is, the dynamic slots 810_1 to 810_m may have different time lengths.

  Each mini-slot 820 includes a set of macro ticks 831 and 832. Each communication node sets the boundary between the macrotics 831 and 832 as a minislot activity point 840, and identifies the dynamic slots 810_1 to 810_m according to the presence / absence of data transmission / reception at the minislot activity point 840.

  More specifically, the transmitting communication node starts data transmission at one minislot activity point in one dynamic slot and ends at the last minislot activity point. At the end of data transmission, the communication node increments the identification number (counter value) of the dynamic slot by “1”. On the other hand, the receiving communication node monitors the presence / absence of data reception (active / idle of the reception channel) for each minislot activity point, and sets the counter value of the dynamic slot to “1” when “no data reception”. Incrementing the counter value is interrupted when the data is received. As a result, the counter values of the dynamic slots are matched between the communication nodes on the transmission side and the reception side (that is, the phases of the dynamic slots 810 are matched) (see, for example, Patent Document 1).

  In recent years, the use of a communication method in the dynamic segment has been demanded as an alternative to an event trigger method represented by CAN (Controller Area Network) (a communication method in which a node generates a communication request in accordance with an event).

JP-T-2006-509388

  However, in Patent Document 1 described above, when one communication node in a dynamic segment erroneously identifies a dynamic slot due to the influence of noise or the like, communication between the one communication node and another communication node is not possible. Therefore, there is a problem that the communication efficiency is remarkably lowered. This is because a phase shift of a dynamic slot occurs between communication nodes.

  This problem will be described in detail by taking as an example a case where two communication nodes 1a and 1b communicate via the network bus B1 as shown in FIG.

  As shown in FIG. 8B, the communication nodes 1a and 1b sequentially assign slots independently of each other, and assign IDs (Identifiers) to the slots. In the following description, this ID is referred to as an allocation slot ID.

  Now, it is assumed that the communication node 1a transmits the frame FR1 through the transmission channel Tx in the slot having the allocation slot ID 100s = “5”. At this time, the communication node 1a adds the allocation slot ID 100s = “5” to the frame FR1. When the transmission of the frame FR1 is completed, the communication node 1a increments the allocation slot ID 100s to “6” to prepare for the next communication.

  On the other hand, the communication node 1b receives the frame FR1 in the slot with the allocation slot ID 100s = “5” via the reception channel Rx. At this time, since the assigned slot ID 100s matches the slot ID added to the frame FR1, the communication node 1b determines that the frame FR1 has been normally received. When the reception of the frame FR1 is completed, the communication node 1b increments the allocation slot ID 100s to “6” to prepare for the next communication.

  Thereafter, it is assumed that only the communication node 1a detects the activation of the reception channel Rx accompanying the occurrence of noise in the slot with the allocation slot ID 100s = “6”. In this case, the communication node 1a interrupts the increment of the assigned slot ID during the noise generation period. On the other hand, the communication node 1b that detects the idle of the reception channel Rx continues incrementing the assigned slot ID.

  As a result, for example, as shown in the figure, the allocation slot ID 100s in the communication node 1a is “7”, while the allocation slot ID 100s in the communication node 1b is “8”. That is, the phases of the slots do not match between the communication nodes 1a-1b. For this reason, subsequent communication between the communication nodes 1a-1b becomes impossible.

  Specifically, for example, when the communication node 1b transmits the frame FR2 with the slot ID = “8” added, the communication node 1a adds the assigned slot ID 100s = “7” in the own communication node to the frame FR2. Since the slot ID does not match, it is determined that a reception error has occurred in the frame FR2. Similarly, when the communication node 1a transmits the frame FR3 to which the slot ID = “9” is added, the communication node 1b transmits the assigned slot ID 100s = “10” in the communication node and the slot ID added to the frame FR3. Therefore, it is determined that a reception error has occurred in the frame FR3.

  A communication control circuit according to an aspect of the present invention is implemented in a communication node, receives an allocation unit that allocates a plurality of time slots used for communication with another communication node, and a frame from the other communication node A determination unit that determines whether or not the frame is received in one time slot to be received, and when the frame is not received in the one time slot, the phase of the subsequent time slot is set to the other communication node. And an instruction unit for instructing correction in accordance with the phase of the time slot in the communication node.

  A communication control circuit according to another aspect of the present invention is mounted on a communication node, assigns a plurality of time slots used for communication with another communication node, and responds to an instruction from the other communication node. The phase of the time slot is corrected in accordance with the phase of the time slot in the other communication node.

  In addition, the communication node according to one aspect of the present invention allocates a plurality of time slots used for communication with other communication nodes, and a frame from the other communication node is received in one time slot to receive the frame. If the frame is not received in the one time slot, the phase of the subsequent time slot is matched with the phase of the time slot in the own communication node when the frame is not received in the one time slot. A control circuit for instructing to correct; and a processing circuit for processing the frame when it is received in the one time slot.

  In addition, a communication node according to another aspect of the present invention allocates a plurality of time slots used for communication with other communication nodes, and sets the phase of the time slot according to an instruction from the other communication node. A control circuit that performs correction in accordance with the phase of the time slot in the other communication node; and a generation circuit that generates a frame to be transmitted in one time slot.

  In addition, a communication system according to one embodiment of the present invention includes a plurality of communication nodes that respectively allocate a plurality of time slots used for communication. In this communication system, one communication node determines whether or not a frame from another communication node is received in one time slot to receive the frame, and the frame is received in the one time slot. If not, the other communication node is instructed to correct the phase of the subsequent time slot in accordance with the phase of the time slot in the own communication node. The other communication node corrects the phase of the time slot in its own communication node according to the instruction.

  A communication control method according to an aspect of the present invention provides a communication control method in a communication node. This communication control method allocates a plurality of time slots used for communication with another communication node, determines whether or not a frame from the other communication node is received in one time slot to receive the frame, When the frame is not received in the one time slot, the other communication node is instructed to correct the phase of the subsequent time slot in accordance with the phase of the time slot in the communication node.

  A communication control method according to another aspect of the present invention provides a communication control method in a communication node. In this communication control method, a plurality of time slots used for communication with another communication node are allocated, and in response to an instruction from the other communication node, the phase of the time slot is set to the phase of the time slot in the other communication node. Correct according to.

  The communication control program according to an aspect of the present invention receives a process for assigning a plurality of time slots used for communication with another communication node to the communication node and a frame from the other communication node. A process for determining whether or not the frame has been received in one power slot, and when the frame is not received in the one time slot, the phase of the subsequent time slot is set to the communication node with respect to the other communication node. And a process for instructing correction in accordance with the phase of the time slot at.

  Furthermore, the communication control program according to another aspect of the present invention includes a process of assigning a plurality of time slots used for communication with another communication node to the communication node, and an instruction from the other communication node, And processing for correcting the phase of the time slot in accordance with the phase of the time slot in the other communication node.

  That is, in the present invention, one communication node that has detected a time slot phase shift due to the influence of noise or the like causes another communication node to correct the phase shift. For this reason, it is possible to greatly shorten the communication disabled period between the communication nodes in the dynamic segment described above.

  According to the present invention, it is possible to improve the communication efficiency in the dynamic segment, and thus it is possible to ensure the real-time property of various control processes in the communication system.

It is the block diagram which showed the structural example of the communication node which concerns on embodiment of this invention. It is the block diagram which showed the structural example of the protocol controller used for the communication control circuit which concerns on embodiment of this invention. It is the flowchart figure which showed the example of a frame reception process in the communication control circuit which concerns on embodiment of this invention. It is the time chart figure which showed the frame transmission / reception operation example in the communication node which concerns on embodiment of this invention. It is the flowchart figure which showed the example of a correction frame transmission process in the communication control circuit which concerns on embodiment of this invention. It is the flowchart figure which showed the example of a slot correction process in the communication control circuit which concerns on embodiment of this invention. It is the figure which showed the structural example of the communication cycle in FlexRay. It is a figure for demonstrating the subject of the communication system in a dynamic segment.

  Embodiments of a communication control circuit according to the present invention and a communication node that implements the communication control circuit will be described below with reference to FIGS. In the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted as necessary for the sake of clarity.

[Configuration example]
The communication node 1 according to the present embodiment shown in FIG. 1 is executed by a transceiver 10 that performs frame transmission / reception via the network bus B1, a communication control circuit 20, a CPU (Central Processing Unit) 30, and the CPU 30. The memory 40 stores programs and the like, various devices 50 such as sensors, and an external I / F 60 that functions as an interface with these devices 50. The communication control circuit 20, the CPU 30, the memory 40, and the external I / F 60 are interconnected by an internal bus B2. The CPU 30 corresponds to the processing circuit and the generation circuit described above, and processes a frame (hereinafter, referred to as a reception frame) FRr received from another communication node, while the other communication node A frame to be transmitted (hereinafter sometimes referred to as a transmission frame) FRt is generated. In the following description, the reception frame FRr and the transmission frame FRt may be collectively referred to as a symbol FR.

  Further, the communication control circuit 20 conforms to the FlexRay, a shift register 21 that drives (samples) the reception frame FRr and the transmission frame FRt bit by bit, a frame buffer 22 for storing the reception frame FRr and the transmission frame FRt. And a protocol controller 23 for transferring the frame FR between the shift register 21 and the frame buffer 22. Here, in the frame buffer 22, an area for storing the reception frame FRr (hereinafter referred to as a reception frame storage area) 221 and an area for storing the transmission frame FRt (hereinafter referred to as a transmission frame storage area). 222) is formed. The received frame FRr includes a slot ID (hereinafter referred to as reception slot ID) 100r added by another communication node at the time of transmission and data generated by the other communication node (hereinafter referred to as reception data). 200r) is included. Similarly, in the transmission frame FRt, a slot ID (hereinafter referred to as a transmission slot ID) 100t in the communication node 1 to be transmitted, and data generated by the CPU 30 (hereinafter referred to as transmission data) are transmitted. ) 200t.

  Further, as shown in FIG. 2, the protocol controller 23 includes a slot allocation unit 231, a reception error determination unit 232, a slot correction instruction unit 233, and a slot correction information table 234.

  Among them, the slot allocation unit 231 sequentially allocates slots in the communication node 1 and assigns an allocation slot ID 100s to each slot, as in the above-described Patent Document 1, and receives a reception error determination unit 232 and a slot correction instruction unit. 233, respectively.

  In addition, the reception error determination unit 232 compares the allocation slot ID 100s output from the slot allocation unit 231 with the reception slot ID 100r added to the reception frame FRr acquired from the shift register 21 to thereby determine the frame FRr. Determine reception errors. If no reception error has occurred, the reception error determination unit 232 transfers the reception frame FRr to the frame buffer 22.

  On the other hand, when a reception error has occurred, the reception error determination unit 232 executes processing related to the slot correction frame FRa shown in (A) and (B) below. Here, the slot correction frame FRa is a frame for causing another communication node to correct the phase shift of the slot. The slot correction frame FRa is used because transmission other than the frame is prohibited in the FlexRay. When the communication node 1 is operated in accordance with a communication standard that permits transmission other than frames, various control signals or the like may be used instead of the slot correction frame FRa.

(A) Slot ID in the communication node 1 (hereinafter referred to as a correction frame transmission slot ID) 100ta to which the slot correction frame FRa is to be transmitted, and a correction value (hereinafter referred to as a slot ID) instructed to other communication nodes (Referred to as correction slot ID) 100a and processing for storing these IDs 100ta and 100a in the slot correction information table 234.
(B) Processing for outputting the reception error detection signal SG to the slot correction instruction unit 233 and instructing transmission of the slot correction frame FRa.

  When the reception error determination unit 232 detects reception of the slot correction frame FRa from another communication node, the reception error determination unit 232 executes processing related to slot correction shown in (C) below. Here, the reception error determination unit 232 detects reception of the slot correction frame FRa when a specific correction frame code 400 is set in the reception frame FRr. The correction frame code 400 is stored in advance in the slot correction information table 234.

 (C) The correction slot ID 100a set in the slot correction frame FRa is stored in the slot correction information table 234, and a slot correction instruction INS is output to the slot allocation unit 231 to correct the allocation slot ID 100s. Processing to correct with slot ID 100a.

  In addition, the slot correction instruction unit 233, when the allocation slot ID 100s output from the slot allocation unit 231 and the correction frame transmission slot ID 100ta stored in the slot correction information table 234 match, from the internal temporary buffer 2331 The correction frame FRa is read and transferred to the shift register 21. Here, the temporary buffer 2331 stores a slot correction frame FRa and a transmission request bit 300 provided corresponding to the frame FRa. The slot correction instruction unit 233 sets the transmission request bit 300 to “ON” when receiving the reception error detection signal SG from the reception error determination unit 232, and the allocation slot ID 100s and the correction frame transmission slot ID 100ta match. Wait to do. The slot correction frame FRa has the same format as the transmission frame FRt shown in FIG. The slot correction instruction unit 233 sets the correction slot ID 100a stored in the slot correction information table 234 and the correction frame code 400 described above in the transmission data 200t in the slot correction frame FRa.

  Although not shown, the communication control circuit 20 also includes a transmission unit that transmits the transmission frame FRt (transfer from the frame buffer 22 to the shift register 21) in the same manner as in Patent Document 1 described above.

  Next, the operation of the present embodiment will be described with reference to FIGS.

[Example of operation]
As shown in FIG. 3, first, the transceiver 10 shown in FIG. 1 stores the frame FRr received via the network bus B1 in the shift register 21 in the communication control circuit 20 (step S1). Upon detecting this, the reception error determination unit 232 in the protocol controller 23 determines whether or not the reception slot ID 100r added to the reception frame FRr matches the allocation slot ID 100s output from the slot allocation unit 231. (Step S2).

  As shown in FIG. 4, the communication node 1 shown in FIG. 1 is applied as the communication nodes 1a and 1b shown in FIG. 8 (a), and the communication nodes 1a and 1b are similar to those in FIG. 8 (b). For example, when receiving and transmitting frames FR1 to FR3, the reception error determination unit 232 in the communication node 1b that has received the frame FR1 receives the reception slot ID 100r ("5") and the assigned slot ID in step S2. It is determined that 100s ("5") matches. Then, the reception error determination unit 232 transfers the frame FR1 to the frame buffer 22 (step S3). The CPU 30 detecting this reads out the frame FR1 from the frame buffer 22 and processes it.

  Thereafter, it is assumed that only the communication node 1a detects the activation of the reception channel Rx accompanying the occurrence of noise in the slot with the allocation slot ID 100s = “6”. In this case, the slot allocation unit 231 in the communication node 1a interrupts the increment of the allocation slot ID 100s during the noise generation period. On the other hand, the slot allocation unit 231 in the communication node 1b that detects the idle of the reception channel Rx continues incrementing the allocation slot ID 100s. As a result, as in FIG. 8B, the allocation slot ID 100s in the communication node 1a is “7”, while the allocation slot ID 100s in the communication node 1b is “8”. That is, the phases of the slots do not match between the communication nodes 1a-1b.

  In this case, the reception error determination unit 232 in the communication node 1a that has received the frame FR2 detects a mismatch between the reception slot ID 100r (“8”) and the allocation slot ID 100s (“7”) in step S2. Then, the reception error determination unit 232 determines whether or not the frame FR2 is the slot correction frame FRa (step S4).

  Now, since the frame FR2 is not the slot correction frame FRa (because the correction frame code 400 described above is not set), the reception error determination unit 232 detects a reception error of the frame FR2 (step S5), and performs a slot correction instruction. The slot correction frame FRa is transmitted by the cooperative operation with the unit 233 (step S6).

  Specifically, as shown in FIG. 5, first, the reception error determination unit 232 determines the correction frame transmission slot ID 100ta and the correction slot ID 100a and stores them in the slot correction information table 234 (step S61). In the example of FIG. 4, the correction frame transmission slot ID 100ta is set to the slot ID ("8") immediately after the reception error is detected, and the correction slot ID 100a is the next slot ID ("9") of the correction frame transmission slot ID 100ta. ") Is set.

  Then, the reception error determination unit 232 generates a reception error detection signal SG for the slot correction instruction unit 233, and sets the transmission request bit 300 shown in FIG. 2 to “ON” (step S62).

  Upon detecting this, the slot correction instruction unit 233 sets the contents of the slot correction frame FRa in the temporary buffer 2331. Specifically, the slot correction instruction unit 233 sets the correction frame transmission slot ID 100ta and the correction slot ID 100a read from the slot correction information table 234 to the transmission slot ID 100t and the transmission data 200t in the slot correction frame FRa, respectively. (Step S63).

  Then, the slot correction instruction unit 233 waits for the allocation slot ID 100s output from the slot allocation unit 231 and the correction frame transmission slot ID 100ta to match (that is, the transmission timing of the slot correction frame FRa arrives) ( Step S64).

  When the allocation slot ID 100s matches the correction frame transmission slot ID 100ta, the slot correction instruction unit 233 transfers the slot correction frame FRa to the shift register 21 (step S65). The slot correction frame FRa is transmitted to the network bus B1 by the transceiver 10 (see FIG. 1).

  Returning to FIG. 2, the reception error determination unit 232 in the communication node 1 b that has received the slot correction frame FRa goes through the above-described steps S 2 and S 4, and then assigns the assigned slot ID 100 s through a cooperative operation with the slot assignment unit 231. The correction process is executed (step S7).

  Specifically, as shown in FIG. 6, first, the reception error determination unit 232 extracts the correction slot ID 100a from the slot correction frame FRa and stores it in the slot correction information table 234 (step S71). Then, the reception error determination unit 232 generates a slot correction instruction INS for the slot allocation unit 231 (step S72).

  Receiving this instruction INS, the slot allocation unit 231 corrects the next allocation slot ID 100s to the correction slot ID 100a read from the slot correction information table 234 (step S73).

  In the example of FIG. 4, the assigned slot ID 100s immediately after receiving the slot correction frame FRa in the communication node 1b is corrected to “9”. Accordingly, the frame FR3 with the slot ID = “9” transmitted by the communication node 1a is normally received by the communication node 1b. Further, the phase of each subsequent slot (each assigned slot ID) also matches between the communication nodes 1a and 1b.

  As described above, in the present embodiment, even when a slot phase shift occurs due to noise generation between communication nodes, the communication disabled period is significantly larger than that in Patent Document 1 described above. It can be shortened. Further, when the slot correction frame is transmitted immediately after detecting the phase shift of the slot, the communication disabled period can be minimized.

  Note that the present invention is not limited to the above-described embodiments, and it is apparent that various modifications can be made by those skilled in the art based on the description of the scope of the claims. For example, each process of the communication control circuit shown in the above embodiment can be provided as a program for causing a communication node to execute (for example, a plug-in to firmware incorporated in an existing communication control circuit). .

1, 1a, 1b Communication node 10 Transceiver 20 Communication control circuit 21 Shift register 22 Frame buffer 23 Protocol controller 30 CPU
40 Memory 50 Various devices 60 External I / F
100s Allocated slot ID
100r Receive slot ID
100t Transmission slot ID
100ta correction frame transmission slot ID
100a Correction slot ID
200r reception data 200t transmission data 221 reception frame storage area 222 transmission frame storage area 231 slot allocation unit 232 reception error determination unit 233 slot correction instruction unit 234 slot correction information table 300 transmission request bit 400 correction frame code 700 static segment 710, 710_1 ˜710 — 1 Static slot 800 Dynamic segment 810, 810 — 1 to 810 — m Dynamic slot 820, 820 — 1 to 820 — n Minislot 831, 832 Macrotic 840 Minislot activity point 900 Idle time 2331 Temporary buffer FR, FR1 to FR3 Frame FRr Received frame FRt Transmission frame FRa Slot correction frame SG Reception error detection signal INS Slot correction instruction B1 Network Kubus B2 Internal bus Tx Transmission channel Rx Reception channel

Claims (17)

A communication control circuit implemented in a communication node,
An assigning unit for assigning a plurality of time slots used for communication with other communication nodes;
A determination unit for determining whether or not a frame from the other communication node is received in one time slot to receive the frame;
An instruction unit that instructs the other communication node to correct the phase of the subsequent time slot in accordance with the phase of the time slot in the communication node when the frame is not received in the one time slot; ,
A communication control circuit. In claim 1,
An identifier of a time slot used for transmission by the other communication node is added to the frame,
The assigning unit assigns an identifier to each of the plurality of time slots;
The communication is characterized in that the determination unit determines whether or not the frame has been received in the one time slot by comparing an identifier added to the frame with an identifier given by the allocation unit. Control circuit. In claim 1 or 2,
The communication control circuit, wherein the instruction unit instructs the correction by a frame. In claim 3,
The communication control circuit, wherein the instruction unit transmits a frame instructing the correction in a next time slot that is continuous with the one time slot. A communication control circuit implemented in a communication node,
A plurality of time slots used for communication with other communication nodes are allocated, and the phase of the time slot is corrected in accordance with the time slot phase of the other communication node according to an instruction from the other communication node. Communication control circuit. In claim 5,
The communication control circuit, wherein the instruction is performed by a frame from the other communication node. A plurality of time slots used for communication with other communication nodes are allocated, and it is determined whether or not a frame from the other communication node is received in one time slot to receive the frame. A control circuit that instructs the other communication nodes to correct the phase of the subsequent time slot in accordance with the phase of the time slot in the communication node,
Processing circuitry for processing the frame when it is received in the one time slot;
A communication node with A plurality of time slots used for communication with other communication nodes are allocated, and the phase of the time slot is corrected in accordance with the time slot phase of the other communication node according to an instruction from the other communication node. A control circuit;
A generation circuit for generating a frame to be transmitted in one time slot;
A communication node with A plurality of communication nodes that respectively allocate a plurality of time slots used for communication,
If one communication node receives a frame from another communication node in one time slot to receive it, and if the frame is not received in the one time slot, the other communication node Instructing the communication node to correct the phase of the subsequent time slot in accordance with the phase of the time slot in the communication node,
The communication system in which the other communication node corrects the phase of the time slot in the own communication node according to the instruction. A communication control method in a communication node,
Allocate multiple time slots used for communication with other communication nodes,
It is determined whether or not the frame from the other communication node is received in one time slot to receive the frame,
A communication control method for instructing the other communication node to correct the phase of the subsequent time slot in accordance with the phase of the time slot in the communication node when the frame is not received in the one time slot. . In claim 10,
Whether or not the frame is received in the one time slot is added to the frame, the identifier of the time slot used for transmission by the other communication node, and the identifier assigned to each of the plurality of time slots. The communication control method characterized by determining by comparison with. In claim 10 or 11,
A communication control method, wherein the correction is instructed by a frame. In claim 12,
A communication control method, wherein a frame instructing the correction is transmitted in a next time slot following the one time slot. A communication control method in a communication node,
Allocate multiple time slots used for communication with other communication nodes,
A communication control method for correcting a phase of the time slot according to an instruction from the other communication node according to a phase of the time slot in the other communication node. In claim 14,
The communication control method, wherein the instruction is performed by a frame from the other communication node. In the communication node,
A process of assigning a plurality of time slots used for communication with other communication nodes;
A process of determining whether or not a frame from the other communication node has been received in one time slot to receive the frame;
If the frame is not received in the one time slot, instructing the other communication node to correct the phase of the subsequent time slot according to the phase of the time slot in the communication node;
Communication control program to execute. In the communication node,
A process of assigning a plurality of time slots used for communication with other communication nodes;
In accordance with an instruction from the other communication node, a process of correcting the phase of the time slot according to the phase of the time slot in the other communication node;
Communication control program to execute.

Images