JP5203358B2 - データをプリフェッチする装置および方法 - Google Patents
データをプリフェッチする装置および方法 Download PDFInfo
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- JP5203358B2 JP5203358B2 JP2009514258A JP2009514258A JP5203358B2 JP 5203358 B2 JP5203358 B2 JP 5203358B2 JP 2009514258 A JP2009514258 A JP 2009514258A JP 2009514258 A JP2009514258 A JP 2009514258A JP 5203358 B2 JP5203358 B2 JP 5203358B2
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- 238000000034 method Methods 0.000 title claims description 19
- 238000012549 training Methods 0.000 description 16
- 238000010586 diagram Methods 0.000 description 13
- 230000000694 effects Effects 0.000 description 11
- 230000008901 benefit Effects 0.000 description 7
- 230000008859 change Effects 0.000 description 6
- 230000001343 mnemonic effect Effects 0.000 description 6
- 101100321720 Arabidopsis thaliana PP2AA1 gene Proteins 0.000 description 4
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
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- 239000004065 semiconductor Substances 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/383—Operand prefetching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/24—Loading of the microprogram
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/6024—History based prefetching
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Description
Claims (10)
- 第1の命令の実行の一環として情報がアクセスされる第1のメモリロケーションがキャッシュにおいて利用可能でない場合、第1のキャッシュミス標識を受信するステップ(711)と、
前記第1のキャッシュミス標識を受信すると、第1のテーブルの第1のレコードに情報を記憶するステップ(712)であって、前記情報は、
前記第1の命令の位置を特定する命令情報(412,421)と、
前記第1のメモリロケーションを特定するメモリロケーション情報(422,411,413)とを有するステップと、
第2の命令の実行の一環として情報がアクセスされる第2のメモリロケーションがキャッシュにおいて利用可能でない場合、第2のキャッシュミス標識を受信するステップと、
前記第2のメモリロケーションが前記第1のエントリに記憶されている前記第1のメモリロケーションから定義された距離内にあると判定されると、前記第1のレコードに第1のプリフェッチ情報(421,414)を記憶するステップとを含み、
前記第1のプリフェッチ情報は、前記第2のメモリロケーションに基づくメモリ位置情報を含み、前記第1のプリフェッチ情報の記憶後は、前記第1のレコードは、前記第1のメモリロケーションを特定する前記メモリロケーション情報および前記第2のメモリロケーションを特定する前記メモリ位置情報を有する、方法。 - 前記第1のプリフェッチ情報は前記第2のメモリアドレスを含むメモリ位置範囲を特定している請求項1記載の方法。
- 前記第1のプリフェッチ情報は参照メモリ位置に対するオフセットを含む、請求項2記載の方法。
- 前記第1のプリフェッチ情報は前記第2のメモリアドレスを含む、請求項1記載の方法。
- 前記第2のキャッシュミス標識を受信すると、前記第1のテーブルの第2のレコードに情報を記憶するステップを更に有し、前記情報は、
前記第2の命令の位置を特定する命令情報(412,422)と、
前記第2のメモリ位置を特定するメモリ位置情報(422,411,413)とを有する請求項1に記載の方法。 - 前記第2のメモリ位置が、前記第1のエントリに記憶されている前記第1のメモリ位置の定義された距離内にあることが判定されると、前記第1のレコードに記憶されている値(421,415)をインクリメントするステップを更に有する請求項1記載の方法。
- 前記第1のテーブル(331)は、連想メモリ(CAM)であり、前記連想メモリ(CAM)の命令位置情報をアドレス指定するために内容が使用される請求項1記載の方法。
- 前記第1の命令の前記位置で命令を実行すると、第2のキャッシュミス標識を受信するステップ(713)と、
前記第1のレコードが前記第1の命令の前記位置を特定する命令情報を含むことが判定されると、プリフェッチするメモリを決定するステップ(733)を更に含む、請求項1記載の方法。 - プリフェッチする前記メモリは複数の不連続なメモリ領域を含む請求項8に記載の方法。
- 前記第2のキャッシュミス標識を受信し、前記第1のレコードが前記第1の命令の前記位置を特定する命令情報を含むことを決定すると、前記第1のレコードに記憶されている値(923)をインクリメントするステップを更に含む、請求項8に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/448,337 | 2006-06-07 | ||
US11/448,337 US7774578B2 (en) | 2006-06-07 | 2006-06-07 | Apparatus and method of prefetching data in response to a cache miss |
PCT/US2007/008372 WO2007145700A1 (en) | 2006-06-07 | 2007-04-05 | Apparatus and method of prefetching data |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009540429A JP2009540429A (ja) | 2009-11-19 |
JP5203358B2 true JP5203358B2 (ja) | 2013-06-05 |
Family
ID=38509069
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009514258A Active JP5203358B2 (ja) | 2006-06-07 | 2007-04-05 | データをプリフェッチする装置および方法 |
Country Status (8)
Country | Link |
---|---|
US (1) | US7774578B2 (ja) |
JP (1) | JP5203358B2 (ja) |
KR (1) | KR101423748B1 (ja) |
CN (1) | CN101467135A (ja) |
DE (1) | DE112007001397B4 (ja) |
GB (1) | GB2453079B (ja) |
TW (1) | TW200821925A (ja) |
WO (1) | WO2007145700A1 (ja) |
Families Citing this family (35)
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US8391309B2 (en) * | 2007-02-20 | 2013-03-05 | Arris Group, Inc. | Method and system for using mnemonic symbols to provision channel attributes with an attribute mask |
GB2466695B (en) * | 2007-06-18 | 2011-11-23 | Fujitsu Ltd | Processor and prefetch support program |
US9274965B2 (en) | 2008-12-15 | 2016-03-01 | International Business Machines Corporation | Prefetching data |
US8195889B2 (en) * | 2009-03-25 | 2012-06-05 | Advanced Micro Devices, Inc. | Hybrid region CAM for region prefetcher and methods thereof |
US8677049B2 (en) * | 2009-04-13 | 2014-03-18 | Advanced Micro Devices, Inc. | Region prefetcher and methods thereof |
US8850123B2 (en) | 2010-10-19 | 2014-09-30 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Cache prefetch learning |
US20120144124A1 (en) * | 2010-12-07 | 2012-06-07 | Advanced Micro Devices, Inc. | Method and apparatus for memory access units interaction and optimized memory scheduling |
CN102156633A (zh) * | 2011-04-18 | 2011-08-17 | 北京北大众志微系统科技有限责任公司 | 预执行指导的数据预取方法及系统 |
US8856452B2 (en) * | 2011-05-31 | 2014-10-07 | Illinois Institute Of Technology | Timing-aware data prefetching for microprocessors |
US9026739B2 (en) | 2012-03-07 | 2015-05-05 | Advanced Micro Devices, Inc. | Multimode prefetcher |
US9176878B2 (en) * | 2012-03-15 | 2015-11-03 | Oracle International Corporation | Filtering pre-fetch requests to reduce pre-fetching overhead |
US9098418B2 (en) * | 2012-03-20 | 2015-08-04 | Apple Inc. | Coordinated prefetching based on training in hierarchically cached processors |
US9311247B1 (en) | 2012-03-20 | 2016-04-12 | Marvell International Ltd. | Method and apparatus for detecting patterns of memory accesses in a computing system with out-of-order program execution |
US9164900B1 (en) | 2012-05-23 | 2015-10-20 | Marvell International Ltd. | Methods and systems for expanding preload capabilities of a memory to encompass a register file |
US9116815B2 (en) * | 2012-06-20 | 2015-08-25 | Advanced Micro Devices, Inc. | Data cache prefetch throttle |
US9390018B2 (en) | 2012-08-17 | 2016-07-12 | Advanced Micro Devices, Inc. | Data cache prefetch hints |
US9348753B2 (en) | 2012-10-10 | 2016-05-24 | Advanced Micro Devices, Inc. | Controlling prefetch aggressiveness based on thrash events |
US9021210B2 (en) | 2013-02-12 | 2015-04-28 | International Business Machines Corporation | Cache prefetching based on non-sequential lagging cache affinity |
US9047173B2 (en) * | 2013-02-21 | 2015-06-02 | Advanced Micro Devices, Inc. | Tracking and eliminating bad prefetches generated by a stride prefetcher |
KR102070136B1 (ko) | 2013-05-03 | 2020-01-28 | 삼성전자주식회사 | 프리페치를 위한 캐시 제어 장치 및 그 캐시 제어 장치를 이용한 프리페치 방법 |
US9256541B2 (en) * | 2014-06-04 | 2016-02-09 | Oracle International Corporation | Dynamically adjusting the hardware stream prefetcher prefetch ahead distance |
US9971694B1 (en) | 2015-06-24 | 2018-05-15 | Apple Inc. | Prefetch circuit for a processor with pointer optimization |
US9904624B1 (en) | 2016-04-07 | 2018-02-27 | Apple Inc. | Prefetch throttling in a multi-core system |
US10180905B1 (en) | 2016-04-07 | 2019-01-15 | Apple Inc. | Unified prefetch circuit for multi-level caches |
US10296460B2 (en) * | 2016-06-29 | 2019-05-21 | Oracle International Corporation | Prefetch bandwidth throttling by dynamically adjusting miss buffer prefetch-dropping thresholds |
US10331567B1 (en) | 2017-02-17 | 2019-06-25 | Apple Inc. | Prefetch circuit with global quality factor to reduce aggressiveness in low power modes |
KR102429429B1 (ko) | 2017-03-24 | 2022-08-04 | 삼성전자주식회사 | 전자 장치 및 그 동작방법 |
US11232533B2 (en) * | 2019-03-15 | 2022-01-25 | Intel Corporation | Memory prefetching in multiple GPU environment |
US11726917B2 (en) * | 2020-06-26 | 2023-08-15 | Advanced Micro Devices, Inc. | Method and apparatus for a page-local delta-based prefetcher |
US11561796B2 (en) * | 2020-07-15 | 2023-01-24 | International Business Machines Corporation | Linked miss-to-miss instruction prefetcher |
JP2022097858A (ja) | 2020-12-21 | 2022-07-01 | 富士通株式会社 | 計算機および計算方法 |
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US20240184702A1 (en) * | 2022-12-02 | 2024-06-06 | SiFive, Inc. | Prefetching Cache Blocks Based on an Address for a Group and a Bit Field |
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JP3969009B2 (ja) * | 2001-03-29 | 2007-08-29 | 株式会社日立製作所 | ハードウェアプリフェッチシステム |
US6782453B2 (en) | 2002-02-12 | 2004-08-24 | Hewlett-Packard Development Company, L.P. | Storing data in memory |
US7139897B2 (en) | 2002-04-01 | 2006-11-21 | Hewlett-Packard Development Company, L.P. | Computer instruction dispatch |
CN1849591A (zh) * | 2002-11-22 | 2006-10-18 | 皇家飞利浦电子股份有限公司 | 使用高速缓存未命中模式来寻址跨距预测表 |
-
2006
- 2006-06-07 US US11/448,337 patent/US7774578B2/en active Active
-
2007
- 2007-04-05 WO PCT/US2007/008372 patent/WO2007145700A1/en active Application Filing
- 2007-04-05 KR KR1020097000208A patent/KR101423748B1/ko active IP Right Grant
- 2007-04-05 JP JP2009514258A patent/JP5203358B2/ja active Active
- 2007-04-05 CN CNA200780021102XA patent/CN101467135A/zh active Pending
- 2007-04-05 DE DE112007001397.4T patent/DE112007001397B4/de active Active
- 2007-04-05 GB GB0900132A patent/GB2453079B/en active Active
- 2007-04-27 TW TW096114931A patent/TW200821925A/zh unknown
Also Published As
Publication number | Publication date |
---|---|
CN101467135A (zh) | 2009-06-24 |
US7774578B2 (en) | 2010-08-10 |
TW200821925A (en) | 2008-05-16 |
GB0900132D0 (en) | 2009-02-11 |
KR20090026333A (ko) | 2009-03-12 |
US20070288697A1 (en) | 2007-12-13 |
KR101423748B1 (ko) | 2014-08-01 |
WO2007145700A1 (en) | 2007-12-21 |
DE112007001397B4 (de) | 2020-10-29 |
GB2453079B (en) | 2011-06-29 |
JP2009540429A (ja) | 2009-11-19 |
DE112007001397T5 (de) | 2009-04-23 |
GB2453079A (en) | 2009-03-25 |
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