JP5202472B2 - Instruction placement program, instruction placement apparatus, and instruction placement method - Google Patents

Description

  The present invention relates to an instruction arrangement program, an instruction arrangement apparatus, and an instruction arrangement method for the purpose of power saving of a memory.

  Conventionally, portable devices such as mobile phones and small information terminals have been widely used, and development of power saving technology has been actively promoted in an environment where these portable devices are driven by power supplied from a storage battery. . As a power saving technique, a technique for guaranteeing efficient operation of a logic part such as a reduction in processing load of a logic part of a portable device and processing distribution is mainly provided. However, in recent years, the capacity of the memory mounted on the portable device is also increasing from the viewpoint of the operating environment recommended by the OS and various applications and the improvement of the processing speed. Therefore, the memory has more influence on the power and circuit scale than the logic of the portable device, and attention is focused on the power saving technology for the memory.

  As a power-saving technique that has already been provided, a technique is known in which a memory is divided into memory banks for each predetermined capacity, and power supply to unused memory banks is dynamically controlled. When the power supply to the memory bank is actually controlled, a time overhead is required between the normal mode in which power is supplied and the standby mode in which power is not supplied. Therefore, a technique for constructing a system that eliminates overhead by analyzing a switching state between a call state and a standby state and reflecting the analysis result is disclosed (for example, see Patent Document 1 below).

JP 2002-26803 A

  However, in the case of the above-described conventional technology, although power saving can be achieved, the application target is limited to a portable device having a telephone function for generating a call and waiting. Generally, a code for calling an instruction provided as a firmware is stored in a memory bank. Therefore, as in the case of a mobile phone terminal, if the instructions used for each situation can be clearly classified when calling and waiting, if the instruction codes for calling the classified instructions are arranged in different memory banks, Good.

  However, the instruction codes cannot be uniquely classified as described above except for devices having a telephone function. As a result, even if the instruction code is distributed, it is necessary to constantly supply power to each memory bank, or the switching process of the memory bank that is the power supply destination frequently occurs, resulting in inefficient power supply. There was a problem of becoming.

  In order to solve the above-described problems caused by the prior art, the present disclosure provides an instruction placement program and instruction placement that enable efficient power supply by appropriately placing instruction codes in a memory bank regardless of the function of the device. It is an object of the present invention to provide an apparatus, an instruction arrangement method, and a power control system that realizes power saving of a memory bank by a target apparatus in which instruction codes are arranged by the above-described technique.

  In order to solve the above-described problem and achieve the object, the present disclosure provides a process in which a computer acquires a call graph representing a call relationship between instructions in firmware applied to a target device, and the acquired call graph Are classified into the first instruction group located in a predetermined hierarchy or higher from the top and the second instruction group other than the instruction, and the first instruction group. Processing for creating placement information set so that a code for calling an instruction is placed in the first memory bank to which power is always supplied among the memory banks mounted on the target device, and the created placement And a process of outputting information.

  According to the disclosed technique, the call relationship between instructions is specified by a call graph, and is classified into a frequently used instruction group and other instruction groups. Then, among the memory banks installed in the target device, the memory bank that is the power supply destination is created by creating the placement information that is set to place the frequently used instruction group in the memory bank to which power is always supplied Therefore, efficient power control can be achieved by avoiding frequent switching between the two.

  According to the instruction allocation program, the instruction allocation apparatus, and the instruction allocation method, the instruction code is appropriately allocated to the memory bank regardless of the function of the apparatus to enable efficient power supply and to the power control system. According to this, there is an effect that the power saving of the memory bank is realized by the target device in which the instruction code is arranged by the above technique.

It is explanatory drawing which shows the outline | summary of the instruction arrangement | positioning process concerning this Embodiment. It is explanatory drawing which shows the structural example of an electric power control system. It is explanatory drawing which shows an example of a recursive call. 6 is a call graph illustrating an example of firmware having a configuration in which a MAIN function is at the highest level. It is a call graph which shows the calling relationship of an actual function. It is a block diagram which shows the hardware constitutions of the instruction arrangement | positioning apparatus concerning this Embodiment. It is a block diagram which shows the functional structure of the instruction arrangement | positioning apparatus concerning this Embodiment. It is explanatory drawing which shows the procedure of a command arrangement | positioning process. It is explanatory drawing which shows the structure of a control apparatus. It is explanatory drawing which shows the structural example of a control signal. 5 is a flowchart (part 1) illustrating a procedure for creating arrangement information according to the first embodiment. 7 is a flowchart (part 2) illustrating a procedure for creating arrangement information according to the first embodiment. 6 is a flowchart (part 3) illustrating the arrangement information creation procedure according to the first embodiment. 10 is a flowchart (part 4) illustrating a procedure for creating arrangement information according to the first embodiment. 10 is a flowchart (part 5) illustrating a procedure for creating arrangement information according to the first embodiment. It is explanatory drawing which shows the image of counting of the number of branches. It is explanatory drawing which shows instruction arrangement | positioning when it is counted that the number of branches is 2 or less. It is explanatory drawing which shows the example of a movement to a constantly ON bank. It is explanatory drawing which shows a process when the capacity | capacitance in a bank is over. It is explanatory drawing which shows the relationship between the static call graph of the function contained in a program code, and a memory map. It is explanatory drawing which shows the calculation process of the division position when there is no branch in a function. It is explanatory drawing which shows the calculation process of the division position when there is a branch in a function. It is explanatory drawing which shows the structure of the electric power control system by a multi-core. It is explanatory drawing which shows the example of electric power control by a multi-core. It is a flowchart which shows the output procedure of a log. It is a data table which shows the format of a log. It is explanatory drawing which shows the data size example of each function. It is a data table which shows the example of a log output. It is a data table which shows the output example of the log after correction. It is a flowchart which shows the source correction procedure using a log. It is a block diagram which shows the functional structure of the instruction arrangement | positioning apparatus in Examples 4-9. It is explanatory drawing which shows an example of a call graph. FIG. 10 is an explanatory diagram illustrating an instruction arrangement process according to a fourth embodiment. 4 is a data table showing a data example of a table C. 3 is a data table showing a data example of a table S. 4 is a data table showing a data example of a table M. It is explanatory drawing which shows the detailed process of a parent function determination part. It is a data table which shows the example of creation of Table 1. It is explanatory drawing which shows the detailed process of an always ON memory allocation part. It is a flowchart which shows the procedure of always ON memory allocation processing. It is a data table which shows the example of data of table M_rest * table 3 at the time of initialization. 3 is a data table showing an example of creating table 2. It is a flowchart which shows the procedure of the allocation process to the table 3. It is a data table which shows the example of data of table M_rest. 4 is a data table showing an example of assignment to table 3. It is a data table which shows the execution result of always ON memory allocation processing. It is explanatory drawing which shows the detailed process of a code amount calculation part. It is a flowchart which shows the procedure of code amount calculation. 5 is a data table showing an example of creating table 4. It is explanatory drawing which shows the detailed process of a power control memory allocation part. It is a flowchart which shows the procedure of power control memory allocation. It is a data table which shows the example of data of table M_rest * table 5 at the time of initialization. It is a data table which shows the sorted table 4. It is a flowchart which shows the procedure of the allocation process to the table 5. It is a data table which shows the example of data of table M_rest according to total code amount. 6 is a data table showing an example of data assigned to the table 5. It is a data table which shows the execution result of the allocation process of a power control memory. It is explanatory drawing which shows the detailed process of an allocation adjustment and an address calculation part. It is a flowchart which shows the procedure of an allocation adjustment process. It is a data table which shows the example of data of the table 3 after allocation adjustment. It is a data table which shows the example of an output of Table 6-1. It is a flowchart which shows the procedure of an address calculation process. It is a data table which shows the data example of the array addr at the time of initialization. It is a flowchart which shows the procedure of the memory address setting process of always ON memory. It is a data table which shows the data example of the table 6 and the array addr at the time of the start of address calculation of always ON memory. It is a data table which shows the example of a data of the table 6 and array addr at the time of completion of address calculation of always ON memory. It is a flowchart which shows the procedure (the 1) of the memory address setting process of a power control memory. It is a flowchart which shows the procedure (the 2) of the memory address setting process of a power control memory. It is a data table which shows the example of data of the table 6 and array addr at the time of the address calculation start of a power control memory. It is a data table which shows the example of data of the table 6 and array addr after execution of address calculation of a power control memory. It is a data table which shows the example of data of the table 6 and the array addr at the time of address calculation about a descendant function. It is a data table which shows the example of data of Table 6 and array addr at the time of the completion of address calculation about a descendant function. It is explanatory drawing which shows the process of the parent function determination part in Example 5. FIG. It is explanatory drawing which shows the parent function determination process using a weighted sum. It is a data table which shows the example of weighting. FIG. 20 is an explanatory diagram illustrating a memory allocation process according to a sixth embodiment. It is a data table which shows the example of data of the memory information with allocation priority information. It is a flowchart which shows the procedure of the sort at the time of always ON memory allocation. It is a data table which shows the example of data of the memory information with the allocation priority information after a sort. It is a flowchart which shows the procedure of the sort at the time of power control memory allocation. FIG. 10 is an explanatory diagram illustrating power control memory allocation processing according to a seventh embodiment. It is a flowchart which shows the procedure of evaluation of remaining memory amount. It is a data table which shows the example of data of the table 5 and table M_rest at the time of evaluation of remaining memory amount. FIG. 20 is an explanatory diagram illustrating function replication processing according to an eighth embodiment. 22 is a flowchart illustrating a procedure of function replication processing according to an eighth embodiment. It is a data table which shows the example of data of the table C used as the function replication object. It is a data table which shows the example of data of the table C after function duplication completed. It is a flowchart which shows the procedure (the 1) of the function duplication process in Example 9. It is a flowchart which shows the procedure (the 2) of the function duplication process in Example 9. It is a data table which shows the example of data of the table C after function duplication completed. It is a data table which shows the example of data of table M_rest after function duplication.

  Exemplary embodiments of an instruction arrangement program, an instruction arrangement apparatus, and an instruction arrangement method according to the present invention will be explained below in detail with reference to the accompanying drawings.

(Outline of instruction placement processing)
First, an overview of the instruction placement process according to the present embodiment will be described. FIG. 1 is an explanatory diagram showing an overview of instruction placement processing according to the present embodiment. In the present embodiment, firstly, the arrangement information 105 in which the instruction code arrangement position of the memory bank mounted on the target device for which power saving of the memory is desired is set is created.

  As a specific procedure, first, the firmware source 101 of the target device is compiled by the compiler 110 to extract the object 102. At the same time, the call graph creation unit 120 creates a call graph 103 representing the call relationship between instructions from the source 101. Thereafter, the instruction allocation device 100 divides the memory 102 mounted in the object 102, the call graph 103, and the target device prepared as described above (the total number of memories into the number of memory banks in each capacity). The memory division information 104 indicating whether the data is divided is acquired, and the arrangement information 105 is created. The created arrangement information 105 is used for instruction code arrangement in the power control system 200 in the memory bank of the target device.

  Here, FIG. 2 is an explanatory diagram illustrating a configuration example of the power control system. As shown in FIG. 2, in the present embodiment, a target device including a processor 201, a peripheral circuit 202, a power source 203, a control device 204, a memory bank (banks 0 to 3) 205, and a bus 206. Of these, the hardware (power supply 203, control device 204, and memory bank 205) related to power control to the memory bank 205 will be described below as the power control system 200. As a matter of course, the configuration in FIG. 2 is an example of the target device, and the number of processors 201 and the contents of the peripheral circuit 202 are not particularly limited as long as the configuration corresponding to the power control system 200 is included.

  In addition, the memory banks in which the instruction codes are arranged are roughly divided into two types: “always ON banks” to which power is always supplied and “power control banks” to which power is supplied only when reading instruction codes. It shall be prepared. For example, in the case of the memory bank 205 of FIG. 2, the banks 0 and 1 are always set to the ON bank, the banks 2 and 3 are set to the power control bank, and so on.

  Therefore, the memory bank 205 is provided with a control device 204 as a control mechanism for controlling ON / OFF of power. Note that the total number of memory banks 205 mounted differs depending on the target device, and depending on the configuration of instructions in the firmware, the capacity of instruction codes placed in the always-on banks also increases and decreases, and the number of always-on banks also changes. . Accordingly, the control device 204 needs to be prepared in a number corresponding to the number of memory banks 205.

  As described above, the hardware configuration of the target device for using the arrangement information 105 created by the instruction arrangement processing according to the present embodiment has been described. In addition, the arrangement information ensures efficient power supply. In order to create 105, the following prerequisites must be satisfied as a firmware configuration.

1) Does not include a recursive call 2) Does not include a pointer function 3) Has a configuration in which a MAIN function is positioned at the highest level without an OS

  FIG. 3 is an explanatory diagram showing an example of a recursive call. The recursive call of the above 1) means a configuration in which a once called function is called by a lower function. When a recursive call is included, when a call graph described later is created, a circular graph is formed as shown in FIG. 3, and appropriate instruction arrangement cannot be performed.

  In addition, in the case of the above 2) pointer function, in a configuration in which a function stored at a specific address is called in an instruction as described below, instructions to be called are scattered everywhere. That is, it indicates a configuration in which an address 0x08000000 is placed in the following func ().

Voice func ()
{
...
IF (FLAG == 1) bra 0x08000000
...

  FIG. 4A is a call graph illustrating an example of firmware having a configuration in which the MAIN function is at the highest level. The configuration in which the MAIN function in 3) is positioned at the highest level is a configuration in which the MAIN function is positioned at the highest level and functions representing other instructions are arranged hierarchically as shown in FIG. Means. FIG. 4B is a call graph showing an actual function call relationship. In the call graph shown in FIG. 4A, since the functions called at a plurality of locations are different from each other, a plurality of the same functions are displayed. Actually, as shown in FIG. 4B, even if functions called at a plurality of places are represented as one point, they are configured in the same calling relationship as in FIG.

  As described above, both call graphs in FIGS. 4-1 and 4-2 have the same call relationship, and even if the same function appears in a plurality of places as in FIG. 4-1, it is actually the same. It is called by the instruction code placed at the location. In the following, in consideration of visual intelligibility, instruction placement processing will be described using a call graph that represents functions called from a plurality of functions as shown in FIG.

(Hardware configuration of instruction placement device)
Next, the hardware configuration of the instruction arrangement device 100 according to the present embodiment will be described. FIG. 5 is a block diagram showing a hardware configuration of the instruction arrangement device according to the present exemplary embodiment. In FIG. 5, the instruction placement device 100 includes a CPU (Central Processing Unit) 501, a ROM (Read-Only Memory) 502, a RAM (Random Access Memory) 503, a magnetic disk drive 504, a magnetic disk 505, and a communication. An I / F (Interface) 506, an input device 507, and an output device 508 are provided. Each component is connected by a bus 510.

  Here, the CPU 501 governs overall control of the instruction arrangement device 100. The ROM 502 stores various programs such as a boot program and an instruction arrangement program for realizing the instruction arrangement processing according to the present embodiment. The RAM 503 is used as a work area for the CPU 501. The magnetic disk drive 504 controls data update / reference with respect to the magnetic disk 505 according to the control of the CPU 501. The magnetic disk 505 stores data written under the control of the magnetic disk drive 504. In the hardware configuration of FIG. 5, the magnetic disk 505 is used as the recording medium, but other recording media such as an optical disk and a flash memory may be used.

  The communication I / F 506 is connected to a network (NET) 509 such as a LAN (Local Area Network), a WAN (Wide Area Network), and the Internet through a communication line, and other information processing apparatuses and other external devices are connected via the network 509. Connected to the device. The communication I / F 506 controls an internal interface with the network 509 and controls input / output of data from an external device. As a configuration example of the communication I / F 506, for example, a modem or a LAN adapter may be employed.

  The input device 507 accepts an external input to the instruction arrangement device 100. Specific examples of the input device 507 include a keyboard and a mouse. In the case of a keyboard, for example, keys for inputting letters, numbers, and various instructions are provided, and data is input. Moreover, a touch panel type input pad or a numeric keypad may be used. In the case of a mouse, for example, the cursor is moved, a range is selected, or a window is moved or the size is changed. Further, a trackball or a joystick may be used as long as they have the same function as a pointing device.

  The output device 508 outputs the arrangement information created by the instruction arrangement process. Specific examples of the output device 508 include a display and a printer. In the case of a display, for example, data such as a cursor, an icon or a tool box, a document, an image, and function information is displayed. Further, a CRT, a TFT liquid crystal display, a plasma display, or the like can be employed as this display. In the case of a printer, for example, image data and document data are printed. Further, a laser printer or an ink jet printer can be employed.

(Functional configuration of instruction placement device)
Next, a functional configuration of the instruction arrangement device will be described. FIG. 6 is a block diagram showing a functional configuration of the instruction arrangement device according to the present exemplary embodiment. As illustrated in FIG. 6, the instruction arrangement device 100 includes an acquisition unit 601, a classification unit 602, a creation unit 603, an output unit 604, a determination unit 605, an extraction unit 606, and a calculation unit 607. It is. Specifically, the functions (acquisition unit 601 to calculation unit 607) serving as the control unit store, for example, an instruction arrangement program stored in a storage area such as the ROM 502, RAM 503, and magnetic disk 505 shown in FIG. The function is realized by executing or by the communication I / F 506.

  The acquisition unit 601 has a function of acquiring a call graph representing a call relationship between instructions in firmware applied to the target device. The call graph 103 is created in advance by the call graph creation unit 120 or the like as shown in FIG. Since the call graph creation unit 120 is realized by a call graph creation tool (for example, codevidz, gprof, pycallgraph, etc.) widely used as a known technique, detailed description thereof is omitted. The acquired call graph is stored in a storage area such as the RAM 503 and the magnetic disk 505.

  The classification unit 602 has a function of classifying the instructions represented by the call graph 103 acquired by the acquisition unit 601. Specifically, the classification unit 602 is positioned above a predetermined hierarchy from the highest-level instruction represented by the MAIN function among the instructions represented by the call graph 103 (for example, an instruction group as illustrated in FIG. 4A). And a second instruction group other than the first instruction group. For example, a classification such as an instruction within two layers from the top and other instructions is performed. Data representing the classification result is stored in a storage area such as the RAM 503 and the magnetic disk 505.

  In this manner, by providing the classification unit 602, it is possible to classify instructions in the firmware into instructions with high call frequency and other instructions. Here, as a basic technique for classifying into instructions with high calling frequency and other instructions, the hierarchy in the call graph 103 is used as a judgment criterion. The classifying unit 602 can also use processing results obtained by a determining unit 605, an extracting unit 606, and a calculating unit 607, which will be described later, as a method for classifying instructions with a high call frequency (for details, refer to each function). In the description of the part).

  The creation unit 603 creates the placement information 105 that sets in which memory bank the instruction code for calling up the command according to the classification result by the classification unit 602 is placed. Specifically, the arrangement information 105 set so that the code for calling the instruction classified into the first instruction group by the classification unit 602 is always arranged in the ON bank is created. In addition, the creation unit 603 sets the code for calling the instructions classified into the second instruction group (instructions other than the first instruction group among the instructions in the firmware) to be arranged in the power control bank. The arrangement information 105 is created.

  Furthermore, the creation unit 603 creates placement information that is set so that instructions that match the instructions in the upper hierarchy are placed in the same power control bank when setting the placement of the code that calls the second instruction group. To do. In other words, the creation unit 603 prevents setting such that the instruction codes of the instructions classified into the second instruction group are unnecessarily arranged in any of the power control banks. Then, the creation unit 603 can perform setting so that at least instructions having the same higher order instruction are arranged in the same power control bank.

  Therefore, in the example of FIG. 4A, when the instructions up to the upper two layers are classified into the first instruction group, the lower instruction groups (C1, C2, D1 to D3, E1 to E3) called from B1 are changed. The lower instruction group (C3, D2, D4, E2 to E4) called from B2 is set to be placed in the same power control bank. The created arrangement information 105 is stored in a storage area such as the RAM 503 and the magnetic disk 505.

  In this way, by providing the creation unit 603, it is possible to create the placement information 105 that is set so that the instruction code of the frequently called instruction (first instruction group) is always placed in the ON bank. By placing instructions with a high calling frequency preferentially in the always-on bank, the opportunity to call instructions placed in the power control bank is reduced. That is, since the frequency of calling instructions arranged in a power control bank that may not be supplied with power can be suppressed to a low level, the overhead described in the conventional problem is unlikely to occur.

  The output unit 604 has a function of outputting the arrangement information 105 created by the creation unit 603. The output format includes, for example, display on a display provided as the output device 508, print output to a printer, and transmission to an external apparatus through the communication I / F 506. The output arrangement information 105 is stored in a storage area such as the RAM 503 and the magnetic disk 505.

  The determination unit 605 has a function of determining whether or not a specific command is included in the commands represented by the call graph 103 acquired by the acquisition unit 601. The specific command determined by the determination unit 605 can be arbitrarily set by the user. Therefore, a frequently used instruction can be set as a specific instruction according to the configuration of the instruction in the firmware. The determination result by the determination unit 605 is stored in a storage area such as the RAM 503 and the magnetic disk 505. When the determination unit 605 determines that a specific command is included, the creation unit 603 creates placement information that is set to place a code that calls the specific command in the always-on bank. .

  In this manner, by providing the determination unit 605, it is possible to create arrangement information set so that the instruction code of the designated instruction is always arranged in the ON bank regardless of the hierarchy represented by the call graph 103. Therefore, it is possible to flexibly set the instruction code arrangement in accordance with the firmware instruction configuration.

  The extraction unit 606 has a function of extracting an instruction that is a call target from a predetermined number or more of the instructions represented by the call graph 103 acquired by the acquisition unit 601. The predetermined number can be appropriately set by the user. Therefore, when 3 is set as the predetermined number, for example, the extracting unit 606 refers to the call relationship of the call graph 103 and extracts an instruction in which the call relationship is generated three times or more. The extraction result by the extraction unit 606 is stored in a storage area such as the RAM 503 and the magnetic disk 505. When an instruction is extracted by the extraction unit 606, the creation unit 603 creates placement information that is set to place a code that calls the extracted command in the always-on bank.

  In this manner, by providing the extraction unit 606, it is possible to extract an instruction that may be called from a plurality of instructions. The high possibility of being called from a plurality of instructions means that the frequency of use is high. Therefore, by providing the extraction unit 606, as in the determination unit 605 described above, a command that is frequently used can be automatically specified without specifying a command that is assumed to be frequently used by the user's manual work. Can be extracted.

  The calculation unit 607 has a function of calculating the total amount of code data set to be always placed in the ON bank according to the placement information. By calculating the total amount of data when the instruction code is arranged in advance by the calculation unit 607, it is possible to determine whether or not the instruction code can always be stored in the ON bank. The calculated data is stored in a storage area such as the RAM 503 and the magnetic disk 505. The creation unit 603 changes the number of always-on banks according to the value of the total amount of data calculated by the calculation unit 607, and distributes the code for calling the first instruction group to the constantly-on banks after the change. Create placement information that is set to be placed.

  The calculation unit 607 may calculate the total amount of data for each code set to be arranged in the same memory bank 205 according to the arrangement information regardless of the always-on bank or the power control bank. Further, the total amount of data of each bank calculated by the calculation unit 607 is provided to the user by being output by the output unit 604.

  In this manner, by providing the calculation unit 607, it is possible to determine whether or not the instruction code classified as the first instruction group can be physically placed in the always-on bank. In addition to the always-on bank, it can be determined whether the second command group classified for placement in the power control bank can be placed in the power control bank. Based on this calculation result, it is possible to determine whether instruction codes cannot be placed (bank capacity is insufficient) or not, and the number of always-on banks and power control banks can be increased or decreased, making efficient bank configuration Is possible.

(Instruction placement procedure)
Next, the procedure of instruction placement processing by the instruction placement apparatus 100 will be described. FIG. 7 is an explanatory diagram showing a procedure of instruction arrangement processing. As shown in FIG. 7, in the following description, a case will be described in which the firmware instruction code arrangement information 105 represented by the call graph 103 illustrated in FIG.

1)
First, since it is necessary to set at least one always-on bank as an initial setting, one of the memory banks 205 (for example, bank 0) is set to the always-on bank to control power. Shall not be performed. In addition, the total number of memory banks 205 is set to N (= 4) in order to control the placement process in the power control bank according to the procedure described later.

2)
Next, referring to the call relationship between the MAIN function and the interrupt handler in the call graph 103, the branch to the lower-order function having the direct call relationship is specified in order. When the number of branches specified here is N-1, the function immediately after the branch is set as the highest function of each bank. In the case of FIG. 7, two branches B1 and B2 are identified from the MAIN function, and one branch B3 is identified from the interrupt handler, for a total of three functions. As described above, since N = 4, the number of branches = N−1, and the functions B1, B2, and B3 are the highest functions.

  When the specified number of branches is less than N-1, the MAIN function is further shifted to a lower function to specify a branch. For example, in the example of FIG. 7, the lower C3 is further specified from B1, and the lower C1, C2 and B2. After specifying the lower branch, if it is still less than N−1, the branch to the lower function is further specified, and the same specifying process is repeated until the specified function becomes N−1.

  If the number of branches exceeds N-1 when a lower function is specified, the specifying process is terminated and a function connected to the lower level from each branch destination is called. Calculate the total size of the instruction code. However, when the size is calculated, functions used in multiple branch destinations are excluded. For example, in FIG. 7, when calculating the sum of the functions connected to the lower level from B1, D2, D3, E2, and E3 are also connected to the lower level of B2 and B3 in the same hierarchy. Therefore, it is excluded when calculating the total size of instruction codes connected to B1 or less. N-1 items are selected from the larger size thus obtained and set as the most significant function of each bank.

3)
The top-level function calculated in the above 2) and a set of functions lower than that are arranged in the power control bank in the memory bank 205. The remaining functions (MAIN, interrupt handler, etc.) are always placed in the ON bank.

4)
According to the above 3), the rough instruction code arrangement is completed, and then an adjustment process for more efficient arrangement is performed according to the contents of the function. First, among the functions arranged in the power control banks other than the always-on bank, functions and library functions used in a plurality of banks are moved to the always-on bank.

5)
Further, the size of each power control bank excluding the always-on bank is compared with the sum of instruction codes of the arranged functions. As a result of the comparison, for the power control bank in which it is determined that the instruction code cannot be stored, the process further proceeds to a process for dividing each function in the bank. For example, a branchable function is searched by referring to the lower level connection for the highest level function in the bank. Again, as in 2) above, the total size of instruction codes for calling a function connected to the lower level from the branch destination is calculated, and the branch is selected so that it can be placed in the power control bank.

6)
Next, in the memory bank 205, the head part of the highest function arranged in the power control bank is always turned ON for the time required for the power control overhead.

7)
Thereafter, the size of the always-on bank is compared with the total size of instruction codes of the arranged functions. As a result of this comparison, if it is determined that the instruction code cannot be stored in the always-on bank, the number of always-on banks in the memory bank 205 is increased, and the placement process in the power control bank is performed as described above. ) If the number of ON banks cannot be increased any more due to the implementation of the memory bank 205, the processing is terminated as it cannot be stored (providing this result to the user to correct the source 101). Used).

8)
When the processing up to the above 7) is completed, the top address (after division) and end address of the highest-order function arranged in each memory bank 205 are output as addresses for triggering power control ON and OFF as arrangement information 105. Provided. FIG. 8 is an explanatory diagram showing the configuration of the control device, and FIG. 9 is an explanatory diagram showing a configuration example of the control signal. When power control is performed by the control device 204 configured as shown in FIG. 8 using the layout information 105 created as described above, the address of the layout information 105 output by the process of 8) above is set in hardware. Add code to startup

  Then, when the control device 204 is booted, an address is set in hardware, and dynamic power control becomes possible. When the power control is started, a determination process is executed in response to a control signal reset instruction, as shown in FIG. When the PC (program counter) coincides with the ON address, it enters an operating state, and when it coincides with the OFF address, it enters a standby state.

  As described above, since the function is set for each memory bank 205 by using the instruction arrangement processing according to the present embodiment, only the always-on bank or only the always-on bank + 1 bank is always in operation, and the remaining The bank is a power control bank and is normally in a standby state. More specifically, in the example of FIG. 7, when the total number of memory banks 205 is 4 and the number of always-on banks is 1, compared to the case where power control is not performed for each memory bank 205, it is always 2 Banks and higher are in standby state. Therefore, significant power saving can be expected.

  Also, the arrangement information 105 is created in which frequently used instructions that are frequently called are always arranged in the ON bank. Accordingly, it is possible to reduce the overhead by reducing the number of times of switching to the power control bank, and it is possible to expect a power saving effect in that the standby state of the power control bank can be maintained for a long time. Several specific examples for realizing the above-described instruction arrangement processing will be described below.

Example 1
First, an example of specific logic when creating the arrangement information 105 according to the procedure described in FIG. 10 to 14 are flowcharts illustrating the arrangement information creation procedure according to the first embodiment. In order to create the arrangement information 105, first, in the flowchart of FIG. 10, first, variables used to create the arrangement information 105 are initialized (step S1001).

In step S1001, specifically, the following variables are initialized.
N: Total number of memory banks 205 P: Size of each memory bank 205 k: Number of always-on banks l: Number of branches currently reached in the call graph 103 m, n, i: Variables for counting

  Then, the variable k is set to 1 (step S1002), and the k banks among the memory banks 205 are always set to ON banks (step S1003). Next, the variable l = 1 is set (step S1004), and the number of functions is counted for each branch number l from the MAIN function (S1005). Here, FIG. 15 is an explanatory diagram showing an image of counting the number of branches. As shown in FIG. 15, according to the connection state of the call graph 103, if the number of branches is 1 = 1, the number of functions is counted as 2, and if the number of branches is 1 = 2, the number of functions is counted as 4.

  Next, the number of functions in the branch number l is compared with N−1 (step S1006). In other words, N−1 means the total number of power control banks in the memory bank 205 excluding the always-on bank. If it is determined in step S1006 that the number of functions is equal to N−1 (step S1006: Yes), the process proceeds to step S1201 in FIG.

  On the other hand, if it is determined in step S1006 that the number of functions is not equal to N-1 (step S1006: No), it is determined whether the number of functions is less than N-1 (step S1007). Here, if it is determined that the number of functions is smaller than N−1 (step S1007: Yes), the power control bank has a margin, so the number of branches 1 is incremented by 1 to increase the number of functions (step S1007). S1008) The process of step S1005 is performed again.

  When it is determined in step S1007 that the number of functions is not smaller than N−1 (step S1007: No), that is, the number of functions is larger than that of the power control bank (in the determination of step S1006). Because it is judged that the number is not the same). Therefore, the process proceeds to step S1101 in FIG.

  In the flowchart of FIG. 11, first, variables m and n are set to 0 (step S1101). Next, it is determined whether or not the nth func [m] [n] of the function branched from the mth function after l branching from the MAIN function is a function that is used elsewhere (step S1102). As described above, since m and n are set to the initial value 0, the values of m and n are added according to the processing described later, and the determination in step S1102 is performed without leaking all functions.

  If it is determined in step S1102 that the designated function is not used elsewhere (step S1102: No), cumulative addition is performed for the amount of instruction code under m. That is, provisional size [m] = provisional size [m] + (size of func [m] [n]) (step S1103). If the provisional size is obtained in step S1103, or if it is determined in step S1102 that the specified function is not used elsewhere (step S1102: Yes), all the subordinates of the mth function have been counted. It is determined whether or not (step S1104).

  If it is determined in step S1104 that there is a function that has not yet been counted (step S1104: No), n is incremented by 1 (step S1108), and the process proceeds to step S1102. On the other hand, when it is determined in step S1104 that all functions have been counted (step S1104: Yes), it is determined whether or not the variable m is smaller than the branch number l-1 (step S1105). If it is determined that the value is smaller (step S1105: Yes), m is incremented by 1 (step S1106), and the process proceeds to step S1102.

  On the other hand, if it is determined in step S1105 that the variable m is not smaller than the branch number l-1 (step S1105: No), the size in the upper l-1 is extracted as the code size (step S1107). The code size extracted here is the size obtained by extracting the top l-1 pieces of the temporary size [m] calculated in step S1103. Here, FIG. 16 is an explanatory diagram showing an instruction arrangement when it is counted that the number of branches is 2 or less. Thus, when the code size is specified, the process proceeds to step S1201 in FIG.

  As shown in FIG. 16, after shifting from the MAIN function to the number of branches l = 1 (S1) and further shifting to the number of branches l = 2 by comparison with N−1 (S2), when B1 is focused, B1 is When the function is m = 0, B2 and C1 are specified as functions under the control of m = 0. At this time, B2 becomes a function of n = 0, C1 becomes a function of n = 1, and B1, B2, and C1 are processed as described in FIG. 11 as a function 1600 under m = 0.

  In the flowchart of FIG. 12, first, a function that does not fall into the code size upper l−1 is always moved to the ON bank (step S1201). Thereafter, the variable n is set to 1 (step S1202), and the functions used in the bank n other than the bank n are always moved to the ON bank (step S1203).

  Finally, it is determined whether or not the variable n is smaller than the total number N of memory banks 205 (step S1204). If it is determined that the variable n is smaller (step S1204: Yes), n is incremented (step S1205). Based on the newly set n, the process of step S1203 is performed. If it is determined that the variable n is not smaller than the total number N of memory banks (step S1204: No), the process proceeds to step S1301 in FIG.

  Here, FIG. 17 is an explanatory diagram showing an example of movement to the always-on bank. As shown in FIG. 17, the MAIN function and A1 and A2 that did not enter the upper code size 1-1 are placed in bank 0, which is always the ON bank. Even if the function is specified under m = 0 by the processing of FIG. 12, the instructions B2 and C1 used elsewhere are always moved to bank 0, which is also an OB bank.

  Next, in the flowchart of FIG. 13, first, the variable n is always set to the value of the ON bank k (step S1301), and the variable m is set to 0 (step S1302). Note that m used here means the number of times of thinking (number of times of execution of processing). Further, the counting variable i is set to 1 (step S1303). Then, it is determined whether or not the i-th layer from the upper layer is always moved to the ON bank (step S1304).

  If it is determined that the i-th hierarchy from the upper hierarchy is not always moved to the ON bank (step S1304: No), the functions in the bank are counted (step S1305). Then, based on the counting result, it is determined whether or not the function in the bank fits in the memory bank 205 (step S1306). Here, when it is determined that the value falls within the range (step S1306: Yes), it is further determined whether the variable n is smaller than the total number N of the memory banks 205 (step S1307). If it is determined that the value is not small (step S1307: NO), the process directly proceeds to step S1401 in FIG.

  On the other hand, if it is determined in step S1307 that the variable n is smaller than the total number N of memory banks 205 (step S1307: Yes), n is incremented by 1 (step S1308), and the process proceeds to step S1302. If it is determined in step S1304 that the i-th layer from the upper layer is always moved to the ON bank (step S1304: Yes), the function in the bank is not stored in the memory bank in step S1306. If it is determined that there is not (step S1306: No), m is incremented by 1 (step S1309), and the process proceeds to step S1310.

  In step S1310, first, i is incremented by 1 (step S1310). Next, it is determined whether or not there is an i-th function from the upper layer (step S1311). If it is determined that there is no i-th function from the upper layer (step S1311: No), it is further determined whether there is an i + 1-th function from the upper layer (step S1312).

  In step S1312, when it is determined that there is no i + 1-th function from the upper layer (step S1312: No), the size is set to 0 (step S1313), and the process proceeds to step S1307. On the other hand, when it is determined that there is an i + 1-th function from the upper layer (step S1312: Yes), the process proceeds to step S1310 and i is incremented by one.

  If it is determined in step S1311 that there is an i-th function from the upper layer (step S1311: Yes), it is further determined whether there is one i-th function from the upper layer (step S1314). If it is determined that there is one i-th function from the upper layer (step S1314: YES), the process proceeds to step S1305.

  On the other hand, if it is determined in step S1314 that there is not one i-th function from the upper layer (step S1314: No), the branch having the largest size at the i-th depth is selected (step S1315). . Then, functions selected in the i-th hierarchy and thereafter, that is, functions other than the function selected in step S1315 are always moved to the ON bank (step S1316), and the process proceeds to step S1305.

  As described above, the processing shown in FIG. 13 allows the instruction placement apparatus 100 to adjust so that the sum of the instruction codes placed in the bank does not overflow. Here, FIG. 18 is an explanatory diagram showing processing when the capacity in the bank is over. For example, when the capacity per memory bank 205 is 16 [Kbytes], when the size of the upper instruction B1 of the instructions arranged in the bank 1 exceeds 16 [Kbytes] as shown in FIG. The commands B2 and C1 are always moved to the ON bank. Further, when the total size of the arranged instructions exceeds 16 [Kbytes] as in the bank 3, the smallest C4 is always moved to the ON bank. That is, the combination of B3 and C3 is arranged in the bank 3, and the total size is 13 [Kbytes]. Therefore, the arrangement is such that as much free space as possible is not generated in the bank 3.

  In the flowchart of FIG. 14, first, the head portion of the highest function of each bank is always moved to the ON bank (step S1401). In order to perform this step S1401, it is necessary to divide the target function. Therefore, the process for dividing the top part of the upper function will be described with reference to FIGS.

  FIG. 19 is an explanatory diagram showing a relationship between a static call graph of a function included in a program code and a memory map. In the example shown in FIG. 19, the main function funcM is arranged with the memory 0 being always ON bank. Further, the memory 0 is provided with constant voltage portions Z1 and Z2 of a function func1 and a function func2 called by the main function funcM. Further, in the memory 0, another function func3 called by the function func1 and the function func2 is arranged. On the other hand, the memories 1 and 2 are memories that function as power control banks, and low voltage portions K1 and K2 of the functions func1 and function func2 are arranged.

  In the process of step S1401 of FIG. 14, the functions classified as the upper functions of the power control bank are divided and always placed in the ON bank as in the functions func1 and func2 of FIG. Here, FIG. 20 is an explanatory diagram showing the calculation processing of the division position when there is no branch in the function. FIG. 21 is an explanatory diagram illustrating a division position calculation process when the function has a branch.

  When dividing a function as shown in FIG. 19, it is necessary to consider whether the function has no branch or not. First, in the case of a function having no branch as shown in FIG. 20A, first, a predetermined number of cycles N is set. This is the number of cycles for overhead due to power control. As shown in (B), a cycle for executing one instruction is defined as one cycle, and when the instruction in N cycles is traced, the farthest address that can be reached through the branch point is defined as the farthest address. Divide a part as a division point.

  Also, in the case of a function having a branch as shown in FIG. 21A, basically, as described above, the cycle number N is set in the same manner as in the case where there is no branch. Search for a route. In the case of FIG. 21, since a route 1 and a route 2 are generated, the farthest address that can be reached in N cycles is obtained for each route as shown in (B), and this becomes a dividing point, and the function is divided.

  Returning to the flowchart of FIG. 14, when the process of step S1401 is completed, it is next determined whether or not the size of the always-on bank is less than P (step S1402). If it is determined in step S1402 that the size of the bank is always less than P (step S1402: Yes), the top address of the highest function of the power control bank (after division in step S1401) and the end address are arranged. It outputs as the information 105 (step S1403). Finally, a branch instruction is added to the arrangement information 105 at the location divided in step S1401 (step S1404), and the series of processing ends.

  On the other hand, if it is determined in step S1402 that the always-on bank size is not less than P (step S1402: No), it is further determined whether or not the always-bank size is larger than P (step S1405). If it is determined that the size of the always-on bank is larger than P (step S1405: Yes), it is determined that the number of always-on banks is insufficient, and the number of always-on banks k is incremented by 1 (step S1405). S1406), the processing from step S1001 in FIG. 10 is started again. On the other hand, if it is determined in step S1405 that the size of the always-on bank is not larger than P (step S1405: No), the number of always-on banks is insufficient, but the number of always-on banks cannot be increased any more. It is determined that there is no solution without creating the optimal arrangement information 105 (step S1407), and the series of processes is terminated.

  As described above, in the first embodiment, in order to efficiently call the function represented by the call graph 103 from either the always-on bank or the power control bank based on the algorithm shown in FIGS. The set arrangement information 105 can be created.

(Example 2)
In the second embodiment, the creation of the placement information 105 when placing the firmware instruction code adapted to the target device having a multi-core will be described. FIG. 22 is an explanatory diagram showing a configuration of a multi-core power control system. As shown in FIG. 22, in the case of the power control system 2200, the instruction codes are called independently by the plurality of processors 201.

  Therefore, in the case of the power control system 2200, among the plurality of processors 201, the arrangement information 105 is created for each of the call operations of the core 1 mainly including the processor 1 and the core 2 mainly including the processor 2. And applied to the memory bank 205.

  Here, FIG. 23 is an explanatory diagram illustrating an example of power control by multi-core. In the case of multi-core as shown in FIG. 23, in order to create the arrangement information 105 for the core 1 and the arrangement information 105 for the core 2, respectively, the memory bank 205 is also classified into the core 1 and the core 2 in advance. It is necessary to keep. Furthermore, a single core can be applied to each core (cores 1 and 2) by bringing the communication function to the top as in the MAIN function and forming a tree. At this time, if the use bank is not divided for each core, the processing described in the first embodiment is applied as it is if the top MAIN function and the communication function are considered to be as many as the number of cores. can do.

(Example 3)
In the third embodiment, the instruction arrangement using the log regarding the data amount in the memory bank 205 is optimized when the arrangement information 105 is created. As described in the first embodiment, in the present embodiment, the algorithm shown in FIGS. 10 to 14 is used when the arrangement information 105 is created. In the third embodiment, the processing result relating to the size comparison in the bank in this algorithm is output as a log. The output log is used to correct the configuration of the firmware source itself in order to create more efficient arrangement information 105.

  FIG. 24 is a flowchart illustrating a log output procedure. The flowchart of FIG. 24 is a flowchart showing the process of FIG. In the third embodiment, the results of step S1306 and step S1313 in the process of FIG. 13 are output as a log (steps S2401 and S2402). In step S1306, the determination result is output as a log regardless of Yes / No.

  For example, FIG. 25 is a data table showing a log format. In steps S2401 and S2402 described with reference to FIG. 24, a log based on a format such as the data table 2500 is output. FIG. 26 is an explanatory diagram showing an example of the data size of each function. By executing the algorithm of the first embodiment, the data size of the functions constituting the call graph 103 is calculated.

  FIG. 27 is a data table showing a log output example. When a log is output for the call graph 103 as shown in FIG. 26, first, the result of thought 1 (first process) of the data table 2700 is provided. The user can correct the arrangement information 105 with reference to the provided data table 2700.

  As in the data table 2700, in the thought 1, the capacity of the bank 3 has exceeded, and it can be determined that correction is necessary. Therefore, in thought 2, bank 3 is divided and the function is moved to bank 0. This time, bank 0 exceeds the capacity. Therefore, in the thought 3, the bank 1 is newly recalculated as a constantly ON bank. As a result of the thought 3, since the bank 3 exceeds the capacity, it is possible to divide the bank 3 again by the thought 4 and move the function to the bank 0 to create the arrangement information 105 in which the capacity shortage is resolved. The result is thought 4, which is output as an answer.

  Further, from the viewpoint of reducing the number of always-on banks as much as possible, a modification different from that of the data table 2700 can be performed. Referring to the log of the data table 2700, the capacity of the banks 1 and 2 still has room. The problem is that when the surplus of the bank 3 is brought to the bank 0, the bank 0 falls into a capacity shortage. If the function of bank 0 can be distributed to banks 1 and 2, only one ON bank is required at all times.

  Therefore, a plurality of instruction codes for calling the function C2 having the same contents but different names are prepared. Here, FIG. 28 is a data table showing a log output example after correction. The aliases C2_1 and C2_2 are set in accordance with the difference between the lower-level instructions called for the function C2. In this case, as in the data table 2700, the function C2_1 and the function C2_2 that are the same instruction are arranged in different banks. In this case, the number of always-on banks can be limited to one, and the capacity problem of the power control bank can be solved.

  As described above, in the third embodiment, auxiliary information for manually correcting the arrangement information 105 by a user is output as a log. FIG. 29 is a flowchart showing a source correction procedure using a log. In the flowchart of FIG. 29, first, the instruction placement apparatus 100 outputs an execution log accompanying execution of the instruction placement process (step S2901). Next, the user analyzes the log output in step S2901, and corrects the arrangement information 105 of the source 101 (see FIG. 1) input to the instruction arrangement apparatus 100 (step S2902).

  When the modification of the source 101 in step S2902 is completed, the instruction placement apparatus 100 executes an instruction placement process using the modified source and outputs an execution log (step S2903). The user refers to the execution log output in step S2903 and determines whether or not the execution result is OK (step S2904). If it is determined in step S2904 that there is a problem with the execution result (step S2904: No), the process returns to step S2902 again to shift to the source (correction source) correction process. On the other hand, if it is determined in step S2904 that there is no problem in the execution result and the result is OK (step S2904: Yes), the series of processing ends as it is. Thus, in the third embodiment, the information created by the placement information 105 creation process in the first embodiment can be output to assist the user in correcting the placement information 105.

  As described above in Examples 1 to 3, according to the instruction placement program, the instruction placement apparatus, and the instruction placement method according to the present embodiment, the call relation between the instructions is specified by the call graph 103 and used. It is classified into a high-frequency instruction group and other instruction groups. And the arrangement information 105 set so that the instruction group with high use frequency is arranged in the memory bank 205 to which power is always supplied among the memory banks 205 mounted in the target device is created. As a result, it is possible to avoid a situation where the memory bank 205 as a power supply destination is frequently switched and to achieve efficient power control.

  Therefore, regardless of the hardware configuration of the memory bank 205 of the target device that uses the arrangement information 105, an instruction code is appropriately arranged in the memory bank 205 to enable efficient power supply. Furthermore, power saving of the memory bank 205 can be realized by arranging the instruction code according to the placement information created by the above-described processing.

  On the other hand, even when the first to third embodiments are used, a situation where power saving cannot be expected occurs. For example, when there are more than a predetermined number of instructions called from a plurality of functions (for example, a number that has a capacity that cannot be stored in one memory bank), the plurality of memory banks 205 must be used as an ON bank at all times. Don't be. As a result, the number of memories that must always be supplied with power increases, and the power saving effect due to instruction placement processing is diminished.

  Thus, the following Examples 4 to 9 will be described as examples for obtaining a power saving effect even when the number of instructions called from a plurality of functions is a predetermined number or more. Specifically, in the case of the fourth to ninth embodiments, instructions that are called from two or more functions are further divided into cases according to the contents of the call, and are always placed in the ON bank and placed in the power control bank. To be ordered. Thus, in the fourth embodiment, a process for allocating instructions called from two or more functions to the memory bank 205 will be described. In the fifth to ninth embodiments, application examples using the allocation process of the fourth embodiment will be described.

(Functional Configuration of Instruction Arrangement Apparatus in Examples 4 to 9)
FIG. 30 is a block diagram illustrating a functional configuration of the instruction arrangement device according to the fourth to ninth embodiments. In the case of the fourth to ninth embodiments, the instruction arrangement device 100 further includes a parent function determination unit 3001, a constantly ON memory allocation unit 3002, and a code amount calculation unit as functional units in the classification unit 602 illustrated in FIG. 3003, a power control memory allocation unit 3004, and an allocation adjustment / address calculation unit 3005. Then, the instruction placement apparatus 100 creates the placement information 105 using the source 101, the call graph 103, and the memory partition information 104 as in the first to third embodiments.

  Note that when the arrangement information 105 is created in the fourth to ninth embodiments, the function call relation information 103-1 representing the call relation of each function in the source 101 and each function included in the call graph 103 are called. The function code amount information 103-2 representing the capacity of the code for use and the memory structure information 104-1 representing the structure of the memory bank 205 included in the memory partition information 104 are used.

  FIG. 31 is an explanatory diagram of an example of a call graph. In the following description of the fourth to ninth embodiments, a case where the call graph 103 created from the source 101 has a call relationship as shown in FIG. 31 will be described as an example. Further, in order to distinguish from the first to third embodiments, the variable representing the number of layers is set to “L”.

  The parent function determination unit 3001 has a function of determining a main parent function among the functions f constituting the source 101. The main parent function of the function f refers to a function having the highest number of calls to the function f among the parent functions of the function f. The parent function determination unit 3001 determines the main parent function with reference to the case of the call graph 103 of the source 101 (Examples 4 to 9, having the calling relationship of FIG. 31).

  The always-on memory allocation unit 3002 has a function of determining a function to be arranged in the memory bank 205 used as the always-on bank of the memory bank 205 group among the functions constituting the source 101. Specifically, in the hierarchical relationship represented by the call graph 103, the number of hierarchies in which the function to be arranged in the memory bank 205 that is always ON bank is arranged, and specifically, where to allocate in the always ON memory is determined. To do.

  The code amount calculation unit 3003 has a function of calculating the code amount for each subtree when the source 101 is decomposed into subtrees. Note that it is possible to arbitrarily set what subtree the call graph 103 is decomposed into. However, since the main parent function information determined by the parent function determination unit 3001 is used, a tree structure is obtained. Can be determined uniquely.

  The power control memory allocation unit 3004 has a function of determining a function to be arranged in the memory bank 205 used as a power control bank other than the always-on bank among the functions constituting the source 101. Specifically, a function other than the function determined to be placed in the always-on bank by the always-on memory allocation unit 3002 is determined in which of the remaining power control banks.

  The allocation adjustment / address calculation unit 3005 is a constantly ON bank based on the arrangement relationship of parent functions (which function and which function are arranged in the same memory bank 205) among the functions determined to be arranged in the power control bank. It has an adjustment process (assignment adjustment) that does not require the arrangement part and a function that calculates the address of the beginning of the function for calling the arranged function (address calculation). Allocation adjustment results in a more efficient code, such as reducing the amount of code allocated to the always-on bank and reducing the insertion of unnecessary power control codes and branch or jump instructions. Further, by calculating the address, it is possible to specify the address when the allocated function is actually arranged.

  Hereinafter, embodiments 4 to 9 of instruction placement processing using the instruction placement device 100 having the functional configuration as shown in FIG. 30 will be described in order.

Example 4
In the fourth embodiment, as in the first to third embodiments, the function from the main function to the function within several layers and the function reaching the address reaching within the overhead for canceling the power control are always arranged in the ON bank. On the other hand, in the case of the fourth embodiment, a function that is called from a plurality (two or more) of functions is always placed in the ON bank according to the relationship between the function that becomes the call source and the function that becomes the call destination. And a function to be divided into a function to be arranged in the same power control bank.

  FIG. 32 is an explanatory diagram illustrating instruction arrangement processing according to the fourth embodiment. In the case of the fourth embodiment, when the source 101 is input, the parent function determination unit 3001 creates a table C and a table S as preparation processing for function determination. Further, when executing the table instruction arrangement processing, in addition to the table C and the table S, a table M representing the memory structure information 104-1 is also created from the memory division information 104.

  FIG. 33 is a data table showing a data example of the table C, and FIG. 34 is a data table showing a data example of the table S. The table C is configured to display a list of the calling relationships of the functions constituting the source 101. Of the functions constituting the source 101, a function that becomes a call source (calls some function) is called a “parent function”, and a function that becomes a call destination (called from some function) is called a “child function”.

  Therefore, in the case of the data table 3300 illustrated in FIG. 33, the main function (MAIN) calls four child functions (A1, A2, A3, A4) according to the execution status of the object 102 that compiled the source 101. The calling relationship is as follows. Further, the table S is configured to display a list of code amounts for each function. The code amount represented by the table S includes a “size” representing the total code amount for each function, a “first half size” and a “second half” when the function is divided, as in the data table 3400 illustrated in FIG. There are three types: “size”.

  FIG. 35 is a data table showing a data example of the table M. In addition to the tables C and S, the instruction arrangement device 100 is provided with a table M representing the configuration of each memory bank 205. The table M has a configuration in which the configuration of the memory bank 205 is displayed as a list, and is created from the memory structure information 104-1. Specifically, as shown in the data table 3500 of FIG. 35, the start address and the size are associated with each of the memory banks 205 of the banks 0 to 4.

  First, the parent function determination unit 3001 refers to the table S, identifies the parent function having the largest number of calls for each function, and creates the table 1 that lists the identification results. On the other hand, the always-on memory allocation unit 3002 refers to the table S and the table M to determine the number of layers of functions to be arranged in the always-on bank and the memory allocation. As a result of processing by the always-on memory allocation unit 3002, a table 3 representing the number of layers L and the result of allocation to the always-on bank is created. The table 2 is created during the internal processing of the always-on memory allocation unit 3002, and will be described in detail when the always-on memory allocation unit 3002 is described.

  Next, the code amount calculation unit 3003 uses the tables 1, S, C and the number of hierarchies L to calculate the code amount for each subtree and creates the table 4. The subtree is a descendant function group obtained by extracting all child functions having a calling relationship with this function when a certain function is a parent function. The descendant function means a function group that covers a child function of a certain parent function (first generation of child functions) and a grandchild function that is a child function of the first generation of child functions (second generation of child functions). The table 4 extracts descendant functions having a calling relationship for each function, and displays a list of the calculation results of the total code amount of the descendant functions in association with each other (details will be described later).

  Then, the power control memory allocation unit 3004 performs memory allocation for each subtree using the tables 3, 4, M, and S. Therefore, the power control memory allocation unit 3004 performs an allocation process as to which bank in the power control bank the descendant function of each function is allocated. Then, the allocation result by the power control memory allocation unit 3004 is output as the table 5.

  Finally, the allocation adjustment / address calculation unit 3005 creates a table 6 as a memory map based on the tables 3 and 5 using the tables M and S. The table 6 has a configuration in which a start address and a memory name to be arranged are displayed in a list in association with all functions constituting the source 101. The table 6 created by the allocation adjustment / address calculation unit 3005 is stored as the arrangement information 105. Hereinafter, processing of each functional unit described above will be described in detail.

<Processing of parent function determination unit>
FIG. 36 is an explanatory diagram showing detailed processing of the parent function determination unit. When the source 101 is input, the parent function determination unit 3001 counts the number of calls for each function for each function constituting the source 101 (step S3601). The table 1-1 is created by the count process in step S3601.

  The table 1-1 has a configuration in which a call destination function and the number of calls are associated and displayed for each function constituting the source 101. That is, in the table 1-1 illustrated in FIG. 36, it can be seen that the MAIN function calls the function A1 10 times. Then, the parent function determination unit 3001 creates a table 1 by referring to the table 1-1 and selecting a caller function having the maximum number of times for each callee function (step S3602).

  Table 1 shows the function of the caller that is calling most for each function. Therefore, in the case of FIG. 36, in Table 1, the caller that calls the function A1 most is the MAIN function, and the caller that calls the function B1 most is the function A1.

  FIG. 37 is a data table showing a creation example of the table 1. As in the data table 3701 in FIG. 37, the table 1-1 created by the processing in step S3601 associates a call destination child function and the number of calls for each function in the source 101. The number of times displayed in the table 1-1 is not a value specified from the call history during actual operation, but a static value specified from the call relationship of the call graph 103 as shown in FIG. It is. Therefore, the value is uniquely determined by the call graph 103 represented by the source 101.

  Also, as shown in FIG. 37, when creating table 1 with reference to table 1-1, first, table 1-2 is created. The table 1-2 is configured by sorting the table 1-1 by the child function field like the data table 3702. By creating the table 1-2, the parent function (caller) having the highest number of times is made clear for each child function. Therefore, if the parent function having the maximum number of times is selected for each child function of the table 1-2, the table 1 having the configuration like the data table 3703 is automatically created.

<Processing of always-on memory allocation unit>
FIG. 38 is an explanatory diagram showing detailed processing of the always-on memory allocation unit. The always-on memory allocation unit 3002 uses the tables S and M and the table 1 created by the parent function determination unit 3001 to assign the number L of functions to be placed in the always-on bank and the function to be placed in the always-on bank. A table 3 representing the result is created. It should be noted that the function assigned to the always-on bank by the always-on memory allocation unit 3002 may be changed by an allocation adjustment / address calculation unit 3005, which will be described later.

  FIG. 39 is a flowchart showing the procedure of the always-on memory allocation process. The flowchart of FIG. 39 represents a procedure for creating the table 3 that lists the number of functions L arranged in the always-on bank and the functions arranged in the always-on bank as the always-on memory allocation process. 39. By executing each process of FIG. 39, among the functions constituting the source 101, function candidates that are always placed in the ON bank (as described above, the assignment adjustment / address calculation unit 3005 may change them). ) Can be extracted.

  In FIG. 39, first, the values of variables N, L, and N_ON used for allocation processing are initialized (step S3901). The variable N represents the total number of memory banks 205, the variable L represents the number of layers of functions placed in the always-on bank, and the variable N_ON represents the number of always-on banks. Since the variable N is uniquely determined according to the configuration in the power control system, the variable N is a fixed value. Other variables L and N_ON are set to a minimum value of 1 at the time of initialization.

  Next, the function branch number F corresponding to the number of layers is set (step S3902). Specifically, F is set to the number of branches from the current layer number L to the layer number L + 1. Next, it is determined whether the number of branches F is NN_ON, that is, whether the number is less than the number of power control banks (step S3903). Here, when it is determined that F <N−N_ON, that is, the number of branches F is smaller than the number of power control banks (step S3903: Yes), the number of layers L is incremented by +1 (step S3904), and step S3902 is performed again. Perform the process.

  If it is determined in step S3903 that the number of branches F is equal to or greater than the number of power control banks (step S3903: No), the table M_rest / table 3 is then initialized (step S3905). The table M_rest is configured to display a list of remaining capacities after the function is arranged in each memory bank 205 represented by the table M.

  FIG. 40 is a data table showing a data example of the table M_rest / table 3 at the time of initialization. At the time of initialization in step S3905, no function is assigned to any memory bank 205. Therefore, the table M_rest has the same value as the table M like the data table 4010. Similarly, the table 3 is in an empty state to which no function is assigned unlike the data table 4020.

  When each table is initialized, a function func that satisfies a predetermined condition is added to the table 2 (step S3906). Table 2 is a table for extracting function candidates to be always placed in the ON bank.

  FIG. 41 is a data table showing an example of creating the table 2. In step S3906, a function func satisfying the following conditions is added to the table 2 from the function field table S [func] constituting the table S. The added function is set as a function field table 2 [func] constituting the table 2 as in the data table 4100.

Functions up to L number of layers:
Table 2 [func]. Size = table S [func]. Size (“table 2 [func] .size” indicates the value of the size field of the entry whose function field, which is the leftmost field of table 2, is func. When there are two fields, designation of field names after “.” May be omitted.)
Function of number of layers L + 1:
Table 2 [func]. Size = table S [func]. Division first half size Number of layers L + 2 or less, among functions that are called from a plurality of functions:
Table 2 [func]. Size = table S [func]. First half size

  Returning to the description of FIG. 39, the allocation processing to the table 3 is performed in the order of the size of the function func stored in the table 2 (step S3907). In step S3907, allocation processing is performed in order of functions having the largest size. Hereinafter, the procedure of the allocation process will be described in detail.

  FIG. 42 is a flowchart showing the procedure of the allocation process to the table 3. The flowchart of FIG. 42 represents a procedure for extracting a function assigned to the table 3 by the First Hit algorithm for the functions extracted from the table M to the table 2. By executing each process of FIG. 42, it is possible to determine a function that is always placed in the ON bank.

  42, first, the first memory m satisfying the following formula (1) is extracted from the elements m belonging to the memory name field of the table M (step S4201).

  M_rest [m] ≧ table 2 [func] (1)

  Next, a value obtained by subtracting table 2 [func] from the extracted memory M_rest [m] is newly set to M_rest [m] (step S4202). Finally, table 3 [m]. Func is added to the function (step S4203), and the series of allocation processes is terminated.

  43 is a data table showing an example of data in the table M_rest, and FIG. 44 is a data table showing an example of assignment to the table 3. When the value of the table M_rest is configured as in the data table 4100, in step S4201, the bank 0 is extracted as the first element m that satisfies the size of M_rest [m] ≧ table 2 [func]. Accordingly, in step S4202, 4096-3000 = 1096 [bytes] is set as the size of the bank 0 as in the data table 4300. Further, the MAIN function is added to the entry of the bank 0 in the table 3 as in the data table 4400 by the processing in step S4203.

  Returning to the explanation of FIG. 39, when the process of step S3907 is completed, it is next determined whether or not the number of non-empty entries in the table 3 is larger than N_ON (step S3908). If it is determined that the number of non-empty entries in the table 3 is greater than N_ON (step S3908: Yes), the number of always ON banks is insufficient, so the value of N_ON is incremented by +1 and the value of L is set to 1. After setting (step S3909), the processing from step S3902 is repeated again.

  On the other hand, if it is determined that the number of non-empty entries in the table 3 is not more than N_ON (step S3908: No), the function assigned to the table 3 can always be placed in the ON bank, so it is currently set. The number of hierarchies L and the table 3 are output (step S3910), and the series of allocation processes is terminated.

  FIG. 45 is a data table showing the execution result of the always-on memory allocation process. As a result of executing the flowchart of FIG. 39, the data table 4510 is output as the table M_rest, and the data table 4520 is output as the table 3.

<Processing of code amount calculation unit>
FIG. 46 is an explanatory diagram showing detailed processing of the code amount calculation unit. The code amount calculation unit 3003 uses the tables S and C, the table 1 created by the parent function determination unit 3001 and the number of hierarchies L created by the always-on memory allocation unit 3002 to arrange in the power control bank. Calculate the total amount of descendant function code. Table 4 is created by calculation processing by the code amount calculation unit 3003.

  FIG. 47 is a flowchart showing the procedure for calculating the code amount. The flowchart in FIG. 47 represents a procedure for creating the table 4 representing the code amount of the descendant function other than the function determined as the parent function. 47 is executed, it is possible to specify the code amount of the function group arranged in the same power control bank.

  The code amount calculation unit 3003 first extracts the function func of the (L + 1) layer on the table 1 (step S4701). Next, the value of each extracted function func is set as follows (step S4702).

F_D = {descendant on func table 1}
s = table S [func]. Sum of size field of table S of each function included in division latter half size + F_D

  Then, each value in the table 4 is set as follows using the set value in step S4702 (step S4703). The table 4 after setting is output (step S4704), and a series of calculation processing is terminated.

Table 4 [func]. Descendant function = F_D
Table 4 [func]. Total code amount = s

  For example, when L + 1 = 2 (hierarchy), the function func extracted in step S4701 is A1, A2, A3, A4. In the function A1, when the process of step S4702 is performed, F_D = {B1, B2, B3, B10, C1} is set. These values are descendant functions of A1 in Table 1, B1, B2, B3, and B10 are child functions of A1, and C1 is a child function of B10.

  Similarly, s = 112860 [bytes]. Specifically, s = second half size of function A1 + size of function B1 + size of function B2 + size of function B3 + size of function B10 + size of function C1 = 2460 + 2560 + 2560 + 2560 + 2560 + 160 = 1860 [bytes].

  FIG. 48 is a data table showing a creation example of the table 4. In step S4702, first, each value is set for the function A1, and a data table 4810 is created. Similarly, values are set for other functions, and a data table 4820 is created and output as the table 4.

<Processing of power control memory allocation unit>
FIG. 49 is an explanatory diagram showing detailed processing of the power control memory allocation unit. The power control memory allocation unit 3004 uses the tables S and M, the table 3 created by the always-on memory allocation unit 3002, and the table 4 created by the code amount calculation unit 3003 to control power for each subtree. A table 5 to which banks are assigned is created. As described above, the power control memory allocation unit 3004 processes a function group associated with the same parent function as a descendant function as a subtree.

  FIG. 50 is a flowchart showing a procedure for power control memory allocation. The flowchart of FIG. 50 shows the procedure of the allocation process to the memory bank 205 for the functions of the (L + 1) th layer and below. By executing each process of FIG. 50, among the functions constituting the source 101, the remaining functions whose arrangement destinations are not determined can be assigned to an appropriate power control bank.

  In FIG. 50, first, the values of the table M_rest and the table 5 are initialized (step S5001). In the table M_rest, when the function set in the table 3 is not an empty set, that is, 0 [byte] for a bank in which some function is set, and the size set in the table M for other banks. Is used as is. In addition, the function (parent function) in table 5 is used as the function in table 5 (parent function), and the descendant function in table 4 is used as the descendant function in table 5.

  FIG. 51 is a data table showing a data example of the table M_rest / table 5 at the time of initialization. When initialization is performed as in step S5001, the table M_rest has a size set to 0 [0] because functions are already set in the banks 0 and 1 that are always used as ON banks as in the data table 5110. byte]. Since no function is set in the remaining banks 2 to 4, the values in the table M are set as they are. In the table 5, the set value of the table 4 is set as it is like the data table 5120.

  Returning to the description of FIG. 50, after initializing each table, the function of the table 4 is assigned to the power control bank by the First Hit Dedecoring algorithm. That is, the functions in Table 4 are rearranged in the descending order of the total code amount (Step S5002), and the allocation process of Table 5 is executed in the order in which the functions in Table 4 are rearranged (Step S5003). When the process of step S5003 ends, the power control memory allocation unit 3004 outputs the table 5 (step S5004). Hereinafter, the allocation process in step S5003 will be described in detail.

  FIG. 52 is a data table showing the sorted table 4. The table 4 sorted by the processing in step S5002 is arranged in the descending order of the total code amount as in the data table 5200.

  FIG. 53 is a flowchart showing the procedure of the allocation process to the table 5. The flowchart in FIG. 53 shows the procedure of the allocation process to the table 5 in step S5003. 53 is executed, a memory bank 205 (power control bank) to which a descendant function of each function set in the table 5 is assigned can be set.

  In FIG. 53, first, of the elements m appearing in the memory name field of the table M, M_rest [m] ≧ table 4 [func]. The first memory m that satisfies the total code amount is extracted (step S5301). Then, from the extracted M_rest [m], Table 4 [func]. The code amount obtained by subtracting the total code amount is set to the size of M_rest [m] (step S5302). Thereafter, the extracted m is set as the allocation memory of the table 5 [func] (step S5303).

  FIG. 54 is a data table showing a data example of the table M_rest according to the total code amount, and FIG. 55 is a data table showing a data example assigned to the table 5. When the value of the table M_rest is configured as in the data table 5110, the bank 2 is extracted as the element m in step S5301. Accordingly, in step S5302, 18384-12860 = 3524 [bytes] is set as the size of the bank 2 as in the data table 5400. Further, bank 2 is set in the table 5 as the allocation memory of the function A1, as in the data table 5500, by the processing in step S5303.

  FIG. 56 is a data table showing the execution result of the power control memory allocation process. When the allocation process for all the functions set in the table 4 in step S5004 is completed, the data table 5610 is created as the table M_rest and the data table 5620 is created as the table 5, respectively.

<Processing of allocation adjustment / address calculation unit>
FIG. 57 is an explanatory diagram showing detailed processing of the allocation adjustment / address calculation unit. In the allocation adjustment / address calculation unit 3005, two processes of always-on bank arrangement correction (step S5701) and address calculation (step S5702) are performed. First, a table 6-1 is created using the table C, the tables 3 and 5, and the number of hierarchies L. Thereafter, the table 6 is created using the tables S and M, the tables 5 and 6-1, and the number L of layers.

  FIG. 58 is a flowchart showing the procedure of allocation adjustment processing. The flowchart in FIG. 58 represents the procedure for always-on bank arrangement correction in step S5701. By executing each processing of FIG. 58, it is possible to create a table 6-1 in which it is determined whether the function set in the table 3 is suitable as a function that is always placed in the ON bank.

  58, first, a function func on the table 3 is extracted (step S5801), and it is determined whether or not the extracted function func is in the L + 2 hierarchy or lower in the table 1 (step S5802). If it is determined in step S5802 that the extracted function func is below the L + 2 hierarchy in table 1 (step S5802: Yes), whether or not the extracted function func has a plurality of parent functions on table C is determined. Is determined (step S5803).

  If it is determined in step S5803 that the extracted function func has a plurality of parent functions on the table C (step S5803: Yes), the extracted function func is further divided into the same bank on the table 5 in the same bank. It is determined whether or not there is (step S5804). In step S5804, when it is determined that the extracted function func is divided into the same bank on the table 5 (step S5804: Yes), func is deleted from the table 3 (step S5805).

  When the process of step S5805 is completed, it is next determined whether or not all the extracted function func have been processed (step S5806). If an unprocessed function func remains (step S5806: No), the process proceeds to step S5805. Returning to the processing of S5802, the same processing is performed for the unprocessed function func.

  When it is determined that the extracted function func is not lower than the L + 2 hierarchy in the table 1 (step S5802: No), when it is determined that there are not a plurality of parent functions on the table C (step S5803: No), If it is determined on the table 5 that the parent function is not divided into the same bank (step S5804: NO), the process proceeds to step S5806, and the process is repeated until there is no unprocessed function func. Thereafter, when it is determined that an unprocessed function func does not remain (step S5806: Yes), a series of allocation adjustment processing ends.

  FIG. 59 is a data table showing a data example of the table 3 after allocation adjustment. The functions MAIN, A1,..., A4 on the table 3 are stored in the table 3 as they are because they are not lower than L + 2 = 3 layers. In the case of the functions B2 and B3, there are three or lower layers, and there are a plurality of parent functions in the table C. However, since the parent functions are not in the same bank on the table 5, they are stored in the table 3 as they are. On the other hand, the function B4 is not more than three layers, and since there are a plurality of parent functions in the table C and the parent functions are in the same bank, the function B4 is deleted from the bank 0 as in the data table 5900.

  FIG. 60 is a data table showing an output example of the table 6-1. When the processing of FIG. 58 is completed for all the functions on the table 3, a data table 6000 in which B7 and C2 are further deleted from the table 3 is created. A table obtained by deleting a function under a predetermined condition from the table 3 like the data table 6000 is output as the table 6-1.

  FIG. 61 is a flowchart showing the procedure of the address calculation process. The flowchart in FIG. 61 shows the procedure of address calculation processing, which is the second step in the allocation adjustment / address calculation unit 3005. By performing the processing of FIG. 61, it is possible to specify an address when each function is arranged in the memory.

  In FIG. 61, first, the array addr [m] = (table M [m] .start address) is initialized (step S6101). Further, memory address setting processing is performed for each function on the table 6-1 in func1, and for each function on the table 5 in func2 (steps S6102 and S6103). When the above processing ends, the table 6 reflecting the memory address setting result is output (step S6104), and the series of address calculation processing ends.

  FIG. 62 is a data table showing a data example of the array addr at the time of initialization. The array addr has a configuration in which the start address settings for each memory bank 205 are listed. Therefore, here, as in the data table 6200, start addresses for the five memory banks 205 of the banks 0 to 4 are set.

  FIG. 63 is a flowchart showing the procedure of the memory address setting process for the always-on memory. The flowchart in FIG. 63 shows the procedure of memory address setting processing in func1 in step S6102. By executing the processing of FIG. 63, it is possible to set the memory address for each function arranged in the always-on bank.

  In FIG. 63, first, m and s are set as follows (step S6301).

m = Table 6-1 [func1]. Memory name s = table S [func1]. Size (when func1 is L level or higher)
Or s = table S [func1]. First half size (when func1 is not higher than L level)

  Next, the following entry is added to the table 6 (step S6302). Finally, s is added to the array addr [m] (step S6303), and the series of address setting processes is terminated.

Table 6 [func1]. Address = addr [m]
Table 6 [func1]. Memory name = m

  FIG. 64 is a data table showing a data example of the table 6 / array addr at the start of address calculation of the always-on memory. 63 is executed, m = bank 0, s = table S [MAIN]. A table 6 to which size = 3000 is added is set. Therefore, a new start address is added to bank 0 as in the data table 6420 in the array addr.

  FIG. 65 is a data table showing a data example of the table 6 / array addr when the address calculation of the always-on memory is completed. When all the functions set in the table 6-1 are processed by the processing of FIG. 63, the table 6 in which addresses such as the data table 6510 are set is created. Similarly, a new start address is added to the banks 0 and 1 in the array addr as in the data table 6520.

  66 and 67 are flowcharts showing the procedure of the memory address setting process of the power control memory. The flowcharts in FIGS. 66 and 67 show the procedure of the memory address setting process in func2 in step S6103. By executing the processing of FIGS. 66 and 67, the memory address for each function arranged in the power control bank can be set.

  In FIG. 66, first, memory address setting processing is executed with func3 as func2 (step S6601). Similarly, func3 is stored in table 5 [func2]. As each function of the descendant function, a memory address setting process is executed (step S6602), and the series of processes ends.

  FIG. 67 shows the memory address setting process in steps S6601 and S6602 described above. In FIG. 67, first, m, s, and f are set as follows (step S6701).

m = table 5 [func2]. Memory name s = table S [func3]. Second half size of division (when func3 is included in table 6-1)
Or s = table S [func3]. Size (when func3 is not included in table 6-1)
Character string with “_L” concatenated after f = func3

  Next, the following entry is added to the table 6 (step S6702). Finally, s is added to the array addr [m] (step S6703), and the series of address setting processes is terminated.

Table 6 [f]. Address = addr [m]
Table 6 [f]. Memory name = m

  FIG. 68 is a data table showing a data example of the table 6 / array addr at the start of address calculation of the power control memory. 66 and 67, when processing is performed with func2 = A1, m = bank 2, s = table S [A1]. The latter half size = 2460. Therefore, the function A1_L is added to the table 6 as in the data table 6810. In addition, by the memory address setting process this time, the start address of the bank 2 is newly added to the array addr according to the function A1_L as in the data table 6820.

  FIG. 69 is a data table showing a data example of the table 6 / array addr after execution of address calculation of the power control memory. 66 and 67, when processing is performed with func2 = A1 and the memory address setting processing is performed for the descendant function of the table 5 [A1], the target func3 is the function B1. Therefore, m = bank 2, s = table S [A1]. Size = 2560 (since B1 is not included in Table 6). Therefore, a function B1_L is added to the table 6 as in the data table 6910. In addition, by the memory address setting process this time, the start address of the bank 2 is newly added to the array addr according to the function B1_L as in the data table 6920.

  FIG. 70 is a data table showing a data example of the table 6 and the array addr at the time of address calculation for the descendant function. 66 and 67, when all the memory address setting processes are performed for the descendant functions of the table 5 [A1], the functions A_1, B1_L, B2_L, B3_L, B10, and C1_L are stored in the table 6 as in the data table 7010. Added. Further, the array addr is added according to the entry to which the start address of the bank 2 is added as in the data table 7020.

  FIG. 71 is a data table showing a data example of the table 6 / array addr at the time of completion of address calculation for the descendant function. 66 and 67, when the memory address setting processing is performed for all the functions of the table 5, the table 6 such as the data table 7110 of FIG. 71 and the array addr such as the data table 7120 are created.

  The table 6 created by the allocation adjustment / address calculation unit 3005 is used as arrangement information 105 for arrangement processing of each function constituting the source 101.

  As described above, by realizing the processing of the fourth embodiment, even when a large number of functions have to be always placed in the ON bank when the first to third embodiments are used, The detailed situation of the call relationship such as presence / absence and whether or not descendant functions are arranged in the same memory bank 205 is determined. Only functions that are called more frequently than the other parent functions and that are determined to be more efficient when placed in the always-on bank are placed in the always-on bank. Therefore, it is possible to perform instruction arrangement processing having a power saving effect regardless of the calling relationship between the functions constituting the source 101.

(Example 5)
In the fifth embodiment, in consideration of an operation history using the source 101, a process for determining a parent function that is actually frequently called as a main parent function is added. Specifically, the parent function determination unit 3001 newly acquires information related to the function call history. For parent functions with a large call history, weighting is performed so that the main parent functions are preferentially determined.

  FIG. 72 is an explanatory diagram illustrating processing of the parent function determination unit according to the fifth embodiment. As shown in FIG. 72, in the case of the fifth embodiment, in addition to the source 101, a call history 7200 for each function constituting the source 101 is added as input information to the parent function determination unit 3001. The parent function determination unit 30001 creates the table 1 by counting the number of calls and weighting the source 101 as static information and the call history 7200 as dynamic information.

  FIG. 73 is an explanatory diagram showing parent function determination processing using a weighted sum. FIG. 74 is a data table showing an example of weighting. As shown in FIG. 73, the parent function determination unit 3001 refers to the input source 101, counts the number of calls for each function for each function, and creates a table 1-1 (step S7301). Similarly, the parent function determination unit 3001 creates a table 1-3 by counting the number of calls for each function for each function with reference to the input call history 7200 (step S7302). Thereafter, the parent function determination unit 3001 adds the count results of steps S7301 and S7302 and further creates a table 1-4 in consideration of the weighted sum (step S7303).

  As illustrated in FIG. 74, in the table 1-1 created in step S7301, the number of calls of each parent function is counted for each child function from the call graph 103, like the parent function determination unit 3001 of the fourth embodiment. The data table 7410 is configured. Further, the table 1-3 created in step S7302 has a configuration like a data table 7420 in which the actual number of calls recorded in the call history 7200 is counted.

  In step S7303, a weighted sum is set according to how the count results of the tables 1-1 and 1-3 are reflected. In FIG. 74, since the main parent function is determined by using the information of the call history 7200, the ratio of the count number of the static table 1-1 and the count number of the dynamic table 1-3 is 1: 9 is set.

  Therefore, the table 1-4 is set as a point where the addition result of the number of counts x1 of the table 1-1 and the number of counts x9 of the table 1-3 represents the priority of calling the parent function and the child function. The data table 7430 is configured. For example, the call-related point of MAIN-A1 is determined as 2 (number of times) × 1 (weight) +15 (number of times) × 9 (weight) = 137 (points).

  Finally, the parent function determination unit 3001 refers to the table 1-4 created in step S7303 and selects the caller function having the maximum number of times for each callee function as the main parent function (step S7304). ), Create table 1. Therefore, unlike the case of the fourth embodiment, the table 1 created in step S7304 has a configuration in which the call history 7200 is reflected.

  As described above, by realizing the processing of the fifth embodiment, it is possible to assume a calling situation that is closer to the actual operation of the processing using the source 101. That is, among the parent functions that can be called from a plurality of functions, the parent function that is likely to be actually called is always preferentially assigned to the ON bank. Therefore, it is possible to enhance the power saving effect due to the function distribution based on the created arrangement information 105.

(Example 6)
In the sixth embodiment, a process for preferentially setting a memory to be used as a power control bank in the prepared memory bank 205 group is added. Examples of the memory that is preferentially used as the power control bank include a memory that can change voltage at high speed and a memory that consumes less power. By using a memory having the above-described features as a power control bank, power consumption can be reduced as compared with a case where a power control bank is set at random.

  FIG. 75 is an explanatory diagram of the memory allocation process according to the sixth embodiment. In the sixth embodiment, a table M with allocation priority information (hereinafter referred to as “table M ′”) is used for allocation processing in the always-on memory allocation unit 3002 and the power control memory allocation unit 3004. To do. Accordingly, both the table 3 created by the always-on memory allocation unit 3002 and the table 5 created by the power control memory allocation unit 3004 have values referring to the table M ′.

  FIG. 76 is a data table showing a data example of memory information with allocation priority information. The table M ′ provided as the memory information with the allocation priority has a configuration in which the priority is associated with each memory bank 205 as in the data table 7600. The priority is set so that the value increases as the memory bank 205 that is to be always ON is set. The priority may be set manually by the user, or the upper program may be uniquely set from the specifications of the memory bank 205 provided as the power control system, and there is no particular limitation.

  In the case of the sixth embodiment, the always-on memory allocation unit 3002 and the power control memory allocation unit 3004 have a procedure for sorting the priority order of the table M ′ as the preceding process for executing the allocation process described in the fourth embodiment. Added.

  FIG. 77 is a flowchart showing the procedure for sorting when the always-on memory is allocated. In FIG. 77, first, the table M 'is sorted in order of priority (step S7701). Then, the number of hierarchies and memory allocation to be always arranged in the OM memory are determined according to the sorted table M '(step S7702), and the series of processes is terminated.

  FIG. 78 is a data table showing a data example of memory information with allocation priority information after sorting. In the sorting process in step S7701, the entries in the table M ′ are rearranged in descending order of priority, so that the configuration is changed to a data table 7800.

  FIG. 79 is a flowchart showing the sorting procedure when allocating power control memory. In FIG. 79, first, the table M 'is sorted in order of priority (step S7901). Then, memory allocation for each subtree is determined in accordance with the sorted table M ′ (step S7902), and a series of processing ends. As is apparent from the flowcharts of FIGS. 77 and 79, the sixth embodiment can be easily realized by adding a step for executing the sort process to the fourth embodiment.

  As described above, by realizing the processing of the sixth embodiment, when there is a memory suitable for use as a power control bank in the memory bank 205 group, this memory is preferentially used as the power control bank. Can be used as Therefore, efficient power supply utilizing the function of the memory becomes possible, and further power saving effect can be expected.

(Example 7)
The seventh embodiment enables more precise evaluation of the remaining capacity of the memory bank 205 simultaneously with the allocation process of each memory bank 205. By accurately evaluating the free capacity of the memory bank 205 after the function is placed, even if it is determined that the function can be placed or cannot be placed with a slight evaluation error, the memory capacity is utilized to the maximum. can do.

  FIG. 80 is an explanatory diagram of power control memory allocation processing according to the seventh embodiment. In the seventh embodiment, the power control memory allocation unit 3004 newly adds a step of evaluating the remaining memory amount after executing the allocation process. By this additional step, the remaining memory amount is evaluated more precisely than in the fourth embodiment.

  FIG. 81 is a flowchart showing a procedure for evaluating the remaining memory capacity. The flowchart in FIG. 81 represents a process executed after step S5303 in the flowchart showing the procedure of the allocation process to the table 5 described in FIG.

  In FIG. 81, first, it is determined whether or not there is a function called from another power control bank among the functions assigned to the table 5 (step S8101). If it is determined that there is a function called from another power control bank (step S8101: YES), the memory amount for the corresponding function is evaluated (step S8102), and the series of evaluation processes is terminated.

  Specifically, the evaluation processing in step S8102 first obtains the function func 'called from another power control bank and the memory amount of the memory m' to which func 'is allocated. The list of the memory m 'is a table 3' in FIG. Then, the current remaining memory amount M_rest [m ′] is changed from the table S [m ′] size to the table S [m ′]. A value obtained by adding a value obtained by subtracting the size of the latter half of the division is an accurate remaining memory amount. If it is determined in step S8101 that there is no function called from another power control bank (step S8101: No), the series of evaluation processes is terminated as it is.

  FIG. 82 is a data table showing a data example of the table 5 and the table M_rest when the remaining memory amount is evaluated. For example, when the memory amount evaluation process is performed for the function A1 to the function A4, the table 5 has a configuration like the data table 8210. For example, if C1 assigned to bank 2 is called by a function other than the functions A1 to A4, M_rest [bank 2] = M_rest [bank 2] + (table S [C1] .size−table S [C1]. The latter half size). Therefore, M_rest [Bank 2] = 3524 + (2560-2460) = 3624, and the data table 8220 is configured.

  As described above, in the seventh embodiment, the remaining memory amount is evaluated for each function of the L + 1 hierarchy. In the case of the fourth embodiment, for example, there is overhead, but on the other hand, the functions that are always placed in the ON bank to be called from the plurality of memory banks 205 are calculated with overlapping memory amounts. It was. On the other hand, in the seventh embodiment, since the memory amount is correctly calculated, it is possible to use the previously calculated overlapped capacity as a free area. Therefore, the total number of memory banks 205 to be used can be reduced, and a reduction in power consumption can be expected.

(Example 8)
The eighth embodiment is a first technique for duplicating a function called from a plurality of functions. In the eighth embodiment, when indicated by the call graph 103, the number of parent functions called from a plurality of functions is reduced by duplicating the code of the function corresponding to the terminal hierarchy.

  FIG. 83 is an explanatory diagram of function replication processing according to the eighth embodiment. In the eighth embodiment, a function duplicating unit 8300 for duplicating a function is added to the preceding stage of the parent function determining unit 3001. The function duplicating unit 8300 duplicates the function in the terminal hierarchy with reference to the calling relationship. Therefore, each function unit after the parent function determination unit 3001 performs processing using the copied source 8301 in which the function is copied by the function copying unit 8300 instead of the source 101.

  FIG. 84 is a flowchart illustrating the procedure of function replication processing according to the eighth embodiment. The flowchart in FIG. 84 shows the procedure of the function duplication process started with the input of the source 101 and the table C as a trigger. By executing each process in FIG. 84, a function that satisfies a predetermined condition can be automatically replicated.

  In FIG. 84, first, func determines whether or not the function corresponds to the end of table C (step S8401). When it is determined that func is a function corresponding to the end of the table C (step S8401: Yes), it is determined whether func is a function having a plurality of parents (step S8402).

  If it is determined in step S8402 that func is a function having a plurality of parents (step S8402: Yes), the func name is rewritten and copied (step S8403). In step S8403, specifically, first, func is copied by the number of parent functions, and the function name is funcPi_func (where funcPi (i = 1, 2,... (Number of parent functions)) is a parent function). change. After that, the part that calls func in funcPi is rewritten to call funcPi_func.

  When func is copied in step S8403, a series of processing ends. If it is determined in step S8401 that func is not a function corresponding to the end of table C (step S8401: No), or if it is determined in step S8402 that func is not a function having a plurality of parents ( In step S8402: No), since it is not necessary to prepare a replica for each, a series of processing ends.

  FIG. 85 is a data table showing a data example of the table C to be a function replication target, and FIG. 86 is a data table showing a data example of the table C after the function replication is completed. When the table C configured as the data table 8500 is input to the function duplication unit 8300, the functions C1 and C2 satisfy the conditions of steps S8401 and S8402. Therefore, as in the data table 8600, the function duplication unit 8300 duplicates B9_C1 by adding B9 and “_” of the caller to the head of the function C1. Similarly, B10_C1, B11_C2, and B12_C2 are duplicated.

Example 9
The ninth embodiment is a second technique for duplicating a function called from a plurality of functions. Unlike the eighth embodiment, in the ninth embodiment, the power control memory allocation unit 3004 executes a process of copying a function called from a plurality of functions. The power control memory allocation unit 3004 allocates a group of functions in the L + 1 layer or lower in order of increasing total code amount to the memory bank 205 using the First Fit Decreasing algorithm. Therefore, in the ninth embodiment, the code representing the function is duplicated at the timing when it is found that the parent function (calling source) is arranged in a plurality of banks as a result of the allocation process.

  87 and 88 are flowcharts showing the procedure of the function replication process in the ninth embodiment. The flowcharts of FIGS. 87 and 88 show the procedure of the allocation process to the table 5 as in FIG. 87 and 88, the descendant functions of each function set in Table 5 are assigned, and functions called from a plurality of functions are appropriately duplicated, and the duplicate function is assigned to the power control bank. You can also.

  87 and 88, first, M_rest [m] ≧ table S [func] .m among the elements m appearing in the memory name field of the table M. The first memory satisfying the size is extracted (step S8701). Then, the extracted M_rest [m] is set to a difference size from the total code amount in Table 4 (step S8702). Then, table 5 [func]. The extracted m is set as the allocation memory (step S8703).

  Further, it is determined whether there is a function called from another power control bank (step S8704). If it is determined in step S8704 that there is a function called from another power control bank (step S8704: Yes), the memory amount for the corresponding function is evaluated (step S8705). On the other hand, if it is determined that there is no function to be called from another power control bank (step S8704: No), the series of processing ends.

  Next, the processing in step S8705 will be described in detail with reference to FIG. In FIG. 88, first, it is determined whether or not the func to be processed is a function corresponding to the end of the table C (step S8801). If it is determined that func is a function corresponding to the end of the table C (step S8801: YES), then the func name is rewritten and copied (step S8802). Thereafter, the duplicated function is added to the descendant function, the allocated memory is set again (step S8803), and the series of processing ends.

  Note that details of the duplication process in step S8803 are the same as those in the eighth embodiment, and a description thereof will be omitted here. If it is determined in step S8801 that func is not a function corresponding to the end of the table C (step S8801: No), it is not necessary to duplicate the function, so the allocation memory is set (step S8804) and is left as it is. A series of processing ends.

  FIG. 89 is a data table showing a data example of the table C after the function replication, and FIG. 90 is a data table showing a data example of the table M_rest after the function replication. In the case of normal allocation processing, a table 5 such as a data table 8920 is created. Therefore, by adding the processes of FIGS. 87 and 88, the descendant function B9_C1 copied to the function A4 is added as in the data table 8910. By adding the copied descendant function B9_C1, the value of the table M_rest also uses the additional memory as in the bank 4 of the data table 9000, and the remaining memory amount is changed.

  As described above, by realizing the processing of the eighth and ninth embodiments, only a relatively simple measure such as adding the function duplicating unit 8300 to the fourth embodiment or adding the processing to the power control memory allocation unit 3004. Thus, a function called from a plurality of functions can be duplicated. In other words, for functions that are called by a plurality of functions in a lower hierarchy, since a copy is prepared in advance, it is possible to prevent occurrence of caller functions that are arranged in a plurality of memory banks 205, It is possible to prevent an increase in the number of always-on banks and maintain a power saving effect.

  The parent function setting process using the function call history described in the fifth embodiment, the memory van 205 setting process according to the priority described in the sixth embodiment, the memory amount calculation described in the seventh embodiment, Further, the instruction duplication processing described in the eighth and ninth embodiments may be applied to the first to third embodiments.

  As described in Examples 4 to 9 above, according to the instruction placement program, the instruction placement apparatus, and the instruction placement method according to the present embodiment, the call relationship between the instructions is specified by the call graph 103, The command group is classified into a frequently used instruction group and other instruction groups. Furthermore, in Examples 4 to 9, conditions that take into account the use frequency and the arrangement efficiency are provided. Therefore, the arrangement information 105 is created so that only the minimum necessary instruction group among the frequently used instruction groups is arranged in the memory bank 205 to which power is always supplied. As a result, regardless of the state of the call relationship represented by the call graph 103, it is possible to avoid a situation in which the memory bank 205 as the power supply destination is frequently switched and to achieve efficient power control.

  The instruction arrangement method described in the present embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. The command arrangement program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. The instruction placement program may be distributed via a network such as the Internet.

  In addition, the instruction placement apparatus 100 described in the present embodiment is a specific application IC (hereinafter simply referred to as “ASIC”) such as a standard cell or a structured ASIC (Application Specific Integrated Circuit), or a PLD (Programmable) such as an FPGA. It can also be realized by Logic Device). Specifically, for example, the function (acquisition unit 601 to calculation unit 607) of the above-described instruction arrangement device 100 is defined by HDL description, and the HDL description is logically synthesized and given to the ASIC or PLD. The device 100 can be manufactured.

  The following additional notes are disclosed with respect to the embodiment described above.

(Appendix 1) Computer
An acquisition means for acquiring a call graph representing a call relationship between instructions in firmware applied to a target device;
Among the instructions represented by the call graph acquired by the acquisition means, a classification means for classifying into a first instruction group located above a predetermined hierarchy from the top and a second instruction group other than the instruction,
The code for calling the instructions classified into the first instruction group by the classification means is set to be arranged in the first memory bank to which power is always supplied among the memory banks mounted on the target device. Creating means for creating the arranged information,
Output means for outputting the arrangement information created by the creating means;
An instruction placement program characterized by causing it to function as

(Additional remark 2) The said preparation means produces the arrangement | positioning information set so that the code for calling the instruction classified into the said 2nd instruction group might be arrange | positioned to memory banks other than the said 1st memory bank The instruction arrangement program according to appendix 1, characterized by:

(Supplementary note 3)
Function as a determination unit that determines whether or not a specific command is included in the command represented by the call graph acquired by the acquisition unit;
The creation means creates placement information set to place a code that calls the particular instruction in the first memory bank when the judgment means determines that the specific instruction is included. The instruction arrangement program according to appendix 1 or 2, characterized in that:

(Supplementary note 4)
Among the instructions represented by the call graph acquired by the acquisition means, function as an extraction means for extracting instructions that are call targets from a predetermined number of instructions,
The creation means arranges a code for calling the extracted instruction in the first memory bank when the extraction means extracts instructions to be called from the predetermined number of instructions or more. 4. The instruction placement program according to any one of appendices 1 to 3, wherein the placement information set in the above is created.

(Supplementary note 5)
The extraction unit extracts an instruction that is a library function from among the instructions represented by the call graph acquired by the acquisition unit,
The creation means creates placement information set to place a code that calls the extracted instruction in the first memory bank when an instruction that is a library function is extracted by the extraction means. The instruction arrangement program according to appendix 4, characterized in that:

(Supplementary note 6)
Calculating means for calculating a total amount of code data set to be arranged in the first memory bank according to the arrangement information;
The creating means changes the number of the first memory banks according to the value of the total amount of data calculated by the calculating means, and the first instruction group is stored in the changed first memory bank. 6. The instruction arrangement program according to any one of appendices 1 to 5, wherein arrangement information set so as to distribute and arrange codes to be called is created.

(Additional remark 7) The said creation means sets so that the instructions in which the instruction | command of an upper hierarchy corresponds among the codes which call the said 2nd instruction group may be arrange | positioned in the same memory bank other than the said 1st memory bank The instruction placement program according to any one of appendices 1 to 6, wherein the placement information is created.

(Supplementary note 8) The calculation means calculates the total amount of data for each code set to be arranged in the same memory bank according to the arrangement information,
The instruction output program according to any one of appendices 5 to 7, wherein the output means outputs a total amount of data calculated by the calculation means.

(Additional remark 9) The said classification | category means newly classify | categorizes the instruction which satisfy | fills a predetermined condition among the instructions classified into the said 1st instruction group into the said 2nd instruction group. The instruction arrangement program according to any one of 8.

(Supplementary Note 10) For the instructions classified into the first instruction group, the classification means newly adds instructions other than the instruction that has the highest number of calls from the same instruction specified from the call graph. The instruction placement program according to appendix 9, wherein the instruction placement program is classified into the second instruction group.

(Supplementary Note 11) For the instructions classified into the first instruction group, each of the classification means includes an instruction other than the instruction having the highest number of calls from the same instruction specified from the operation history of the firmware. The instruction placement program according to appendix 9, wherein the instruction placement program is newly classified into the second instruction group.

(Additional remark 12) The said creation means produces the arrangement information set so that the code | cord | chord for calling the said 1st instruction group preferentially may be arrange | positioned to the memory bank designated from the said memory bank. The instruction arrangement program according to any one of appendices 1 to 11.

(Additional remark 13) The said calculation means is a code which calls the same instruction | indication arrange | positioned in the said 1st memory bank from the total amount of the data of the code | cord | chord set when arrange | positioning to the said 1st memory bank obtained as a calculation result Subtract the capacity of
The output means includes
The instruction arrangement program according to appendix 6, wherein a subtraction result obtained by the calculating means is output.

(Supplementary note 14)
Among the lowermost instructions represented by the call graph, function as a duplicating means for creating a duplicate of an instruction called from a plurality of instructions as an instruction different from the instruction,
The instruction according to any one of appendices 1 to 8, wherein the classification means classifies the instructions created by the duplication means into the first instruction group and the second instruction group, respectively. Placement program.

(Supplementary note 15)
Among the lowermost instructions represented by the call graph, function as a duplicating means for creating a duplicate of an instruction called from a plurality of instructions as an instruction different from the instruction,
Any one of appendices 9 to 13, wherein the classifying unit newly classifies an instruction satisfying a predetermined condition from among the instructions classified into the first instruction group, into the second instruction group. The instruction arrangement program according to one.

(Supplementary note 16)
Of the second instruction group classified by the classification means, function as a duplication means for creating a duplicate of an instruction called from a plurality of instructions as an instruction different from the instruction,
The classifying means classifies the copied instruction into the first instruction group and the second instruction group, respectively, when the instruction is duplicated by the duplicating means. The instruction arrangement program according to any one of 8 to 8.

(Supplementary note 17)
Of the second instruction group classified by the classification means, function as a duplication means for creating a duplicate of an instruction called from a plurality of instructions as an instruction different from the instruction,
In the case where a copy of the instruction is created by the duplication unit, the classification unit newly adds an instruction satisfying a predetermined condition from among the instructions classified in the first instruction group for the instruction after the duplication. The instruction arrangement program according to any one of appendices 9 to 13, wherein the instruction arrangement program is classified into the second instruction group.

(Supplementary Note 18) Acquisition means for acquiring a call graph representing a call relationship between instructions in firmware applied to a target device;
Among the instructions represented by the call graph acquired by the acquisition means, a classification means for classifying into a first instruction group located above a predetermined hierarchy from the top and a second instruction group other than the instruction;
The code for calling the instructions classified into the first instruction group by the classification means is set to be arranged in the first memory bank to which power is always supplied among the memory banks mounted on the target device. Creating means for creating the arranged information,
Output means for outputting the arrangement information created by the creating means;
An instruction arrangement device comprising:

(Supplementary note 19)
An acquisition step of acquiring a call graph representing a call relationship between instructions in firmware applied to the target device;
Of the instructions represented by the call graph obtained by the obtaining step, a classification step for classifying into a first instruction group located above a predetermined hierarchy from the top and a second instruction group other than the instruction,
A code for calling the instructions classified into the first instruction group by the classification step is set to be arranged in the first memory bank to which power is always supplied among the memory banks mounted on the target device. Creation process to create the arranged information,
An output step of outputting the arrangement information created by the creation step;
Instruction placement method characterized by executing

DESCRIPTION OF SYMBOLS 100 Instruction arrangement apparatus 101 Source 102 Object 103 Call graph 104 Memory division information 105 Arrangement information 110 Compiler 120 Call graph creation part 200 Power control system 201 Processor 202 Peripheral circuit 203 Power supply 204 Control apparatus 205 Memory bank 206 Bus 601 Acquisition part 602 Classification part 603 creation unit 604 output unit 605 determination unit 606 extraction unit 607 calculation unit 3001 parent function determination unit 3002 always-on memory allocation unit 3003 code amount calculation unit 3004 power control memory allocation unit 3005 allocation adjustment / address calculation unit

Claims (6)

Computer
An acquisition means for acquiring a call graph representing a call relationship between instructions in firmware applied to a target device;
Among the instructions represented by the call graph acquired by the acquisition means, a classification means for classifying into a first instruction group located above a predetermined hierarchy from the top and a second instruction group other than the instruction,
The code for calling the instructions classified into the first instruction group by the classification means is set to be arranged in the first memory bank to which power is always supplied among the memory banks mounted on the target device. Creating means for creating the arranged information,
Output means for outputting the arrangement information created by the creating means;
An instruction placement program characterized by causing it to function as   The creation means creates placement information set so that a code for calling an instruction classified into the second instruction group is placed in a memory bank other than the first memory bank. The instruction arrangement program according to claim 1. Said computer further
Function as a determination unit that determines whether or not a specific command is included in the command represented by the call graph acquired by the acquisition unit;
The creation means creates placement information set to place a code that calls the particular instruction in the first memory bank when the judgment means determines that the specific instruction is included. The instruction arrangement program according to claim 1 or 2, characterized in that   4. The classification means according to claim 1, wherein the instruction that satisfies a predetermined condition among the instructions classified into the first instruction group is newly classified into the second instruction group. The instruction arrangement program according to any one of the above. An acquisition means for acquiring a call graph representing a call relationship between instructions in firmware applied to a target device;
Among the instructions represented by the call graph acquired by the acquisition means, a classification means for classifying into a first instruction group located above a predetermined hierarchy from the top and a second instruction group other than the instruction;
The code for calling the instructions classified into the first instruction group by the classification means is set to be arranged in the first memory bank to which power is always supplied among the memory banks mounted on the target device. Creating means for creating the arranged information,
Output means for outputting the arrangement information created by the creating means;
An instruction arrangement device comprising: Computer
An acquisition step of acquiring a call graph representing a call relationship between instructions in firmware applied to the target device;
Of the instructions represented by the call graph obtained by the obtaining step, a classification step for classifying into a first instruction group located above a predetermined hierarchy from the top and a second instruction group other than the instruction,
A code for calling the instructions classified into the first instruction group by the classification step is set to be arranged in the first memory bank to which power is always supplied among the memory banks mounted on the target device. Creation process to create the arranged information,
An output step of outputting the arrangement information created by the creation step;
Instruction placement method characterized by executing

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