JP5200692B2 - Data processing apparatus, voltage control method for data processing apparatus, and image forming apparatus - Google Patents

Description

The present invention relates to a data processing device having a circuit configuration for applying a termination voltage to a connection line connecting a data processing means and a main storage device, a voltage control method for the data processing device, and an image forming apparatus.

  DDR-SDRAM (Double-Data-Rate Synchronous Random Access Memory) has a function to shift to a mode with less power consumption than normal operation called power-down mode or self-refresh mode when there is no access for a certain period of time. Have. A high-speed signal such as DDR-SDRAM is connected to a termination voltage via a termination resistor on a data communication line and a control line between the data processing means and the DRAM. This termination voltage plays a role of reducing malfunctions due to the waveform reflection peculiar to high-speed signals and the shoulder (stepped waveform) resulting from this, but the termination resistor behaves as a simple pull-up resistor when data processing is not performed. For this reason, it is known that a current flows unnecessarily from the termination voltage.

  For this reason, conventionally, various techniques have been proposed that achieve power saving in the above-described power-down mode or refresh mode. For example, in Patent Document 1, in the power-down mode or the self-refresh mode, a termination voltage system is provided for each terminal logic of the data processing means, and a voltage plane in the board is divided, and this is cut off or selected for survival. A technique for reducing the power consumption of the termination voltage and data processing means is disclosed.

JP 2006-331305 A

  However, the technique of Patent Document 1 requires a power supply system for each terminal logic, and has a problem that layout space is increased and layout is difficult because the voltage planes in the board are divided. In addition, since the current value flowing through the termination voltage is several amperes, voltage stabilizing means such as a regulator is used as the interruption means, which causes a problem that the circuit size is increased and the cost is increased. Further, when a regulator is used as the shut-off means, there is a problem that it takes time for the voltage to stabilize when returning from the power-down mode or the refresh mode.

  The present invention has been made in view of the above, and provides a data processing apparatus, a termination voltage control method for a data processing apparatus, and an image forming apparatus capable of more efficiently reducing power consumption due to a termination voltage. For the purpose.

To solve the above problems and achieve the object, a plurality invention, for connecting the storage means, data processing means for performing a predetermined data processing, and said data processing means and said storage means according to claim 1 It is connected to the respective connection lines, and a voltage application means for applying a predetermined voltage through a resistor to the connecting line, is connected between the resistor and the connection line, to the data processing state of the data processing means And an energization cut-off means for controlling energization of the predetermined voltage in response to the data processing when there is no access for more than a certain time between the storage means and the data processing means among the plurality of connection lines. The connection line connected to the terminal which sets the terminal logic of the means to the high impedance state is connected to the voltage applying means without going through the energization cutoff means .

The invention according to claim 2 is characterized in that, in the invention according to claim 1, the resistor is a termination resistor, and the predetermined voltage is a termination voltage.

According to a third aspect of the present invention, in the first or second aspect of the invention, the data processing means outputs a signal for turning on the energization of the predetermined voltage to the energization cut-off means at the time of data processing. When there is no data processing to be performed, a signal for turning off the energization of the predetermined voltage is output to the energization cut-off means, and the energization cut-off means is configured to output the predetermined voltage based on the signal input from the data processing means. This is characterized in that the energization of is turned on / off.

According to a fourth aspect of the present invention, in the invention according to any one of the first to third aspects, the power cut-off means is a data processing state of the data processing means among signals flowing through the plurality of connection lines. The energization of the predetermined voltage is turned on / off based on the signal level of a specific signal that varies depending on the signal level.

The invention according to claim 5 is the invention according to claim 4, wherein the signal level of the specific signal input to the energization cutoff unit is negated, and the contribution of the specific signal to the energization cutoff unit is made. It further comprises invalidating means for invalidating.

The invention according to claim 6 is the invention according to claim 5 , wherein the data processing means controls the invalidation means to validate and invalidate the contribution of the specific signal to the energization cutoff means. And switching between.

According to a seventh aspect of the present invention, in the invention according to the fifth or sixth aspect , the invalidation means is configured to apply the specific signal to the energization cutoff means based on an invalidation control signal input from the outside. Switching between enabling and disabling contributions.

The invention according to claim 8 is the invention according to any one of claims 1 to 7 , wherein the energization cutoff means is a semiconductor switch.

The invention according to claim 9 is the invention according to claim 8 , wherein the semiconductor switch is a bus switch or a field effect transistor.

The invention according to claim 10 is the invention according to claim 8 or 9 , wherein the resistance is a resistance component that the semiconductor switch has when energized.

The invention according to claim 11 is connected to a storage unit, each of the plurality of connection lines for connecting the data processing means for performing a predetermined data processing, and said data processing means and said memory means, said connection lines A voltage application method for applying a predetermined voltage via a resistor to a data processing apparatus, and a current control unit connected between the connection line and the resistor , in response to said data processing status of the data processing means, viewed including the current interrupting step of controlling the energization of the predetermined voltage, the plurality of connection lines, a fixed time between said data processing means and said memory means that the data processing means connected to the connection line to the terminal pin logic to a high impedance state of being connected to said voltage applying means not through the energizing interrupting means when more than there is no access And butterflies.

The invention according to claim 12 is connected to each of a storage means , a data processing means for performing predetermined data processing relating to image formation, and a plurality of connection lines connecting the storage means and the data processing means. A voltage applying unit that applies a predetermined voltage to the connection line via a resistor; and a connection between the connection line and the resistor, and the energization of the predetermined voltage according to a data processing state of the data processing unit A power interruption means for controlling the data processing means, and when there is no access for more than a certain time between the storage means and the data processing means among the plurality of connection lines, the terminal logic of the data processing means is in a high impedance state. The connection line connected to the terminal is connected to the voltage application means without going through the energization cutoff means.

According to the first, eleventh, and twelfth aspects, by providing the current cutoff means for controlling the current supply of a predetermined voltage according to the data processing state of the data processing means between the connection line and the resistor , the voltage system and without dividing the voltage plane, it is possible to cut off the voltage in accordance with the data processing state of the data processing means, it is possible to suppress the installation space, is possible to reduce the power consumption by the voltage more efficiently it can. Further, since the value of the current flowing through the current interrupting means can be suppressed, a small and inexpensive semiconductor switch or the like can be used as the current interrupting means, and an increase in circuit size and cost related to the interrupting means can be suppressed. . In addition, since there is no need for voltage energization control for a communication line that becomes high impedance when there is no data processing to be executed by the data processing means, the number of parts can be reduced by not connecting the energization cutoff means. .

According to the third aspect of the present invention , when there is no data processing to be executed in the data processing means, it is possible to turn off energization of the predetermined voltage , so that power consumption due to the voltage can be efficiently reduced. .

Further, according to claim 4, by utilizing the existing signal comprising data processing means, without providing a mechanism for controlling the energization interrupting means, predetermined when the data processing is not to be performed on the data processing means the energization voltage it is possible to turn off, it is possible to suppress the increase in the number of components and cost can be reduced power consumption by the voltage efficiently.

Further, according to claims 5 and 6 , since the data processing means can switch between the validation and invalidation of the contribution to the power cut-off means by the specific signal, it can be performed in an arbitrary period according to the environment to be used. Power consumption due to a predetermined voltage can be reduced.

Further, according to claim 7 , since it is possible to switch between the validation and invalidation of the contribution of the specific signal to the power cut-off means based on the invalidation control signal input from the outside, the environment to be used It is possible to reduce power consumption due to a predetermined voltage during an arbitrary period according to the above.

Further, according to the eighth and ninth aspects , the circuit size and cost can be suppressed by using the semiconductor switch as the energization cutoff means.

According to the tenth aspect , since the resistance component that the semiconductor switch has when energized can be used as the resistance , the number of components can be suppressed.

Exemplary embodiments of a data processing apparatus, a voltage control method for the data processing apparatus, and an image forming apparatus according to the present invention will be explained below in detail with reference to the accompanying drawings.

[First Embodiment]
FIG. 1 is a diagram showing an overall configuration of an image forming apparatus 100 suitable for explanation of each of the following embodiments. The image forming apparatus 100 is an MFP (Multi Functional Peripheral) having a plurality of functions, and as shown in FIG. 1, an automatic duplex document feeder 111 (hereinafter referred to as RADF), a scanner unit 112, and a document A reading unit 11 including a table 113, an image forming unit 12 including a paper conveyance unit 121, a laser writing unit 122, and an electrophotographic processing unit 123, a post-processing unit 13, and a FAX unit 14. I have.

  In the image forming apparatus 100, the reading unit 11 and the image forming unit 12 form an image and print on paper, and the post-processing unit 13 performs output paper alignment, stapling, and punch hole processing.

  The image data read by the reading unit 11 is output to the image forming unit 12. The RADF 111 reverses the front and back surfaces of a document on which a single-sided image has been read by the scanner unit 112 from a document tray (not illustrated) to a discharge tray (not illustrated) via a document table 113 and the document table again. A double-sided document feed path leading to a single-sided or double-sided document can be handled. The scanner unit 112 irradiates a document with a lamp and forms an image of reflected light of the document on a light receiving surface of a photoelectric conversion element with a lens, a mirror, or the like.

  The photoelectric conversion element converts the reflected light on the document surface of the document into an electrical signal and outputs it to a main CTL substrate 15 described later. The image forming unit 12 includes a paper transport unit 121 that transports paper, a laser writing unit 122, and an electrophotographic process unit 123. The paper transport unit 121 includes a sub transport path that reverses the front and back surfaces of the paper that has passed through the fixing roller and leads it to the electrophotographic process unit 123 again in the double-sided copying mode in which images are formed on both sides of the paper.

  The laser writing unit 122 is a semiconductor laser that emits laser light based on image data supplied from a main CTL substrate 15 to be described later, and a photoconductor of the electrophotographic process unit 123 that passes the light emitted from the semiconductor laser through a mirror or a lens. Light distribution on the drum surface. An electrostatic latent image is formed on the surface of the photosensitive drum, and the toner image is made visible by supplying toner from the developing device.

  The toner image is transferred onto the paper guided from the paper transport unit 121, and then heated and pressurized by the fixing roller, and the toner image is melted and fixed on the surface of the paper. As described above, after the paper writing is completed, a part of the output paper is provided in the post-processing unit 13, the staple and punch holes are processed, and the paper is discharged to the tray. In this embodiment, the printing method of the image forming unit 12 is an electrophotographic method. However, the printing method is not limited to this, and other printing methods such as an inkjet method, a sublimation type thermal transfer method, a direct thermal recording method, and a melt type thermal transfer method. May be used.

  The FAX unit 14 transmits a fax signal of image data read by the reading unit 11 and image data supplied from a main CTL board 15 described later via a telephone line (for example, an analog public network PSTN). Further, the facsimile signal received via the telephone line is output to the main CTL board 15.

  Next, a detailed configuration and function of the image forming apparatus 100 will be described with reference to FIG. FIG. 2 is a block diagram showing a detailed configuration of the image forming apparatus 100 suitable for the description of each embodiment below. As shown in FIG. 2, the image forming apparatus 100 includes functional units related to image formation of the reading unit 11, the image forming unit 12, the post-processing unit 13, and the FAX unit 14, a main CTL substrate 15, and a display. An operation unit 16 and a power supply unit 17 are provided.

  The main CTL board 15 includes a CPU 151, a data processing unit 152, an I / O controller 153, an option slot 154, and a data storage unit 155.

  Here, the CPU 151 is a central processing unit that performs overall control of the image forming apparatus 100. Specifically, the CPU 151 executes predetermined program data stored in the data storage unit 155, thereby initializing each unit of the image forming apparatus 100, shifting / returning to an energy saving mode to be described later, image formation, and the like. Perform various processes.

  The data processing unit 152 is a functional unit for executing predetermined data processing related to the operation of the image forming apparatus 100 under the control of the CPU 151. For example, predetermined image processing is performed on the image data input from the I / O controller 153 and the image data stored in the data storage unit 155. Details of the data processing unit 152 will be described later.

  The I / O controller 153 is a communication control circuit that includes an interface for connecting to the external device 200 via a network such as the Internet (Network in the figure). Specifically, the I / O controller 153 outputs the image data transmitted from the external device 200 to the data processing unit 152.

  The option slot 154 is a slot (bridge) for connecting a USB device, an IEEE1394 device, or the like. Note that the types of devices to be connected are not limited to these, and it is possible to provide a standard slot according to the device to be used.

  The data storage unit 155 stores image data to be printed by the image forming apparatus 100 and is stored in a storage medium such as a hard disk drive (HDD). The data storage unit 155 stores various program data and setting information related to the control of the image forming apparatus 100 in advance.

  The display operation unit 16 is a touch panel type input device, and performs, for example, various messages indicating operation prompts and processing statuses under the control of the CPU 151, and inputs such as setting of printing conditions for image formation. Accept. In the present embodiment, the display operation unit 16 in which the input device and the display device are integrated is used. However, the present invention is not limited to this, and the input device and the display device may be separated.

  The power supply unit 17 converts power supplied from an external commercial power supply into power required in the image forming apparatus 100 and supplies the power to each part of the image forming apparatus 100.

  FIG. 3 is a block diagram showing a configuration of the data processing unit 20 of the present embodiment corresponding to the data processing unit 152. As shown in the figure, the data processing unit 20 includes an ASIC 21, a volatile memory 22, a termination voltage unit 23, and an energization cutoff unit 24.

  The ASIC 21 is an integrated circuit prepared for predetermined data processing related to the operation of the image forming apparatus 100 under the control of the CPU 151. Specifically, when a processing request for instructing execution of predetermined data processing is input from the CPU 151 or the like, the ASIC 21 requests using the volatile memory 22 connected by a plurality of connection lines 25 as a work area. The processed data is executed.

  The volatile memory 22 is a main storage device of the image forming apparatus 100, and DDR-SDRAM, DRAM (Dynamic Random Access Memory), or the like can be used. Note that the volatile memory 22 has a function of shifting to a mode in which power consumption is suppressed compared to a normal operation mode called a power-down mode or a self-refresh mode when there is no access to the ASIC 21 for a certain period of time. Shall.

  The termination voltage unit 23 is a power supply circuit that supplies a termination voltage for terminating a signal between the ASIC 21 and the volatile memory 22. Here, the termination voltage unit 23 is connected to each of the connection lines 25 via a termination resistor 26.

  The energization cutoff unit 24 is connected between the termination resistor 26 and the connection line 25 and turns on energization of the termination voltage applied from the termination voltage unit 23 to each connection line 25 in accordance with a control signal input from the ASIC 21. (Energized) / off (shut off). In this way, since the current cut-off section 24 is connected to the downstream side of the termination resistor 26 when viewed from the termination voltage section 23, the current value flowing through the current cut-off section 24 can be suppressed, and thus a small and low-priced semiconductor It is possible to use a switch as the energization cutoff unit 24.

  For example, a bus switch that is a semiconductor switch capable of turning on / off a plurality of connections can be used as the energization cutoff unit 24. By using this bus switch, the termination voltage applied from the termination voltage unit 23 to each connection line 25 can be turned on / off at a time according to the control signal (H level / L level) input from the ASIC 21. It becomes possible.

  In the above configuration, when the volatile memory 22 is in the power down mode or the self-refresh mode, the terminals of the volatile memory 22 are in a high impedance state. However, in the ASIC 21, the logic is different for each terminal, and the H level (high level), L Level (low level) or high impedance state. At this time, the drive current flows from the terminal having the H level to the terminal having the L level and the termination voltage unit 23, while the terminal having the L level is current from the terminal having the H level and the termination voltage unit 23. Pull in. That is, although the ASIC 21 is not performing processing, the above two types of currents flow, and thus current flows unnecessarily from the termination voltage unit 23.

  Therefore, the ASIC 21 controls the energization cut-off unit 24 to cut off the energization from the termination voltage unit 23, thereby suppressing the generation of the two types of unnecessary currents. Specifically, the ASIC 21 outputs a control signal for turning off (cuts off) energization to the energization cut-off unit 24 during a period when data processing is not performed in its own circuit, so that the energization cut-off unit 24 connects from the termination voltage unit 23. The terminal voltage supplied to the line 25 is cut off.

  Hereinafter, the operation of the ASIC 21 will be described with reference to FIG. FIG. 4 is a flowchart showing a procedure of energization control processing by the ASIC 21.

  First, the ASIC 21 determines whether or not a processing request for requesting execution of data processing is input from the CPU 151 (step S11). Here, when it is determined that the processing request is not input (step S11; No), the ASIC 21 outputs a control signal (energization off signal) for interrupting energization to the energization interrupting unit 24 (step S12), and step S11. Return to the process. The data processing requested from the CPU 151 includes, for example, storage processing of data read by the reading unit 11 in the volatile memory 22, reading processing of image data stored in the volatile memory 22, and processing for image data. Although predetermined image processing etc. are mentioned, it shall not be limited to these processes.

  On the other hand, when it is determined in step S11 that a processing request has been input (step S11; Yes), the ASIC 21 outputs a control signal (energization on signal) that instructs the energization cutoff unit 24 to energize (step S13). Subsequently, the ASIC 21 executes the requested data processing while using the volatile memory 22 as a work area (step S14), and returns to the processing of step S11.

  The ASIC 21 performs the energization process described above, so that the termination supplied from the termination voltage unit 23 to the connection line 25 during a period when the ASIC 21 is not performing the process, that is, in the power-down mode or the self-refresh mode of the volatile memory 22. The voltage can be cut off.

  As described above, according to the present embodiment, when the ASIC 21 has no data processing to be executed by the energization interruption unit 24 connected between the connection line 25 and the termination resistor 26, the energization of the termination voltage is turned off (interruption). Therefore, power consumption due to the termination voltage can be efficiently reduced. Further, since the value of the current flowing through the energization cutoff unit 24 can be suppressed, a small and inexpensive semiconductor switch can be used as the energization cutoff unit 24, and an increase in circuit size and cost related to the energization cutoff unit 24 is suppressed. be able to.

[Second Embodiment]
Next, as a second embodiment, a configuration example in which a field effect transistor that is a semiconductor switch is used for the above-described energization cutoff unit 24 will be described. In addition, about the element similar to 1st Embodiment mentioned above, it shows using the same code | symbol and the description is abbreviate | omitted suitably.

  FIG. 5 is a block diagram showing a configuration of the data processing unit 30 of the present embodiment corresponding to the data processing unit 152. As shown in the figure, the data processing unit 30 includes an ASIC 32, a volatile memory 22, a termination voltage unit 23, and an energization cutoff unit 31.

  The energization cutoff unit 31 includes a number of FETs (field effect transistors) 311 corresponding to the number of connection lines 25, and the terminal voltage unit 23 and each connection line 25 are connected by these FETs 311. Specifically, the termination voltage unit 23 and each connection line 25 are connected via the drain terminal and the source terminal of each FET 311, and a control signal from the ASIC 32 is input to the gate terminal of each FET 311. It is configured as follows.

  The basic operation of the ASIC 32 is the same as that of the ASIC 21 described above, but by outputting an L level control signal to the gate terminal of each FET 311 during a period when there is no data processing to be processed by its own circuit, The drain-source resistance is increased, and the termination voltage supplied from the termination voltage unit 23 to the connection line 25 is blocked by the energization cutoff unit 31. Note that the L level control signal is smaller than the pinch-off voltage of the FET 311.

  Further, the ASIC 32 outputs a control signal of H level to the gate terminal of each FET 311 during a period in which data processing is performed in its own circuit, thereby reducing the drain-source resistance of each FET 311, and terminating by the energization cutoff unit 31. Control is performed so that the termination voltage is supplied from the voltage unit 23 to the connection line 25. It is assumed that the H level control signal is larger than the pinch-off voltage of the FET 311.

  Note that, when the FET 311 is used as the energization cutoff unit 31 as in this embodiment, a resistance component is generated during energization due to the device characteristics of the FET. Therefore, by handling this resistance component as the terminating resistor 26, the terminating resistor 26 itself can be omitted as shown in FIG.

  As described above, according to the present embodiment, when the ASIC 32 has no data processing to be executed by the energization interruption unit 31 connected between the connection line 25 and the termination resistor 26, the energization of the termination voltage is turned off (interruption). Therefore, power consumption due to the termination voltage can be efficiently reduced. In addition, it is possible to use a small and low-priced semiconductor switch as the energization cutoff unit 31, and to suppress an increase in circuit size and cost related to the energization cutoff unit 31. Further, by using the resistance component that the semiconductor switch has when energized as the termination resistor, the termination resistor can be made unnecessary, so that the number of components can be suppressed.

  In the present embodiment, an example in which an enhancement type FET is used as a semiconductor switch has been described. However, a depletion type FET may be used. In this case, a control signal output from the ASIC 32 to the energization cutoff unit 31 may be used. It is possible to cope by reversing the logic from this configuration. Moreover, it is good also as an aspect using other semiconductor switches, such as MOSFET.

  As a modified example of this configuration, the connection line 25 connected to the terminal in the high impedance state among the terminals of the ASIC 32 may be short-circuited to the termination voltage unit 23 without passing through the energization cutoff unit 31. . Hereinafter, a modification of the data processing unit 30 will be described with reference to FIG.

  FIG. 6 is a block diagram showing a configuration of a data processing unit 30a according to a modification of the present embodiment. As shown in the figure, the data processing unit 30 a includes an ASIC 32, a volatile memory 22, a termination voltage unit 23, and an energization cut-off unit 31, similarly to the data processing unit 30 described above.

  Here, when the volatile memory 22 is in the power-down mode or the self-refresh mode, the power cut-off section 31 is not connected to the connection line 25 in which the terminal logic of the ASIC 32 is in a high impedance (Hiz) state. That is, the termination voltage from the termination voltage unit 23 is always applied to the connection line 25 in which the terminal logic of the ASIC 32 is in a high impedance (Hiz) state.

  As described above, when the volatile memory 22 is in the power-down mode or the self-refresh mode, the terminals of the volatile memory 22 are in a high impedance state. Therefore, no current flows into the connection line 25 connected between the terminal of the ASIC 32 whose terminal logic is in the high impedance (Hiz) state and the terminal of the volatile memory 22. That is, the data processing unit 30a has a configuration in which the power supply control by the power supply cutoff unit 31 is kept to the minimum necessary from the configuration of the data processing unit 30. Thereby, the number of FETs 311 constituting the energization cutoff unit 31 can be reduced as compared with the data processing unit described above.

  In the configuration of FIG. 6, the termination voltage unit 23 and the connection line 25 are connected via the termination resistor 26. However, when the resistance component of the energization cutoff unit 31 can be used as the termination resistor 26. Is good also as a mode which handles the electricity supply interruption | blocking part 31 as the termination resistance 26. FIG.

[Third Embodiment]
Next, as a third embodiment, a configuration example in which energization control of the energization cutoff unit 31 is performed using a CKE (ClockK Enable) signal output from the ASIC will be described. In addition, about the element similar to 1st, 2nd embodiment mentioned above, it shows using the same code | symbol and the description is abbreviate | omitted suitably.

  FIG. 7 is a block diagram showing a configuration of the data processing unit 40 of the present embodiment corresponding to the data processing unit 152. As shown in the figure, the data processing unit 40 according to the present embodiment includes an ASIC 41, a volatile memory 22, a termination voltage unit 23, and an energization cutoff unit 31.

  The ASIC 41 has a terminal for outputting the CKE signal, and outputs the CKE signal to the volatile memory 22 via the connection line 25 connected to the terminal. Here, the CKE signal is a signal that is at the H level while the ASIC 41 performs data processing, and is at the L level while the data processing is not performed. The volatile memory 22 can determine whether or not the ASIC 41 is processing data based on the level of the input CKE signal.

  The gate terminal of each FET 311 included in the energization cutoff unit 31 is short-circuited to the connection line 25 connected to the output terminal of the CKE signal in the ASIC 41, and the CKE signal output from the ASIC 41 is connected to the gate terminal of each FET 311. It is configured to be entered. Note that the connection line 25 connected to the CKE signal output terminal of the ASIC 41 is excluded from the target of energization control by the energization cut-off unit 31.

  Each FET 311 of the energization cutoff unit 31 performs on / off control of energization from the termination voltage unit 23 to each of the connection lines 25 according to the level of the CKE signal input from the gate terminal. That is, the energization cut-off unit 31 controls the termination voltage to be supplied from the termination voltage unit 23 to the connection line 25 when the CKE signal is at the H level, that is, while the ASIC 41 performs data processing. The energization cutoff unit 31 cuts off the termination voltage supplied from the termination voltage unit 23 to the connection line 25 when the CKE signal is at L level, that is, during a period when the ASIC 41 does not perform data processing.

  Next, the operation of the data processing unit 40 will be described with reference to FIG. FIG. 8 is a flowchart showing a procedure of energization control processing executed by the ASIC 41. As an initial state of this process, it is assumed that the ASIC 41 continues the H level state of the CKE signal after executing the data processing requested by the CPU 151.

  First, the ASIC 41 determines whether or not a processing request for requesting execution of data processing from the CPU 151 is input within a predetermined time from the previous input (step S21). If it is determined that the input has been made within the predetermined time (step S21; Yes), the ASIC 41 executes the requested data processing while using the volatile memory 22 as a work area (step S22), and the process of step S21. Return to again. In addition, although the predetermined time used as the input interval of a process request shall not be ask | required especially, you may make it correspond with the transfer time to the power consumption mode of the volatile memory 22, for example.

  On the other hand, if it is determined in step S21 that the processing request is not input within the predetermined time (step S21; No), the ASIC 41 sets the CKE signal to the L level (step S23), and proceeds to the processing of step S24. With the processing in step S23, the energization cutoff unit 31 cuts off the termination voltage from the termination voltage unit 23 to the connection line 25, and the volatile memory 22 shifts to the power consumption mode (power-down mode or self-refresh mode). .

  In subsequent step S24, the ASIC 41 waits until a processing request is input from the CPU 151 (step S24; No). If the ASIC 41 determines that a processing request has been input (step S24; Yes), the ASIC 41 sets the CKE signal to the H level in order to execute the requested data processing (step S25). With the processing in step S25, the energization cutoff unit 31 sets the termination voltage from the termination voltage unit 23 to the connection line 25 in the energized state, and the volatile memory 22 cancels the power saving mode. Subsequently, the ASIC 41 executes the requested data processing while using the volatile memory 22 as a work area (step S26), and returns to the processing of step S21 again.

  As described above, according to the present embodiment, by using an existing signal (CKE signal) included in the ASIC 41, data processing to be executed by the ASIC 41 without preparing a function for controlling the energization cutoff unit 31. Since the termination voltage can be turned off when there is no power, increase in the number of components and cost can be suppressed, and power consumption due to the termination voltage can be efficiently reduced.

  If the logic of the CKE signal is output in an inverted state, an inverting circuit (NOT element) for inverting the signal level of the CKE signal is separately provided, and the CKE signal output from the ASIC 41 is inverted by the inverting circuit. By inputting to the gate terminal of each FET 311, it is possible to perform energization control of the energization cutoff unit 31 using the existing signal included in the ASIC 41 as described above. Alternatively, a depletion type FET 312 described later may be used.

  Further, in the configuration of FIG. 7, the termination voltage unit 23 and the connection line 25 are configured to be connected via the termination resistor 26, but when the resistance component of the energization cutoff unit 31 can be used as the termination resistor 26. Is good also as a mode which handles the electricity supply interruption | blocking part 31 as the termination resistance 26. FIG.

[Fourth Embodiment]
Next, as a fourth embodiment, a configuration example that makes it possible to invalidate the contribution of the CKE signal to the current cut-off section 31 in the configuration using the CKE signal described in the third embodiment will be described. To do. In addition, about the element similar to 1st, 2nd, 3rd embodiment mentioned above, it shows using the same code | symbol and the description is abbreviate | omitted suitably.

  FIG. 9 is a block diagram showing a configuration of the data processing unit 50 of the present embodiment corresponding to the data processing unit 152. As shown in the figure, the data processing unit 50 according to the present embodiment includes an ASIC 51, a volatile memory 22, a termination voltage unit 23, an energization cutoff unit 31, a tristate inversion circuit 52, and a pull-down resistor 53. And.

  The basic operation of the ASIC 51 is the same as that of the ASIC 41 described above, but a control signal for invalidating the contribution of the CKE signal to the energization cut-off unit 31 is output to the gate terminal of the tristate inversion circuit 52. ing. Further, the CKE signal of the ASIC 51 is output to the volatile memory 22 and is also output to the X terminal of the tristate inversion circuit 52.

  The tri-state inversion circuit 52 is a logic circuit (tri-state buffer) having an output value of Hiz (high impedance) that is not in any state other than H level and L level, and is input to the gate terminal and the X terminal. The value determined according to the signal value is inverted and output to the gate terminal of the FEP 312. Specifically, the tri-state inversion circuit 52 outputs Hiz when the signal level input to the gate terminal and the X terminal is “L, L” or “L, H”, and H when it is “H, L”. When it is “H, H”, L is output.

  The FET 312 is a depletion type FET and has a logic opposite to that of the FET 311 described above. That is, by applying an H level voltage to the gate terminal of each FET 311, the termination voltage supplied from the termination voltage unit 23 to the connection line 25 is cut off, and an L level voltage is applied to the gate terminal of each FET 311. Thus, the termination voltage is supplied from the termination voltage unit 23 to the connection line 25.

  One end of a pull-down resistor 53 is connected between the tri-state inverting circuit 52 and the gate terminal of the FET 312. The other end of the pull-down resistor 53 is grounded, and pulls down the high impedance signal value output from the tri-state inverting circuit 52 to the GND level.

  In the configuration of FIG. 9, the ASIC 51 can invalidate the contribution of the CKE signal to the energization cutoff unit 31 by setting the level of the energization control signal output to the tristate inversion circuit 52 to L. Further, by setting the level of the energization control signal to H, the contribution of the CKE signal to the energization cutoff unit 31 can be validated. Hereinafter, the validation / invalidation of the CKE signal by the energization control signal will be described.

  FIG. 10 is a timing chart showing the relationship between the energization control signal, the CKE signal, and the operation of the energization cutoff unit 31. In the figure, an example of operation starting from the time of power-on of the image forming apparatus 100 is shown, but it is not limited to this.

  As shown in FIG. 10, it is assumed that the ASIC 51 outputs an L level energization control signal to the tri-state inversion circuit 52 when the image forming apparatus 100 is powered on. At this time, even if the level of the CKE signal is changed, the voltage input to the energization cutoff unit 31 (the gate terminal of the FET 312) is at the L level, that is, the negated state due to the action of the tri-state inverting circuit 52 and the pull-down resistor 53. Therefore, the termination voltage is supplied from the termination voltage unit 23 to the connection line 25. That is, when the ASIC 51 outputs the L level energization control signal, the contribution of the CKE signal to the energization cutoff unit 31 becomes invalid.

  Subsequently, when the ASIC 51 outputs an H level energization control signal at a predetermined timing, it is input to the energization cut-off unit 31 (the gate terminal of the FET 312) only when the CKE signal is at the L level due to the action of the tristate inversion circuit 52. As a result, the terminal voltage supplied to the connection line 25 from the terminal voltage unit 23 is cut off. That is, when the ASIC 51 outputs the H level energization control signal, the contribution of the CKE signal to the energization cutoff unit 31 becomes effective.

  Thereafter, when the energization control signal is switched from the H level to the L level, the voltage input to the energization cutoff unit 31 (the gate terminal of the FET 312) becomes the L level regardless of the data processing status of the ASIC 51, and the energization by the CKE signal is performed. The contribution to the blocking unit 31 is invalidated.

  As described above, according to the present embodiment, the control of the ASIC 51 can switch between the validation and invalidation of the contribution to the energization cutoff unit 31 by the CKE signal, and thus an arbitrary period according to the environment to be used In addition, power consumption due to the termination voltage can be reduced.

  The timing at which the energization control signal is set to the L level and the H level is not limited to the above example, and can be switched at an arbitrary timing.

[Fifth Embodiment]
Next, as a fifth embodiment, in the configuration described in the fourth embodiment, the energy-saving transition signal that instructs the transition to the energy-saving mode that is input from the outside, with the contribution of the CKE signal to the energization cutoff unit 31. A configuration example to be invalidated will be described. In addition, about the element similar to 1st, 2nd, 3rd, 4th embodiment mentioned above, it shows using the same code | symbol and the description is abbreviate | omitted suitably.

  FIG. 11 is a block diagram showing a configuration of the data processing unit 60 of the present embodiment corresponding to the data processing unit 152. As shown in the figure, the data processing unit 60 according to the present embodiment includes an ASIC 41, a volatile memory 22, a termination voltage unit 23, a current cut-off unit 31, a tri-state inversion circuit 52, and a pull-down resistor 53. And.

  As shown in FIG. 11, an energy saving transition signal for instructing a transition to an energy saving mode input from an external circuit such as the CPU 151 is input to the gate terminal of the tri-state inverting circuit 52. Here, the “energy saving mode” is a special operation state for suppressing the power consumption of the image forming apparatus 100 and is also called a sleep mode. In the special operation state for suppressing the power consumption, there are several levels depending on how much power consumption is suppressed.

  For example, there are several operation states such as reducing the clock speed of the CPU 151 or cutting off the power supply to the devices in the device. In any operation state, the transition is performed according to the energy saving transition signal output from the CPU 151. Here, in the “energy saving mode”, the supply from the termination voltage unit 23 is performed during the period when the ASIC 41 does not perform data processing. It is assumed that power is cut off.

  Here, among the energy saving transition signals input from the CPU 151, the H level signal instructs the transition to the energy saving mode (hereinafter referred to as the energy saving transition signal ON), and the L level signal is not in the energy saving mode. (Normal operation mode) shall be instructed. That is, since the energy saving transition signal is the same as the energization control signal in the fourth embodiment described above, the invalidation / validation of the contribution of the CKE signal to the energization cutoff unit 31 is controlled by the signal level of the energy saving transition signal. Will be. Hereinafter, the H level energy saving transition signal is referred to as “ON state”, and the L level energy saving transition signal is referred to as “OFF state”.

  Note that the factor (trigger) for shifting to the energy saving mode is not particularly limited. For example, the CPU 151 has the function units (reading unit 11, image forming unit 12, post-processing unit 13, FAX unit 14, display operation). When the unit 16) confirms that the processing is not performed for a predetermined time, or when the user explicitly instructs the transition to the energy saving mode via the display operation unit 16 or the like, the energy saving transition signal is set to the H level. It is good also as an aspect to do.

  The factor for returning from the energy saving mode is not particularly limited. For example, when the display operation unit 16 or the like is operated by a user, or an original is placed on the reading unit 11 by an output signal from a sensor (not shown). When the CPU 151 detects this, the energy saving transition signal may be set to the L level.

  FIG. 12 is a timing chart showing the relationship among the energy saving transition signal, the CKE signal, and the operation of the energization cutoff unit 31. In the figure, an example of operation starting from the time of power-on of the image forming apparatus 100 is shown, but it is not limited to this.

  As illustrated in FIG. 12, it is assumed that the CPU 151 outputs an energy saving transition signal in an OFF state to the tri-state inversion circuit 52 when the image forming apparatus 100 is turned on. At this time, even if the level of the CKE signal changes depending on the data processing status of the ASIC 41, the voltage input to the energization cutoff unit 31 (the gate terminal of the FET 312) is L level due to the action of the tristate inversion circuit 52 and the pull-down resistor 53. That is, since the negated state is established, the termination voltage is supplied from the termination voltage unit 23 to the connection line 25. That is, when the energy saving mode of the image forming apparatus 100 is in the OFF state, the contribution to the energization cutoff unit 31 by the CKE signal is invalid.

  Subsequently, when the CPU 151 outputs an energy saving transition signal in the ON state, the voltage input to the energization cut-off unit 31 (the gate terminal of the FET 312) is H only when the CKE signal is at the L level due to the action of the tristate inversion circuit 52. Therefore, the termination voltage supplied from the termination voltage unit 23 to the connection line 25 is cut off. In other words, when the energy saving mode of the image forming apparatus 100 is in the ON state, the contribution to the power cut-off unit 31 by the CKE signal is effective.

  Thereafter, when the energy saving transition signal is switched from the ON state to the OFF state, that is, when a return from the energy saving mode is requested, the energization cut-off unit 31 (the gate terminal of the FET 312) is connected regardless of the data processing status of the ASIC 41. The input voltage becomes L level, and the contribution of the CKE signal to the energization cut-off unit 31 is invalidated.

  Next, the operation of the data processing unit 60 will be described with reference to FIG. FIG. 13 is a flowchart illustrating a procedure of energy saving control processing executed by each unit of the data processing unit 60.

  First, the CPU 151 determines whether there is a factor for shifting to the energy saving mode at all times or at predetermined time intervals (step S31; No). When the CPU 151 confirms the existence of the above-described cause of transition to the energy saving mode (step S31; Yes), the CPU 151 inputs an ON state energy saving transition signal to the gate terminal of the tristate inversion circuit 52 (step S32). As a result, the contribution of the CKE signal to the energization cutoff unit 31 is validated (step S33).

  Next, the CPU 151 determines whether or not there is a factor for returning from the energy saving mode, and when it is determined that the above-described return factor does not exist (step S34; No), the CPU 151 maintains the energy saving transition signal in the ON state. In subsequent step S35, the ASIC 41 determines whether or not a processing request for requesting execution of data processing is input from the CPU 151 (step S35).

  If it is determined in step S35 that a processing request has been input (step S35; Yes), the ASIC 41 performs data processing requested by the processing request. During this time, since the CKE signal of the ASIC 41 becomes H level, the energization cut-off unit 31 energizes the connection line 25 with the termination voltage from the termination voltage unit 23 (step S36).

  When the ASIC 41 completes the data processing requested by the processing request (step S37), since the CKE signal of the ASIC 41 becomes L level, the energization cutoff unit 31 determines the termination voltage supplied from the termination voltage unit 23 to the connection line 25. It shuts off (step S38) and returns to the process of step S34.

  If it is determined in step S35 that a processing request has not been input (step S35; No), the CKE signal of the ASIC 41 is at the L level, so that the energization cutoff unit 31 is connected from the termination voltage unit 23 to the connection line 25. The supplied termination voltage is cut off (step S38), and the process returns to step S34.

  On the other hand, in step S34, when the CPU 151 confirms the presence of the cause of return from the energy saving mode (step S34; Yes), the CPU 151 inputs an energy saving transition signal in the OFF state to the gate terminal of the tristate inversion circuit 52 (step S39). As a result, the contribution of the CKE signal to the energization cut-off unit 31 is invalidated (step S40). Subsequently, the CPU 151 returns the image forming apparatus from the energy saving mode to the normal operation mode (step S41), and ends this process.

  As described above, according to this embodiment, based on the energy saving transition signal input from the CPU 151 outside the data processing unit 60, switching between enabling and disabling the contribution to the power cut-off unit 31 by the CKE signal is performed. Therefore, power consumption due to the termination voltage can be reduced when the image forming apparatus 100 is in the energy saving mode.

  As mentioned above, although this invention has been demonstrated using the 1st-5th embodiment, a various change or improvement can be added to embodiment mentioned above. Moreover, the structure and function demonstrated in the 1st-5th embodiment mentioned above can be combined freely.

  For example, in the above-described embodiment, the example in which the data processing apparatus (data processing units 20, 30 (30a), 40, 50, 60) is applied to the image forming apparatus has been described. However, the present invention is not limited to this, and a PC (Personal Computer) is used. ) And the like may be applied to the information processing apparatus.

  As described above, the data processing apparatus, the termination voltage control method of the data processing apparatus, and the image forming apparatus according to the present invention have a circuit configuration in which the termination voltage is applied to the connection line that connects the data processing unit and the main storage device. This is effective, and is particularly suitable for controlling energization of the termination voltage when there is no data processing to be executed in the data processing means.

1 is a diagram illustrating an overall configuration of an image forming apparatus. 1 is a block diagram illustrating a detailed configuration of an image forming apparatus. It is the block diagram which showed the structure of the data processing part which concerns on 1st Embodiment. It is the flowchart which showed the procedure of the electricity supply control process which concerns on 1st Embodiment. It is the block diagram which showed the structure of the data processing part which concerns on 2nd Embodiment. It is the block diagram which showed the structure of the data processing part which concerns on the modification of 2nd Embodiment. It is the block diagram which showed the structure of the data processing part which concerns on 3rd Embodiment. It is the flowchart which showed the procedure of the electricity supply control process which concerns on 3rd Embodiment. It is the block diagram which showed the structure of the data processing part which concerns on 4th Embodiment. It is the timing chart which showed the relationship between an electricity supply control signal, a CKE signal, and operation | movement of an electricity supply interruption | blocking part. It is the block diagram which showed the structure of the data processing part which concerns on 5th Embodiment. It is the timing chart which showed the relationship between an energy saving transition signal, a CKE signal, and operation | movement of an electricity supply interruption | blocking part. It is the flowchart which showed the procedure of the energy-saving control process which concerns on 5th Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Image forming apparatus 11 Reading part 111 Automatic duplex document feeder (RADF)
DESCRIPTION OF SYMBOLS 112 Scanner unit 113 Document stand 12 Image formation part 121 Paper conveyance part 122 Laser writing unit 123 Electrophotographic process part 13 Post-processing part 14 FAX part 15 Main CTL board | substrate 151 CPU
152 Data Processing Unit 153 I / O Controller 154 Option Slot 155 Data Storage Unit 16 Display Operation Unit 17 Power Supply Unit 20 Data Processing Unit 21 ASIC
22 Volatile Memory 23 Termination Voltage Unit 24 Current Blocking Unit 25 Connection Line 26 Terminal Resistance 30 Data Processing Unit 30a Data Processing Unit 31 Current Blocking Unit 311 FET
312 FET
32 ASIC
40 Data processing part 41 ASIC
50 Data processing unit 51 ASIC
52 Tri-state inverting circuit 53 Pull-down resistor 60 Data processing unit 200 External device

Claims (12)

Storage means;
Data processing means for performing predetermined data processing;
It is connected to each of the plurality of connection lines for connecting the data processing means and said memory means, and a voltage applying means for applying a predetermined voltage through a resistor to the connection line,
An energization cut-off means connected between the connection line and the resistor and controlling energization of the predetermined voltage according to a data processing state of the data processing means;
With
Of the plurality of connection lines, a connection line connected to a terminal that sets the terminal logic of the data processing means to a high impedance state when there is no access for a certain time or more between the storage means and the data processing means, A data processing apparatus, wherein the data processing apparatus is connected to the voltage application means without going through the energization cutoff means . The data processing apparatus according to claim 1, wherein the resistor is a termination resistor, and the predetermined voltage is a termination voltage. The data processing means outputs a signal for turning on energization of the predetermined voltage to the energization cutoff means during data processing, and outputs a signal for turning off energization of the predetermined voltage when there is no data processing to be executed. Output to the power-off means,
3. The data processing apparatus according to claim 1, wherein the energization cutoff unit turns on / off energization of the predetermined voltage based on a signal input from the data processing unit. The energization cut-off means turns on / off energization of the predetermined voltage based on a signal level of a specific signal that varies according to a data processing state of the data processing means among signals flowing through the plurality of connection lines. The data processing device according to claim 1, wherein the data processing device is a data processing device. 5. The apparatus according to claim 4, further comprising: a nullifying unit that negates a signal level of the specific signal input to the power cut-off unit and negates the contribution of the specific signal to the power cut-off unit. The data processing apparatus described in 1. 6. The data processing apparatus according to claim 5, wherein the data processing unit controls the invalidation unit to switch between the validation and invalidation of the contribution to the energization cutoff unit by the specific signal. 7. The invalidation means switches between validation and invalidation of contribution to the energization cutoff means by the specific signal based on an invalidation control signal input from the outside. The data processing apparatus described in 1. The data processing apparatus according to claim 1, wherein the energization cutoff unit is a semiconductor switch. 9. The data processing apparatus according to claim 8, wherein the semiconductor switch is a bus switch or a field effect transistor. 10. The data processing apparatus according to claim 8 , wherein the resistance is a resistance component that the semiconductor switch has when energized . Applying a storage unit, a data processing unit for performing predetermined data processing, which is connected with the storage means to each of the plurality of connection lines for connecting the data processing unit, a predetermined voltage through a resistor to the connection line A voltage control method executed by a data processing device comprising:
By energization interrupting means connected between said resistor and said connection line, according to the data processing state of the data processing unit, viewed including the current interrupting step of controlling the energization of said predetermined voltage,
Of the plurality of connection lines, a connection line connected to a terminal that sets the terminal logic of the data processing means to a high impedance state when there is no access for a certain time or more between the storage means and the data processing means, A voltage control method , wherein the voltage application means is connected to the voltage application means without going through the energization cutoff means . Storage means;
Data processing means for performing predetermined data processing relating to image formation ;
Voltage application means connected to each of a plurality of connection lines connecting the storage means and the data processing means, and applying a predetermined voltage to the connection lines via a resistor;
An energization cut-off means connected between the connection line and the resistor and controlling energization of the predetermined voltage according to a data processing state of the data processing means;
With
Of the plurality of connection lines, a connection line connected to a terminal that sets the terminal logic of the data processing means to a high impedance state when there is no access for a certain time or more between the storage means and the data processing means, An image forming apparatus, wherein the image forming apparatus is connected to the voltage application means without going through the energization cutoff means.

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